Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a pixel group located on a side of a driving circuit layer away from a substrate, and the pixel group comprises at least two sub-pixels with the same light-emitting color. The pixel group is arranged in one-to-one correspondence with a driving circuit, and the pixel group is electrically connected with one driving circuit and at least two first power lines. The voltage values transmitted by the at least two first power lines are different. At least two sub-pixels are driven by one driving circuit, the pixel circuit space is reduced, more sub-pixels can be accommodated in the same unit area, the second electrodes of the multiple sub-pixels connected with the same driving circuit are disconnected with each other, the voltage of the second electrode of the sub-pixel can be individually controlled, the brightness of the sub-pixel can be individually controlled, and the display effect of the display panel is ensured.

Description

Technical Field

[0001] This application relates to the field of display device technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic Light Emitting Diode (OLED) display technology is considered one of the most promising next-generation display technologies. Compared to LCD technology, OLED technology offers advantages such as low energy consumption, low cost, self-emissiveness, wide viewing angles, and fast response times. With the rise of the metaverse concept, the demand for micro-display technologies such as AR / VR and even MR is becoming increasingly urgent. However, current OLED displays are limited by the space constraints of pixel circuitry, preventing them from achieving high pixel resolution and even lower angular resolution, thus failing to deliver the display effects and immersive experience of true micro-displays. Summary of the Invention

[0003] Based on this, this application provides a display panel and display device that can effectively improve the pixel resolution of a microdisplay.

[0004] In a first aspect, this application provides a display panel, including: substrate; A driving circuit layer, located on one side of the substrate, includes multiple driving circuits and multiple first power lines; Multiple sub-pixels are located on the side of the driving circuit layer away from the substrate. The multiple sub-pixels are arranged in an array along a first direction and a second direction. Each sub-pixel includes a first electrode, a light-emitting unit, and a second electrode. A pixel group, located on the side of the driving circuit layer facing away from the substrate, includes at least two sub-pixels with the same emission color. Each pixel group is configured in a one-to-one correspondence with a driving circuit. The pixel group is electrically connected to one of the driving circuits and at least two first power lines, wherein the voltage values ​​transmitted by the at least two power lines are different.

[0005] Preferably, the display panel further includes an isolation structure located on the side of the driving circuit layer opposite to the substrate, the extension direction of the isolation structure being perpendicular to the arrangement direction of the sub-pixels in the pixel group, and at least a portion of the second electrodes being disconnected from each other through the isolation structure; Preferably, the orthographic projection area of ​​the side of the isolation structure away from the substrate on the substrate is greater than or equal to the orthographic projection area of ​​the side of the isolation structure facing the substrate on the substrate. Preferably, the angle between the side of the isolation structure facing the pixel group and the plane where the substrate is located is less than or equal to 90°; Preferably, in the direction perpendicular to the substrate, the cross-section of the isolation structure is an inverted trapezoid; Preferably, the isolation structure includes an insulating material; Preferably, a cover layer is sequentially disposed on the side of the isolation structure away from the substrate, at least a portion of the cover layer being made of the same material as the second electrode, and the cover layer being disconnected from the adjacent second electrode at the sidewall of the isolation structure.

[0006] Preferably, a single driving circuit is electrically connected to the first electrode corresponding to at least two sub-pixels having the same emission color; Preferably, the display panel further includes a first planarization layer, a first transition layer, and a second planarization layer located on the side of the driving circuit layer opposite to the substrate. The first electrode is located on the side of the second planarization layer opposite to the substrate. The first planarization layer includes a plurality of first vias. The first transition layer includes a plurality of first connecting lines. The second planarization layer includes a plurality of second vias. The driving circuit is connected to the first connecting lines through the first vias. The first connecting lines are connected to the first electrode through at least two second vias. Preferably, the first vias corresponding to multiple pixel groups located in the same row are arranged in a row along the first direction; Preferably, in the first direction, a plurality of the first vias located in the same row are arranged at equal intervals.

[0007] Preferably, the number of power lines corresponding to the same pixel group is the same as the number of sub-pixels included in the pixel group; The driving circuit is electrically connected to the first electrode, and the second electrodes of the sub-pixels electrically connected to the driving circuit are disconnected from each other. The second electrodes are connected to the power lines, and the power lines connected to different second electrodes in the same pixel group are different. Preferably, the display panel further includes a display area and a non-display area, the sub-pixel array is arranged in the display area, the isolation structure extends from the display area to the non-display area, and the power line is located in the non-display area; Preferably, the second electrode located between two adjacent isolation structures extends from the display area to the non-display area and is connected to the power line; Preferably, the second electrodes of the multiple sub-pixels located between adjacent isolation structures are interconnected; The first power line includes at least two sub-power lines, which transmit different voltage values. The adjacent and disconnected second electrodes are connected to different sub-power lines in the extension direction perpendicular to the isolation structure.

[0008] Preferably, the display panel further includes an auxiliary connection layer, the auxiliary connection layer is located on the side of the isolation structure facing the substrate, the orthographic projection of the auxiliary connection layer on the substrate overlaps with the orthographic projection of the isolation structure on the substrate, and at least a portion of the auxiliary connection layer is located on the side of the isolation structure facing the sub-pixel, and the second electrode is overlapped with the auxiliary connection layer; Preferably, the orthographic projection of the auxiliary connection layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate; Preferably, the isolation structure encloses a plurality of isolation openings, the isolation openings exposing at least a portion of the first electrode, the auxiliary connection layer includes a plurality of auxiliary lines, the auxiliary lines are arranged in a one-to-one correspondence with the sub-pixels, the orthographic projection of the auxiliary lines on the substrate is located on at least one side of the orthographic projection of the sub-pixels on the substrate, and at least two auxiliary lines located in the same pixel group transmit different voltage values.

[0009] Preferably, the display panel further includes a pixel definition layer located on the side of the first electrode facing away from the substrate, the auxiliary connection layer and the isolation structure are located on the side of the pixel definition layer facing away from the substrate, the pixel definition layer has a pixel opening, the pixel opening corresponds one-to-one with the sub-pixel, the pixel opening exposes at least part of the first electrode, the orthographic projection of the pixel opening on the substrate is within the orthographic projection range of the isolation opening on the substrate, and part of the light-emitting unit and the second electrode extend from the pixel opening to the side of the pixel definition layer facing away from the substrate.

[0010] Preferably, the isolation structure encloses and forms a plurality of isolation openings, each isolation opening corresponding to a pixel group. The orthographic projection of at least two sub-pixels on the substrate is located within the orthographic projection range of the isolation opening on the substrate. The second electrodes located within the same isolation opening are interconnected. At least two second electrodes of the pixel group are electrically connected to one of the driving circuits. The first electrodes within the pixel group are respectively connected to one of the at least two power lines. The voltage values ​​transmitted by the at least two power lines are different.

[0011] Preferably, the isolation structure encloses and forms a plurality of isolation openings, and the isolation openings are configured to correspond one-to-one with the sub-pixels; The display panel also includes an auxiliary connection layer located on the side of the isolation structure facing the substrate. The auxiliary connection layer includes a plurality of auxiliary lines, and the auxiliary lines are configured to correspond one-to-one with the sub-pixels. The orthographic projection of the auxiliary line on the substrate is located on at least one side of the orthographic projection of the sub-pixel, at least a portion of the auxiliary line is exposed in the isolation opening, and the second electrode is disposed in contact with the auxiliary connection line; Preferably, the auxiliary lines located in the same pixel group are interconnected and electrically connected to the driving circuit corresponding to the same pixel group.

[0012] In another aspect, this application provides a display device including a display panel as described in any of the above claims.

[0013] The display panel provided in this application drives at least two sub-pixels through a driving circuit, reducing the pixel circuit space and enabling more sub-pixels to be accommodated in the same unit area. Furthermore, the second electrodes of multiple sub-pixels connected to the same driving circuit are disconnected from each other, allowing for individual control of the voltage of the second electrodes of the sub-pixels. This enables individual control of the brightness of the sub-pixels, ensuring the display effect of the display panel. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a diagram of a display panel provided in one embodiment of this application; Figure 2 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 3 This is an equivalent circuit diagram of a pixel group provided in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 5 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 6 This is a schematic diagram of the structure of a light-emitting unit provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 8 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 9 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 10 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 11 This is an equivalent circuit diagram of a pixel group provided in another embodiment of this application; Figure 12This is a schematic diagram of the structure of a display panel provided in another embodiment of this application; Figure 13 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application; Figure 14 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application; Figure 15 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application; Figure 16 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application; Figure 17 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application; Figure 18 This is a schematic diagram of the encapsulation layer structure provided in another embodiment of this application.

[0016] Explanation of reference numerals in the attached figures: 100, Substrate; 200, Driving circuit layer; 210, Driving circuit; 220, Power line; 221, First sub-power line; 222, Second sub-power line; 223, Third sub-power line; 224, Fourth sub-power line; 300, Pixel group; 310, First pixel group; 320, Second pixel group; 330, Third pixel group; 410, Sub-pixel; 411, First sub-pixel; 412, Second sub-pixel; 413, Third sub-pixel; 420, First electrode; 430, Light-emitting unit; 440, Second electrode; 450, Cover layer; 460, Encapsulation layer; 500, Isolation structure; 510, Isolation opening; 600, First transition layer; 610, First transition line; 620, Second transition layer; 621, Second transition line; 630, Third transition layer; 640, Third transition layer; 700, First planarization layer; 710, First via; 720, Second via; 730, Fourth via; 740, Fifth via; 750, Second planarization layer; 800, Auxiliary connection layer; 810, First auxiliary connection line; 820, Second auxiliary connection line; 830, Auxiliary line; 900, Pixel definition layer; 910, Pixel opening. Detailed Implementation

[0017] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0018] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0019] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0020] In the field of micro-display technology, including AR / VR and even MR, display quality is typically determined by angular resolution (PPD). Angular resolution is the number of pixels per degree within the field of view. A higher PPD results in a more detailed image, a weaker screen-door effect, and sharper text; in other words, a higher angular resolution leads to better image detail and immersion on the micro-display. Within the same field of view, PPI is a key factor determining display quality. Therefore, in the field of micro-display technology, the required PPI for display panels is at least higher than 1000, while micro-displays requiring a PPI as high as 2000-3500 are needed for even better display effects. However, existing products use a one-to-one correspondence between pixel circuits and sub-pixels, controlling the brightness of sub-pixels through a single pixel circuit to achieve image changes. Due to the large number of transistors and capacitor area in pixel circuits, the area of ​​a single pixel circuit is often larger than the area of ​​a sub-pixel, preventing further increases in PPI.

[0021] Figure 1 This is a schematic diagram of a display panel according to one embodiment of this application. The display panel can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. The display panel includes a display area AA with display function and a non-display area NA.

[0022] The display area AA of the display panel can be rectangular, square, circular, oval, or other shapes.

[0023] The display area AA includes a plurality of pixels arranged in a first direction XX and a second direction YY. Each pixel includes a plurality of sub-pixels 410 that display different colors. In some embodiments, sub-pixels 410 include a first sub-pixel 411, a second sub-pixel 412, and a third sub-pixel 413. For example, the first sub-pixel 411 is a blue sub-pixel, the second sub-pixel 412 is a green sub-pixel, and the third sub-pixel 413 is a red sub-pixel. In some embodiments, sub-pixels 410 may also be sub-pixels that emit white or other colors of light.

[0024] like Figures 2 to 4 As shown, an embodiment of the first aspect of this application provides a display panel, including: substrate 100; The driving circuit layer 200 is located on one side of the substrate 100 and includes multiple driving circuits 210 and multiple power lines 221. Multiple sub-pixels are located on the side of the driving circuit layer 200 away from the substrate 100. Multiple sub-pixels 410 are arranged in an array along the first direction XX and the second direction YY. Sub-pixels 410 include a first electrode 420, a light-emitting unit 430 and a second electrode 440. Pixel group 300, located on the side of driving circuit layer 200 opposite to substrate 100, includes at least two sub-pixels 410 with the same emission color. Pixel group 300 and driving circuit 210 are arranged in a one-to-one correspondence. The pixel group 300 is electrically connected to a driving circuit 210 and at least two power lines 220, and the power signals transmitted by the at least two power lines 220 electrically connected to the pixel group 300 are different.

[0025] In the display panel provided in this application embodiment, at least two sub-pixels 410 with the same luminous color are electrically connected by a driving circuit 210, thereby reducing the number of driving circuits 210 and increasing the number of sub-pixels 410 per unit display area. At the same time, multiple power lines 221 that transmit different voltage values ​​are provided to ensure that sub-pixels 410 driven by the same driving circuit 210 can be connected to different voltage signals. By providing the same signal through the same driving circuit 210 and providing different voltage values ​​through the power lines 210, the display differentiation of multiple sub-pixels 410 within the same pixel group 300 is achieved, which is more conducive to the display effect of the display panel.

[0026] In one embodiment, the number of first power lines 221 corresponding to the same pixel group 300 is the same as the number of sub-pixels 410 included in the pixel group 300. Sub-pixel 410 includes a first electrode 420, a light-emitting unit 430, and a second electrode 440. The driving circuit 210 is electrically connected to the first electrode 420. The second electrodes 440 of the sub-pixels electrically connected to the driving circuit 210 are disconnected from each other. The second electrodes 440 are connected to the power line 220. The voltage values ​​of the power line 220 connected to different second electrodes 440 in the same pixel group 300 are different.

[0027] Within the same pixel group 300, by setting the number of power lines 220 to be the same as the number of sub-pixels 410, the power signals connected to each sub-pixel 410 are different, ensuring that the sub-pixels 410 connected to the same driving circuit 210 can be displayed differently, which is beneficial to improving the display effect of high resolution.

[0028] In this embodiment, the first electrode 420 can be the anode of the sub-pixel 410, and the second electrode 440 can be the cathode of the sub-pixel 410. The number of sub-pixels 410 in the same pixel group 300 can be two or three. The more sub-pixels 410 there are, the more power lines 220 connected to the same pixel group 300 there are. Figure 3 An equivalent circuit diagram is shown, illustrating a driving circuit 210 driving the anodes of two sub-pixels 410, with the cathodes of the sub-pixels 410 connected to multiple power lines 220. (See diagram for reference.) Figure 3 As shown, the driving circuit 210 includes a driving transistor T1, a storage capacitor C1, and a data writing transistor T2. The first terminal of the driving transistor T1 is connected to the second power supply signal Vdd, and the second terminal of the driving transistor T1 is connected to the first electrode 420 (anode) of the two sub-pixels 410. The second electrodes 440 (cathodes) of the two sub-pixels 410 are respectively connected to the first sub-power supply signal Vss1 and the second sub-power supply signal Vss2. The first sub-power supply signal Vss1 and the second sub-power supply signal Vss2 are transmitted via different power lines 220. The first terminal of the writing transistor T2 is connected to the data signal Vdata, and the second terminal is connected to the control terminal of the driving transistor T1. The control terminal of the writing transistor T2 is connected to the write control signal Scan. One end of the storage capacitor C1 is connected to the control terminal of the driving transistor T1, and the other end is connected to the second power supply signal Vdd. In this embodiment, the driving circuit is not limited to... Figure 3 The 2T1C shown can also be other driving circuits with multiple functions, such as 3T1C, 5T2C, and 7T1C, which can be connected to the first electrode 420 of multiple sub-pixels 410 with the same luminous color. The driving transistor T1 is not limited to P-type and N-type transistors. Figure 3 In the illustrated embodiment, P-type tubes are preferred.

[0029] In this embodiment, the display panel further includes an isolation structure 500 located on the side of the driving circuit layer 200 facing away from the substrate 100. The extension direction of the isolation structure 500 is perpendicular to the arrangement direction of the sub-pixels 410 within the pixel group 300. At least a portion of the second electrodes 440 are disconnected from each other through the isolation structure 500. By disconnecting the second electrodes 440 from each other, the second electrodes 440 can be connected to different first power signal lines, enabling multiple sub-pixels 410 in the same pixel group 300 to independently control their light emission brightness.

[0030] In one embodiment, sub-pixels 410 are arranged in an array along the first direction XX and the second direction YY in the display area AA of the display panel, and the extension direction of the isolation structure 500 is perpendicular to the arrangement direction of the sub-pixels 410 in the pixel group 300, thereby enabling the isolation structure 500 to disconnect the second electrode 440 in the pixel group 300.

[0031] Figure 2 This embodiment demonstrates one pixel arrangement method, such as... Figure 2 As shown, the plurality of sub-pixels 410 include a first sub-pixel 411, a second sub-pixel 412, and a third sub-pixel 413 with different emission colors, wherein the emission area of ​​the third sub-pixel 413 is larger than that of the first sub-pixel 411 and the second sub-pixel 412. At least two first sub-pixels 411 form a first pixel group 310, at least two second sub-pixels 412 form a second pixel group 320, and at least two third sub-pixels 413 form a third pixel group 330. The first sub-pixels 411 and the third sub-pixels 413 are arranged alternately in the first direction X, the first sub-pixels 411 and the second sub-pixels 412 are arranged alternately in the second direction Y to form a first column, and the third sub-pixels are arranged sequentially in the second direction Y to form a second column, with the first column and the second column alternating in the first direction X.

[0032] The first pixel group 310 corresponding to the first sub-pixel 411 includes two first sub-pixels 411 arranged along the second direction Y, and the two first sub-pixels 411 are separated by a second sub-pixel 412. The second pixel group 320 corresponding to the second sub-pixel 412 includes two second sub-pixels 412 arranged along the second direction Y, and the two second sub-pixels 412 are separated by a first sub-pixel 411. The third pixel group 330 corresponding to the third sub-pixel 413 includes two third sub-pixels 413 arranged along the second direction Y, and the two third sub-pixels 413 are arranged adjacent to each other.

[0033] Multiple pixel groups 300 arranged along the first direction X are interconnected with sub-isolation structures 500 corresponding to different pixel groups 300 in the first direction X, thereby extending the isolation structure 500 in the first direction X and reducing the fabrication process of the first isolation structure 500.

[0034] Figure 4This embodiment demonstrates another pixel arrangement method, such as... Figure 4 As shown, in the first direction X, the first sub-pixel column 411, the second sub-pixel column 412, and the third sub-pixel column 413 are arranged in sequence, that is, the first sub-pixel 411, the second sub-pixel 412, and the third sub-pixel 413 are each arranged as a separate column.

[0035] The first pixel group 310 corresponding to the first sub-pixel 411 includes two first sub-pixels 411 arranged along the second direction Y, and the two first sub-pixels 411 are arranged adjacent to each other. The second pixel group 320 corresponding to the second sub-pixel 412 includes two second sub-pixels 412 arranged along the second direction Y, and the two second sub-pixels 412 are arranged adjacent to each other. The third pixel group 330 corresponding to the third sub-pixel 413 includes two third sub-pixels 413 arranged along the second direction Y, and the two third sub-pixels 413 are arranged adjacent to each other.

[0036] The isolation structures 500 corresponding to the multiple first pixel groups 310, second pixel groups 320 and third pixel groups 330 arranged in the first direction X are interconnected in the first direction X, so as to extend the isolation structure 500 in the first direction X and reduce the preparation steps of the first isolation structure 500.

[0037] exist Figure 2 and Figure 4 In the pixel arrangement shown, the display panel includes multiple isolation structures 500, each isolation structure 500 extending along a first direction X, and the multiple isolation structures 500 are arranged at intervals along a second direction Y.

[0038] The length of the isolation structure 500 is greater than the length of the display area AA of the display panel, ensuring that the second electrodes 440 of the sub-pixels within multiple pixel groups 300 in the same row are separated by the same isolation structure 500.

[0039] In one embodiment, Figure 5 It shows Figure 2 A sectional view along the AA direction, refer to Figure 5 As shown, the orthographic projection area of ​​the side of the isolation structure 500 away from the substrate 100 on the substrate 100 is greater than or equal to the orthographic projection area of ​​the side of the isolation structure 500 facing the substrate 100 on the substrate 100. By setting the isolation structure 500 to have a structure that is larger at the top and smaller at the bottom, when fabricating the second electrode 440, the isolation structure 500 can isolate the second electrode 440 within the pixel group 300, so that each sub-pixel 410 can be connected to the corresponding first power line 221.

[0040] The angle between the side of the isolation structure 500 facing the pixel group 300 and the plane where the substrate 100 is located is less than or equal to 90°.

[0041] In the direction perpendicular to the substrate 100, the cross-section of the isolation structure 500 is an inverted trapezoid. The inverted trapezoidal arrangement makes it easier to isolate the second electrode 440 on the side of the isolation structure 500 away from the substrate 100.

[0042] The isolation structure 500 includes insulating material; the isolation structure 500 can be a single-layer or multi-layer structure, and the material of the isolation structure 500 is an organic adhesive or an inorganic silicon-containing compound, such as PLN organic adhesive, transparent organic adhesive, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0043] In this embodiment, the light-emitting unit 430 of the sub-pixel 410 is as follows: Figure 6 As shown, the light-emitting unit 430 includes a hole injection layer HIL, a hole transport layer HTL, a light-emitting functional layer EML, an electron transport layer ETL, and an electron injection layer EIL stacked along the side away from the substrate 100. The light-emitting unit 430 of the sub-pixel 410 is not limited to the above-mentioned film layers, and can be multiple light-emitting units 430 stacked together. In this embodiment, the light-emitting functional layers of sub-pixels with different emission colors are prepared using a fine metal mask, enabling sub-pixels with different emission colors to emit light independently.

[0044] A cover layer 450 is sequentially disposed on the side of the isolation structure 500 away from the substrate 100. At least part of the cover layer 450 is made of the same material as the second electrode 440. The cover layer 450 and the adjacent second electrode 440 are disconnected at the side wall of the isolation structure 500, so that the isolation structure 500 can effectively isolate the second electrode 440.

[0045] In this embodiment, the cover layer 450 includes a first sub-cover layer and a second sub-cover layer stacked along a direction away from the substrate 100. The first sub-cover layer is made of the same material as the common layer of the light-emitting unit 430, and the second sub-cover layer is made of the same material as the second electrode 440. The thickness of the first sub-cover layer is the same as the total thickness of the inner common layer of the sub-pixel 410, and the thickness of the second sub-cover layer is the same as the thickness of the second electrode 440.

[0046] In existing technologies, the hole injection layer (HIL), hole transport layer (HTL), electron transport layer (ETL), and electron injection layer (EIL) are fabricated using ordinary photomasks. The HIL, HTL, ETL, and EIL layers of adjacent sub-pixels 410 are interconnected, forming a common layer. Due to the presence of this common layer, electrons can be transferred between adjacent sub-pixels 410, leading to leakage crosstalk and causing a degraded display effect.

[0047] In this embodiment of the invention, the isolation structure 500 can not only isolate the second electrode 440, but also isolate the common layer, thereby disconnecting the common layers of each sub-pixel 410 in the pixel group 300 from each other, further improving the display effect, and avoiding the problem of leakage crosstalk when the voltages of the second electrodes 440 of each sub-pixel 410 in the pixel group 300 are different.

[0048] Reference Figure 5 A single driving circuit 210 is electrically connected to the first electrode 420 corresponding to at least two sub-pixels 410 with the same emission color, so that the driving circuit 210 can control the emission of multiple sub-pixels 410 through multiple first electrodes 420.

[0049] In one embodiment, the display panel further includes a first planarization layer 700, a first transition layer 600, and a second planarization layer 750 located on the side of the driving circuit layer 200 facing away from the substrate 100. A first electrode 420 is located on the side of the second planarization layer 750 facing away from the substrate 100. The first planarization layer 700 includes a plurality of first vias 710, the first transition layer 600 includes a plurality of first connecting lines 610, and the second planarization layer 750 includes a plurality of second vias 720. The driving circuit 210 is connected to the first connecting lines 610 through the first vias 710, and the first connecting lines 610 are connected to the first electrode 420 through at least two second vias 720. By configuring the first vias 710, the first connecting lines, and the second vias 720, the driving circuit 210 can simultaneously drive at least two sub-pixels 410, reducing the number of driving circuits 210.

[0050] In this embodiment, the first vias 710 corresponding to multiple pixel groups 300 in the same row are arranged in a row along the first direction X, as shown in the reference. Figure 2 and Figure 4 As shown. By placing the first vias 710 of multiple pixel groups 300 located in the same row in the same row, the area of ​​the first vias 710 is reduced, and the multiple first vias 710 are avoided from being scattered and affecting the flatness of the first electrode 420.

[0051] In the first direction X, multiple first vias 710 located in the same row are equally spaced to ensure that the signal transmission between the first vias 710 does not affect each other.

[0052] Reference Figure 5 As shown, the orthographic projections of the first electrode 420, the second via 720, and the first via 710 on the substrate 100 do not overlap, ensuring that the first electrode 420, the second via 720, and the first via 710 do not affect each other, and ensuring that the filling of the second via 720 is flat and the first electrode 420 is flat.

[0053] In one embodiment, the orthographic projection of the first via 710 on the substrate 100 lies within the orthographic projection range of the isolation structure 500 on the substrate 100. This achieves the shielding of the first via 710 by the isolation structure 500, isolating the first via 710 from the diffraction of ambient light.

[0054] Reference Figure 2 and Figure 4 As shown, the arrangement direction of the multiple first vias 710 is consistent with the extension direction of the isolation structure 500, ensuring that the isolation structure 500 can block the multiple first vias 710.

[0055] In one embodiment, such as Figure 2 As shown, the number of power lines 220 corresponding to the same pixel group 300 is the same as the number of sub-pixels 410 included in the pixel group 300. Sub-pixel 410 includes a first electrode 420, a light-emitting unit 430, and a second electrode 440. The driving circuit 210 is electrically connected to the first electrode 420. The second electrodes 440 of the sub-pixel 410, which are electrically connected to the driving circuit 210, are disconnected from each other. The second electrodes 440 are connected to the power line 220. The voltage values ​​of the power line 220 connected to different second electrodes 440 in the same pixel group 300 are different.

[0056] Figure 2 and Figure 4 The illustration shows a pixel group 300 comprising two sub-pixels 410, each sub-pixel 410 being connected to two power lines 220. In other embodiments, a pixel group 300 comprises three or four sub-pixels 410, with three sub-pixels 410 being connected to three power lines 220, and four sub-pixels 410 being connected to four power lines 220. Furthermore, at least two power lines 220 corresponding to the same pixel group 300 transmit different voltage values. Since the luminous intensity of the sub-pixels 410 is jointly controlled by the driving signal provided by the driving circuit 210 and the voltage transmitted by the power lines 220, for multiple sub-pixels 410 within the same pixel group 300, the driving signal is the same, while the voltage transmitted by the power lines 220 is different, resulting in different luminous intensity of the sub-pixels 410 and enabling the display panel to have superior color display.

[0057] The display panel also includes a display area and a non-display area. The sub-pixel array 410 is arranged in the display area AA, the isolation structure 500 extends from the display area to the non-display area NA, and the power line 220 is located in the non-display area. The second electrode 440, located between two adjacent isolation structures 500, extends from the display area AA to the non-display area NA and is connected to the power line 220, thereby reducing the space occupied by the power line 220 in the display area.

[0058] The second electrodes 440 of multiple sub-pixels 410 located between adjacent isolation structures 500 are interconnected. For example... Figure 2 As shown, two first sub-pixels 411 form a first pixel group 310, two second sub-pixels 412 form a second pixel group 320, and two third sub-pixels 413 form a third pixel group 330. Between adjacent isolation structures 500, the second electrodes 440 of multiple first sub-pixels 411, multiple second sub-pixels 412, and multiple third sub-pixels 413 located in the same row are interconnected, enabling the second electrodes 440 located between adjacent isolation structures 500 to share the same power line 2210, reducing the number of first power lines 221 and achieving a narrow bezel.

[0059] The power line 221 includes at least two sub-power lines that transmit different voltage values. In the extension direction perpendicular to the isolation structure 500, adjacent and disconnected second electrodes 440 are connected to different sub-power lines.

[0060] In one embodiment, such as Figure 2 and Figure 4 As shown, taking a pixel group 300 comprising two sub-pixels 400 as an example, the power line 220 includes a first sub-power line 221 and a second sub-power line 222 distributed along the second direction Y. Multiple pixel groups 300 with the same emission color are arranged along the second direction Y. Sub-pixels 410 located in different pixel groups 300 and in the same row can be connected to the first sub-power line, while sub-pixels 410 located in another row are connected to the second sub-power line 222.

[0061] Reference Figure 4 As shown, in the second direction Y, there are a first pixel group 310, a second sub-pixel group 320, and a third sub-pixel group 330. A sub-pixel 410 in the first sub-pixel group 310 and a sub-pixel 410 in the second sub-pixel group 320 are connected to the same first sub-power line 221. Another sub-pixel 410 in the second pixel group 320 and a sub-pixel 410 in the third pixel group 330 are connected to the same second sub-power line 222.

[0062] The power line 220 includes a first sub-power line 221 and a second sub-power line 222 that transmit different voltage values. The first sub-power line 221 and the second sub-power line 222 are alternately arranged along the second direction Y in the non-display area, so that each row of sub-pixels 410 corresponds to one power line 220, and some rows can share the power line 220 that transmits the same voltage value, reducing the signal transmission sources of the power line 220. For example, the first row of sub-pixels 410 and the third row of sub-pixels 410 are connected to the first sub-power line 221, and the first row of sub-pixels 410 and the third row of sub-pixels 410 are connected to the second sub-power line 220. This means that only two power buses with different voltage values ​​need to be set in the non-display area NA, and the sub-pixels 410 in different pixel groups 300 can share the same power signal, ensuring the individual control of the sub-pixels 410 in the pixel group 300, reducing the number of power lines 220, and achieving a narrow bezel.

[0063] In one embodiment, such as Figure 7 and Figure 8 As shown, the display panel also includes an auxiliary connection layer 800, which is located on the side of the isolation structure 500 facing the substrate 100. The orthographic projection of the auxiliary connection layer 800 on the substrate 100 overlaps with the orthographic projection of the isolation structure 500 on the substrate 100. At least part of the auxiliary connection layer 800 is located on the side of the isolation structure 500 facing the sub-pixel 410. The second electrode 440 is connected to the auxiliary connection layer 800. By setting the auxiliary connection layer 800, the power line 220 signal is prevented from being transmitted only through the second electrode 440. The transmission distance is too long, the voltage transmission is uneven, and the display is uneven.

[0064] The orthographic projection of the auxiliary connection layer 800 on the substrate 100 does not overlap with the orthographic projection of the first electrode 420 on the substrate 100, so as to avoid interference between the signal transmitted by the first electrode 420 and the auxiliary connection layer 800.

[0065] The auxiliary connection layer 800 includes at least two auxiliary lines, which are configured to correspond to the same pixel group 300 and transmit different voltage values ​​to provide different voltage values ​​to at least two sub-pixels 410 within the same pixel group 300.

[0066] The number of auxiliary lines is the same as the number of sub-pixels 410 within the same pixel group 300, ensuring that each sub-pixel 410 within the same pixel group is connected to a different voltage value.

[0067] like Figure 7 and Figure 8As shown, the extension direction of the auxiliary line 830 is the same as the extension direction of the isolation structure 500. The orthographic projection of multiple auxiliary lines 830 corresponding to the same pixel group 300 on the substrate 100 is located within the orthographic projection range of the isolation structure 500 on the substrate 100, reducing the area occupied by the auxiliary lines 830 in the display area and improving the pixel aperture ratio 910. The auxiliary lines 830 extend to the non-display area and connect to the first power line 221.

[0068] like Figure 7 As shown, taking a pixel group 300 containing two sub-pixels 410 as an example, the auxiliary connection layer 800 includes a first auxiliary connection line 810 and a second auxiliary connection line 820. The first auxiliary connection line 810 is connected to one sub-pixel 410 within the pixel group 300, and the second auxiliary connection line 820 is connected to the other sub-pixel 410 within the pixel group 300. For multiple pixel groups 300 corresponding to adjacent isolation structures 500, the sub-pixels 410 located on one side of the isolation structure 500 in the second direction Y are all connected to the second auxiliary connection line 820.

[0069] In one embodiment, such as Figure 5 and Figure 8 As shown, the display panel also includes a pixel definition layer 900 located on the side of the first electrode 420 away from the substrate 100. An auxiliary connection layer 800 and an isolation structure 500 are located on the side of the pixel definition layer 900 away from the substrate 100. The pixel definition layer 900 has a pixel opening 910, which corresponds one-to-one with a sub-pixel 410. The pixel opening 910 exposes at least part of the first electrode 420. The orthographic projection of the pixel opening 910 on the substrate 100 is located on part of the light-emitting unit 430 and the second electrode 440 extending from the pixel opening 910 to the side of the pixel definition layer 900 away from the substrate 100.

[0070] In one embodiment, such as Figure 9 and 10 As shown, the isolation structure 500 encloses and forms a plurality of isolation openings 510, the isolation openings 510 exposing at least a portion of the first electrode 420. The auxiliary connection layer 800 includes a plurality of auxiliary lines 830, the auxiliary lines 830 being arranged one-to-one with the sub-pixels 410. The orthographic projection of the auxiliary lines 830 on the substrate 100 is located on at least one side of the orthographic projection of the sub-pixels 410 on the substrate 100. The voltage values ​​transmitted by the auxiliary lines 830 located in the same pixel group 300 are different.

[0071] Furthermore, such as Figure 10 As shown, the auxiliary line 830 is disposed on the periphery of the sub-pixel 410 to increase the overlap area between the second electrode 440 and the auxiliary connection layer 800.

[0072] Furthermore, the auxiliary lines 830 corresponding to adjacent sub-pixels 410 in the same row can be connected to each other to increase the area of ​​the auxiliary lines 830.

[0073] The mesh isolation structure 500 disconnects the common layer of adjacent sub-pixels 410 from each other, ensuring that there is no leakage or crosstalk between any adjacent sub-pixels 410. The second electrode 440 within the same pixel group 300 is connected to different auxiliary lines 830, enabling differentiated control of the second electrode 440. The corresponding arrangement of the auxiliary lines 830 and sub-pixels 410 further reduces the voltage drop loss of the first power line 221 along the transmission path. The peripheral arrangement of the auxiliary lines 830 ensures the overlap area between the second electrode 440 and the auxiliary connection layer 800, preventing the second electrode 440 from having a partial gap between its side and the auxiliary connection layer 800 due to the obstruction of the isolation structure 500, which could cause the sub-pixel 410 to fail to light up.

[0074] In the above embodiment, the display panel further includes a pixel definition layer 900 located on the side of the first electrode 420 away from the substrate 100, an auxiliary connection layer 800 and an isolation structure 500 located on the side of the pixel definition layer 900 away from the substrate 100, the pixel definition layer 900 having a pixel opening 910, the pixel opening 910 corresponding one-to-one with the sub-pixel 410, the pixel opening 910 exposing at least part of the first electrode 420, the orthographic projection of the pixel opening 910 on the substrate 100 being within the orthographic projection range of the isolation opening 510 on the substrate 100, and part of the light-emitting unit 430 and the second electrode 440 extending from the pixel opening 910 to the side of the pixel definition layer 900 away from the substrate 100.

[0075] In another embodiment of this application, the first electrode 420 is a cathode and the second electrode 440 is an anode. Figure 11 The diagram shows an equivalent circuit diagram of two sub-pixels 410 driven by the same driving circuit 210, with the anodes of each sub-pixel 410 connected to different power lines 220. Figure 11 As shown, the first electrode of the driving transistor T1 is connected to the second power signal Vss, and the second electrode of the driving transistor T1 is connected to the first electrode 420 (cathode) of the two sub-pixels 410. The second electrodes 440 (anodes) of the two sub-pixels 410 are respectively connected to the power signal Vdd1 transmitted by the third sub-power line 223 and the power signal Vdd2 transmitted by the fourth sub-power line 224. Other connections are... Figure 3 Same. Figure 10 In the embodiment shown, the driving transistor T1 is preferably an N-type transistor. Driving the cathode of the sub-pixel 410 through the N-type transistor helps to improve the light emission stability of the sub-pixel 410 and avoids the different resistances of different sub-pixels 410 from affecting the display effect.

[0076] In one embodiment, such as Figure 12 and 13 As shown, the isolation structure 500 encloses multiple isolation openings 510, each corresponding to a pixel group 300. The orthographic projections of at least two sub-pixels 410 onto the substrate 100 lie within the orthographic projection range of the isolation opening 510 onto the substrate 100. Second electrodes 440 located within the same isolation opening 510 are interconnected. Each second electrode 440 of the pixel group is electrically connected to a driving circuit 210. First electrodes 420 within the pixel group are respectively connected to one of at least two power lines 220, and the voltage values ​​transmitted by the at least two first power lines 220 are different. This allows the same driving circuit 210 to drive multiple sub-pixels 410 via the second electrode 440, and allows for differentiated adjustment of the sub-pixels 410 within the pixel group 300 by adjusting the voltage value of the first electrode 420.

[0077] The second electrodes 440 between adjacent pixel groups 300 are disconnected from each other to ensure that the driving signals between sub-pixels 410 do not interfere with each other.

[0078] like Figure 12 As shown, pixel group 300 includes two sub-pixels 410, which are located within the same isolation opening 510. The second electrodes 440 of the sub-pixels 410 located within the same isolation opening 510 are connected to each other and integrally formed. The second electrodes 440 of adjacent pixel groups 300 located in the same row are disconnected from each other, that is, the second electrodes 440 of adjacent sub-pixels 410 located in different pixel groups 300 are disconnected from each other through the isolation structure 500.

[0079] like Figure 13 As shown, the display panel also includes an auxiliary connection layer 800, which is located on the side of the isolation structure 500 facing the substrate 100. The auxiliary connection layer 800 includes a plurality of auxiliary lines 830, which are arranged one-to-one with the isolation openings 510. The orthographic projection of the auxiliary lines 830 on the substrate 100 is located within the orthographic projection range of the isolation structure 500 on the substrate 100. At least a portion of the auxiliary lines 830 are exposed in the isolation openings 510. The second electrode 440 located in the same isolation opening 510 is in contact with the auxiliary lines 830.

[0080] The auxiliary line 830 can be set on any side of the isolation opening 510, or it can be set around the isolation opening 510, with the auxiliary lines 830 corresponding to adjacent isolation openings 510 being set at intervals.

[0081] In this embodiment, the display panel further includes a pixel definition layer 900, which has a plurality of pixel openings 910. The pixel openings 910 are configured in a one-to-one correspondence with the sub-pixels 410. At least some of the sub-pixels 410 are located within the pixel openings 910. The auxiliary line 830 is located on the side of the pixel definition layer 900 away from the substrate 100, and the isolation structure 500 is located on the side of the pixel definition layer 900 away from the substrate 100.

[0082] The display panel also includes a first planarization layer 700, a second planarization layer 750, and a second transition layer 620 located on the side of the driving circuit layer 200 facing away from the substrate 100. The second transition layer 620 is located on the side of the pixel definition layer 900 facing the substrate 100. The second transition layer 620 includes multiple second transition lines 621, and auxiliary lines 830 located in the same isolation opening 510 are connected to the same second transition line 621. The pixel definition layer 900 also includes multiple second vias 720, and at least two auxiliary lines 830 are connected to the second transition lines 621 through the second vias 720. The second transition lines are electrically connected to the driving circuit 210.

[0083] Furthermore, the second adapter cable 621 is electrically connected to the drive circuit 210 through a third via, which penetrates the first planarization layer 700 and the second planarization layer 750.

[0084] In one embodiment, such as Figure 14 and Figure 15 As shown, the isolation structure 500 encloses and forms multiple isolation openings 510, and the isolation openings 510 are set in a one-to-one correspondence with the sub-pixels 410. The display panel also includes an auxiliary connection layer 800 located on the side of the isolation structure 500 facing the substrate 100. The auxiliary connection layer 800 includes a plurality of auxiliary lines 830, which are arranged in a one-to-one correspondence with the sub-pixels 410. The orthographic projection of the auxiliary lines 830 on the substrate 100 is located on at least one side of the orthographic projection of the sub-pixels 410. At least a portion of the auxiliary connection lines are exposed in the isolation opening 510. The second electrode 440 is arranged in contact with the auxiliary lines 830.

[0085] The first planarization layer 700 includes multiple fourth vias 730, the second planarization layer 750 includes multiple fifth vias 740, and a third transition layer 630 is provided between the second planarization layer 750 and the first planarization layer 700. The third transition layer 630 includes multiple third transition lines 631. The auxiliary line 830 is connected to the second transition line 621 through the second via 720 penetrating the pixel definition layer 900. The second transition line 621 is connected to the third transition line 631 through the fourth via 730. The third transition line 631 is connected to the corresponding driving circuit 210 through the fifth via 740.

[0086] In this embodiment, the second adapter wire 621 is disposed on the same layer as the first electrode 420, both located in the first adapter layer 600. In other embodiments, the second adapter wire 621 may also be disposed on a different layer from the first electrode 420.

[0087] Figure 15 for Figure 14 In a cross-sectional view of the same pixel group, power line 220 includes multiple third sub-power lines 223 and fourth sub-power lines 224 located within the display area, wherein the voltage values ​​transmitted by the third sub-power lines 223 and fourth sub-power lines 224 are different. Figure 15 As shown, taking a first pixel group 310 containing two first sub-pixels 411 as an example, within the same pixel group, the first electrode 420 of one first sub-pixel 411 is connected to the third sub-power line 223 through a sixth via, and the other first electrode 420 is connected to the fourth sub-power line 224 through a seventh via. Both the sixth and seventh vias penetrate the first planarization layer 700, and may also penetrate the first planarization layer 700 and part of the driving circuit layer 200. The third sub-power line 223 and the fourth sub-power line 224 may be located in the same layer or in different layers.

[0088] Figure 16 and Figure 17 for Figure 12 , Figure 14 The connection diagram of different pixel groups shows that adjacent pixel groups 300 in the same row share the same power line 220 to reduce the number of power lines 220. Taking a pixel group 300 including two sub-pixels 410 as an example, the first pixel group 310 corresponding to the first sub-pixel 411 and the second pixel group 320 corresponding to the second sub-pixel 412 share the same first power line 221. The sub-pixels 410 within each pixel group 300 are arranged along the second direction Y, and the third sub-power line 223 and the fourth sub-power line 224 corresponding to the sub-pixel 410 are also arranged along the second direction Y. The third sub-power line 223 and the fourth sub-power line 224 both extend along the first direction X.

[0089] Figure 16 It is shown that in adjacent pixel groups 300, the first sub-pixel 411 and the second sub-pixel 412 located in the same row are connected to the same third sub-power line 223, and the first electrode 410 of the first sub-pixel 411 and the second sub-pixel 412 are connected to the same third sub-power line 223.

[0090] In the above embodiments, such as Figure 18 As shown, the display panel also includes an encapsulation layer 460, which includes various inorganic materials such as silicon nitride and silicon oxide. The encapsulation layer 460 is located on the side of the second electrode 440 away from the substrate 100, and the entire encapsulation layer 460 is provided to cover the sidewall of the isolation structure 500 facing the sub-pixel 410, as well as the side of the cover layer 450 away from the substrate 100.

[0091] Another embodiment of this application provides a display device that includes the display panel of any of the above embodiments. The display device may include a device with image processing capabilities, such as a mobile phone, desktop computer, laptop computer, tablet computer, automotive display, wearable device, etc. Because this display device includes the display panel of this application, it has better performance and higher reliability.

[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, include: substrate; A driving circuit layer, located on one side of the substrate, includes multiple driving circuits and multiple first power lines; Multiple sub-pixels are located on the side of the driving circuit layer away from the substrate. The multiple sub-pixels are arranged in an array along a first direction and a second direction. Each sub-pixel includes a first electrode, a light-emitting unit, and a second electrode. A pixel group, located on the side of the driving circuit layer facing away from the substrate, includes at least two sub-pixels with the same emission color. Each pixel group is configured in a one-to-one correspondence with the driving circuit. The pixel group is electrically connected to one of the driving circuits and at least two first power lines, wherein the voltage values ​​transmitted by the at least two power lines are different.

2. The display panel according to claim 1, characterized in that, The display panel further includes an isolation structure located on the side of the driving circuit layer away from the substrate. The extension direction of the isolation structure is perpendicular to the arrangement direction of the sub-pixels in the pixel group, and at least a portion of the second electrodes are disconnected from each other through the isolation structure. Preferably, the orthographic projection area of ​​the side of the isolation structure away from the substrate on the substrate is greater than or equal to the orthographic projection area of ​​the side of the isolation structure facing the substrate on the substrate. Preferably, the angle between the side of the isolation structure facing the pixel group and the plane where the substrate is located is less than or equal to 90°; Preferably, in the direction perpendicular to the substrate, the cross-section of the isolation structure is an inverted trapezoid; Preferably, the isolation structure includes an insulating material; Preferably, a cover layer is sequentially disposed on the side of the isolation structure away from the substrate, at least a portion of the cover layer being made of the same material as the second electrode, and the cover layer being disconnected from the adjacent second electrode at the sidewall of the isolation structure.

3. The display panel according to claim 2, characterized in that, Each of the driving circuits is electrically connected to the first electrode corresponding to at least two sub-pixels having the same emission color; Preferably, the display panel further includes a first planarization layer, a first transition layer, and a second planarization layer located on the side of the driving circuit layer opposite to the substrate. The first electrode is located on the side of the second planarization layer opposite to the substrate. The first planarization layer includes a plurality of first vias. The first transition layer includes a plurality of first connecting lines. The second planarization layer includes a plurality of second vias. The driving circuit is connected to the first connecting lines through the first vias. The first connecting lines are connected to the first electrode through at least two second vias. Preferably, the first vias corresponding to multiple pixel groups located in the same row are arranged in a row along the first direction; Preferably, in the first direction, a plurality of the first vias located in the same row are arranged at equal intervals.

4. The display panel according to claim 1, characterized in that, The number of power lines corresponding to the same pixel group is the same as the number of sub-pixels included in the pixel group; The driving circuit is electrically connected to the first electrode, and the second electrodes of the sub-pixels that are electrically connected to the driving circuit are disconnected from each other. The second electrodes are connected to the power lines, and the power lines connected to different second electrodes in the same pixel group are different. Preferably, the display panel further includes a display area and a non-display area, the sub-pixel array is arranged in the display area, the isolation structure extends from the display area to the non-display area, and the power line is located in the non-display area; Preferably, the second electrode located between two adjacent isolation structures extends from the display area to the non-display area and is connected to the power line; Preferably, the second electrodes of the multiple sub-pixels located between adjacent isolation structures are interconnected; The first power line includes at least two sub-power lines, which transmit different voltage values. The second electrodes, which are adjacent and disconnected from each other, are connected to different sub-power lines in the extension direction perpendicular to the isolation structure.

5. The display panel according to claim 2, characterized in that, The display panel further includes an auxiliary connection layer, which is located on the side of the isolation structure facing the substrate. The orthographic projection of the auxiliary connection layer on the substrate overlaps with the orthographic projection of the isolation structure on the substrate, and at least a portion of the auxiliary connection layer is located on the side of the isolation structure facing the sub-pixel. The second electrode is overlapped with the auxiliary connection layer. Preferably, the orthographic projection of the auxiliary connection layer on the substrate does not overlap with the orthographic projection of the first electrode on the substrate.

6. The display panel according to claim 5, characterized in that, The isolation structure encloses and forms multiple isolation openings, each of which exposes at least a portion of the first electrode. The auxiliary connection layer includes multiple auxiliary lines, each of which is configured to correspond one-to-one with a sub-pixel. The orthographic projection of the auxiliary line onto the substrate is located on at least one side of the orthographic projection of the sub-pixel onto the substrate. At least two auxiliary lines located within the same pixel group transmit different voltage values.

7. The display panel according to claim 1, characterized in that, The display panel further includes a pixel definition layer located on the side of the first electrode facing away from the substrate. The auxiliary connection layer and the isolation structure are located on the side of the pixel definition layer facing away from the substrate. The pixel definition layer has pixel openings, and each pixel opening corresponds to a sub-pixel. Each pixel opening exposes at least a portion of the first electrode. The orthographic projection of the pixel opening on the substrate is within the orthographic projection range of the isolation opening on the substrate. A portion of the light-emitting unit and the second electrode extend from the pixel opening to the side of the pixel definition layer facing away from the substrate.

8. The display panel according to claim 1, characterized in that, The isolation structure encloses and forms multiple isolation openings, each of which corresponds to a pixel group. At least two sub-pixels have their orthographic projections on the substrate located within the orthographic projection range of the isolation opening on the substrate. The second electrodes located within the same isolation opening are interconnected. At least two second electrodes of the pixel group are electrically connected to one of the driving circuits. The first electrodes within the pixel group are respectively connected to one of the at least two power lines. The voltage values ​​transmitted by the at least two power lines are different.

9. The display panel according to claim 1, characterized in that, The isolation structure encloses and forms multiple isolation openings, and each isolation opening is configured to correspond one-to-one with a sub-pixel. The display panel also includes an auxiliary connection layer located on the side of the isolation structure facing the substrate. The auxiliary connection layer includes a plurality of auxiliary lines, and the auxiliary lines are configured to correspond one-to-one with the sub-pixels. The orthographic projection of the auxiliary line on the substrate is located on at least one side of the orthographic projection of the sub-pixel, and at least a portion of the auxiliary line is exposed in the isolation opening; the second electrode is disposed in contact with the auxiliary connection line. Preferably, the auxiliary lines located in the same pixel group are interconnected and electrically connected to the driving circuit corresponding to the same pixel group.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

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