Display device

Abstract

The present application relates to a display device, comprising: a light emitting element layer; an encapsulation layer disposed on the light emitting element layer; and a polarizing film disposed on the encapsulation layer, the encapsulation layer comprising a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, the second inorganic encapsulation layer comprising silicon nitride (SiN x ) and having a sum of a bonding ratio of Si-N and a bonding ratio of N-H that is less than or equal to 89%.

Description

Technical Field

[0001] The implementation generally provides a display device. More specifically, the implementation relates to a display device for providing visual information and an electronic device including therein. Background Technology

[0002] With the development of information technology, display devices are playing an increasingly prominent role as a communication medium between users and information. Correspondingly, the use of display devices such as liquid crystal displays, organic light-emitting diode displays, and plasma displays is increasing.

[0003] This display device incorporates a polarizing film to reduce the reflection of external light from the front surface of the display device. Summary of the Invention

[0004] The implementation provides a display device with improved reliability.

[0005] The embodiments provide electronic devices including display devices.

[0006] In one or more embodiments of this disclosure, the display device may include: a light-emitting element layer; an encapsulation layer on the light-emitting element layer; and a polarizing film on the encapsulation layer, the encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, the second inorganic encapsulation layer including silicon nitride (SiN). x It also has a Si-N bonding ratio of less than or equal to 89% and a sum of NH bonding ratios.

[0007] In one or more embodiments of this disclosure, the electronic device may include a display device and a power module. The display device includes: a light-emitting element layer; an encapsulation layer on the light-emitting element layer; and a polarizing film on the encapsulation layer. The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer. The second inorganic encapsulation layer includes silicon nitride (SiN). x The power module includes a power supply configured to supply external power and a power converter configured to convert the external power to generate a power supply voltage provided to the display device. The power module has a Si-N bonding ratio of less than or equal to 89% and a NH bonding ratio of less than or equal to 89%. Attached Figure Description

[0008] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 A plan view illustrating a display device according to an embodiment of the present disclosure.

[0010] Figure 2To explain Figure 1 A cross-sectional view of the components of the display device.

[0011] Figure 3 To explain Figure 2 A cross-sectional view of the polarizing film assembly.

[0012] Figure 4 To explain Figure 1 A circuit diagram of the circuit structure for one pixel.

[0013] Figure 5 To explain Figure 2 A cross-sectional view of an example of region A.

[0014] Figure 6 The graph illustrates the Si-N bonding ratio, Si-H bonding ratio, and NH bonding ratio measured in the second inorganic encapsulation layer in the comparative examples and embodiments of this disclosure.

[0015] Figure 7 To explain Figure 2 A cross-sectional view of another example of region A.

[0016] Figure 8 A block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0017] Figure 9 Schematic diagrams illustrating electronic devices according to various embodiments. Detailed Implementation

[0018] The display device according to embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0019] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be perpendicular to the first direction DR1. Additionally, a third direction DR3 may be the normal direction of the plane. That is, the third direction DR3 may be perpendicular to the plane.

[0020] Figure 1 A plan view of a display device DD according to an embodiment of the present disclosure is provided.

[0021] refer to Figure 1 The display device DD according to embodiments of the present disclosure may include a display panel DP, a driver integrated circuit DIC, and a circuit board CB.

[0022] The display device DD may have a rectangular shape in a plan view (e.g., a rectangular shape with rounded corners). However, embodiments of this disclosure are not limited to this, and the display device DD may have various shapes in a plan view.

[0023] The display panel (DP) may include a display area (DA) and a peripheral area (PA). The display area (DA) is the area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area (PA) is the area that does not display an image. The peripheral area (PA) may be located around the display area (DA). For example, the peripheral area (PA) may completely surround the display area (DA).

[0024] The display panel DP may include a plurality of pixels PX arranged in the display area DA. The pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, embodiments of the present disclosure are not limited thereto, and the pixels PX may be arranged in various forms.

[0025] Each of the pixels PX may include a driving element (e.g., a driving thin-film transistor) that generates a driving current and a light-emitting element electrically connected to the driving element and generating light based on the driving current. Accordingly, the pixel PX may emit light according to the driving current. By emitting light from the pixel PX, the display area DA may display an image.

[0026] The lines connected to the pixel PX can be further positioned within the display area DA. For example, these lines may include data lines, gate signal lines, and transmit control lines.

[0027] The driver for driving the pixel PX can be located in the peripheral region PA. For example, the driver may include a gate driver and an emitter driver. The gate driver can output a gate signal (e.g., Figure 4 The first gate signal GW, the second gate signal GI, and the third gate signal GB are specified in the data. The transmit driver can output transmit control signals (e.g., ...). Figure 4 (The transmission control signal EM in the image). Pixel PX can emit light based on the signal received from the driver.

[0028] The peripheral area PA may include the pad area PDA. The pad area PDA may be located on one side of the display area DA and may extend in the first direction DR1.

[0029] The driver integrated circuit (DIC) can be combined with the pad area of ​​the display panel (DP) for the PDA. Accordingly, the driver integrated circuit (DIC) is electrically connected to the display panel (DP).

[0030] A driver integrated circuit (DIC) can convert digital data signals in a drive signal into analog data signals and provide analog data signals to the pixel (PX). For example, a driver integrated circuit (DIC) can be a data driver.

[0031] One end of the circuit board CB can be bonded to the pad area of ​​the display panel DP (PDA). Accordingly, the circuit board CB can be electrically connected to the display panel DP. The other end of the circuit board CB can be electrically connected to an external device. Signals generated by the external device (e.g., control signals, etc.) Figure 4 The transmit control signal (EM) and / or voltage (e.g., in the transmission control signal EM) and / or voltage) in the transmission control signal ... (e.g., in the transmission control signal EM) and / or voltage (e.g., in the transmission control signal EM) and / or voltage Figure 4 The driving voltage ELVDD, common voltage ELVSS, and initialization voltage VINT, etc., can be provided to the driving integrated circuit DIC and the pixel PX through the circuit board CB.

[0032] For example, the circuit board CB can be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible flat cable (FFC).

[0033] exist Figure 1 In this context, the driver integrated circuit (DIC) is described as being directly attached to the substrate of the display panel (DP) in a chip-on-plastic (COP) or chip-on-glass (COG) manner. However, the embodiments disclosed herein are not limited to this. For example, the driver integrated circuit (DIC) can be attached to a flexible film in a chip-on-film (COF) manner. In this case, one end of the flexible film can be bonded to the pad area of ​​the PDA, and the other end of the flexible film can be bonded to the circuit board (CB).

[0034] The following text will refer to Figure 2 Describe the stacking structure of the display device DD.

[0035] Figure 2 To explain Figure 1 A cross-sectional view of the components of the display device DD. Figure 3 To explain Figure 2 A cross-sectional view of the polarizing film POL assembly.

[0036] refer to Figure 2 and Figure 3 The display device DD may further include a polarizing film POL, a second adhesive layer ADL2, and a window member WN sequentially disposed on the display panel DP along a third direction DR3. Here, the display panel DP may include: a substrate SUB; a circuit layer DP-CL disposed on the substrate SUB; a light-emitting element layer DP-EL disposed on the circuit layer DP-CL; and an encapsulation layer ENC disposed on the light-emitting element layer DP-EL.

[0037] The substrate SUB can be a glass substrate, a metal substrate, or a polymer substrate. In some embodiments, the substrate SUB can be a flexible polymer substrate. However, the embodiments of this disclosure are not limited to this, and the substrate SUB can be an inorganic layer, an organic layer, or a composite material layer.

[0038] The DP-EL layer may include light-emitting elements that generate light. For example, the light-emitting elements may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic hybrid light-emitting materials, quantum dots, micro light-emitting diodes, or nano light-emitting diodes.

[0039] The encapsulation layer ENC protects the DP-EL light-emitting element layer from foreign substances such as moisture or oxygen. For example, the encapsulation layer ENC may include at least one inorganic layer and at least one organic layer. A more detailed description of the encapsulation layer ENC will be provided later.

[0040] The polarizing film POL can reduce the reflectivity of external light incident from outside the display device DD. In an embodiment, the polarizing film POL may include a first adhesive layer ADL1, a phase retardation layer PHL, a protective layer PRL, a polarizing layer PL, and a hard coating OF, which are stacked sequentially along the third direction DR3.

[0041] A hard coating OF can be applied to one surface of the polarizing layer PL. That is, the hard coating OF can be the top layer of the polarizing film POL. The hard coating OF protects the components of the polarizing film POL from external impacts. For example, the hard coating OF may include triacetyl cellulose (TAC), cyclic olefin polymers (COP), and polymethyl methacrylate (PMMA). These can be used individually or in combination. Additionally, one surface of the hard coating OF can be treated for anti-reflective, anti-glare, and / or anti-fingerprint properties.

[0042] A polarizing layer (PL) can be used to polarize incident light in the direction of the polarization axis. In embodiments, the polarizing layer (PL) may comprise polyvinyl alcohol (PVA). For example, the polarizing layer (PL) may be formed by including a polarizer and / or a dye in a film comprising PVA. The dye may comprise iodine molecules and / or dichroic dye molecules. Optionally, the polarizing layer (PL) may be formed by uniaxially stretching a film comprising PVA and immersing the film in a solution of iodine and / or a dichroic dye. In this case, the iodine molecules and / or dichroic dye molecules may be arranged parallel to the stretching direction. Because iodine molecules and dichroic dye molecules exhibit dichroism, they can absorb light vibrating in the stretching direction and transmit light vibrating in a direction perpendicular to the stretching direction.

[0043] A protective layer PRL can be disposed on the surface of the polarizing layer PL opposite to the surface of the polarizing layer PL that has a hard coating OF. The protective layer PRL can serve as a protective layer that supports the polarizing layer PL and supplements the mechanical strength of the polarizing layer PL. For example, the protective layer PRL may include triacetyl cellulose (TAC), cyclic olefin polymer (COP), and polymethyl methacrylate (PMMA), etc. These can be used alone or in combination with each other. In an embodiment, the protective layer PRL may include triacetyl cellulose.

[0044] A phase retardation layer (PHL) can be disposed on the surface of a protective layer (PRL) opposite to the surface of the protective layer PRL where a polarizing layer (PL) is disposed. The phase retardation layer (PHL) can alter the phase of light. Specifically, the phase retardation layer (PHL) can delay the phase of linearly polarized light from the polarizing layer (PL) and change the polarization state of the linearly polarized light to elliptical or circular polarization. For example, the phase retardation layer (PHL) may include a half-wave plate (HWP) with a λ / 2 characteristic and / or a quarter-wave plate (QWP) with a λ / 4 characteristic, where λ is the wavelength of the light used. The half-wave plate can be a film type or a liquid crystal coating type, and the quarter-wave plate can also be a film type or a liquid crystal coating type.

[0045] The first adhesive layer ADL1 may be disposed on the surface of the phase retardation layer PHL opposite to the surface of the phase retardation layer PHL where the protective layer PRL is disposed. That is, the first adhesive layer ADL1 may be disposed as the bottom layer of the polarizing film POL. The polarizing film POL may be attached to the display panel DP via the first adhesive layer ADL1. Specifically, the polarizing film POL may be attached to the encapsulation layer ENC of the display panel DP via the first adhesive layer ADL1. For example, the first adhesive layer ADL1 may include a pressure-sensitive adhesive (PSA), an optically clear adhesive (OCA), or an optically clear resin (OCR). In an embodiment, the first adhesive layer ADL1 may include a pressure-sensitive adhesive. The pressure-sensitive adhesive may include a polymer curing material. For example, the pressure-sensitive adhesive may include an acrylic resin with acrylic acid as the main component. Acrylic acid may constitute the majority of the components of the acrylic resin.

[0046] The window member WN may be attached to the polarizing film POL via a second adhesive layer ADL2. The window member WN may include a base film comprising a glass film or a synthetic resin film. The window member WN may further include an anti-reflective layer or an anti-fingerprint layer. For example, the second adhesive layer ADL2 may include a pressure-sensitive adhesive, an optically clear adhesive, or an optically clear resin. In an embodiment, the second adhesive layer ADL2 may include a pressure-sensitive adhesive.

[0047] Figure 4 To explain Figure 1 A circuit diagram of the circuit structure of a pixel PX.

[0048] refer to Figure 4 Each pixel PX may include a pixel driving circuit section PC and a light-emitting element LED electrically connected to the pixel driving circuit section PC. The pixel driving circuit section PC can generate a driving current IOLED, and the light-emitting element LED can generate light based on the driving current IOLED.

[0049] For example, the pixel driving circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor CST.

[0050] For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be PMOS transistors. However, the embodiments of this disclosure are not limited to this, and some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be NMOS transistors, and the remainder can be PMOS transistors.

[0051] The pixel driving circuit PC may include NMOS transistors and PMOS transistors. The active pattern of the NMOS transistor may include metal-oxide-semiconductor, and the active pattern of the PMOS transistor may include silicon semiconductor. However, embodiments of this disclosure are not limited thereto, and the active pattern of the NMOS transistor may include silicon semiconductor, and the active pattern of the PMOS transistor may include metal-oxide-semiconductor.

[0052] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2. The second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 can provide a driving current IOLED to a light-emitting element LED. The first transistor T1 may be referred to as a driving transistor.

[0053] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. A first gate signal GW may be applied to the gate electrode of the second transistor T2. A data voltage DATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to a second node N2.

[0054] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the first gate signal GW has an active level, the second transistor T2 can be turned on. In this case, the second transistor T2 can provide the data voltage DATA to the second node N2. Conversely, when the first gate signal GW has an inactive level, the second transistor T2 can be turned off. In this case, the second transistor T2 can block the supply of the data voltage DATA.

[0055] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. A first gate signal GW may be applied to the gate electrode of the third transistor T3. The first electrode of the third transistor T3 may be connected to the third node N3. The second electrode of the third transistor T3 may be connected between the first node N1 and the second electrode of the fourth transistor T4.

[0056] The third transistor T3 can be turned on or off in response to the first gate signal GW. For example, when the first gate signal GW has an active level, the third transistor T3 can be turned on. In this case, the third transistor T3 can cause the first transistor T1 to be diode-connected. That is, the third transistor T3 can compensate for the threshold voltage of the first transistor T1. Conversely, when the first gate signal GW has an inactive level, the third transistor T3 can be turned off. In this case, the first transistor T1 may not be diode-connected.

[0057] The fourth transistor T4 may include a gate electrode, a first electrode, and a second electrode. A second gate signal GI may be applied to the gate electrode of the fourth transistor T4. An initialization voltage VINT may be applied to the first electrode of the fourth transistor T4. The second electrode of the fourth transistor T4 may be connected to the second electrode of the third transistor T3.

[0058] The fourth transistor T4 can be turned on or off in response to the second gate signal GI. For example, when the second gate signal GI has an active level, the fourth transistor T4 can be turned on. In this case, the fourth transistor T4 can provide the initialization voltage VINT to the second electrode of the third transistor T3. Conversely, when the second gate signal GI has an inactive level, the fourth transistor T4 can block the supply of the initialization voltage VINT.

[0059] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. A transmit control signal EM may be applied to the gate electrode of the fifth transistor T5. A drive voltage ELVDD may be applied to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 may be connected to the second node N2.

[0060] The sixth transistor T6 may include a gate electrode, a first electrode, and a second electrode. A transmit control signal EM may be applied to the gate electrode of the sixth transistor T6. The first electrode of the sixth transistor T6 may be connected to the third node N3. The second electrode of the sixth transistor T6 may be connected to the second electrode of the seventh transistor T7.

[0061] The fifth transistor T5 and the sixth transistor T6 can be turned on or off in response to the emission control signal EM. For example, when the emission control signal EM has an active level, the fifth transistor T5 and the sixth transistor T6 can be turned on. In this case, the fifth transistor T5 and the sixth transistor T6 can supply the driving current IOLED generated by the first transistor T1 to the anode electrode of the light-emitting element LED. Conversely, when the emission control signal EM has an inactive level, the fifth transistor T5 and the sixth transistor T6 can block the supply of the driving current IOLED generated by the first transistor T1.

[0062] The seventh transistor T7 may include a gate electrode, a first electrode, and a second electrode. A third gate signal GB may be applied to the gate electrode of the seventh transistor T7. An initialization voltage VINT may be applied to the first electrode of the seventh transistor T7. The second electrode of the seventh transistor T7 may be connected to the second electrode of the sixth transistor T6.

[0063] The seventh transistor T7 can be turned on or off in response to the third gate signal GB. For example, when the third gate signal GB has an active level, the seventh transistor T7 can be turned on. In this case, the seventh transistor T7 can provide the initialization voltage VINT to the anode electrode of the light-emitting element LED. Conversely, when the third gate signal GB has an inactive level, the seventh transistor T7 can block the supply of the initialization voltage VINT.

[0064] In one embodiment, the first electrode of each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 can be a source electrode, and the second electrode of each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 can be a drain electrode. However, the embodiments of this disclosure are not limited to this. The first electrode of at least one of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 can be a drain electrode, and the first electrodes of the remaining first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 can be source electrodes.

[0065] The storage capacitor CST may include a first electrode and a second electrode. A drive voltage ELVDD may be applied to the first electrode of the storage capacitor CST. The second electrode of the storage capacitor CST may be connected to a first node N1.

[0066] The light-emitting element (LED) may include an anode electrode and a cathode electrode. The anode electrode of the LED may be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. A common voltage ELVSS may be applied to the cathode electrode of the LED. The common voltage ELVSS may have a lower voltage level than the drive voltage ELVDD.

[0067] although Figure 4 The illustration describes a pixel driving circuit PC comprising seven transistors and one capacitor, but embodiments of this disclosure are not limited thereto.

[0068] Figure 5 To explain Figure 2 A cross-sectional view of an example of region A.

[0069] refer to Figure 5 As described above, the display panel DP may include: a substrate SUB; a circuit layer DP-CL disposed on the substrate SUB; a light-emitting element layer DP-EL disposed on the circuit layer DP-CL; and an encapsulation layer ENC disposed on the light-emitting element layer DP-EL. Here, the circuit layer DP-CL may include a buffer layer BFR, a transistor TR, a gate insulating layer GIL, a sandwich insulating layer ILD, and a via insulating layer VIA, and the light-emitting element layer DP-EL may include a pixel defining layer PDL and a light-emitting element LED.

[0070] A buffer layer (BFR) can be disposed on the substrate SUB. The buffer layer BFR prevents metal atoms or impurities from diffusing from the substrate SUB into the transistor TR. Additionally, if the surface of the substrate SUB is uneven, the buffer layer BFR can improve the surface flatness of the substrate SUB. For example, the buffer layer BFR may comprise an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon carbide (SiC) x ) and silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. Buffer layers (BFRs) can have a single-layer structure or a multi-layer structure in which multiple layers are stacked.

[0071] An active pattern (ACT) may be disposed on a buffer layer (BFR). The active pattern (ACT) may include a metal-oxide-semiconductor (MODS), an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), or an organic semiconductor. The active pattern (ACT) may include a source region, a drain region, and a channel region located between the source and drain regions.

[0072] For example, metal oxide semiconductors may include zinc oxide (e.g., ZnO or ZnO2), gallium oxide (GaO) x ), tin oxide (SnO x Indium oxide (InO) x Indium gallium oxide (IGO), indium zinc oxide (IZO), indium tin oxide (ITO), indium zinc tin oxide (IZTO), and indium gallium zinc oxide (IGZO), etc. These can be used individually or in combination with each other.

[0073] A gate insulating layer (GIL) may be disposed on the buffer layer (BFR). The GIL may be sufficiently large to cover the active pattern ACT and may have a substantially flat upper surface without creating steps around the active pattern ACT. Optionally, the GIL may cover the active pattern ACT and be disposed with a uniform thickness along the contour of the active pattern ACT. For example, the GIL may comprise an inorganic insulating material, such as silicon oxide (SiO2). x), silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) and silicon dioxide (SiO2) x C y These can be used individually or in combination with each other. The gate insulation layer (GIL) can have a single-layer structure or a multi-layer structure in which multiple layers are stacked.

[0074] The gate electrode (GAT) can be disposed on the gate insulating layer (GIL). The gate electrode (GAT) can overlap with the channel region of the active pattern (ACT) in a planar view. The gate electrode (GAT) can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. Examples of metals include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), and scandium (Sc). Examples of conductive metal oxides and transparent conductive materials include indium tin oxide and indium zinc oxide. Examples of metal nitrides include aluminum nitride (AlN). x ), tungsten nitride (WN) x ) and chromium nitrides (CrN) x These can be used individually or in combination with each other. The gate electrode (GAT) can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0075] A sandwich insulating layer (ILD) may be disposed on the gate insulating layer (GIL). The sandwich insulating layer (ILD) may completely or sufficiently cover the gate electrode (GAT) and have a substantially flat upper surface without creating steps around the gate electrode (GAT). Optionally, the sandwich insulating layer (ILD) may cover the gate electrode (GAT) and be disposed with a uniform thickness along the contour of the gate electrode (GAT). For example, the sandwich insulating layer (ILD) may comprise inorganic insulating materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, and silicon carbide. These may be used individually or in combination with each other. The sandwich insulating layer (ILD) may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0076] The source electrode SE and drain electrode DE can be disposed on the interlayer insulating layer ILD. The source electrode SE can be connected to the source region of the active pattern ACT through contact holes penetrating the gate insulating layer GIL and the first portion of the interlayer insulating layer ILD. The drain electrode DE can be connected to the drain region of the active pattern ACT through contact holes penetrating the gate insulating layer GIL and the second portion of the interlayer insulating layer ILD. For example, each of the source electrode SE and drain electrode DE may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. These can be used individually or in combination. Each of the source electrode SE and drain electrode DE may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0077] Accordingly, a transistor TR, including an active pattern ACT, a gate electrode GAT, a source electrode SE, and a drain electrode DE, can be formed in the display area DA and on the substrate SUB.

[0078] A via insulating layer (VIA) may be disposed on the interlayer insulating layer (ILD). The via insulating layer (VIA) may be sufficiently covering the source electrode (SE) and the drain electrode (DE). The via insulating layer (VIA) may include organic insulating materials. For example, the via insulating layer (VIA) may include organic insulating materials such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, silicone resin, and epoxy resin. These may be used alone or in combination with each other. The via insulating layer (VIA) may have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0079] The anode electrode ADE can be disposed on the through-hole insulating layer VIA. The anode electrode ADE can be connected to the drain electrode DE (or source electrode SE) through a contact hole penetrating the through-hole insulating layer VIA. The anode electrode ADE can be a transmission electrode, a semi-transmission electrode, or a reflection electrode.

[0080] For example, the anode electrode ADE may include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These can be used individually or in combination with each other. In one embodiment, the anode electrode ADE may have a stacked structure composed of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO). However, embodiments of this disclosure are not limited to this.

[0081] A pixel defining layer (PDL) may be disposed on the via insulating layer (VIA). The PDL may cover the edge of the anode electrode (ADE). A pixel opening may be defined in the PDL, exposing at least a portion of the upper surface of the anode electrode (ADE). For example, the PDL may comprise inorganic and / or organic insulating materials. In one embodiment, the PDL may comprise organic insulating materials such as phenolic resin, polyacrylate resin, polyimide resin, polyamide resin, epoxy resin, and silicone resin. These may be used alone or in combination with each other. In another embodiment, the PDL may comprise inorganic and / or organic insulating materials containing a light-shielding material such as a black pigment or black dye.

[0082] The light-emitting layer EL can be disposed on the anode electrode ADE. Specifically, the light-emitting layer EL can be disposed in the pixel opening of the pixel defining layer PDL. The light-emitting layer EL can include a light-emitting material (e.g., an organic light-emitting material or an inorganic light-emitting material) that emits light of a predetermined color. For example, the light-emitting layer EL can include a light-emitting material that emits red light, green light, or blue light.

[0083] The cathode electrode (CTE) can be disposed on the pixel defining layer (PDL) and the light-emitting layer (EL). The cathode electrode (CTE) can be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. For example, the cathode electrode (CTE) can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These can be used individually or in combination. The cathode electrode (CTE) can have a single-layer structure or a multilayer structure in which multiple layers are stacked.

[0084] Accordingly, a light-emitting element (LED), comprising an anode electrode (ADE), a light-emitting layer (EL), and a cathode electrode (CTE), can be formed in the display area (DA) on the substrate (SUB). The LED can be electrically connected to a transistor (TR). Accordingly, the LED can receive a drive signal from the transistor TR and generate light based on the drive signal.

[0085] The encapsulation layer ENC can be disposed on the cathode electrode CTE. In an embodiment, the encapsulation layer ENC may include: a first inorganic encapsulation layer IEL1; an organic encapsulation layer OEL disposed on the first inorganic encapsulation layer IEL1; and a second inorganic encapsulation layer IEL2 disposed on the organic encapsulation layer OEL.

[0086] The first inorganic encapsulation layer IEL1 may include a silicon compound. For example, the first inorganic encapsulation layer IEL1 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. In an embodiment, the first inorganic encapsulation layer IEL1 may include silicon nitride (SiN). x However, the embodiments disclosed herein are not limited thereto.

[0087] In embodiments, the refractive index of the first inorganic encapsulation layer IEL1 may be in the range of about 1.88 to about 1.90. Preferably, the refractive index of the first inorganic encapsulation layer IEL1 may be about 1.89. However, embodiments of this disclosure are not limited to this. In this disclosure, the expression "about A" may indicate a value in the range from A minus a predetermined margin (e.g., 5% of A) to A plus the same margin.

[0088] For example, the first inorganic encapsulation layer IEL1 can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process. However, embodiments of this disclosure are not limited to this.

[0089] Organic encapsulation layers (OELs) may have a substantially flat upper surface. For example, an organic encapsulation layer (OEL) may comprise a polymer-cured material, such as polyacrylate. However, embodiments of this disclosure are not limited to this. For example, an organic encapsulation layer (OEL) may be formed by supplying organic materials using an inkjet printing process. However, embodiments of this disclosure are not limited to this.

[0090] The second inorganic encapsulation layer IEL2 may include a silicon compound. For example, the second inorganic encapsulation layer IEL2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. In an embodiment, the second inorganic encapsulation layer IEL2 may include silicon nitride (SiN). x (For example, H:SiN) x or hydrogenated SiN x ).

[0091] For example, the second inorganic encapsulation layer IEL2 can be formed by a plasma-enhanced chemical vapor deposition (PECVD) process. However, the embodiments disclosed herein are not limited to this.

[0092] In the implementation, when the second inorganic encapsulation layer IEL2 includes silicon nitride (SiN) x In this case, the sum of the Si-N bonding ratio and the NH bonding ratio in the second inorganic encapsulation layer IEL2 can be about 89% or less. Preferably, the sum of the Si-N bonding ratio and the NH bonding ratio in the second inorganic encapsulation layer IEL2 can be in the range of about 80% or more and about 89% or less. In this case, the Si-N bonding ratio in the second inorganic encapsulation layer IEL2 can be in the range of about 85% or more and about 86% or less. In addition, the Si-H bonding ratio in the second inorganic encapsulation layer IEL2 can be in the range of about 11% or more and about 20% or less. Preferably, the Si-H bonding ratio in the second inorganic encapsulation layer IEL2 can be in the range of about 11% or more and about 12% or less.

[0093] The plasma-enhanced chemical vapor deposition process used to form the second inorganic encapsulation layer IEL2 may use reactive gases including hydrogen (H2), nitrogen (N2), ammonia (NH3), and silane (SiH4). The Si-N bonding ratio, NH bonding ratio, and Si-H bonding ratio in the second inorganic encapsulation layer IEL2 can be controlled by adjusting the flow rates of hydrogen (H2), nitrogen (N2), ammonia (NH3), and silane (SiH4).

[0094] When the sum of the Si-N bonding ratio and the NH bonding ratio in the second inorganic encapsulation layer IEL2 exceeds approximately 89%, the silicon nitride in the second inorganic encapsulation layer IEL2 can react with moisture due to external permeation to generate ammonia (NH3), and the ammonia (NH3) can react with carboxylic acids (e.g., acrylic acid) in the first adhesive layer ADL1 to form ammonium ions (NH4+). + Ammonium ions (NH4+) generated inside the first adhesive layer ADL1 + The polarizing layer PL can be moved to the polarizing film POL. In this case, the polarizing layer PL may change color. If the polarizing layer PL changes color, the performance, durability, and lifespan of the polarizing film POL may deteriorate.

[0095] Here, the Si-N bonding ratio in the second inorganic encapsulation layer IEL2 can refer to the ratio of the number of Si atoms bonded to N atoms in the second inorganic encapsulation layer IEL2 to the total number of Si-N bonds, Si-H bonds, and NH bonds. The NH bonding ratio in the second inorganic encapsulation layer IEL2 can refer to the ratio of the number of N atoms bonded to H atoms and H2 in the second inorganic encapsulation layer IEL2 to the total number of Si-N bonds, Si-H bonds, and NH bonds. That is, in this specification, the NH bonding ratio can include both the NH bonding ratio and the N-H2 bonding ratio. Furthermore, the Si-H bonding ratio in the second inorganic encapsulation layer IEL2 can refer to the ratio of the number of Si atoms bonded to H atoms in the second inorganic encapsulation layer IEL2 to the total number of Si-N bonds, Si-H bonds, and NH bonds.

[0096] In embodiments, the refractive index of the second inorganic encapsulation layer IEL2 may be in the range of about 1.88 to about 1.90. Preferably, the refractive index of the second inorganic encapsulation layer IEL2 may be about 1.89. That is, the refractive index of the second inorganic encapsulation layer IEL2 may be substantially the same as the refractive index of the first inorganic encapsulation layer IEL1. In this disclosure, the expression "A and B are substantially the same" means that the absolute value of the difference between A and B is less than a predetermined percentage (e.g., 5%) of A or B, or less than a predetermined percentage (e.g., 5%) of the average value of A and B. However, embodiments of this disclosure are not necessarily limited to this.

[0097] Figure 6 A graph illustrating the Si-N bonding ratio, Si-H bonding ratio, and NH bonding ratio measured in the second inorganic encapsulation layer IEL2 in the comparative examples and embodiments of this disclosure.

[0098] refer to Figure 5 and Figure 6In the comparative example, the second inorganic encapsulation layer IEL2 was formed using silicon nitride, and the measured refractive index of the second inorganic encapsulation layer IEL2 was approximately 1.86. Furthermore, in the central portion of the second inorganic encapsulation layer IEL2, the measured Si-N bonding ratio was approximately 86.68%, the measured Si-H bonding ratio was approximately 9.47%, and the measured NH bonding ratio was approximately 3.85%. At the edge portion of the second inorganic encapsulation layer IEL2, the measured Si-N bonding ratio was approximately 86.01%, the measured Si-H bonding ratio was approximately 10.11%, and the measured NH bonding ratio was approximately 3.88%.

[0099] In this embodiment, the second inorganic encapsulation layer IEL2 is formed using silicon nitride, and the measured refractive index of the second inorganic encapsulation layer IEL2 is approximately 1.89. Furthermore, in the central portion of the second inorganic encapsulation layer IEL2, the measured Si-N bonding ratio is approximately 85.03%, the measured Si-H bonding ratio is approximately 11.21%, and the measured NH bonding ratio is approximately 3.75%. At the edge portion of the second inorganic encapsulation layer IEL2, the measured Si-N bonding ratio is approximately 85.01%, the measured Si-H bonding ratio is approximately 11.18%, and the measured NH bonding ratio is approximately 3.81%.

[0100] The bonding ratio within the second inorganic encapsulation layer IEL2, which includes silicon nitride, was measured using Fourier transform infrared spectroscopy (FT-IR).

[0101] As a result, it was confirmed that when the sum of the Si-N bonding ratio and the NH bonding ratio in the second inorganic encapsulation layer IEL2, which includes silicon nitride and contacts the first adhesive layer ADL1 to attach or bond the polarizing film POL to the encapsulation layer ENC, exceeds approximately 89%, the polarizing film POL discolors due to external moisture penetration. On the other hand, when the sum of the Si-N bonding ratio and the NH bonding ratio in the second inorganic encapsulation layer IEL2, which includes silicon nitride and contacts the first adhesive layer ADL1 to attach or bond the polarizing film POL to the encapsulation layer ENC, is approximately 89% or less, discoloration of the polarizing film POL due to external moisture penetration can be minimized or prevented.

[0102] Figure 7 To explain Figure 2 A cross-sectional view of another example of region A.

[0103] refer to Figure 2 and Figure 7The display device DD may include a display panel DP, a polarizing film POL, a second adhesive layer ADL2, and a window member WN. The display panel DP may include a substrate SUB, a circuit layer DP-CL, a light-emitting element layer DP-EL, and a packaging layer ENC. Here, the circuit layer DP-CL may include a buffer layer BFR, a transistor TR, a gate insulating layer GIL, a sandwich insulating layer ILD, and a through-hole insulating layer VIA, and the light-emitting element layer DP-EL may include a pixel defining layer PDL and a light-emitting element LED.

[0104] However, reference Figure 7 The described display device DD can be compared with the reference. Figure 5 The described display device DD is essentially the same as or similar to the original, and is for reference only. Figure 7 The described display device DD further includes an antioxidant layer OPL. Any repetitive descriptions will be omitted or simplified below.

[0105] The encapsulation layer ENC may include: a first inorganic encapsulation layer IEL1; an organic encapsulation layer OEL disposed on the first inorganic encapsulation layer IEL1; and a second inorganic encapsulation layer IEL2 disposed on the organic encapsulation layer OEL.

[0106] For example, the first inorganic encapsulation layer IEL1 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. In an embodiment, the first inorganic encapsulation layer IEL1 may include silicon nitride (SiN). x However, the embodiments disclosed herein are not limited thereto.

[0107] For example, the second inorganic encapsulation layer IEL2 may include silicon oxide (SiO2). x ), silicon nitride (SiN) x ) and silicon oxynitride (SiO) x N y These can be used individually or in combination with each other. In an embodiment, the second inorganic encapsulation layer IEL2 may include silicon nitride (SiN). x ).

[0108] In the implementation, when the second inorganic encapsulation layer IEL2 includes silicon nitride (SiN) xWhen the bonding ratio of Si-N and NH in the second inorganic encapsulation layer IEL2 is approximately 89% or less, the sum of these bonding ratios can be approximately 89% or less. In this case, the bonding ratio of Si-N in the second inorganic encapsulation layer IEL2 can be in the range of approximately 85% or more and approximately 86% or less. Additionally, the bonding ratio of Si-H in the second inorganic encapsulation layer IEL2 can be in the range of approximately 11% or more and approximately 20% or less. However, embodiments of this disclosure are not limited to these, and when the display device DD satisfies... Figure 7 The implementation method and the second inorganic encapsulation layer IEL2 include silicon nitride (SiN). x When the bonding ratios of Si-N, NH and Si-H in the second inorganic encapsulation layer IEL2 do not meet the above ranges.

[0109] In an embodiment, the display device DD may further include an antioxidant layer OPL disposed between the encapsulation layer ENC and the first adhesive layer ADL1, and comprising an insulating material. Specifically, the antioxidant layer OPL may be disposed between the second inorganic encapsulation layer IEL2 and the first adhesive layer ADL1. That is, the antioxidant layer OPL may directly contact the second inorganic encapsulation layer IEL2 and directly contact the first adhesive layer ADL1. In this case, the second inorganic encapsulation layer IEL2 may indirectly contact the first adhesive layer ADL1 via the intervening antioxidant layer OPL. Accordingly, the generation of ammonium ions (NH4+) inside the first adhesive layer ADL1 due to external moisture penetration can be suppressed. + As a result, the polarizing film POL can be prevented from discoloring due to the penetration of external moisture.

[0110] In one embodiment, the antioxidant layer OPL may include an organic insulating material. In another embodiment, the antioxidant layer OPL may include silicon oxide (SiO2). x ).

[0111] Figure 8 A block diagram illustrating an electronic device 10 according to an embodiment of the present disclosure.

[0112] refer to Figure 8 The electronic device 10 according to embodiments of the present disclosure may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0113] A display device according to embodiments of the present disclosure (e.g., Figure 1 The display device (DD) can be applied to various electronic devices. The electronic device 10 may include the aforementioned display device, and in addition to the aforementioned display device, may further include modules or devices with other functions.

[0114] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0115] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application program stored in the memory 13, the processor 12 can transmit image data signals and / or input control signals to the display module 11, and the display module 11 can process the received signals and output image information through the display screen. The display module 11 may include, but is not limited to, organic light-emitting diodes (e.g., quantum dot organic light-emitting diodes), micro light-emitting diodes, nano light-emitting diodes, and / or liquid crystals.

[0116] The power module 14 may include: a power source that supplies external power, such as a power adapter or battery device; and a power converter that converts the external power supplied by the power source to generate the power supply voltage required for the operation of the electronic device 10 (e.g., ...). Figure 4 The driving voltage ELVDD and the common voltage ELVSS in the power supply (i.e., the power supply voltage generated by the power converter can be provided to the display area). Figure 1 The display area DA in the middle.

[0117] At least one of the components of the electronic device 10 described above may be included in the display device according to the above embodiment. Additionally, some of the individual modules functionally included in a single module may be included in the display device according to the above embodiment, and other parts may be provided separately from the display device according to the above embodiment. For example, the display device according to the above embodiment may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided in the form of other devices within the electronic device 10 besides the display device according to the above embodiment.

[0118] Figure 9 Schematic diagrams illustrating electronic devices according to various embodiments.

[0119] refer to Figure 8 and Figure 9The various electronic devices 10 using the display device according to the embodiments may include image display electronic devices (such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e). The embodiments can also be applied to: wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c), or automotive electronic devices 10_3 including display modules (such as in-vehicle mirror displays and central information displays (CIDs) installed on the dashboard, center console, and instrument panel of a vehicle).

[0120] In one or more embodiments of this disclosure, the display device may include: a light-emitting element layer; an encapsulation layer on the light-emitting element layer; and a polarizing film on the encapsulation layer, the encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer, the second inorganic encapsulation layer including silicon nitride (SiN). x It also has a Si-N bonding ratio of less than or equal to 89% and a NH bonding ratio of 89%.

[0121] In the second inorganic encapsulation layer, the Si-N bonding ratio is greater than or equal to 85% and less than or equal to 86%.

[0122] The Si-H bonding ratio in the second inorganic encapsulation layer is greater than or equal to 11% and less than or equal to 12%.

[0123] The refractive index of the second inorganic encapsulation layer is greater than or equal to 1.88 and less than or equal to 1.90.

[0124] The refractive index of the first inorganic encapsulation layer is equal to the refractive index of the second inorganic encapsulation layer.

[0125] The polarizing film may include: a phase retardation layer on the encapsulation layer; an adhesive layer between the encapsulation layer and the phase retardation layer, and attaching the encapsulation layer and the phase retardation layer; a protective layer on the phase retardation layer; and a polarizing layer on the protective layer.

[0126] The adhesive layer may include pressure-sensitive adhesive (PSA).

[0127] Pressure-sensitive adhesives may include acrylic resins, and acrylic resins may include acrylic acid as a main component.

[0128] The protective layer may include triacetylcellulose (TAC).

[0129] The polarizing layer may include polyvinyl alcohol (PVA).

[0130] The second inorganic encapsulation layer of the encapsulation layer can indirectly contact the polarizing film.

[0131] The display device may further include an antioxidant layer between the encapsulation layer and the polarizing film, the antioxidant layer comprising an insulating material.

[0132] The antioxidant layer may include organic insulating materials.

[0133] Antioxidant layers may include silicon oxide (SiO2) x ).

[0134] The first inorganic encapsulation layer may include silicon nitride.

[0135] In one or more embodiments of this disclosure, the electronic device may include a display device and a power module. The display device includes: a light-emitting element layer; an encapsulation layer on the light-emitting element layer; and a polarizing film on the encapsulation layer. The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer on the first inorganic encapsulation layer, and a second inorganic encapsulation layer on the organic encapsulation layer. The second inorganic encapsulation layer includes silicon nitride (SiN). x The power module includes a power supply configured to supply external power and a power converter configured to convert the external power to generate a power supply voltage supplied to the display device, having a Si-N bonding ratio of less than or equal to 89% and a NH bonding ratio of less than or equal to 89%.

[0136] In the second inorganic encapsulation layer, the Si-N bonding ratio is greater than or equal to 85% and less than or equal to 86%.

[0137] The Si-H bonding ratio in the second inorganic encapsulation layer is greater than or equal to 11% and less than or equal to 12%.

[0138] An electronic device according to an embodiment of the present disclosure, wherein the refractive index of the second inorganic encapsulation layer is greater than or equal to 1.88 and less than or equal to 1.90.

[0139] The polarizing film may include: a phase retardation layer on the encapsulation layer; an adhesive layer between the encapsulation layer and the phase retardation layer, and attaching the encapsulation layer and the phase retardation layer; a protective layer on the phase retardation layer; and a polarizing layer on the protective layer.

[0140] As described above, although this disclosure has been explained with reference to embodiments, those skilled in the art will understand that various modifications and changes may be made to this disclosure without departing from the spirit and scope of this disclosure as defined in the claims.

[0141] This disclosure is applicable to a variety of electronic devices that can be equipped with a display device. For example, this disclosure is applicable to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and laptop computers.

Claims

1. A display device, comprising: Light-emitting element layer; An encapsulation layer, on the light-emitting element layer, the encapsulation layer comprising: First inorganic encapsulation layer; An organic encapsulation layer is placed on the first inorganic encapsulation layer; and A second inorganic encapsulation layer, on top of the organic encapsulation layer, comprises silicon nitride and has a Si-N bonding ratio of less than or equal to 89% and an NH bonding ratio of the sum of the two; and A polarizing film is placed on the encapsulation layer.

2. The display device according to claim 1, wherein the Si-N bonding ratio in the second inorganic encapsulation layer is greater than or equal to 85% and less than or equal to 86%.

3. The display device according to claim 1, wherein the Si-H bonding ratio in the second inorganic encapsulation layer is greater than or equal to 11% and less than or equal to 12%.

4. The display device according to claim 1, wherein the refractive index of the second inorganic encapsulation layer is greater than or equal to 1.88 and less than or equal to 1.

90.

5. The display device according to claim 1, wherein the refractive index of the first inorganic encapsulation layer is equal to the refractive index of the second inorganic encapsulation layer.

6. The display device according to claim 1, wherein the polarizing film comprises: A phase delay layer is provided on the encapsulation layer; An adhesive layer is provided between the encapsulation layer and the phase retardation layer, and is attached to the encapsulation layer and the phase retardation layer. A protective layer is provided on the phase delay layer. as well as A polarizing layer is located on the protective layer.

7. The display device according to claim 1, wherein the second inorganic encapsulation layer of the encapsulation layer indirectly contacts the polarizing film.

8. The display device according to claim 7, further comprising: An antioxidant layer is provided between the encapsulation layer and the polarizing film, and the antioxidant layer includes an insulating material.

9. The display device according to claim 8, wherein the antioxidant layer comprises an organic insulating material.

10. The display device according to claim 8, wherein the antioxidant layer comprises silicon oxide.

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