A test structure and a test method
By setting up common transistor arrays and virtual transistor arrays in the CMOS image sensor, combined with negative scanning and current-voltage curve monitoring, the impact of plasma processes on DINU was resolved, enabling early warning and cost control.
Patent Information
- Application Number
- CN202610772634.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-29
- Publication Date
- 2026-08-25
AI Technical Summary
Existing technologies cannot effectively monitor the impact of plasma processes on the dark current nonuniformity (DINU) of CMOS image sensors, resulting in the inability to detect problems in advance during production and increasing costs.
A test structure is provided that connects the gate layers of multiple transistors in a transistor array together and sets up a virtual transistor array around it. The charge in the gate oxide layer is monitored by combining negative scanning and drain current-gate voltage curves, and the charge trapping situation is determined by using the linear region threshold voltage.
This technology enables early detection of the impact of plasma on DINU during the production process, allowing for early warning and control, and reducing costs.
Smart Images
Figure CN122641313A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a test structure and test method. Background Technology
[0002] In a CMOS image sensor (CIS), even without light, pixels generate weak signals due to "dark current." If the dark current of each pixel is not uniform, it will create fixed noise in the image, affecting image quality. This phenomenon of uneven dark current among pixels is called dark current non-uniformity (DINU). It is an important performance parameter of the entire pixel array in a CMOS image sensor and a key parameter for measuring the quality of a CMOS image sensor, reflecting the degree of non-uniformity of the dark current.
[0003] The presence of gate oxide gate oxide (DINU) directly affects the signal-to-noise ratio and image quality of a chip image sensor (CIS). The plasma process used in chip manufacturing can easily generate a "charging effect," damaging the gate oxide layer on the chip. This damage directly leads to a deterioration in DINU. Therefore, in applications requiring high-quality image output (such as photography and security monitoring), monitoring the potential impact of the charging effect generated by plasma during the manufacturing process on DINU is crucial. Currently, there are no suitable wafer acceptance test (WAT) parameters to monitor the impact of the charging effect on the gate oxide layer. Therefore, it is impossible to detect the impact of on-line plasma on DINU in advance. Monitoring can only be done through chip probing (CP), which results in late detection and high costs. Summary of the Invention
[0004] The purpose of this application is to provide a test structure and test method to detect the impact of online plasma on DINU in advance (during the production process), thereby achieving early warning and control and reducing costs.
[0005] To address the aforementioned technical problems, this application provides a test structure, comprising:
[0006] A transistor array, located on a substrate, includes a plurality of transistors, said transistors comprising:
[0007] A gate oxide layer is located on the substrate;
[0008] The gate layer is located on the gate oxide layer;
[0009] The gate layers of the plurality of transistors are connected in common.
[0010] Furthermore, the number of transistors in the transistor array is 2 to 6.
[0011] Furthermore, it also includes:
[0012] A virtual transistor array, located around the transistor array, and comprising multiple virtual transistors, the structure of the virtual transistor array being identical to that of the transistor array.
[0013] Furthermore, the transistor and the virtual transistor include a PMOS transistor.
[0014] Furthermore, it also includes:
[0015] A gate layer connection line is located on the gate layer, and the gate layers of the plurality of transistors are connected together through the gate layer connection line.
[0016] Furthermore, it also includes:
[0017] The well region is located within the substrate.
[0018] Furthermore, the transistor also includes:
[0019] The source region is located within the well region;
[0020] The drain region is located within the well region;
[0021] The body region is located within the well region.
[0022] To address the aforementioned technical problems, this application also provides a testing method using the testing structure described above. The testing structure further includes a well region located within the substrate; the transistor further includes a source region located within the well region; a drain region located within the well region; and a body region located within the well region, comprising:
[0023] The drain region of the transistor is connected to a negative voltage to ensure that the transistor operates in the linear region;
[0024] The source and body regions of the transistor are connected to the power supply voltage;
[0025] A negative scan is performed on the gate layer of the transistor, starting from 0V and gradually scanning to the negative power supply voltage to ensure that the channel goes from off to fully on.
[0026] During the negative scan, the drain current is recorded to obtain the drain current-gate layer voltage curve.
[0027] A reference current is preset. When the drain current reaches the reference current, the corresponding gate layer voltage is recorded as the linear region threshold voltage. The linear region threshold voltage is compared with the target threshold voltage of normal testing. If the linear region threshold voltage > the target threshold voltage, it indicates that negative charge is trapped in the defects of the gate oxide layer; if the linear region threshold voltage < the target threshold voltage, it indicates that positive charge is trapped in the defects of the gate oxide layer.
[0028] Furthermore, the negative voltage range is -0.1V to -0.05V.
[0029] Furthermore, the reference current formula is as follows:
[0030] I ref =I D0 *(W / L);
[0031] Among them, I ref As the reference current, I D0 W is the reference current per unit width-to-length ratio, where W is the width of the transistor, L is the length of the transistor, and W / L is the width-to-length ratio of the transistor.
[0032] Compared with the prior art, the technical solution of this application has at least one of the following beneficial effects:
[0033] The test structure and method provided in this application eliminate the influence of noise and amplify the effect of charging on the gate oxide by connecting the gate layers of multiple transistors in the transistor array together. Then, the charge in the gate oxide is monitored by testing the threshold voltage of the linear region. If the threshold voltage of the linear region is greater than the target threshold voltage, it indicates that negative charge is trapped in the defects of the gate oxide; if the threshold voltage of the linear region is less than the target threshold voltage, it indicates that positive charge is trapped in the defects of the gate oxide. This allows for early detection of the influence of on-line plasma on DINU during production, enabling early warning and control, and reducing costs.
[0034] Furthermore, process uniformity is improved by setting up a virtual transistor array around the transistor array. Attached Figure Description
[0035] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:
[0036] Figure 1 This is a schematic diagram of a test structure provided in one embodiment of this application;
[0037] Figure 2 This is a flowchart of a testing method provided in one embodiment of this application.
[0038] in, Figure 1 The specific reference numerals in the attached figures are as follows:
[0039] 10 - Shallow trench isolation structure; 20 - Well region; 30 - Gate layer; 31 - Gate layer connection line; 40 - Source region; 50 - Drain region; 100 - Transistor array; 100a - Transistor; 200 - Virtual transistor array; 200a - Virtual transistor.
[0040] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation
[0041] To make the technical solutions and advantages of the embodiments of this application clearer, the technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the implementation methods described herein. Rather, these implementation methods are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.
[0042] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and are only used to facilitate and clarify the illustration of the embodiments of the present application. It is understood that the meanings of "on," "above," and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer. In the embodiments of the present application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.
[0043] As described in the background section, the presence of the gate oxide unit (DINU) directly affects the signal-to-noise ratio and image quality of the chip image sensor (CIS). The plasma processing used in chip manufacturing can easily generate a "charging effect," damaging the gate oxide layer on the chip. This damage directly leads to a deterioration in the DINU. Therefore, in applications requiring high-quality image output (such as photography and security monitoring), monitoring the potential impact of the charging effect generated by the plasma during the manufacturing process on the DINU is crucial. Currently, there are no suitable wafer acceptance test parameters to monitor the impact of the charging effect on the gate oxide layer. Therefore, it is impossible to detect the impact of on-line plasma on the DINU in advance; monitoring can only be done through chip probing methods, which results in late detection and high costs.
[0044] To address the above issues, this application proposes an improved solution: by sharing the gate layers of multiple transistors in the transistor array, the influence of noise is eliminated, the effect of charging on the gate oxide layer is amplified, and the charge in the gate oxide layer is monitored by testing the linear region threshold voltage. If the linear region threshold voltage > the target threshold voltage, it indicates that negative charges are trapped in defects in the gate oxide layer; if the linear region threshold voltage < the target threshold voltage, it indicates that positive charges are trapped in defects in the gate oxide layer. This allows for early detection of the impact of on-line plasma on the DINU during production, enabling early warning and control, and reducing costs.
[0045] Furthermore, process uniformity is improved by setting up a virtual transistor array around the transistor array.
[0046] The test structure proposed in this application will be described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application. Many specific details are set forth in the following description to provide a thorough understanding of this application; however, this application may also be implemented in other ways different from those described herein, and therefore this application is not limited to the specific embodiments disclosed below.
[0047] See Figure 1The test structure provided in this embodiment includes a substrate, a shallow trench isolation structure 10, a well region 20, a transistor array 100, and a virtual transistor array 200. The substrate is preferably a silicon substrate; the shallow trench isolation structure 10 is located within the substrate; the well region 20 is located within the substrate, preferably an input / output N-well region; the transistor array 100 and the virtual transistor array 200 are located on the substrate, with the virtual transistor array 200 surrounding the transistor array 100. The structure of the virtual transistor array 200 is identical to that of the transistor array 100, thereby improving process uniformity; the transistor array 100 includes multiple transistors 100a, and the virtual transistor array 200 includes multiple virtual transistors 100b. The number of transistors 100a in the transistor array 100 is not limited, but is preferably 2 to 6. For example... Figure 1 There are 4 transistors in total; the transistor 100a and the virtual transistor 100b include PMOS transistors, preferably input / output PMOS transistors.
[0048] The transistor 100a includes a gate oxide layer, a gate layer 30, a gate layer interconnect 31, a source region 40, a drain region 50, and a body region. The gate oxide layer is located on the substrate; the gate layer 30 is located on the gate oxide layer; the gate layer interconnect 31 is located on the gate layer 30. The gate layers 30 of the multiple transistors 100a are connected together through the gate layer interconnect 31, thereby eliminating the influence of noise and amplifying the effect of charging on the gate oxide layer. Subsequently, the charge in the gate oxide layer can be monitored by testing the linear region threshold voltage. If the linear region threshold voltage > the target threshold voltage, it indicates that negative charges are trapped in defects in the gate oxide layer; if the linear region threshold voltage < the target threshold voltage, it indicates that positive charges are trapped in defects in the gate oxide layer. This allows for early detection (during production) of the influence of on-line plasma on the DINU, enabling early warning and control, and reducing costs. The source region 40, the drain region 50, and the body region are located within the well region 20.
[0049] In other embodiments, this application also provides a testing method, see below. Figure 2 , Figure 2 The flowchart below shows a test method provided in one embodiment of this application. The test method uses the test structure described above and may include the following steps:
[0050] Step S201: A negative voltage is applied to the drain region of the transistor to ensure that the transistor operates in the linear region;
[0051] Step S202: The source region and body region of the transistor are connected to the power supply voltage;
[0052] Step S203: Perform a negative scan on the gate layer of the transistor, starting from 0V and gradually scanning to the negative power supply voltage to ensure that the channel goes from off to fully on.
[0053] Step S204: During the negative scan, the drain current is recorded to obtain the drain current-gate voltage curve.
[0054] Step S205: A reference current is preset. When the drain current reaches the reference current, the corresponding gate layer voltage is recorded as the linear region threshold voltage. The linear region threshold voltage is compared with the target threshold voltage of normal testing. If the linear region threshold voltage > the target threshold voltage, it indicates that negative charge is trapped in the defects of the gate oxide layer; if the linear region threshold voltage < the target threshold voltage, it indicates that positive charge is trapped in the defects of the gate oxide layer.
[0055] See Figure 1 In step S201 above, the drain regions 50 of transistors 100a in transistor array 100 are each connected to a very small negative voltage V. D This ensures that the transistor 100a operates in the linear region, while the drain region 50 of the transistor 200a in the virtual transistor array 200 is left floating; wherein, the transistor 100a is preferably an input / output PMOS transistor, and for example, the number of transistors 100a is 4, and the voltage range of the negative voltage is -0.1V to -0.05V.
[0056] In step S202 above, the source region 40 and body region of the four transistors 100a in the transistor array 100 are respectively connected to the power supply voltage, for example, 1.8V or 3.3V. The source region 40 and body region of a single transistor 100a can be short-circuited to eliminate the influence of the body effect on the subsequently measured linear region threshold voltage. At the same time, the source region 40 and body region of the transistors 200a in the virtual transistor array 200 are left floating.
[0057] In step S203 above, the gate layers 30 of the four transistors 100a connected in the transistor array 100 are connected to the gate layer voltage V. G A negative scan is performed, starting from 0V and gradually scanning to the negative power supply voltage, ensuring that the channel transitions from off to fully on, while the gate layers 30 of the four virtual transistors 200a connected in the virtual transistor array 200 are left floating. For example, the number of virtual transistor arrays 200 is three.
[0058] In step S204 above, during the negative scan, the drain current I is recorded. D The drain current - gate voltage (I) is obtained. D -V G )curve;
[0059] In step S205 above, a reference current is preset, and the formula for the reference current is:
[0060] I ref =I D0 *(W / L);
[0061] Among them, I ref Reference current; I D0 W is the reference current per unit width-to-length ratio, a fixed process constant, typically -100nA or -300nA for PMOS transistors; W is the width of the transistor; L is the length of the transistor; W / L is the width-to-length ratio of the transistor.
[0062] When the drain current I D Reaching the reference current I ref At that time, record the corresponding gate layer voltage V. G The threshold voltage V in the linear region tlin The threshold voltage V in the linear region tlin The target threshold voltage V of the normal WAT test target In comparison, if the threshold voltage V in the linear region tlin Target threshold voltage V target This indicates that the negative charge is trapped in a defect in the gate oxide layer; if the threshold voltage V in the linear region... tlin <Target threshold voltage V target This indicates that the positive charge is trapped in the defects of the gate oxide layer.
[0063] In summary, the test structure and method provided in this application eliminate the influence of noise and amplify the effect of charging on the gate oxide layer by connecting the gate layers of multiple transistors in the transistor array together. Furthermore, the charge in the gate oxide layer is monitored by testing the linear region threshold voltage. If the linear region threshold voltage > the target threshold voltage, it indicates that negative charges are trapped in defects in the gate oxide layer; if the linear region threshold voltage < the target threshold voltage, it indicates that positive charges are trapped in defects in the gate oxide layer. This allows for early detection of the influence of on-line plasma on the DINU during production, enabling early warning and control, and reducing costs.
[0064] Furthermore, process uniformity is improved by setting up a virtual transistor array around the transistor array.
[0065] It should be noted that although preferred embodiments have been disclosed above in this application, these embodiments are not intended to limit this application. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of this application based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.
Claims
1. A test structure, characterized in that, include: A transistor array, located on a substrate, includes a plurality of transistors, said transistors comprising: A gate oxide layer is located on the substrate; The gate layer is located on the gate oxide layer; The gate layers of the plurality of transistors are connected in common.
2. The test structure as described in claim 1, characterized in that, The transistor array contains 2 to 6 transistors.
3. The test structure as described in claim 1, characterized in that, Also includes: A virtual transistor array, located around the transistor array, and comprising multiple virtual transistors, the structure of the virtual transistor array being identical to that of the transistor array.
4. The test structure as described in claim 1, characterized in that, The transistor and the virtual transistor include PMOS transistors.
5. The test structure as described in claim 1, characterized in that, Also includes: A gate layer connection line is located on the gate layer, and the gate layers of the plurality of transistors are connected together through the gate layer connection line.
6. The test structure as described in claim 1, characterized in that, Also includes: The well region is located within the substrate.
7. The test structure as described in claim 6, characterized in that, The transistor also includes: The source region is located within the well region; The drain region is located within the well region; The body region is located within the well region.
8. A testing method, characterized in that, Using the test structure as described in any one of claims 1 to 7, the test structure further includes a well region located within the substrate; the transistor further includes a source region located within the well region; The drain region is located within the well region; The body region, located within the well region, includes: The drain region of the transistor is connected to a negative voltage to ensure that the transistor operates in the linear region; The source and body regions of the transistor are connected to the power supply voltage; A negative scan is performed on the gate layer of the transistor, starting from 0V and gradually scanning to the negative power supply voltage to ensure that the channel goes from off to fully on. During the negative scan, the drain current is recorded to obtain the drain current-gate layer voltage curve. A reference current is preset. When the drain current reaches the reference current, the corresponding gate layer voltage is recorded as the linear region threshold voltage. The linear region threshold voltage is compared with the target threshold voltage of normal testing. If the linear region threshold voltage > the target threshold voltage, it indicates that negative charge is trapped in the defects of the gate oxide layer; if the linear region threshold voltage < the target threshold voltage, it indicates that positive charge is trapped in the defects of the gate oxide layer.
9. The test method as described in claim 8, wherein the negative voltage range is -0.1V to -0.05V.
10. The test method as described in claim 8, characterized in that, The formula for the reference current is: I ref =I D0 *(W / L); Among them, I ref As the reference current, I D0 W is the reference current per unit width-to-length ratio, where W is the width of the transistor, L is the length of the transistor, and W / L is the width-to-length ratio of the transistor.