Semiconductor structure and method of manufacturing the same, electronic device
By forming process holes in the semiconductor structure and laterally etching the sacrificial layer, the device optimization problem of IGZO material under process constraints is solved, the device performance of the semiconductor structure is improved, and etching damage is avoided.
Patent Information
- Application Number
- CN202510199378.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-21
- Publication Date
- 2026-08-25
AI Technical Summary
Due to process limitations, IGZO materials are difficult to further optimize and improve in semiconductor devices, which affects device performance.
A semiconductor structure manufacturing method includes forming process holes and laterally etching a sacrificial layer to form isolation trenches, then stacking an initial semiconductor layer, a dielectric layer and a gate, and finally removing the sacrificial layer to form isolated first and second semiconductor layers to avoid etching damage.
This improves the device performance of the semiconductor structure, ensuring that the initial semiconductor layer can form the first semiconductor layer of the corresponding device after isolation, and is isolated from it, avoiding damage to the channel layer by the etching process.
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Figure CN122641331A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking daily. Based on this, using indium gallium zinc oxide (IGZO) as the channel layer of devices is beneficial for improving device performance. However, due to the material properties of IGZO, its processing limitations can hinder further optimization and improvement of the devices. Summary of the Invention
[0003] Based on this, the present disclosure provides a semiconductor structure and its manufacturing method, as well as an electronic device, which is beneficial for optimizing and improving the semiconductor structure fabrication process and device performance.
[0004] In a first aspect, this application provides a method for manufacturing a semiconductor structure, comprising the following steps:
[0005] A substrate is provided, and a stacked unit is formed on the substrate; the stacked unit includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, a sacrificial layer, and a support material layer sequentially stacked in a direction away from the substrate;
[0006] Patterned stacked units form process holes that penetrate the support material layer, sacrificial layer, second dielectric layer, second conductive layer and first dielectric layer along the direction perpendicular to the substrate, and the process holes expose the first conductive layer;
[0007] Based on the transverse etching of the sacrificial layer of the process hole, a partition groove is formed around the process hole;
[0008] An initial semiconductor layer, a dielectric layer, and a gate are sequentially stacked within process vias and isolation trenches;
[0009] A third conductive material layer is formed on the top surface of the support material layer, the initial semiconductor layer, the dielectric layer, and the gate.
[0010] A third conductive material layer and a support material layer are patterned to form a support layer that partially covers the initial semiconductor layer, and a third conductive layer that at least covers the gate.
[0011] Remove the sacrificial layer;
[0012] The initial semiconductor layer is patterned until the dielectric layer is exposed, forming a first semiconductor layer and a second semiconductor layer located on the upper and lower sides of the isolation trench, respectively.
[0013] According to some embodiments, the manufacturing method further includes forming an isolation structure in the removal regions of the third conductive material layer, the support material layer, and the initial semiconductor layer, as well as on the side of the third conductive layer facing away from the substrate.
[0014] According to some embodiments, the lateral etching of the sacrificial layer based on the process hole includes: lateral etching of the sacrificial layer using a dry etching process or an atomic layer etching process.
[0015] According to some embodiments, the patterned stacked unit forms a process via penetrating the support material layer, sacrificial layer, second dielectric layer, second conductive layer, and first dielectric layer along a direction perpendicular to the substrate, including the following steps:
[0016] A hard mask layer and an anti-reflection layer are sequentially stacked on the side of the stacked unit away from the substrate;
[0017] A photolithographic pattern is formed in the anti-reflection layer and the hard mask layer, and the photolithographic pattern is used to define the formation location of the process holes;
[0018] Process holes are formed by etching stacked units based on photolithographic patterns.
[0019] According to some embodiments, the sacrificial layer is formed of the same material as the hard mask layer; the support material layer is formed of the same material as the antireflective layer.
[0020] According to some embodiments, the materials used to form the sacrificial layer include spin-coated carbon, advanced patterned thin film materials, or aluminum oxide.
[0021] According to some embodiments, the material forming the support material layer includes silicon oxynitride.
[0022] According to some embodiments, the materials used to form the first semiconductor layer and the second semiconductor layer include metal oxide semiconductor materials.
[0023] According to some embodiments, the first conductive layer includes a first conductive line extending along a first direction parallel to the substrate, and the second conductive layer includes a second conductive line extending along a second direction parallel to the substrate, the second direction intersecting the first direction; wherein, the orthographic projection of the process hole on the substrate is located in the overlapping area of the orthographic projections of the first conductive line and the second conductive line on the substrate.
[0024] Secondly, this application provides a semiconductor structure that can be fabricated using the semiconductor structure manufacturing methods described in some of the above embodiments. The semiconductor structure includes: a substrate, stacked units, a first semiconductor layer, a second semiconductor layer, a dielectric layer, a gate, and a third conductive layer.
[0025] The stacked unit is located on a substrate and includes: a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer and a support layer sequentially stacked in a direction away from the substrate; a process via penetrating the support layer, the second dielectric layer, the second conductive layer and the first dielectric layer; and a partition trench located between the support layer and the second dielectric layer and surrounding the process via; the process via includes a first hole located on the side of the partition trench near the substrate and a second hole located on the side of the partition trench away from the substrate; the first hole exposes the first conductive layer.
[0026] The first semiconductor layer covers the bottom surface of the isolation trench near the substrate, the inner wall of the first hole, and the first conductive layer.
[0027] The second semiconductor layer covers the top surface of the isolation trench on the side away from the substrate and the inner wall of the second hole;
[0028] The dielectric layer at least covers the surfaces of both the first semiconductor layer and the second semiconductor layer facing the process vias and the isolation trenches;
[0029] The gate covering dielectric layer is located away from the surface of the first semiconductor layer and the second semiconductor layer, and is filled with process vias and isolation trenches;
[0030] The third conductive layer at least covers the gate.
[0031] According to some embodiments, a first semiconductor layer and a second semiconductor layer are spaced apart in a direction perpendicular to the substrate, the space being greater than or equal to a target threshold.
[0032] Thirdly, this application also provides an electronic device, including a semiconductor structure prepared by the manufacturing method of the semiconductor structure described in some of the above embodiments; or the semiconductor structure described above.
[0033] The embodiments disclosed herein may have, or at least have, the following advantages:
[0034] In the above-described semiconductor structure manufacturing method, after forming a process hole penetrating the support material layer, sacrificial layer, second dielectric layer, second conductive layer, and first dielectric layer along the vertical substrate direction, and laterally etching the sacrificial layer based on the process hole to form an isolation trench surrounding the process hole, an initial semiconductor layer, dielectric layer, and gate can be sequentially stacked within the process hole and the isolation trench. A third conductive material layer is formed on the top surface of the support material layer and the initial semiconductor layer, dielectric layer, and gate. Then, the third conductive material layer and support material layer are patterned to correspondingly form a support layer and a third conductive layer. Afterward, the sacrificial layer is removed, and the initial semiconductor layer is patterned until the dielectric layer is exposed, thereby forming a first semiconductor layer and a second semiconductor layer located on the upper and lower sides of the isolation trench, respectively. Thus, the manufacturing method provided in this application is easy to implement. The initial semiconductor layer in this application can have a large etching isolation window based on the thickness of the sacrificial layer, and ensure that the initial semiconductor layer can form the first semiconductor layer of the corresponding device and the isolated second semiconductor layer after isolation, so as to avoid damage to the first semiconductor layer (i.e., the channel layer of the corresponding device) caused by the etching process, thereby effectively improving the device performance of the semiconductor structure. Attached Figure Description
[0035] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor structure provided in some embodiments;
[0037] Figure 2 This is a schematic cross-sectional view of a structure obtained after forming a stacked unit, as provided in some embodiments;
[0038] Figure 3 This is a top view schematic diagram of a first conductive line and a second conductive line provided in some embodiments;
[0039] Figure 4 This is a schematic cross-sectional view of a structure obtained after forming a process hole, as provided in some embodiments;
[0040] Figure 5 This is a cross-sectional schematic diagram of a structure obtained after forming a partition groove, as provided in some embodiments;
[0041] Figure 6 This is a schematic cross-sectional view of a structure obtained after forming a gate material layer, as provided in some embodiments;
[0042] Figure 7 This is a schematic cross-sectional view of a structure obtained after forming a third conductive material layer, as provided in some embodiments;
[0043] Figure 8 This is a three-dimensional structural diagram of a structure obtained after forming a support layer and a third conductive layer, provided in some embodiments;
[0044] Figure 9 This is a schematic cross-sectional view of a structure obtained after removing the sacrificial layer, as provided in some embodiments;
[0045] Figure 10 This is a schematic cross-sectional view of a structure obtained after forming a first semiconductor layer and a second semiconductor layer, as provided in some embodiments.
[0046] Figure 11 This is a schematic cross-sectional view of a structure obtained after forming an isolation structure, as provided in some embodiments; and, Figure 11 This is also a cross-sectional schematic diagram of a semiconductor structure provided in some embodiments.
[0047] Explanation of reference numerals in the attached figures:
[0048] 1-Substrate, 11-Isolation layer, 2-Stacked unit, 21-First conductive layer, 211-First conductive line, 22-First dielectric layer, 23-Second conductive layer, 231-Second conductive line, 24-Second dielectric layer, 25-Sacrificial layer, 260-Support material layer, 26-Support layer, H-Process via, H1-First via, H2-Second via, G-Isolation trench, 30-Semiconductor material layer, 3A-Initial semiconductor layer, 31-First semiconductor layer, 32-Second semiconductor layer, 4-Dielectric layer, 40-Dielectric material layer, 5-Gate, 50-Gate material layer, 6-Third conductive layer, 60-Third conductive material layer, 7-Isolation structure, 81-Hard mask layer, 82-Anti-reflection layer. Detailed Implementation
[0049] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.
[0051] The term "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0052] It is understood that the terms “first,” “second,” “third,” “fourth,” etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.
[0053] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0054] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0055] Please see Figure 1 This application provides a method for manufacturing a semiconductor structure, which may include the following steps S100~S800.
[0056] S100, a substrate is provided, and a stacked unit is formed on the substrate. The stacked unit includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, a sacrificial layer, and a support material layer sequentially stacked in a direction away from the substrate.
[0057] S200, a patterned stacked cell, forms a process via penetrating the support material layer, sacrificial layer, second dielectric layer, second conductive layer, and first dielectric layer along a direction perpendicular to the substrate. The process via exposes the first conductive layer.
[0058] For example, the first conductive layer includes a first conductive line extending along a first direction parallel to the substrate. The second conductive layer includes a second conductive line extending along a second direction parallel to the substrate. The second direction intersects, for example, the first direction. The orthographic projection of the process via onto the substrate lies within the overlapping region of the orthographic projections of both the first and second conductive lines onto the substrate.
[0059] S300, based on the transverse etching of the sacrificial layer of the process hole, forms a partition groove surrounding the process hole.
[0060] S400, in which the initial semiconductor layer, dielectric layer and gate are sequentially stacked in process vias and isolation trenches.
[0061] S500 forms a third conductive material layer on the top surface of the support material layer, the initial semiconductor layer, the dielectric layer, and the gate.
[0062] S600, a third conductive material layer and a support material layer are patterned to form a support layer that partially covers the initial semiconductor layer, and a third conductive layer that at least covers the gate.
[0063] S700, remove the sacrificial layer.
[0064] S800, patterning the initial semiconductor layer to expose the dielectric layer, forming a first semiconductor layer and a second semiconductor layer located on the upper and lower sides of the isolation trench, respectively.
[0065] In this embodiment, after forming a process via penetrating the support material layer, sacrificial layer, second dielectric layer, second conductive layer, and first dielectric layer along the vertical substrate direction, and laterally etching the sacrificial layer based on the process via to form an isolation trench surrounding the process via, an initial semiconductor layer, dielectric layer, and gate can be sequentially stacked within the process via and the isolation trench. A third conductive material layer is formed on the top surface of the support material layer, the initial semiconductor layer, the dielectric layer, and the gate. Then, the third conductive material layer and the support material layer are patterned to correspondingly form a support layer and a third conductive layer. Afterward, the sacrificial layer is removed, and the initial semiconductor layer is patterned until the dielectric layer is exposed, thereby forming a first semiconductor layer and a second semiconductor layer located on the upper and lower sides of the isolation trench, respectively. Thus, the manufacturing method provided in this embodiment is easy to implement. The initial semiconductor layer in this embodiment can have a large etching isolation window based on the thickness of the sacrificial layer, and ensures that the initial semiconductor layer can form the first semiconductor layer of the corresponding device and the isolated second semiconductor layer after isolation, so as to avoid damage to the first semiconductor layer (i.e., the channel layer of the device) caused by the etching process, thereby effectively improving the device performance of the semiconductor structure.
[0066] In some embodiments, the manufacturing method further includes step S900.
[0067] S900, an isolation structure is formed in the removal regions of the third conductive material layer, the support material layer and the initial semiconductor layer, as well as on the side of the third conductive layer away from the substrate.
[0068] It should be added that, in some embodiments, the aforementioned stacked units can be further stacked along the direction perpendicular to the substrate to form corresponding devices, referring to the process described in steps S100 to S900 above. Optionally, to match the circuit connection relationship between adjacent devices, process steps for forming interconnect structures to connect adjacent devices can be adaptively added. This application does not limit this aspect.
[0069] In some embodiments, the patterning of stacked units in step S200 to form process holes penetrating the support material layer, sacrificial layer, second dielectric layer, second conductive layer and first dielectric layer along the direction perpendicular to the substrate may include the following steps S210 to S230.
[0070] S210, a hard mask layer and an anti-reflection layer are sequentially stacked on the side of the stacked unit away from the substrate.
[0071] S220, a photolithographic pattern is formed in the anti-reflective layer and the hard mask layer, which is used to define the formation location of the process holes.
[0072] S230 forms process holes by etching stacked units based on photolithography patterns.
[0073] For example, the sacrificial layer is formed using the same material as the hard mask layer.
[0074] In some examples, the materials used to form the sacrificial layer include, but are not limited to, spin-coated carbon, advanced patterned thin film materials, or alumina.
[0075] For example, the material forming the support layer is the same as the material forming the anti-reflective layer.
[0076] In some examples, the supporting material layer is formed by materials including, but not limited to, silicon oxynitride.
[0077] In some embodiments, step S300, which involves laterally etching the sacrificial layer based on the process hole, includes: laterally etching the sacrificial layer using a dry etching process or an atomic layer etching process.
[0078] In some embodiments, the materials used to form the first semiconductor layer and the second semiconductor layer include metal oxide semiconductor materials.
[0079] It should be understood that while the steps in the above manufacturing method are described sequentially according to their step numbers, these steps are not necessarily executed in the order indicated by their step numbers. Unless otherwise explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a portion of each step may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.
[0080] To more clearly illustrate the manufacturing method provided in the embodiments of this application, the following embodiments are combined with... Figures 2-11 Some embodiments of the manufacturing method are described in detail.
[0081] In step S100, please refer to Figure 2 A substrate 1 is provided, and a stacked unit 2 is formed on the substrate 1. The stacked unit 2 includes a first conductive layer 21, a first dielectric layer 22, a second conductive layer 23, a second dielectric layer 24, a sacrificial layer 25, and a support material layer 260, which are sequentially stacked along a direction away from the substrate 1 (e.g., the Z direction).
[0082] For example, substrate 1 may include, but is not limited to, a silicon (Si) substrate. The substrate may also include silicon-germanium (SiGe) substrates, silicon-germanium-carbon (SiGeC) substrates, silicon-carbide (SiC) substrates, gallium-arsenide (GaAs) substrates, indium-arsenide (InAs) substrates, indium-phosphide (InP) substrates, or other III / V or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may also include semiconductor substrates such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate 1 should not limit the scope of protection of this application. Exemplarily, substrate 1 may also refer to a dielectric layer formed on silicon. Alternatively, other thin films, such as isolation layer 11, may also be formed on substrate 1. Isolation layer 11 includes, but is not limited to, a silicon oxide layer.
[0083] For example, please refer to Figure 3 The first conductive layer 21 includes a first conductive line 211 extending along a first direction (e.g., the Y direction) parallel to the substrate 1. The second conductive layer 23 includes a second conductive line 231 extending along a second direction (e.g., the X direction) parallel to the substrate 1. The second direction (e.g., the X direction) intersects the first direction (e.g., the Y direction), for example, orthogonally.
[0084] For example, the first conductive layer 21 and the second conductive layer 23 are made of the same material, such as titanium nitride.
[0085] For example, the first dielectric layer 22 and the second dielectric layer 24 are made of the same material, such as silicon oxide.
[0086] For example, the materials used to form the sacrificial layer 25 include, but are not limited to, spin-on carbon (SOC), advanced patterning film (APF), or aluminum oxide (AlO). The sacrificial layer 25 needs to have a high etch selectivity ratio with the second dielectric layer 24 and the initial semiconductor layer, so as to ensure that the impact or damage to the semiconductor layer caused by the etching of the sacrificial layer 25 can be greatly reduced or eliminated when the sacrificial layer 25 is subsequently removed.
[0087] For example, the support material layer 260 includes, but is not limited to, silicon oxynitride.
[0088] In step S200, please combine Figure 2 and Figure 4 Understandably, patterned stacked units 2 form process vias H that penetrate the support material layer 260, sacrificial layer 25, second dielectric layer 24, second conductive layer 23, and first dielectric layer 22 along a direction perpendicular to the substrate 1 (e.g., the Z direction). The process vias H expose the first conductive layer 21.
[0089] In some examples, the sacrificial layer 25 is a spin-coated carbon layer, which can prevent sidewall depressions or significant damage caused by etching of the process hole H under the protection of the polymer.
[0090] In some examples, the sacrificial layer 25 is an aluminum oxide layer, which can be etched using a mixed solution of ammonia and ultrapure water. This allows the sacrificial layer 25 to have a higher etching selectivity than other layers and form a more controllable etching morphology, thereby avoiding sidewall depressions or damage caused by etching of the process hole H.
[0091] Here, ultrapure water refers to water with a resistivity of 18 MΩ·cm at 25℃.
[0092] For example, step S200 may include steps S210 to S230.
[0093] In step S210, please refer to Figure 2 A hard mask layer 81 and an anti-reflection layer 82 are sequentially stacked on the side of the stacked unit 2 away from the substrate 1.
[0094] For example, the sacrificial layer 25 is formed of the same material as the hard mask layer 81.
[0095] For example, the material forming the support material layer 260 is the same as the material forming the anti-reflective layer 82.
[0096] In step S220, a photolithographic pattern is formed in the anti-reflection layer 82 and the hard mask layer 81. The photolithographic pattern is used to define the formation location of the process hole H.
[0097] In step S230, please refer to Figure 4 Based on the photolithography pattern etching of the stacked unit 2, process holes H are formed.
[0098] Here, the first conductive layer 21 can serve as an etching stop layer for the process hole H. That is, when forming the process hole H in step S200, etching stops at the surface of the first conductive layer 21 away from the substrate 1 or within the first conductive layer 21.
[0099] For example, multiple process vias H are arrayed, for instance, arranged in columns along a first direction (e.g., the Y direction) and in rows along a second direction (e.g., the X direction). The second direction (e.g., the X direction) intersects the first direction (e.g., the Y direction), for example, orthogonally. Thus, a column of process vias H can be formed on the side of a first conductive line 211 facing away from the substrate 1. A row of process vias H can be spaced through a second conductive line 231.
[0100] For example, the orthographic projection of the process hole H on the substrate 1 is located in the overlapping area of the orthographic projections of the first conductive line 211 and the second conductive line 231 on the substrate 1.
[0101] In step S300, please refer to Figure 5 Based on the process hole H, the sacrificial layer 25 is etched laterally to form the isolation groove G surrounding the process hole H.
[0102] For example, the sacrificial layer 25 is etched laterally (etched back) using either a dry etching process or an atomic layer etching (asher) process. The etching size of the sacrificial layer 25 can be selected and set to match design requirements.
[0103] In step S400, please refer to Figure 6 and Figure 7 The initial semiconductor layer 3, dielectric layer 4 and gate 5 are sequentially stacked in the process hole H and the isolation trench G.
[0104] For example, the initial semiconductor layer 3, dielectric layer 4, and gate 5 can be deposited using an atomic layer deposition (ALD) process, corresponding to the deposition of semiconductor material layer 30, dielectric material layer 40, and gate material layer 50 (e.g., ...). Figure 6 Afterwards (as shown in the image), the excess gate material layer 50, dielectric material layer 40, and semiconductor material layer 30 are ground using a chemical mechanical polishing (CMP) process until the support material layer 260 is exposed (as shown in the image). Figure 7(As shown in the image) is obtained afterward.
[0105] For example, the semiconductor material layer 30 includes, but is not limited to, a metal oxide semiconductor material layer. The semiconductor material layer 30 located on the bottom surface of the process via H is in contact with the corresponding first conductive line in the first conductive layer 24.
[0106] Optionally, the metal oxide semiconductor material may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), and indium gallium silicon oxide (InGaSi). Materials include indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO). Specifically, the goal is to ensure that the leakage current of the corresponding device (e.g., transistor) meets the requirements, and adjustments can be made according to the actual situation.
[0107] As a further example, the semiconductor material layer 30 is an indium gallium zinc oxide (IGZO) layer.
[0108] For example, the dielectric material layer 40 is formed of a High-K dielectric material, which may include one or more High-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, for instance, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), etc., High-K dielectric materials.
[0109] For example, the gate material layer 50 may be formed using indium zinc oxide (IZO), tungsten (W), indium tin oxide (ITO), or titanium nitride (TiN).
[0110] In step S500, please continue reading. Figure 7A third conductive material layer 60 is formed on the top surface of the support material layer 260 and the initial semiconductor layer 3, dielectric layer 4, and gate 5.
[0111] For example, the third conductive material layer 60 includes, but is not limited to, a titanium nitride layer, which may be formed, for example, by a low-temperature atomic layer deposition process with a deposition temperature not exceeding 400°C.
[0112] For example, the third conductive material layer 60 can be used as a storage node SN after the third conductive layer 6 is patterned and formed.
[0113] In step S600, please refer to Figure 8 The third conductive material layer 60 and the support material layer 260 are patterned to form a support layer 26 that partially covers the initial semiconductor layer 3, and a third conductive layer 6 that at least covers the gate 5.
[0114] For example, the third conductive layer 6 covers the top surface of the support layer 26 and the initial semiconductor layer 3, dielectric layer 4, and gate 5.
[0115] Here, the patterning of the third conductive material layer 60 and the support material layer 260 can be stopped after etching through a single patterning process (e.g., photolithography) until the sacrificial layer 25 is exposed. Furthermore, the etching boundaries of the support layer 26 and the third conductive layer 6 can be aligned with the maximum contour boundary of the isolation trench G, but are not limited to this. For example, the etching boundaries of the support layer 26 and the third conductive layer 6 are designed to ensure that the third conductive layer 6 can effectively cover the top surface of the gate 5.
[0116] In step S700, please refer to Figure 9 Remove the sacrificial layer 25.
[0117] For example, the sacrificial layer 25 is removed by an asher process, which can avoid etching damage to the initial semiconductor layer 3.
[0118] In this embodiment, after removing the sacrificial layer 25, the sidewalls of the initial semiconductor layer 3 located within the isolation trench G can be exposed, allowing for subsequent isolation of the initial semiconductor layer 3 via lateral etching. Thus, by controlling the film thickness of the sacrificial layer 25, not only can the etching window of the initial semiconductor layer 3 be significantly increased, but etching damage to the subsequently formed first semiconductor layer 31 and second semiconductor layer 32 can also be effectively avoided due to etching of the initial semiconductor layer 3.
[0119] In step S800, please refer to Figure 10 The initial semiconductor layer 3 is patterned until the dielectric layer 4 is exposed, forming a first semiconductor layer 31 and a second semiconductor layer 32 located on the upper and lower sides of the isolation trench G, respectively.
[0120] Here, the first semiconductor layer 31 can serve as the semiconductor layer (i.e., the channel layer of the device) of its corresponding device, and the second semiconductor layer 32 is connected to the third conductive layer 62 and isolated from the first semiconductor layer 31, which can effectively isolate the electrical connection between the first semiconductor layer 31 and the third conductive layer 62.
[0121] In step S900, please refer to Figure 11 An isolation structure 7 is formed in the removal areas of the third conductive material layer 60, the support material layer 260 and the initial semiconductor layer 3, and on the side of the third conductive layer 6 away from the substrate 1.
[0122] For example, the isolation structure 7 can be formed by depositing an oxide material, such as tetraethyl orthosilicate (TEOS), using an atomic layer deposition process. Furthermore, the surface of the isolation structure 7 can be polished using a chemical mechanical polishing process.
[0123] It should be added that, in some embodiments, the aforementioned stacked units 2 can be stacked along the direction perpendicular to the substrate and the corresponding device can be formed by referring to the process described in steps S100 to S900. For example, a memory cell with a dual-transistor zero-capacitor (e.g., 2TOC) architecture can be prepared accordingly, that is, both transistors in the memory cell can be prepared by the process described in steps S100 to S900.
[0124] In addition, optionally, to match the circuit connection relationship between adjacent devices, process steps to form interconnect structures to connect adjacent devices can be adaptively added. This application does not specifically limit this aspect.
[0125] This application also provides a semiconductor structure that can be fabricated using the semiconductor structure manufacturing methods described in the foregoing embodiments. This semiconductor structure also possesses the technical advantages of the aforementioned manufacturing methods, and will not be detailed here. Furthermore, the relevant features of each component in this semiconductor structure can be found in the relevant descriptions in the foregoing embodiments.
[0126] Please see Figure 11 The semiconductor structure includes: a substrate 1, a stacked unit 2, a first semiconductor layer 31, a second semiconductor layer 32, a dielectric layer 4, a gate 5, and a third conductive layer 6.
[0127] The stacked unit 2 is located on the substrate 1 and includes: a first conductive layer 21, a first dielectric layer 22, a second conductive layer 23, a second dielectric layer 24, and a support layer 26 sequentially stacked in a direction away from the substrate 1 (e.g., the Z direction); a process via H penetrating the support layer 26, the second dielectric layer 24, the second conductive layer 23, and the first dielectric layer 22; and a partition trench G located between the support layer 26 and the second dielectric layer 24 and surrounding the process via H. The process via H includes a first via H1 located on the side of the partition trench G closest to the substrate 1, and a second via H2 located on the side of the partition trench G away from the substrate 1; the first via H1 exposes the first conductive layer.
[0128] Accordingly, the first semiconductor layer 31 covers the bottom surface of the isolation trench G near the substrate 1, the inner wall of the first hole H1, and the first conductive layer 21, and can serve as the channel layer for the corresponding device. The second semiconductor layer 32 covers the top surface of the isolation trench G away from the substrate 1 and the inner wall of the second hole H2, and is isolated from the first semiconductor layer 31. The dielectric layer 4 covers at least the surfaces of the first semiconductor layer 31 and the second semiconductor layer 32 facing the process hole H and the isolation trench G. The gate 5 covers the surface of the dielectric layer 4 away from the first semiconductor layer 31 and the second semiconductor layer 32, and fills the process hole H and the isolation trench G. The third conductive layer 6 covers at least the gate 5, for example, it can cover the support layer 26 and the top surfaces of the second semiconductor layer 32, the dielectric layer 4, and the gate 5.
[0129] In some embodiments, the first semiconductor layer 31 and the second semiconductor layer 32 are spaced apart in a direction perpendicular to the substrate 1 (e.g., the Z direction), and the spaced apart is greater than or equal to a target threshold.
[0130] Here, the target threshold is the difference between the film thickness of the sacrificial layer 25 and the sum of the film thicknesses of the first semiconductor layer 31 and the second semiconductor layer 32 in the aforementioned embodiments.
[0131] For example, please refer to Figure 3 The first conductive layer 21 includes a first conductive line 211 extending along a first direction (e.g., the Y direction) parallel to the substrate 1. The second conductive layer 23 includes a second conductive line 231 extending along a second direction (e.g., the X direction) parallel to the substrate 1. The second direction (e.g., the X direction) intersects the first direction (e.g., the Y direction), for example, orthogonally.
[0132] For example, multiple process vias H are arrayed, for instance, arranged in columns along a first direction (e.g., the Y direction) and in rows along a second direction (e.g., the X direction). The second direction (e.g., the X direction) intersects the first direction (e.g., the Y direction), for example, orthogonally. Thus, a column of process vias H can be formed on the side of a first conductive line 211 facing away from the substrate 1. A row of process vias H can be spaced through a second conductive line 231.
[0133] For example, the orthographic projection of the process hole H on the substrate 1 is located in the overlapping area of the orthographic projections of the first conductive line 211 and the second conductive line 231 on the substrate 1.
[0134] For example, the first conductive layer 21 and the second conductive layer 23 are made of the same material, such as including a titanium nitride layer.
[0135] For example, the first dielectric layer 22 and the second dielectric layer 24 are made of the same material, such as a silicon oxide layer.
[0136] For example, the support layer 26 includes, but is not limited to, a silicon oxynitride layer.
[0137] For example, the first semiconductor layer 31 and the second semiconductor layer 32 are made of the same material, such as, but not limited to, a metal oxide semiconductor layer.
[0138] For example, gate 5 may include, but is not limited to, an indium zinc oxide (IZO) layer.
[0139] It should be added that, in some embodiments, the aforementioned stacked unit 2 can be at least two and stacked along the direction perpendicular to the substrate 1. Furthermore, the aforementioned first semiconductor layer 31, second semiconductor layer 32, dielectric layer 4, gate 5, and third conductive layer 6 can be matched with each stacked unit 2 to form a corresponding device.
[0140] For example, two stacked units 2 are stacked along the direction perpendicular to the substrate 1, and the first semiconductor layer 31 corresponding to each stacked unit 2 can be used as the channel layer of the upper and lower devices respectively, so as to prepare a memory cell with a dual-transistor zero-capacitor (e.g., 2T0C) architecture.
[0141] This application also provides an electronic device in some embodiments. The electronic device includes one or more semiconductor structures as described in the above embodiments, or semiconductor structures prepared by the manufacturing method of the semiconductor structures described in the above embodiments.
[0142] For example, electronic devices include data storage devices, photocopiers, network devices, home appliances, instruments, mobile phones, computers, and other devices with data storage functions.
[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0144] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, and a stacked unit is formed on the substrate; the stacked unit includes a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, a sacrificial layer, and a support material layer sequentially stacked in a direction away from the substrate; The stacked units are patterned to form process vias that penetrate the support material layer, the sacrificial layer, the second dielectric layer, the second conductive layer, and the first dielectric layer along a direction perpendicular to the substrate; the process vias expose the first conductive layer; The sacrificial layer is etched laterally based on the process hole to form a partition groove surrounding the process hole; An initial semiconductor layer, a dielectric layer, and a gate are sequentially stacked within the process via and the isolation trench; A third conductive material layer is formed on the top surface of the support material layer, the initial semiconductor layer, the dielectric layer, and the gate. The third conductive material layer and the support material layer are patterned to form a support layer that partially covers the initial semiconductor layer, and a third conductive layer that at least covers the gate. Remove the sacrificial layer; The initial semiconductor layer is patterned to expose the dielectric layer, forming a first semiconductor layer and a second semiconductor layer located on the upper and lower sides of the isolation trench, respectively.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Also includes: An isolation structure is formed in the removal regions of the third conductive material layer, the support material layer, and the initial semiconductor layer, as well as on the side of the third conductive layer facing away from the substrate.
3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The lateral etching of the sacrificial layer based on the process hole includes: lateral etching of the sacrificial layer using a dry etching process or an atomic layer etching process.
4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The patterning of the stacked units forms process vias penetrating the support material layer, the sacrificial layer, the second dielectric layer, the second conductive layer, and the first dielectric layer along a direction perpendicular to the substrate, including: A hard mask layer and an anti-reflection layer are sequentially stacked on the side of the stacked unit opposite to the substrate; A photolithographic pattern is formed in the anti-reflection layer and the hard mask layer, and the photolithographic pattern is used to define the formation location of the process aperture; The process holes are formed by etching the stacked units based on the photolithographic pattern.
5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The sacrificial layer is formed of the same material as the hard mask layer. The supporting material layer is formed of the same material as the anti-reflective layer.
6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Includes at least one of the following schemes: The materials used to form the sacrificial layer include spin-coated carbon, advanced patterned thin film materials, or aluminum oxide. The supporting material layer is formed of silicon oxynitride; The materials used to form the first semiconductor layer and the second semiconductor layer include metal oxide semiconductor materials.
7. The method for manufacturing a semiconductor structure according to any one of claims 1 to 6, characterized in that, The first conductive layer includes a first conductive line extending along a first direction parallel to the substrate; the second conductive layer includes a second conductive line extending along a second direction parallel to the substrate; the second direction intersects the first direction; The orthographic projection of the process hole on the substrate is located within the overlapping area of the orthographic projections of the first conductive line and the second conductive line on the substrate.
8. A semiconductor structure, characterized in that, include: Substrate; A stacked unit, located on the substrate, includes: a first conductive layer, a first dielectric layer, a second conductive layer, a second dielectric layer, and a support layer sequentially stacked in a direction away from the substrate; a process via penetrating the support layer, the second dielectric layer, the second conductive layer, and the first dielectric layer; and a partition trench located between the support layer and the second dielectric layer and surrounding the process via; the process via includes a first hole located on the side of the partition trench near the substrate, and a second hole located on the side of the partition trench away from the substrate; the first hole exposes the first conductive layer; The first semiconductor layer covers the bottom surface of the isolation trench near the substrate, the inner wall of the first hole, and the first conductive layer. The second semiconductor layer covers the top surface of the isolation trench on the side opposite to the substrate and the inner wall of the second hole; A dielectric layer that at least covers the surfaces of the first semiconductor layer and the second semiconductor layer facing the process via and the isolation trench; The gate covers the surface of the dielectric layer opposite to the first semiconductor layer and the second semiconductor layer, and fills the process via and the isolation trench; A third conductive layer covers at least the gate.
9. The semiconductor structure according to claim 8, characterized in that, The first semiconductor layer and the second semiconductor layer are spaced apart in a direction perpendicular to the substrate, and the spaced apart is greater than or equal to a target threshold.
10. An electronic device, characterized in that, include: A semiconductor structure prepared by the manufacturing method of the semiconductor structure according to any one of claims 1 to 7; Alternatively, the semiconductor structure as described in claim 8 or 9.