8-inch silicon-diamond hybrid bonded wafer and method of making the same

Abstract

The application discloses an 8-inch silicon-diamond hybrid bonding wafer and relates to the technical field of semiconductor hetero-integration. The application discloses an 8-inch silicon-diamond hybrid bonding wafer and relates to the technical field of semiconductor hetero-integration. The diamond substrate is an 8-inch diamond wafer. The bonding transition layer is arranged between the diamond substrate and the silicon-based functional layer, and the bonding transition layer comprises a SiO2 layer and a Cu bump array. If heat cannot be conducted and released from the inside of the chip in time, the device junction temperature will be increased, and then the working stability, service life and electrical performance of the device are affected. The application sets the hybrid bonding transition layer composed of the SiO2 layer and the Cu bump array between the 8-inch silicon-based functional layer and the diamond substrate, so that the wafer has high mechanical bonding strength, heat conduction capacity and alignment precision.

Description

Technical Field

[0001] This invention relates to the field of semiconductor heterogeneous integration technology, specifically to an 8-inch silicon-diamond hybrid bonding wafer and its fabrication method. Background Technology

[0002] As integrated circuits evolve towards higher integration, higher power density, and miniaturization, the heat generated by chips during operation is constantly increasing. This is especially true in 3D integrated chips, high-power radio frequency devices, and power semiconductor devices, where localized heat concentration is prone to occur. If heat cannot be conducted and dissipated from the chip in a timely manner, it will lead to an increase in the device junction temperature, thereby affecting the device's operational stability, lifespan, and electrical performance. Therefore, improving the heat dissipation capability of silicon-based devices has become a crucial technical challenge in the manufacturing of high-end semiconductor devices.

[0003] Silicon materials possess mature processing technology and a complete industrial chain. Most current integrated circuit manufacturing processes use silicon-based wafers as the primary substrate. Diamond materials, with their high thermal conductivity, good insulation properties, and high mechanical strength, are considered excellent materials for heat dissipation in high-power devices. Integrating silicon-based functional layers with diamond substrates can improve chip heat dissipation by leveraging diamond's high thermal conductivity while maintaining silicon-based process compatibility, thereby enhancing overall device performance.

[0004] Existing silicon-diamond integration methods mainly include mechanical bonding, adhesive bonding, metal interlayer connection, and direct bonding. While mechanical bonding is relatively simple, it's difficult to form stable atomic or molecular-level bonds between the silicon wafer and the diamond wafer, resulting in uneven interface contact and the formation of micro-gaps, leading to higher interfacial thermal resistance. Adhesive bonding can reduce processing difficulty to some extent, but the adhesive itself typically has low thermal conductivity, making it prone to aging, cracking, or debonding under high temperature, high power, or long-term operating conditions, affecting device reliability. Using a single metal interlayer for connection can improve thermal and electrical conductivity to some extent, but the difference in thermal expansion coefficients between silicon and diamond can easily cause stress concentration at the interface during thermal cycling, leading to cracks, warping, or delamination.

[0005] Hybrid bonding technology can leverage the advantages of both dielectric and metal layer bonding. The dielectric layer provides a better mechanical bonding foundation, while the metal layer forms thermal and electrical conduction channels, thus improving the overall performance of the bonding interface. However, in the case of 8-inch large-size wafers, the overall flatness, surface roughness, alignment accuracy, interface cleanliness, and thermal stress release of the silicon and diamond wafers all significantly affect the bonding effect. The presence of particles, contaminants, bubbles, or localized height differences on the wafer surface can easily lead to voids, unbonded areas, or localized cracks at the bonding interface. Especially during large-area wafer-level bonding, the uneven stress and temperature distribution between the edge and center regions makes interface defects more likely.

[0006] Furthermore, existing technologies in silicon-diamond wafer integration typically struggle to simultaneously achieve low interfacial thermal resistance, high bonding strength, high alignment accuracy, and process compatibility. While some solutions improve interfacial bonding strength, they suffer from insufficient thermal conductivity; others improve thermal conductivity but exhibit poor alignment accuracy and large-size wafer consistency; still others require complex or specialized equipment, making them difficult to directly integrate with existing 8-inch semiconductor production lines. Therefore, there is still a need for a silicon-diamond hybrid bonding structure and its fabrication method suitable for 8-inch wafer-level manufacturing to reduce interfacial thermal resistance, improve bonding strength, suppress interfacial bubbles and cracks, and meet the stability and mass production requirements of subsequent high-end semiconductor device manufacturing. Summary of the Invention

[0007] The main objective of this invention is to provide an 8-inch silicon-diamond hybrid bonding wafer and its preparation method, which can effectively solve the problems in the background art.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An 8-inch silicon-diamond hybrid bonding wafer includes a diamond substrate, a bonding transition layer, and a silicon-based functional layer arranged sequentially from bottom to top; the diamond substrate is an 8-inch diamond wafer; the bonding transition layer is disposed between the diamond substrate and the silicon-based functional layer, and the bonding transition layer includes a SiO2 layer and a Cu bump array; the silicon-based functional layer is an 8-inch silicon wafer, and the side of the silicon-based functional layer facing the bonding transition layer has metallized pads that match the Cu bump array.

[0009] Preferably, the diamond substrate is a single-crystal diamond wafer, the thickness of the diamond substrate is 500μm to 1000μm, the thermal conductivity is not less than 1900W / (m·K), and the surface flatness is not greater than 1.5μm.

[0010] Preferably, the thickness of the SiO2 layer is 100nm to 200nm; the diameter of the Cu bumps in the Cu bump array is 1μm to 3μm, the spacing between adjacent Cu bumps is 5μm to 10μm, and the height of the Cu bumps is 50nm to 100nm.

[0011] Preferably, the silicon-based functional layer is a P-type silicon wafer, and the thickness of the silicon-based functional layer is 300μm to 500μm.

[0012] Preferably, the bonding alignment accuracy of the 8-inch silicon-diamond hybrid bonding wafer is no greater than 0.1 μm, and the interface thermal resistance is no greater than 5 × 10⁻⁶. -6 m 2 • K / W, bond strength not less than 35 MPa.

[0013] A method for fabricating an 8-inch silicon-diamond hybrid bonding wafer, the method comprising the following steps: S1. Substrate pretreatment: The diamond substrate is subjected to chemical mechanical polishing and surface activation treatment to make the bonding surface of the diamond substrate achieve a preset flatness and surface cleanliness. S2. Pretreatment of silicon-based functional layer: The silicon-based functional layer is thermally oxidized to form a SiO2 layer, and a Cu bump array is formed by photolithography and electroplating processes. S3. Precise alignment and bonding: Using a double-sided alignment method, with the edge alignment mark as a reference, the silicon-based functional layer and the diamond substrate are aligned and bonded. S4. Stepwise mixing and bonding: Stepwise mixing and bonding is performed in a vacuum environment to form molecular bonds in the SiO2 layer and metallurgical bonds in the Cu bump array. S5. Annealing treatment: The wafer after hybrid bonding is annealed to release the bonding stress between the diamond substrate and the silicon-based functional layer. S6. Post-processing: The surface of the annealed wafer is trimmed to obtain an 8-inch silicon-diamond hybrid bonded wafer.

[0014] Preferably, in step S1, after chemical mechanical polishing of the diamond substrate, the surface roughness Ra of the diamond substrate is ≤0.3nm; the surface activation treatment is oxygen plasma treatment with a treatment power of 200W to 300W and a treatment time of 5min to 10min.

[0015] Preferably, in step S3, the double-sided alignment method is completed using a double-sided alignment lithography machine, and the alignment accuracy between the silicon-based functional layer and the diamond substrate is controlled to be ≤0.1μm.

[0016] Preferably, in step S4, the stepwise mixing bonding includes a first bonding stage and a second bonding stage; the bonding temperature of the first bonding stage is 200℃ to 300℃, and the holding time is 1h, for achieving molecular bonding of the SiO2 layer; the bonding temperature of the second bonding stage is 400℃ to 450℃, the holding time is 2h, and a bonding pressure of 5MPa to 10MPa is applied, for achieving metallurgical bonding of the Cu bump array; in step S5, the annealing treatment is carried out in a nitrogen atmosphere, the annealing temperature is 500℃ to 600℃, the annealing time is 3h, and the cooling rate is controlled at 5℃ / min.

[0017] Compared with the prior art, the present invention has the following beneficial effects: By placing a hybrid bonding transition layer consisting of a SiO2 layer and a Cu bump array between an 8-inch silicon-based functional layer and a diamond substrate, the wafer simultaneously possesses high mechanical bonding strength, thermal conductivity, and alignment accuracy. The SiO2 layer forms a stable molecular bonding interface, while the Cu bump array forms a metallurgical bonding interface and provides thermal and electrical conduction channels, thereby effectively reducing interface thermal resistance and improving heat dissipation performance during high-power device operation. Through double-sided alignment and step-by-step vacuum hybrid bonding processes, misalignment, bubbles, voids, and cracks occurring during large-size wafer bonding can be reduced, improving the bonding reliability of silicon-diamond wafers. Annealing and post-processing further release bonding stress and improve wafer surface flatness, making the wafer compatible with existing 8-inch semiconductor process lines and suitable for high-end semiconductor applications such as 3D integrated chips and high-power RF devices. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the preparation method steps of the present invention; Detailed Implementation

[0019] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0020] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "front end," "rear end," "both ends," "one end," and "the other end," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0022] Example Please see Figure 1 The present invention provides the following technical solution: This embodiment provides an 8-inch silicon-diamond hybrid bonding wafer and its fabrication method. The wafer comprises, from bottom to top, a diamond substrate, a bonding transition layer, and a silicon-based functional layer. The diamond substrate is an 8-inch single-crystal diamond wafer with a thickness of 800 μm and a thermal conductivity of not less than 1900 W / (m·K). The silicon-based functional layer is an 8-inch P-type silicon wafer with a thickness of 400 μm. The bonding transition layer is disposed between the diamond substrate and the silicon-based functional layer, and includes a SiO2 layer and a Cu bump array. The SiO2 layer forms a stable dielectric bonding interface, and the Cu bump array forms thermally and electrically conductive channels and improves the overall bonding strength of the wafer. This structure is consistent with the "diamond substrate, bonding transition layer, and silicon-based functional layer" scheme in the original document, and incorporates the technical specifications regarding the SiO2 layer, Cu bump array, and 8-inch wafer.

[0023] In the fabrication process, step S1, substrate pretreatment, was performed first. An 8-inch single-crystal diamond wafer was selected as the diamond substrate, and its bonding surface was chemically and mechanically polished to control the surface roughness Ra below 0.3 nm and the surface flatness below 1.5 μm. Subsequently, the polished diamond substrate was subjected to oxygen plasma treatment at a power of 250 W for 8 minutes. This treatment removes organic contaminants and minute impurities from the diamond substrate surface and improves its surface activity, providing better surface conditions for subsequent dielectric bonding.

[0024] Then, step S2, silicon-based functional layer pretreatment, is performed. An 8-inch P-type silicon wafer is selected as the silicon-based functional layer. After cleaning the bonding surface of the silicon wafer, a SiO2 layer is formed on the surface of the silicon-based functional layer through a thermal oxidation process. The thickness of the SiO2 layer is controlled to be 150 nm. Subsequently, a bump pattern is formed on the surface of the silicon-based functional layer using a photolithography process, and then a Cu bump array is formed through an electroplating process. The diameter of the Cu bumps is 2 μm, the spacing between adjacent Cu bumps is 8 μm, and the height of the Cu bumps is 80 nm. After the Cu bump array is formed, the silicon-based functional layer is subjected to plasma cleaning to remove surface residues and ensure the cleanliness of the subsequent bonding interface.

[0025] Next, step S3, precise alignment and bonding, is performed. The pre-treated diamond substrate and silicon-based functional layer are placed in a double-sided alignment device, and aligned using the wafer edge alignment marks as a reference. During alignment, the Cu bump array on the surface of the silicon-based functional layer is matched with the corresponding metallization pads, and the alignment accuracy between the diamond substrate and the silicon-based functional layer is controlled to be no greater than 0.1 μm. After alignment, the bonding surfaces of the silicon-based functional layer and the diamond substrate are initially bonded to form the wafer assembly to be bonded.

[0026] Then, step S4, stepwise hybrid bonding, is performed. The wafer assembly to be bonded is placed in a vacuum bonding apparatus, and stepwise bonding is carried out under vacuum. In the first stage, the bonding temperature is raised to 250℃ and held for 1 hour to induce molecular bonding between the SiO2 layers, thereby forming a stable dielectric interface. In the second stage, the bonding temperature is raised to 430℃ and held for 2 hours, while a bonding pressure of 8 MPa is applied to induce metallurgical bonding of the Cu bump array. This stepwise bonding method allows dielectric bonding and metal bonding to be completed under suitable temperature and pressure conditions, reducing the generation of interface bubbles, voids, and cracks.

[0027] The next step is annealing, step S5. The wafer, after hybrid bonding, is placed in a nitrogen atmosphere for annealing at 550°C for 3 hours, with a cooling rate of 5°C / min. Annealing releases the bonding stress between the diamond substrate and the silicon functional layer caused by differences in thermal expansion, reducing the risk of wafer warpage and further improving the stability of the bonding interface.

[0028] Finally, step S6 post-processing is performed. The annealed wafer undergoes chemical mechanical polishing and surface finishing to control the overall flatness of the wafer to below 2μm, resulting in an 8-inch silicon-diamond hybrid bonded wafer. Testing shows that the interfacial thermal resistance of this wafer is no greater than 5 × 10⁻⁶. -6 m 2The bonding strength is not less than 35 MPa (K / W), and no obvious delamination was observed after thermal cycling testing. Therefore, this embodiment, through a hybrid bonding structure of SiO2 layer and Cu bump array, enables the wafer to simultaneously possess good bonding strength, thermal conductivity, and alignment accuracy, making it suitable for high-end semiconductor applications such as 3D integrated chips and high-power RF devices.

[0029] In this embodiment, an 8-inch silicon-based functional layer is hybrid-bonded to a diamond substrate, combining silicon-based semiconductor technology with the high thermal conductivity of diamond materials. The diamond substrate can rapidly conduct heat generated during the operation of the silicon-based functional layer, reducing localized heat concentration on the chip and thus improving the operational stability of high-power devices and 3D integrated chips. Compared with traditional mechanical bonding or adhesive bonding methods, this invention does not rely on a low thermal conductivity adhesive layer as the main bonding medium, thus effectively reducing interface thermal resistance and improving the overall heat dissipation capacity of the wafer.

[0030] This invention employs a SiO2 layer and a Cu bump array to form a bonding transition layer. The SiO2 layer forms a stable dielectric bonding interface, improving the mechanical bonding strength between wafers; the Cu bump array forms a metallic bonding interface, enhancing thermal and electrical conductivity at the interface. The combination of these two materials is not a simple bonding of individual materials, but rather a synergistic optimization of mechanical bonding, thermal conduction, and electrical connectivity, making the overall performance of the silicon-diamond wafer more suitable for high-end semiconductor devices.

[0031] This invention employs a double-sided alignment method, using edge alignment marks as a reference for precise alignment, ensuring high alignment accuracy between the silicon-based functional layer and the diamond substrate even under large-size wafer conditions. This method helps guarantee accurate mating between the Cu bump array and the corresponding metallized pads, reducing misalignment, poor connections, or localized non-bonding issues, thereby meeting the wafer-level alignment accuracy requirements of 3D integrated chips and fine wiring structures.

[0032] This invention employs a stepwise hybrid bonding process, first forming molecular bonds in the SiO2 layer, and then forming metallurgical bonds with the Cu bump array. This method allows dielectric bonding and metal bonding to be completed separately under suitable process conditions, reducing interfacial bubbles, voids, cracks, and stress concentration problems caused by one-time high-temperature and high-pressure bonding, and improving the uniformity and reliability of the bonding interface.

[0033] This invention incorporates annealing and post-processing steps after hybrid bonding. Annealing releases bonding stress between the diamond substrate and the silicon functional layer caused by differences in material thermal expansion, reducing the risk of wafer warpage, delamination, and cracking. Post-processing further refines the wafer surface, improving overall wafer flatness and facilitating subsequent chip manufacturing processes. Therefore, this invention not only improves wafer heat dissipation and bonding strength but also enhances the fabrication stability and mass production adaptability of large-size silicon-diamond hybrid bonded wafers. These advantages correspond to the technical effects described in the original document, such as "reducing interface thermal resistance, increasing bonding strength, improving alignment accuracy, suppressing interface bubbles and cracks, and compatibility with 8-inch semiconductor process lines."

[0034] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. An 8-inch silicon-diamond hybrid bonding wafer, characterized in that, The device comprises, from bottom to top, a diamond substrate, a bonding transition layer, and a silicon-based functional layer; the diamond substrate is an 8-inch diamond wafer; the bonding transition layer is disposed between the diamond substrate and the silicon-based functional layer, and the bonding transition layer includes a SiO2 layer and a Cu bump array; the silicon-based functional layer is an 8-inch silicon wafer, and the side of the silicon-based functional layer facing the bonding transition layer has metallized pads that match the Cu bump array.

2. The 8-inch silicon-diamond hybrid bonding wafer according to claim 1, characterized in that, The diamond substrate is a single-crystal diamond wafer with a thickness of 500μm to 1000μm, a thermal conductivity of not less than 1900W / (m·K), and a surface flatness of not more than 1.5μm.

3. The 8-inch silicon-diamond hybrid bonding wafer according to claim 1, characterized in that, The thickness of the SiO2 layer is 100nm to 200nm; the diameter of the Cu bumps in the Cu bump array is 1μm to 3μm, the spacing between adjacent Cu bumps is 5μm to 10μm, and the height of the Cu bumps is 50nm to 100nm.

4. The 8-inch silicon-diamond hybrid bonding wafer according to claim 1, characterized in that, The silicon-based functional layer is a P-type silicon wafer, and the thickness of the silicon-based functional layer is 300μm to 500μm.

5. The 8-inch silicon-diamond hybrid bonding wafer according to claim 1, characterized in that, The bonding alignment accuracy of the 8-inch silicon-diamond hybrid bonding wafer is no greater than 0.1 μm, and the interface thermal resistance is no greater than 5 × 10⁻⁶. -6 m 2 • K / W, bond strength not less than 35 MPa.

6. A method for fabricating an 8-inch silicon-diamond hybrid bonded wafer, characterized in that, The method for preparing the 8-inch silicon-diamond hybrid bonding wafer according to any one of claims 1 to 5 comprises the following steps: S1. Substrate pretreatment: The diamond substrate is subjected to chemical mechanical polishing and surface activation treatment to make the bonding surface of the diamond substrate achieve a preset flatness and surface cleanliness. S2. Pretreatment of silicon-based functional layer: The silicon-based functional layer is thermally oxidized to form a SiO2 layer, and a Cu bump array is formed by photolithography and electroplating processes. S3. Precise alignment and bonding: Using a double-sided alignment method, with the edge alignment mark as a reference, the silicon-based functional layer and the diamond substrate are aligned and bonded. S4. Stepwise mixing and bonding: Stepwise mixing and bonding is performed in a vacuum environment to form molecular bonds in the SiO2 layer and metallurgical bonds in the Cu bump array. S5. Annealing treatment: The wafer after hybrid bonding is annealed to release the bonding stress between the diamond substrate and the silicon-based functional layer. S6. Post-processing: The surface of the annealed wafer is trimmed to obtain an 8-inch silicon-diamond hybrid bonded wafer.

7. The method for preparing an 8-inch silicon-diamond hybrid bonding wafer according to claim 6, characterized in that, In step S1, after chemical mechanical polishing of the diamond substrate, the surface roughness Ra of the diamond substrate is ≤0.3nm; the surface activation treatment is oxygen plasma treatment with a treatment power of 200W to 300W and a treatment time of 5min to 10min.

8. The method for preparing an 8-inch silicon-diamond hybrid bonding wafer according to claim 6, characterized in that, In step S3, the double-sided alignment method is completed using a double-sided alignment lithography machine, and the alignment accuracy between the silicon-based functional layer and the diamond substrate is controlled to be ≤0.1μm.

9. The method for preparing an 8-inch silicon-diamond hybrid bonding wafer according to claim 6, characterized in that, In step S4, the stepwise hybrid bonding includes a first bonding stage and a second bonding stage; the bonding temperature of the first bonding stage is 200℃ to 300℃, and the holding time is 1h, used to achieve molecular bonding of the SiO2 layer; the bonding temperature of the second bonding stage is 400℃ to 450℃, the holding time is 2h, and a bonding pressure of 5MPa to 10MPa is applied, used to achieve metallurgical bonding of the Cu bump array; in step S5, the annealing treatment is carried out in a nitrogen atmosphere, the annealing temperature is 500℃ to 600℃, the annealing time is 3h, and the cooling rate is controlled at 5℃ / min.

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