Semiconductor device

Abstract

To reduce the influence of a time constant caused by a parasitic capacitance of a rectifying element or the like and suppress oscillation caused by switching of the rectifying element, a semiconductor device is configured to include a rectifying element, a determination circuit configured to determine on / off of the rectifying element based on a voltage between a pair of output terminals of the rectifying element, an amplification circuit configured to perform on / off control of the rectifying element based on a determination result of the determination circuit, and a voltage division circuit connected between an output terminal of the amplification circuit or an input terminal of the rectifying element and one of the output terminals of the rectifying element, the determination circuit taking a voltage division voltage of a node of the voltage division circuit as a positive input or a negative input.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] As a technology related to semiconductor devices, there is the technology disclosed in Patent Document 1. Patent Document 1 discloses a technology comprising: a rectifier element that performs synchronous rectification; a determination circuit that determines whether the rectifier element is turned on or off based on the voltage between a pair of main terminals of the rectifier element; and a gate drive circuit that turns the rectifier element on / off according to the determination result. This rectifier circuit is a synchronous rectifier circuit based on voltage determination.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-116077 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] Furthermore, in synchronous rectification circuits using voltage determination methods, especially autonomous synchronous rectification circuits, a closed-loop operation occurs where the rectified signal from the determination circuit is fed back via the rectifier element. In this closed-loop operation, when the rectifier element is turned on, the voltage drop between the output terminals (source and drain terminals) of the rectifier element decreases due to the reduction in resistance, causing the determination circuit to disconnect. During the repetition of this operation, a delay occurs due to the time constant caused by parasitic capacitance and other factors of the rectifier element, which can easily lead to oscillations caused by the switching of the rectifier element.

[0008] The present invention was made in view of the following situation, and its purpose is to reduce the influence of time constant caused by parasitic capacitance of rectifier elements and suppress oscillation caused by switching of rectifier elements.

[0009] Methods for solving problems

[0010] To address the aforementioned issues, for example, the structure described in the claims may be employed.

[0011] This application includes several means to solve the above-mentioned problems. One example is a semiconductor device comprising: a rectifier element; a determination circuit that determines whether the rectifier element is turned on or off based on the voltage between a pair of output terminals of the rectifier element; an amplifier circuit that controls the rectifier element to be turned on or off based on the determination result of the determination circuit; and a voltage divider circuit connected between the output terminal of the amplifier circuit or the input terminal of the rectifier element and one output terminal of the rectifier element, wherein the determination circuit uses the voltage divided by the voltage divider circuit as a positive or negative input.

[0012] Invention Effects

[0013] According to the present invention, the influence of time constant caused by parasitic capacitance of rectifier elements can be reduced, and oscillations caused by switching of rectifier elements can be suppressed.

[0014] Other issues, structures, and effects not described above will become clear through the following description of the means of carrying out the invention (hereinafter referred to as the implementation method). Attached Figure Description

[0015] Figure 1 This is a circuit diagram illustrating a structural example of the synchronous rectifier circuit according to the first embodiment of the present invention.

[0016] Figure 2 This is a waveform diagram of half-wave rectification performed in the synchronous rectifier circuit of the reference example.

[0017] Figure 3 This is a waveform diagram of the rectification process in the synchronous rectifier circuit of the reference example.

[0018] Figure 4 This is a waveform diagram illustrating the delay caused by the gate capacitance of the rectifier element in the synchronous rectifier circuit of the reference example.

[0019] Figure 5 This is a waveform diagram illustrating the conditions under which the synchronous rectifier circuit in the reference example does not oscillate.

[0020] Figure 6 This is a waveform diagram of half-wave rectification performed in the synchronous rectifier circuit of the first embodiment of the present invention.

[0021] Figure 7 This is a circuit diagram illustrating a structural example of the autonomous synchronous rectifier circuit according to the second embodiment of the present invention.

[0022] Figure 8 This is a circuit diagram showing a preferred structural example of an amplifier circuit used as a third embodiment of the present invention.

[0023] Figure 9 The waveforms show the operating voltage, series current, and through current of the N-channel MOSFET and P-channel MOSFET in a source-grounded inverter.

[0024] Figure 10 This is a circuit diagram illustrating a structural example of the output stage of the amplifier circuit according to the fourth embodiment of the present invention.

[0025] Figure 11It is a waveform diagram of the operating voltage, current when connected in series, and current at intermediate voltage of the N-channel MOSFET and P-channel MOSFET in the drain-grounded amplifier circuit.

[0026] Figure 12 This is a circuit diagram illustrating a structural example of the amplifier circuit according to the fifth embodiment of the present invention. Detailed Implementation

[0027] Hereinafter, embodiments (models) for carrying out the present invention will be described with reference to the accompanying drawings. In this specification and the drawings, repeated descriptions of constituent elements having substantially the same function or structure are omitted by using the same reference numerals.

[0028] First Implementation Method

[0029] [Example of a synchronous rectifier circuit structure]

[0030] In a first embodiment of the present invention, a synchronous rectification circuit is exemplified as a semiconductor device. Figure 1 This is a circuit diagram illustrating a structural example of the synchronous rectifier circuit according to the first embodiment of the present invention.

[0031] like Figure 1 As shown, the synchronous rectification circuit 10 of the first embodiment is a synchronous rectification circuit with a voltage determination method, including a rectifier element 11, a determination circuit 12, an amplifier circuit 13, and a voltage divider circuit 14.

[0032] Here, the rectifier element 11 is exemplified by a synchronous rectifier circuit 20 using a MOSFET constructed with an SJ (superjunction). The rectifier element 11 is connected between a pair of output terminals 15 and 16. That is, one output terminal (e.g., the drain terminal) of the rectifier element 11 is connected to output terminal 15, and the other output terminal (e.g., the source terminal) is connected to output terminal 16. The power supply voltage VIN is applied to the decision circuit 12 and the amplifier circuit 13 through the input terminal 17.

[0033] For example, the determination circuit 12 sets the voltage at the source terminal of the rectifier element 11 as a positive input and sets the voltage at node n1 of the voltage divider circuit 14, i.e. the voltage divided by the voltage divider circuit 14, as a negative input, thereby performing the determination process of whether the rectifier element 11 is turned on (forward) or turned off (reverse).

[0034] In addition, here, assuming that the amplifier circuit 13 is non-inverting logic, the voltage of the voltage divider circuit 14 is set to negative input. However, the amplifier circuit 13 can also be set to inverting logic. In this case, the determination circuit 12 sets the voltage of the voltage divider circuit 14 to positive input.

[0035] The amplifier circuit 13 controls the conduction (forward) / discontinuation (reverse) of the rectifier element 11 based on the determination result of the determination circuit 12. That is, the amplifier circuit 13 is the gate driver that drives the input terminal (gate terminal) of the rectifier element 11.

[0036] The voltage divider circuit 14 is connected between the output terminal of the amplifier circuit 13 and one output terminal (e.g., the drain terminal) of the rectifier element 11. Specifically, the voltage divider circuit 14 consists of a resistor element 141 with one end connected to one output terminal (e.g., the drain terminal) of the rectifier element 11, and a resistor element 142 connected between the other end of the resistor element 141 and the output terminal of the amplifier circuit 13. The common connection node of the resistor elements 141 and 142 becomes the node n1 from which the voltage divider voltage is derived.

[0037] Furthermore, this circuit structure assumes that the output terminal of the amplifier circuit 13 is directly connected to the input terminal (gate terminal) of the rectifier element 11. Under this premise, the voltage divider circuit 14 is connected between the output terminal of the amplifier circuit 13 and one output terminal of the rectifier element 11. However, this connection structure is not limited to this. For example, if there are some circuits (e.g., resistors) between the output terminal of the amplifier circuit 13 and the input terminal of the rectifier element 11, the voltage divider circuit 14 can also be configured to be connected between the input terminal and one output terminal of the rectifier element 11.

[0038] [Regarding oscillations caused by the switching of rectifier components]

[0039] Here, for the synchronous rectification circuit 10 of the first embodiment of the above structure, a synchronous rectification circuit with a circuit structure that only feeds back the drain-source voltage (drain-source voltage) of the rectifier element 11 will be described as a reference example. In the synchronous rectification circuit of the reference example that only feeds back the drain-source voltage of the rectifier element 11, a time constant is generated due to the parasitic capacitance of the rectifier element 11, etc., and a delay is generated due to the influence of this time constant. Moreover, when the forward current when the rectifier element 11 is turned on is small, the control of the rectifier element 11 on / off is not fixed, and oscillations caused by the switching of the rectifier element 11 are generated (see reference). Figure 2 ).

[0040] Figure 2 The waveform diagram shows a synchronous rectifier circuit in a reference example where half-wave rectification is performed with only the drain-source voltage of the rectifier element 11 being fed back. Additionally, Figure 3 The waveform diagram shows the operation of the synchronous rectifier circuit in the reference example during rectification. Figure 3The waveform diagram shows the drain-source voltage Vds of rectifier element 11, the output voltage Vcmp_out of decision circuit 12, the output voltage Vamp_out of amplifier circuit 13, the on-resistance Rds of rectifier element 11, and the current Ids flowing through rectifier element 11. The drain-source voltage Vds of rectifier element 11 is fed back to decision circuit 12.

[0041] exist Figure 4 The waveform diagram shows the case where a delay occurs in the gate capacitance Cg of the rectifier element 11 in the synchronous rectifier circuit of the reference example of the circuit structure that only feeds back the drain-source voltage of the rectifier element 11. Figure 4 The waveform diagram shows the waveforms of the drain-source voltage Vds of the rectifier element 11, the output voltage Vcmp_out of the determination circuit 12, and the output voltage Vamp_out of the amplifier circuit 13.

[0042] When the drain-source voltage Vds of rectifier element 11 reaches the determination voltage Vcmp of determination circuit 12, the output voltage Vcmp_out of determination circuit 12 reverses from low level (L) to high level (H). In response, the output voltage Vamp_out of amplifier circuit 13 gradually rises from low level to the turn-on voltage of rectifier element 11. At this time, a delay occurs due to the gate capacitance Cg of rectifier element 11 before the output voltage Vamp_out of amplifier circuit 13 reaches the turn-on voltage of rectifier element 11.

[0043] Here, using Figure 5 The waveform diagram illustrates the conditions under which the synchronous rectifier circuit of the reference example, which has a circuit structure that only feeds back the drain-source voltage of the rectifier element 11, does not oscillate. Figure 5 The waveform diagram shows the waveforms of the drain-source voltage Vds of rectifier element 11, the output voltage Vcmp_out of the judgment circuit 12, the output voltage Vamp_out of the amplifier circuit 13, the on-resistance Rds of rectifier element 11, and the current Ids flowing through rectifier element 11.

[0044] The binary control of turning rectifier element 11 on / off can reduce the delay time, but according to the feedback action, if the input and output are inconsistent, the control becomes unstable, and oscillation cannot be avoided in this binary control. With continuous analog control, the action can occur at the point where the input and output are consistent, thus suppressing oscillation. Specifically, the intermediate voltage between the high level (H) and the low level (L) is effective in preventing oscillation. However, even with analog control, if the delay caused by the gate capacitance Cg is large, oscillation cannot be suppressed.

[0045] [Regarding the effects of the synchronous rectification circuit in the first embodiment]

[0046] Compared to the synchronous rectification circuit of the reference example described above, which only feeds back the drain-source voltage of the rectifier element 11, the synchronous rectification circuit 10 of the first embodiment employs a circuit structure in which a voltage divider circuit 14 is provided between the output terminal of the amplifier circuit 13 and one output terminal (e.g., the drain terminal) of the rectifier element 11. Furthermore, the input to the determination circuit 12 is not the drain-source voltage of the rectifier element 11, but rather the voltage between node n1 of the voltage divider circuit 14 and the source terminal of the rectifier element 11. This reduces the influence of the time constant caused by parasitic capacitance of the rectifier element 11 and suppresses oscillations caused by the switching of the rectifier element 11. More specifically, the switching control of the rectifier element 11 at the intermediate voltage of the on-off state is easily performed, thus oscillations are easily converged.

[0047] Figure 6 This diagram shows the waveform during half-wave rectification in the synchronous rectifier circuit 10 of the first embodiment, which includes a feedback circuit that feeds back the output of amplifier circuit 13 to determination circuit 12. The resistor element 142 of voltage divider circuit 14 constitutes the feedback circuit that feeds back the output of amplifier circuit 13 to determination circuit 12.

[0048] Furthermore, in the synchronous rectification circuit 10 of the first embodiment, when the resistance value of resistor 141 is set to R1 and the resistance value of resistor 142 is set to R2 in the voltage divider circuit 14, the gain G of the synchronous rectification circuit 10 becomes G = R1 / (R1 + R2). That is, the gain G of the synchronous rectification circuit 10 is lower than the gain (=1) when the voltage divider circuit 14 is not provided. In this way, by reducing the gain G of the synchronous rectification circuit 10, it is easier to converge to a state where the control input of the rectifier element 11 is consistent with the determination output of the determination circuit 12. This also effectively suppresses the oscillation caused by the switching of the rectifier element 11.

[0049] Second Implementation Method

[0050] [Example of an autonomous synchronous rectifier circuit]

[0051] In the first embodiment of the present invention, an autonomous synchronous rectification circuit is exemplified as a semiconductor device. Figure 7 This is a circuit diagram illustrating a structural example of an autonomous synchronous rectifier circuit according to a second embodiment of the present invention.

[0052] like Figure 7 As shown, the autonomous synchronous rectifier circuit 20 in the second embodiment has a circuit structure that includes a step-down circuit 21, a diode 22, and a capacitor element 23 in addition to the rectifier element 11, the determination circuit 12, the amplifier circuit 13, and the voltage divider circuit 14.

[0053] The step-down circuit 21 consists of N-channel depletion-mode MOSFETs 211 and 212, and resistors 213 and 214. MOSFET 211 is connected between one output terminal (e.g., drain terminal) of rectifier element 11 and one end of resistor 141 in voltage divider circuit 14. The drain terminal of MOSFET 212 is connected to one output terminal (e.g., drain terminal) of rectifier element 11, and its source terminal is connected to the gate terminal of MOSFET 211. Resistors 213 and 214 are connected in series between the gate terminal of MOSFET 211 and the other output terminal (e.g., source terminal) of rectifier element 11. The gate terminal of MOSFET 212 is connected to the common connection node N of resistors 213 and 214.

[0054] [Example of operation of an autonomous synchronous rectifier circuit]

[0055] The buck circuit 21 described above steps down the relatively high AC voltage applied to one output terminal (e.g., the drain terminal) of the rectifier element 11. The voltage stepped down by the buck circuit 21 is supplied to the capacitor element 23 via the diode 22. This charges the capacitor element 23. This charging operation occurs during the positive period of the AC voltage. Furthermore, during the negative period of the AC voltage, the voltage based on the charge on the capacitor element 23 is supplied as a power supply voltage to the determination circuit 12 and the amplifier circuit 13.

[0056] As described above, the autonomous synchronous rectifier circuit 20 according to the second embodiment is a circuit structure in which the negative input terminal of the determination circuit 12 and one output terminal (e.g., the drain terminal) of the rectifier element 11 are not directly connected, but a step-down circuit 21 exists between the two terminals. In the autonomous synchronous rectifier circuit 20 of this circuit structure, when a large current flows from the source terminal (terminal A) of the rectifier element 11 to the drain terminal (terminal B), the negative input terminal (terminal A') and the positive input terminal (terminal B') of the determination circuit 12 have a high resistance, and therefore the same voltage as that between terminals A and B is applied.

[0057] [Regarding the effect of the amplifier circuit in the second embodiment]

[0058] Thus, in the autonomous synchronous rectifier circuit 20 of the second embodiment, when a large current flows from terminal B to terminal A, even though the negative input terminal of the determination circuit 12 is not directly connected to one output terminal (e.g., the drain terminal) of the rectifier element 11, the voltage becomes (AB) = (A'-B'). Therefore, the autonomous synchronous rectifier circuit 20 of the second embodiment can also achieve the same effect as the synchronous rectifier circuit 10 of the first embodiment. That is, by setting the voltage divider circuit 14 and setting the input of the determination circuit 12 to the voltage between node n1 of the voltage divider circuit 14 and the source terminal of the rectifier element 11, the effect of suppressing oscillations caused by the switching of the rectifier element 11 can be obtained.

[0059] Third Implementation Method

[0060] In the second embodiment of the present invention, a preferred structural example of the amplifier circuit 13 used as the synchronous rectifier circuit 10 of the first embodiment or the autonomous synchronous rectifier circuit 20 of the second embodiment will be described. Figure 8 This is a circuit diagram showing a preferred structural example of the amplifier circuit 13 used as a third embodiment of the present invention.

[0061] (Regarding gate drivers with source-grounded structures)

[0062] Amplifier circuit 13 is a gate driver that drives the input terminal (gate terminal) of rectifier element 11. In general gate drivers, circuits with a source-grounded structure, in which a P-channel MOSFET and an N-channel MOSFET are connected in series in sequence, are often used (inverters). This source-grounded gate driver has very high driving performance (driving capability) and gain (amplification), and is suitable for high-speed driving of loads such as gate capacitors (e.g., MOSFET gate driving).

[0063] However, in the case of an inverter with a source-grounded structure, if an intermediate voltage without binarization is applied, both the P-channel MOSFET and the N-channel MOSFET will be turned on simultaneously. This results in a short circuit between the power supply line and the ground line, causing a through current to flow between them. Consequently, the power consumption of the gate driver increases, leading to increased power consumption in the synchronous rectification circuit of amplifier circuit 13.

[0064] Figure 9 The waveforms show the operating voltage, series current, and through current of the N-channel and P-channel MOSFETs in an inverter with a source-grounded structure.

[0065] exist Figure 9In the waveform diagram, the vertical axis is the gate-source voltage Vgs of the rectifier element, the horizontal axis is the drain current Id, the source current Is, VC is the maximum power supply voltage, and Vth is the threshold voltage of the rectifier element.

[0066] Furthermore, the current capability of a single P-channel MOSFET is illustrated using a dashed waveform diagram, while the current capability of a single N-channel MOSFET is illustrated using a dotted line.

[0067] [Example of the amplifier circuit structure in the third embodiment]

[0068] Compared to a typical gate driver (amplifier circuit) with a source-grounded structure, the amplifier circuit 13 of the third embodiment is a multi-stage circuit structure with a drain-grounded structure. Figure 8 The diagram illustrates the circuit structure of a unit circuit 13_1 to 13_n cascaded together with an n-stage drain-grounded structure.

[0069] Focusing on the first stage, the unit circuit 13_1 of the first stage becomes a drain-grounded structure in which the high-side N-channel MOSFET nm_1 and the low-side P-channel MOSFET pm_1 are connected in series between the positive power supply V+ and the negative power supply V-. Specifically, the drain terminal of the high-side N-channel MOSFET nm_1 is connected to the positive power supply V+, and the drain terminal of the low-side P-channel MOSFET pm_1 is connected to the negative power supply V-. The source terminals and gate terminals of the two MOSFETs nm_1 and pm_1 are connected to each other.

[0070] Furthermore, the gate common connection node is used as the input terminal, and the source common connection node is used as the output terminal.

[0071] [Regarding the effect of the amplifier circuit in the third embodiment]

[0072] The above-described unit circuits are connected in multiple stages. The output terminals of the previous stage and the input terminals of the next stage are connected between the unit circuits 13_1 to 13_n of each stage, thereby forming an amplifier circuit 13 with a drain-grounded structure.

[0073] In the case of amplifier circuit 13 with drain-ground structure, the gain (amplification) is slightly lower than that of 1, and the driving performance (driving capability) is also generally worse than that of source-ground structure. However, even if there is no binarized intermediate voltage at the input, the positive power supply V+ and the negative power supply V- will not conduct (short circuit). Therefore, no through current flows between the positive power supply V+ and the negative power supply V-, thus the power consumption of amplifier circuit 13 can be suppressed to a low level. Therefore, amplifier circuit 13 of the third embodiment with drain-ground structure is suitable for use in applications where intermediate voltages (see reference) frequently occur. Figure 5The circuit of the amplifier circuit 13 in the synchronous rectifier circuit 10 of the first embodiment or the autonomous synchronous rectifier circuit 20 of the second embodiment, which provides feedback action, can suppress the power consumption of the synchronous rectifier circuit 10 and the autonomous synchronous rectifier circuit 20 to a low level.

[0074] Fourth Implementation Method

[0075] [Example of the amplifier circuit structure in the fourth embodiment]

[0076] The fourth embodiment is one of the improvements to the third embodiment. Figure 10 This is a circuit diagram illustrating an example of the structure of the output stage of the amplifier circuit according to the fourth embodiment of the present invention.

[0077] Figure 10 The diagram illustrates the output stage of the amplifier circuit 13 of the fourth embodiment, specifically the final stage unit circuit 13_n, which is composed of an N-channel MOSFET nm_n and a P-channel MOSFET pm_n. The amplifier circuit 13 of the fourth embodiment has a circuit structure consisting of an N-channel depletion-type MOSFET nmd that provides a pull-down function to the final stage unit circuit 13_n.

[0078] The drain terminal of the N-channel depletion-type MOSFET nmd is connected to the gate terminal of the P-channel MOSFET pm_n, and the gate terminal and source terminal are connected to the negative-side power supply V-. This depletion-type MOSFET nmd is a device in which drain current Id flows even when the gate-source voltage Vgs is negative.

[0079] [Regarding the effect of the amplifier circuit in the fourth embodiment]

[0080] Thus, in the amplifier circuit 13 of the fourth embodiment, a pull-down N-channel depletion-type MOSFET nmd is provided in the final stage unit circuit 13_n. As a result, in the rectifier element 11, even when the gate voltage Vg = the source voltage Vs, it will not float due to the pull-down of the depletion-type MOSFET nmd, thereby stabilizing the operation of the amplifier circuit 13.

[0081] Figure 11 The waveforms show the operating voltage, series current, and intermediate voltage current of the N-channel and P-channel MOSFETs in the drain-grounded amplifier circuit 13. Figure 11 In the waveform diagram, the current capability of a P-channel MOSFET is represented by a dashed line, the current capability of an N-channel MOSFET is represented by a single-dot dashed line, and the current capability of an N-channel depletion-mode MOSFET is represented by a dashed line.

[0082] Fifth Implementation Method

[0083] [Example of the amplifier circuit structure in the fifth embodiment]

[0084] The fifth implementation is a second improvement on the third implementation. Figure 12 This is a circuit diagram illustrating a structural example of an amplifier circuit according to the fifth embodiment of the present invention.

[0085] The amplifier circuit in the fifth embodiment is configured such that a driver 30 with a small-scale source-ground structure is connected in parallel to the amplifier circuit 13, which is a unit circuit consisting of multiple stages connected to a drain-ground structure. Here, "small-scale" means that the transistor size is smaller than that of the amplifier circuit 13 with a drain-ground structure.

[0086] Here, the drain-grounded amplifier circuit 13 illustrates a circuit structure in which two cascaded unit circuits of the drain-grounded structure are connected. Specifically, the amplifier circuit 13 consists of a first-stage unit circuit 13_1 in which an N-channel MOSFET nm_1 and a P-channel MOSFET pm_1 are connected in series between the positive and negative power supplies, and a second-stage unit circuit 13_2 in which an N-channel MOSFET nm_2 and a P-channel MOSFET pm_2 are connected in series.

[0087] Compared to the amplifier circuit 13 with the drain-grounded structure, the driver 30 with the source-grounded structure becomes a circuit structure of three cascaded stages of the source-grounded circuit (inverter). Specifically, the driver 30 with the source-grounded structure consists of a first-stage inverter 31 with a P-channel MOSFET pm_11 and an N-channel MOSFET nm_11 connected in series between the positive and negative power supplies, a second-stage inverter 32 with a P-channel MOSFET pm_12 and an N-channel MOSFET nm_12 connected in series, and a third-stage inverter 33 with a P-channel MOSFET pm_13 and an N-channel MOSFET nm_13 connected in series.

[0088] [Regarding the effect of the amplifier circuit in the fifth embodiment]

[0089] In the drain-grounded amplifier circuit 13, a dead zone sometimes occurs where the output remains unchanged relative to the input. Therefore, in the amplifier circuit of the fifth embodiment, as described above, the following structure is adopted: a small-scale source-grounded driver 30 is connected in parallel with the drain-grounded amplifier circuit 13; for the drain-grounded amplifier circuit 13 and the source-grounded driver 30, the input nodes of the same logic are connected to each other, and the output nodes are connected to each other. By connecting the nodes of the same logic to each other in this way, the dead zone where the output remains unchanged relative to the input can be avoided.

[0090] Variations

[0091] Furthermore, the present invention is not limited to the embodiments described above. Various other applications and modifications can be made without departing from the spirit of the invention as set forth in the claims. The above embodiments are detailed and specific descriptions of the structure of the semiconductor device for the purpose of readily understanding the present invention, and are not limited to having all the described structures. For example, in the above embodiments, an SJ-structured MOSFET is illustrated as a rectifier element, but it is not limited to SJ-MOSFETs; it can also be a SiC-MOSFET, an IGBT (Insulated Gate Bipolar Transistor), or other power semiconductor elements.

[0092] Symbol Explanation

[0093] 10: Synchronous rectification circuit of the first embodiment; 11: Rectifying element; 12: Decision circuit; 13: Amplifying circuit; 14: Voltage divider circuit; 15, 16: Output terminals; 17: Input terminals; 20: Autonomous synchronous rectification circuit of the second embodiment; 21: Buck circuit; 22: Diode; 23: Capacitor element; 30: Driver with source grounding structure; 31, 32, 33: Inverter.

Claims

1. A semiconductor device, characterized in that, have: Rectifying components; The determination circuit determines whether the rectifier element is on or off based on the voltage between a pair of output terminals of the rectifier element. An amplifier circuit that controls the rectifier element to be turned on / off based on the determination result of the determination circuit; as well as A voltage divider circuit is connected between the output terminal of the amplifier circuit or the input terminal of the rectifier element and one of the output terminals of the rectifier element. The determination circuit sets the voltage divided by the voltage divider circuit as either a positive or negative input.

2. The semiconductor device according to claim 1, characterized in that, The amplifier circuit consists of multiple stages of unit circuits that connect the output terminals of the preceding stage circuit to the input terminals of the following stage circuit. The multi-level unit circuits are circuits with drain-grounded structures composed of N-channel MOSFETs and P-channel MOSFETs connected in series between the positive and negative power supplies.

3. The semiconductor device according to claim 2, characterized in that, The final stage of the amplifier circuit has an N-channel depletion-type MOSFET.

4. The semiconductor device according to claim 2, characterized in that, have: A source-grounded driver is connected in parallel with the amplifier circuit.

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