State detection device for a switching circuit

Abstract

A state detection device of a switching circuit is provided. A processing section makes a first pulse signal different from a second pulse signal. The processing section outputs each pulse signal in such a manner that the relationship between the first pulse signal and the second pulse signal becomes a relationship in which only a part of the on period of the first pulse signal and at least a part of the on period of the second pulse signal overlap each other to have a common on period. The processing section sets, as a first condition, the period during which the high level of a switch input signal is in an on instruction state of a switch to be the same as the on period obtained by removing the common on period of the first pulse signal and the second pulse signal from the on period of the first pulse signal. The processing section sets, as a second condition, the period during which the high level of the switch input signal is in an off instruction state of the switch to be the same as the on period of the first pulse signal. The processing section determines that an electronic component is malfunctioning if at least either one of the first condition and the second condition is not satisfied.

Description

Technical Field

[0001] This disclosure relates to a state detection device for switching circuits. Background Technology

[0002] Previously, methods were known to detect faults in electronic components based on whether the input signals of switching circuits from multiple systems differed. However, this resulted in a large circuit structure when multiple systems had switching contacts. Therefore, even with a circuit structure having only one system's switching contacts, it is desirable to accurately detect faults in electronic components.

[0003] Conventionally, switch input detection circuits are known, for example, that include a connection control unit disposed between a reference potential point (ground) and a switch, and a potential detection unit disposed between a power supply and a switch (see, for example, Patent Document 1). The connection control unit controls the potential of the first terminal side of the switch based on whether the switch is turned on or off. The potential detection unit detects the potential of the second terminal side of the switch. This switch input detection circuit detects whether the switch is turned on or off based on an interruption detection signal used to determine the state of the connection control unit and the potential of the second terminal side of the switch detected by the potential detection unit (switch input signal).

[0004] Conventionally, electronic devices are known, for example, that include a power supply circuit and a switch state determination circuit disposed between a power source and a switch (see, for example, Patent Document 2). These electronic devices detect the state of the switch and whether there is any abnormality in the power supply circuit by comparing a control pulse supplied to the power supply circuit for controlling the power source with a switch input signal detected by the switch state determination circuit.

[0005] Patent Document 1: Japanese Patent Application Publication No. 6-177726

[0006] Patent Document 2: Japanese Patent Application Publication No. 2015-201411 Summary of the Invention

[0007] However, in technologies related to the state detection of switching circuits, in addition to detecting the on and off states of the switch, it is also desirable to accurately detect whether there are faults in various electronic components of the switching circuit. For example, in the aforementioned prior art switch input detection circuits or electronic devices, only the presence or absence of specific abnormalities such as abnormal switch connections or adhesions in the power supply circuit is detected, resulting in the problem that it is impossible to sufficiently detect whether there are faults in electronic components.

[0008] The purpose of this disclosure is to provide a status detection device for switching circuits that can accurately detect whether electronic components are faulty.

[0009] In order to solve the above-mentioned problems and achieve this objective, the present disclosure adopts the following approach.

[0010] A state detection device for a switching circuit according to one aspect of this disclosure includes: a switch; a first drive circuit connected between a first terminal of the switch and a power supply, which switches the conduction state with the power supply according to a first pulse signal; a second drive circuit connected between a second terminal of the switch and a reference potential point, which switches the conduction state with the reference potential point according to a second pulse signal; a switch input detection circuit connected between the first terminal of the switch and the first drive circuit, which outputs a switch input signal related to a signal input to the switch; and a processing unit that supplies the first pulse signal to the first drive circuit, supplies the second pulse signal to the second drive circuit, and receives the switch input signal from the switch input detection circuit, wherein the processing unit makes the first pulse signal different from the second pulse signal, and makes only a portion of the on-time of the first pulse signal... The processing unit determines that the switch is in an on state when at least a portion of the on period of the first pulse signal and the second pulse signal overlaps with each other. The processing unit uses the following conditions as a first condition: when the switch is on, the high-level period of the switch input signal is the same as the on period obtained by subtracting the common on period of the first pulse signal and the second pulse signal from the on period of the first pulse signal. The processing unit uses the following conditions as a second condition: when the switch is off, the high-level period of the switch input signal is the same as the on period of the first pulse signal. If the first condition is met, the processing unit determines that the switch is on. If the second condition is met, the processing unit determines that the switch is off. If neither the first nor the second condition is met, the processing unit determines that there is a fault in the electronic components.

[0011] In the state detection device of the switch circuit described above, the switch input detection circuit sets the switch input signal to a high level when the switch is in a first combination of an indication state of the switch being off and an indication state of the first driving circuit being on; the switch input detection circuit sets the switch input signal to a high level when the switch is in a second combination of an indication state of the switch being on, an indication state of the first driving circuit being on, and an indication state of the second driving circuit being off; and the switch input detection circuit sets the switch input signal to a low level when the combination of the indication state of the switch being on and off and the indication state of the first driving circuit and the indication state of the second driving circuit being on and off is a combination other than the first combination and the second combination.

[0012] The state detection device for the switch circuit described above may include a monitoring circuit connected between the second terminal of the switch and the output terminal of the first drive circuit and the second drive circuit. The monitoring circuit outputs a monitoring signal corresponding to the conduction state of the reference potential point, which corresponds to the operation of the second drive circuit. The processing unit uses the high-level period of the monitoring signal received from the monitoring circuit being the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal as a third condition. If at least one of the first condition, the second condition, and the third condition is not met, the processing unit determines that there is a fault in the electronic components.

[0013] In the state detection device of the switching circuit described above, the monitoring circuit sets the monitoring signal to a high level when it is a third combination of the conducting state of the first driving circuit and the non-conducting state of the second driving circuit, and sets the monitoring signal to a low level when the combination of the conducting and non-conducting states of the first driving circuit and the second driving circuit is a combination other than the third combination.

[0014] A state detection device for a switching circuit according to one aspect of this disclosure includes: a switch; a first drive circuit connected between a first terminal of the switch and a power supply, which switches the conduction state with the power supply according to a first pulse signal; a second drive circuit connected between a second terminal of the switch and a reference potential point, which switches the conduction state with the reference potential point according to a second pulse signal; a switch input detection circuit connected between the second terminal of the switch and the second drive circuit, which outputs a switch input signal related to a signal input to the switch; and a processing unit that supplies the first pulse signal to the first drive circuit, supplies the second pulse signal to the second drive circuit, and receives the switch input signal from the switch input detection circuit, wherein the processing unit makes the first pulse signal different from the second pulse signal, and makes only a portion of the on-time of the second pulse signal... The processing unit determines that the switch is in an on state when at least a portion of the on period of the first pulse signal overlaps with the common on period of the second pulse signal. The processing unit uses the following conditions as a first condition: when the switch is on, the low-level period of the switch input signal is the same as the on period obtained by subtracting the common on period of the first and second pulse signals from the on period of the second pulse signal. The processing unit also uses the following conditions as a second condition: when the switch is off, the low-level period of the switch input signal is the same as the on period of the second pulse signal. If the first condition is met, the processing unit determines that the switch is on. If the second condition is met, the processing unit determines that the switch is off. If neither the first nor the second condition is met, the processing unit determines that there is a fault in the electronic components.

[0015] In the state detection device of the switch circuit described above, the switch input detection circuit sets the switch input signal to a low level when the switch is in a first combination of an indication state of the switch being off and an indication state of the second driving circuit being on; the switch input detection circuit sets the switch input signal to a low level when the switch is in a second combination of an indication state of the switch being on, an indication state of the first driving circuit being off, and an indication state of the second driving circuit being on; and the switch input detection circuit sets the switch input signal to a high level when the combination of the indication state of the switch being on and off and the indication state of the first driving circuit and the indication state of the second driving circuit being on and off is a combination other than the first combination and the second combination.

[0016] The state detection device for the switch circuit described above may include a monitoring circuit connected between the first terminal of the switch and the output terminal of the second drive circuit and the first drive circuit. The monitoring circuit outputs a monitoring signal corresponding to the conduction state of the power supply, which corresponds to the operation of the first drive circuit. The processing unit uses the low-level period of the monitoring signal received from the monitoring circuit as a third condition, which is the same as the on-time obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal. If at least one of the first, second, and third conditions is not met, the processing unit determines that there is a fault in the electronic components.

[0017] In the state detection device of the switching circuit described above, the monitoring circuit sets the monitoring signal to a low level when the monitoring circuit is in a third combination of the non-conducting state of the first driving circuit and the conducting state of the second driving circuit, and sets the monitoring signal to a high level when the combination of the conducting and non-conducting states of the first driving circuit and the second driving circuit is a combination other than the third combination.

[0018] The state detection device for the switch circuit described above includes a processing unit that determines whether a first condition and a second condition based on a first pulse signal, a second pulse signal, a switch input signal, and the on / off state of the switch are met, thereby enabling accurate detection of faults in the electronic components of the switch circuit. Attached Figure Description

[0019] Figure 1 This is a structural diagram of the state detection device for the switching circuit according to an embodiment of the present disclosure.

[0020] Figure 2 This is a circuit structure diagram of the state detection device for the switching circuit according to an embodiment of the present disclosure.

[0021] Figure 3 This diagram illustrates an example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, and the on / off state of the switch in the state detection device of the switch circuit according to an embodiment of the present disclosure.

[0022] Figure 4 This is a structural diagram of the state detection device for a switching circuit according to a first variation of the embodiments of this disclosure.

[0023] Figure 5 This is a circuit structure diagram of the state detection device of the switching circuit of the first variation of the embodiments of this disclosure.

[0024] Figure 6 This is a diagram illustrating a first example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch in the state detection device of the first modified embodiment of the present disclosure. It is also a diagram showing when the first pulse signal Pulse1 and the second pulse signal Pulse2 are pulse signals with the same period and different duty cycles.

[0025] Figure 7 This is a diagram illustrating a second example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch in the state detection device of the first modified embodiment of the present disclosure. It is also a diagram when the first pulse signal Pulse1 and the second pulse signal Pulse2 are pulse signals of different frequencies.

[0026] Figure 8 This is a diagram illustrating a third example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch in the state detection device of the first modified embodiment of the present disclosure. It is a diagram when the first pulse signal Pulse1 and the second pulse signal Pulse2 are pulse signals with the same period and different phases.

[0027] Figure 9 This is a structural diagram of the state detection device for a switching circuit according to a second variation of the embodiments of this disclosure.

[0028] Figure 10 This is a structural diagram of the state detection device for a switching circuit according to a third variation of the embodiments of this disclosure.

[0029] Figure 11 This is a circuit structure diagram of the state detection device for the switching circuit of the third variation of the embodiments of this disclosure.

[0030] Figure 12 This diagram illustrates an example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, and the on / off state of the switch in the state detection device of the switch circuit of the third variation of the present disclosure.

[0031] Figure 13 This is a structural diagram of the state detection device for the switching circuit of the fourth variation of the embodiments of this disclosure.

[0032] Figure 14This is a circuit structure diagram of the state detection device for the switching circuit of the fourth variation of the embodiments of this disclosure.

[0033] Figure 15 This is a diagram illustrating an example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch in the state detection device of the fourth variation of the embodiment of this disclosure.

[0034] Figure 16 This is a perspective view showing the structure of a shift lever device of any one of the state detection devices of the switching circuit of the embodiments, first modification, second modification, third modification and fourth modification of the present disclosure. Detailed Implementation

[0035] Hereinafter, the state detection device of the switching circuit according to the present disclosure will be described with reference to the accompanying drawings.

[0036] Figure 1 This is a structural diagram of the state detection device 10 of the switching circuit in the embodiment. Figure 2 This is a circuit diagram of the state detection device 10 of the switching circuit in the embodiment.

[0037] like Figure 1 as well as Figure 2 As shown, the state detection device 10 of the switching circuit in the embodiment includes, for example, a switch 11, a power supply 12, a reference potential point 13, a first drive circuit 14, a second drive circuit 15, a switch input detection circuit 16, and a processing unit 17.

[0038] Switch 11 is, for example, a sliding contact type mechanical switch.

[0039] Power supply 12 is, for example, a DC power supply.

[0040] Reference potential point 13 is, for example, a reference point with a predetermined reference potential such as a 0V potential grounded to ground.

[0041] The first drive circuit 14 is connected, for example, between the first terminal 11a of the switch 11 and the power supply 12.

[0042] like Figure 2 As shown, the first driving circuit 14 includes, for example, a first transistor 21 and a second transistor 22, a first base resistor 23 and a second base resistor 24, a first base-emitter resistor 25 and a second base-emitter resistor 26.

[0043] The first transistor 21 is, for example, an NPN transistor. The emitter of the first transistor 21 is connected to the reference potential point 13.

[0044] The second transistor 22 is, for example, a PNP transistor. The emitter of the second transistor 22 is connected to the power supply 12. The collector of the second transistor 22 is connected to the first terminal 11a of the switch 11, for example, via the pull-up resistor 31 described later.

[0045] The first base resistor 23 is connected between the first signal output terminal 17a of the processing unit 17 and the base of the first transistor 21. The first signal output terminal 17a of the processing unit 17 is the terminal that outputs the first pulse signal Pulse1, which will be described later.

[0046] The second base resistor 24 is connected to the base of the second transistor 22 and the collector of the first transistor 21.

[0047] The first base-emitter resistor 25 is connected between the base and emitter of the first transistor 21.

[0048] The second base-emitter resistor 26 is connected between the base and emitter of the second transistor 22.

[0049] The first driving circuit 14 drives the power supply 12 on the side of the second transistor 22, for example, through the first transistor 21. The first transistor 21 switches between on and off based on a first pulse signal Pulse1 input from the first signal output terminal 17a of the processing unit 17 to the first base resistor 23. The first pulse signal Pulse1 is a voltage pulse signal based on a predetermined high-level output voltage for on (ON) and a predetermined low-level output voltage for off (OFF). The second transistor 22 switches its conduction state with the power supply 12 by switching it on and off through the first transistor 21. For example, when the first transistor 21 is on, current flows from the emitter through the base to the first transistor 21, thereby switching the second transistor 22 from off to on.

[0050] The second drive circuit 15 is connected, for example, between the second terminal 11b of the switch 11 and the reference potential point 13.

[0051] The second driving circuit 15 includes, for example, a third transistor 27, a third base resistor 28, and a third base-emitter resistor 29.

[0052] The third transistor 27 is, for example, an NPN transistor. The emitter of the third transistor 27 is connected to the reference potential point 13. The collector of the third transistor 27 is connected to the second terminal 11b of the switch 11.

[0053] The third base resistor 28 is connected between the second signal output terminal 17b of the processing unit 17 and the base of the third transistor 27. The second signal output terminal 17b of the processing unit 17 is the terminal that outputs the second pulse signal Pulse2, which will be described later.

[0054] The third base-emitter resistor 29 is connected between the base and emitter of the third transistor 27.

[0055] The second drive circuit 15 drives the reference potential point 13, for example, via a third transistor 27. The third transistor 27 switches between on and off states based on a second pulse signal Pulse2 input from the second signal output terminal 17b of the processing unit 17 to the third base resistor 28, thereby switching the conduction state with respect to the reference potential point 13. The second pulse signal Pulse2 is a voltage pulse signal based on a predetermined high-level output voltage for on (ON) and a predetermined low-level output voltage for off (OFF).

[0056] The switch input detection circuit 16 is connected between the first terminal 11a of the switch 11 and the first drive circuit 14. The switch input detection circuit 16 includes, for example, a pull-up resistor 31, an input protection resistor 32, and a pull-down resistor 33.

[0057] Pull-up resistor 31 is connected, for example, between the collector of the second transistor 22 and the first terminal 11a of the switch 11. Pull-up resistor 31, for example, makes the switch input signal SWin (described later) high (H) when the switch 11 is indicated to be open and the first drive circuit 14 is in the on state.

[0058] The input protection resistor 32 is connected between the first signal input terminal 17c of the processing unit 17 and the first terminal 11a of the switch 11. The first signal input terminal 17c of the processing unit 17 is a terminal that receives the switch input signal SWin, which will be described later. The input protection resistor 32 protects the processing unit 17, for example, against overvoltage inputs caused by surge noise, etc.

[0059] Pull-down resistor 33 is connected between the first signal input terminal 17c of the processing unit 17 and the reference potential point 13. Pull-down resistor 33, for example, prevents the switch input signal SWin from becoming an open circuit output when the potential of either the power supply 12 or the reference potential point 13 cannot be transmitted.

[0060] The switch input detection circuit 16 outputs a switch input signal SWin, which is related to the signal input to the switch 11, to the first signal input terminal 17c of the processing unit 17. The switch input signal SWin is a voltage pulse signal based on high (H) and low (L) voltage levels. The high level (H) of the switch input signal SWin is a voltage greater than a predetermined minimum high-level input voltage that the processing unit 17 can recognize. The low level (L) of the switch input signal SWin is a voltage less than a maximum low-level input voltage that the processing unit 17 can recognize.

[0061] Table 1 below shows the combinations of high and low levels of the switch input signal SWin, the on and off indication states of switch 11, the on and off states of the first drive circuit 14, and the on and off states of the second drive circuit 15.

[0062] As shown in Table 1 below, the switch input detection circuit 16 sets the switch input signal SWin to a high level when the switch 11 is in the off state and the first drive circuit 14 is in the on state (first combination). The switch input detection circuit 16 sets the switch input signal SWin to a high level when the switch 11 is in the on state, the first drive circuit 14 is in the on state, and the second drive circuit 15 is in the off state (second combination). The switch input detection circuit 16 sets the switch input signal SWin to a low level in combinations other than the first and second combinations shown in Table 1 below.

[0063] [Table 1]

[0064]

[0065] The processing unit 17 may include, for example, a software functional unit that functions by executing a predetermined program by a processor such as a CPU (Central Processing Unit). The software functional unit is an ECU (Electronic Control Unit) that includes a processor such as a CPU, ROM (Read Only Memory) for storing programs, RAM (Random Access Memory) for temporarily storing data, and electronic circuitry such as timers. Furthermore, a portion of the processing unit 17 may also include integrated circuits such as LSI (Large Scale Integration).

[0066] The processing unit 17 supplies a first pulse signal Pulse1 to the first drive circuit 14 and a second pulse signal Pulse2 to the second drive circuit 15, and receives a switch input signal SWin from the switch input detection circuit 16.

[0067] The operation of the state detection device 10 of the switching circuit in the following embodiment will be explained.

[0068] Figure 3 This is a diagram illustrating an example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, and the on / off state of the switch 11 in the state detection device 10 of the switch circuit in the embodiment.

[0069] The processing unit 17 determines whether there is a fault in the electronic components of the switch circuit status detection device 10 based on the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, and the on / off state of the switch 11. Furthermore, faults in the electronic components of the switch circuit status detection device 10 do not include, for example, poor contact of the switch 11.

[0070] When determining whether there is a fault in the electronic components of the switching circuit status detection device 10, the processing unit 17 makes the first pulse signal Pulse1 and the second pulse signal Pulse2 different. The processing unit 17 outputs each pulse signal Pulse1 and Pulse2 in such a way that the relationship between the first pulse signal Pulse1 and the second pulse signal Pulse2 is such that they have a common on-time. The common on-time is an on-time period in which only a portion of the on-time of the first pulse signal Pulse1 overlaps with at least a portion of the on-time of the second pulse signal Pulse2.

[0071] The processing unit 17 uses the following as a first condition: the high-level period of the switch input signal SWin indicating that the switch 11 is on is the same as the on-time obtained by subtracting the common on-time period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on-time period of the first pulse signal Pulse1. The processing unit 17 detects the on-state of the switch 11 under the first condition.

[0072] The processing unit 17 uses the high-level period of the switch input signal SWin, which indicates that the switch 11 is open, being the same as the on-time period of the first pulse signal Pulse1 as a second condition. The processing unit 17 detects the open state of the switch 11 under the second condition.

[0073] If at least one of the first condition and the second condition is not met, the processing unit 17 determines that there is a fault in the electronic component in the state detection device 10 of the switching circuit.

[0074] For example, Figure 3 The first pulse signal Pulse1 and the second pulse signal Pulse2 shown are pulse signals with the same period but different duty cycles. The common ON period of the first pulse signal Pulse1 and the second pulse signal Pulse2 is the period from time t1 to time t2 when the switch 11 is OFF, and the period from time t5 to time t6 when the switch 11 is ON.

[0075] If the state detection device 10 of the switching circuit is normal, the high level (H) period of the switch input signal SWin when the switch 11 is OFF is the same as the on period of the first pulse signal Pulse1 (the period from time t1 to time t3) (first condition). The high level (H) period of the switch input signal SWin when the switch 11 is ON is the same as the on period (the period from time t6 to time t7) obtained by subtracting the common on period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on period of the first pulse signal Pulse1 (second condition).

[0076] As described above, the switching circuit state detection device 10 according to the embodiment, by having a processing unit 17 that determines whether a first condition and a second condition are met, can accurately detect whether the electronic components of the switching circuit state detection device 10 are faulty.

[0077] (Modified Example)

[0078] Hereinafter, variations of the embodiments will be described. Furthermore, the same reference numerals will be used for parts that are the same as in the embodiments described above, and descriptions will be omitted or simplified.

[0079] Figure 4 This is a structural diagram of the state detection device 40 of the switching circuit in the first variation of the implementation method. Figure 5 This is a circuit structure diagram of the state detection device 40 of the switching circuit in the first variation of the implementation method.

[0080] like Figure 4 and Figure 5 As shown, the state detection device 40 of the switch circuit in the first modified embodiment includes, for example, a switch 11, a power supply 12, a reference potential point 13, a first drive circuit 14, a second drive circuit 15, a switch input detection circuit 16, a processing unit 17, and a monitoring circuit 41.

[0081] The monitoring circuit 41 is connected between the second terminal 11b of the switch 11 and the collector of the second transistor 22 (i.e., the output terminal of the first drive circuit 14) and the second drive circuit 15. The monitoring circuit 41 includes, for example, a pull-up resistor 51, an input protection resistor 52, and a pull-down resistor 53.

[0082] Pull-up resistor 51 is connected between the collector of the second transistor 22 and the collector of the third transistor 27. Pull-up resistor 51, for example, makes the monitoring signal PMon (described later) high (H) when the switch 11 is open, the first drive circuit 14 is on, and the second drive circuit 15 is off.

[0083] The input protection resistor 52 is connected between the second signal input terminal 17d of the processing unit 17 and the second terminal 11b of the switch 11. The second signal input terminal 17d of the processing unit 17 is a terminal that receives the monitoring signal PMon, which will be described later. The input protection resistor 52 protects the processing unit 17, for example, against overvoltage inputs caused by surge noise, etc.

[0084] Pull-down resistor 53 is connected between the second signal input terminal 17d of the processing unit 17 and the reference potential point 13. Pull-down resistor 53, for example, prevents the monitoring signal PMon from becoming an open circuit output when the potential of either the power supply 12 or the reference potential point 13 cannot be transmitted.

[0085] The monitoring circuit 41 outputs a monitoring signal PMon, corresponding to the conduction state of the reference potential point 13 and corresponding to the operation of the second drive circuit 15, to the second signal input terminal 17d of the processing unit 17. The monitoring signal PMon is a voltage pulse signal based on a high level (H) and a low level (L) of voltage. The high level (H) of the monitoring signal PMon is a voltage greater than a predetermined minimum high-level input voltage that the processing unit 17 can recognize as a high level of input voltage. The low level (L) of the monitoring signal PMon is a voltage less than a maximum low-level input voltage that the processing unit 17 can recognize as a low level of input voltage.

[0086] Table 2 below shows the combinations of high and low levels of the monitoring signal PMon, the on and off states of the first drive circuit 14, and the on and off states of the second drive circuit 15.

[0087] As shown in Table 2 below, in the case of the first drive circuit 14 being in the on state and the second drive circuit 15 being in the off state (in the case of the third combination), the monitoring circuit 41 sets the monitoring signal PMon to a high level. In the cases other than the third combination mentioned above in Table 2 below, the monitoring circuit 41 sets the monitoring signal PMon to a low level.

[0088] [Table 2]

[0089]

[0090] The operation of the state detection device 40 of the switching circuit in the first modified embodiment will be described below.

[0091] Figure 6 This is a first example illustrating the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch 11 in the state detection device 40 of the switch circuit of the first variant of the embodiment. Figure 6This is a diagram showing the first pulse signal Pulse1 and the second pulse signal Pulse2 as pulse signals with the same period but different duty cycles.

[0092] The processing unit 17 of the first modification determines whether there is a fault in the electronic components in the switch circuit state detection device 40 based on the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch 11.

[0093] In the first modified example, when determining whether there is a fault in the electronic components of the switching circuit state detection device 40, the processing unit 17, in the same manner as in the embodiment described above, makes the first pulse signal Pulse1 and the second pulse signal Pulse2 different. The processing unit 17 outputs each pulse signal Pulse1 and Pulse2 in such a way that the relationship between the first pulse signal Pulse1 and the second pulse signal Pulse2 is such that they have a common on-time. The common on-time is an on-time period in which only a portion of the on-time of the first pulse signal Pulse1 overlaps with at least a portion of the on-time of the second pulse signal Pulse2.

[0094] The processing unit 17 sets the high-level period of the monitoring signal PMon as the same as the turn-on period obtained by subtracting the common turn-on period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the turn-on period of the first pulse signal Pulse1 as the third condition.

[0095] If at least one of the first, second, and third conditions is not met, the processing unit 17 determines that there is a fault in the electronic components in the state detection device 40 of the switching circuit.

[0096] like Figure 6 As shown, the common ON period of the first pulse signal Pulse1 and the second pulse signal Pulse2 is the period from time t1 to time t2 when the switch 11 is OFF, and the period from time t5 to time t6 when the switch 11 is ON.

[0097] If the state detection device 40 of the switching circuit is normal, the high level (H) period of the monitoring signal PMon is the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on-time period of the first pulse signal Pulse1 (the period from time t2 to time t3 and the period from time t6 to time t7) (third condition).

[0098] Figure 7This is a second example illustrating the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch in the state detection device 40 of the switch circuit in the first variation of the embodiment. Figure 7 This is a diagram showing the first pulse signal Pulse1 and the second pulse signal Pulse2 as pulse signals with different frequencies.

[0099] like Figure 7 As shown, the common ON period of the first pulse signal Pulse1 and the second pulse signal Pulse2 is the ON period of the first pulse signal Pulse1 during the period from time t1 to time t2 when the switch 11 is OFF, and the ON period of the first pulse signal Pulse1 during the period from time t3 to time t4 when the switch 11 is ON.

[0100] If the state detection device 40 of the switching circuit is normal, the high level (H) period of the switch input signal SWin when the switch 11 is open (OFF) is the same as the on period of the first pulse signal Pulse1 (first condition). The high level (H) period of the switch input signal SWin when the switch 11 is on (ON) is the same as the on period of the first pulse signal Pulse1 obtained by subtracting the common on period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on period of the first pulse signal Pulse1, that is, the on period of the first pulse signal Pulse1 from time t4 to time t5 (second condition).

[0101] If the state detection device 40 of the switching circuit is normal, the high level (H) period of the monitoring signal PMon is the same as the on-time period of the first pulse signal Pulse1 in each of the periods from time t2 to time t3 and from time t4 to time t5 (third condition).

[0102] Figure 8 This is a third example illustrating the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch 11 in the state detection device 40 of the switch circuit of the first variant of the embodiment. Figure 8 This is a diagram showing the first pulse signal Pulse1 and the second pulse signal Pulse2 as pulse signals with the same period but different phases.

[0103] like Figure 8As shown, the common ON period of the first pulse signal Pulse1 and the second pulse signal Pulse2 is the period from time t2 to time t3 when the switch 11 is OFF, and the period from time t6 to time t7 when the switch 11 is ON.

[0104] If the state detection device 40 of the switching circuit is normal, the high level (H) period of the switch input signal SWin when the switch 11 is OFF is the same as the on period of the first pulse signal Pulse1 (the period from time t2 to time t4) (first condition). The high level (H) period of the switch input signal SWin when the switch 11 is ON is the same as the on period (the period from time t7 to time t8) obtained by subtracting the common on period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on period of the first pulse signal Pulse1 (second condition).

[0105] If the state detection device 40 of the switching circuit is normal, the high level (H) period of the monitoring signal PMon is the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on-time period of the first pulse signal Pulse1 (the period from time t3 to time t4 and the period from time t7 to time t8) (third condition).

[0106] Furthermore, the detection methods for the first, second, and third conditions are not limited to detecting the same high-level (H) period that includes the timing of the changes in the high and low levels of each signal SWin and PMon. For example, it could be a method that detects the same high-level (H) period per unit time, or it could be a method that detects the same low-level (L) period other than the high-level (H) period.

[0107] According to the first modification, in addition to the first and second conditions, the processing unit 17 also determines whether a third condition based on the monitoring signal PMon is met, thereby accurately determining whether the electronic components of the second drive circuit 15 are faulty in states such as the open state of the switch 11. Furthermore, even if the electronic components in the switch input detection circuit 16 malfunction, faults in the electronic components of the first drive circuit 14 can also be detected.

[0108] Furthermore, in the above-described embodiments and the first modified example, the switch input detection circuit 16 and the monitoring circuit 41 are provided with pull-down resistors 33 and 53, respectively, but this is not a limitation. For example, in the input circuit of the processing unit 17, pull-down resistors connected between the first signal input terminal 17c and the second signal input terminal 17d and the reference potential point 13 may also be provided.

[0109] Furthermore, in the above-described embodiments and the first variation, the state detection devices 10 and 40 of the switching circuit are provided to have a common processing unit 17, but this is not a limitation. For example, the state detection devices 10 and 40 of the switching circuit may each have multiple processing units with different processing operations.

[0110] Figure 9 This is a structural diagram of the state detection device 10A of the switching circuit in the second variation of the embodiment.

[0111] like Figure 9 As shown, the state detection device 10A of the switch circuit in the second modification includes, for example, a processing unit 17 having a first processing unit 17A and a second processing unit 17B. The first processing unit 17A supplies a first pulse signal Pulse1 to the first drive circuit 14 and a second pulse signal Pulse2 to the second drive circuit 15. The second processing unit 17B receives the switch input signal SWin from the switch input detection circuit 16.

[0112] In the state detection device 10A of the switching circuit in the second modification, for example, the presence or absence of faults in electronic components can be determined by either the first processing device 17A or the second processing device 17B that mutually transmits and receives information, or by other processing devices that comprehensively control the first processing device 17A and the second processing device 17B.

[0113] Furthermore, for example, in the case where the state detection device 40 of the switch circuit in the first modified example described above is equipped with a first processing device 17A and a second processing device 17B, the second processing device 17B can receive the switch input signal SWin from the switch input detection circuit 16 and the monitoring signal PMon from the monitoring circuit 41.

[0114] Furthermore, in the above embodiment, the switch input detection circuit 16 is connected to the first terminal 11a side of the switch 11, but it is not limited to this. For example, the switch input detection circuit 16 can also be connected to the second terminal 11b side of the switch 11.

[0115] Figure 10 This is a structural diagram of the state detection device 10B of the switching circuit in the third variation of the implementation method. Figure 11 This is a circuit diagram of the state detection device 10B of the switching circuit in the third variation of the implementation method.

[0116] like Figure 10 and Figure 11 As shown, the state detection device 10B of the switch circuit in the third modified example includes, for example, a switch 11, a power supply 12, a reference potential point 13, a first drive circuit 14, a second drive circuit 15, a switch input detection circuit 16A, and a processing unit 17.

[0117] The switch input detection circuit 16A is connected between the second terminal 11b of the switch 11 and the power supply 12 and the second drive circuit 15. The switch input detection circuit 16A includes, for example, a pull-up resistor 54, an input protection resistor 55, and a pull-down resistor 56.

[0118] The pull-up resistor 54 is connected, for example, between the power supply 12 and the first signal input terminal 17c of the processing unit 17. The pull-up resistor 54 prevents the switch input signal SWin from becoming an open-circuit output when the potential of either the power supply 12 or the reference potential point 13 cannot be transmitted.

[0119] An input protection resistor 55 is connected between the first signal input terminal 17c of the processing unit 17 and the second terminal 11b of the switch 11. The input protection resistor 55 protects the processing unit 17, for example, against overvoltage inputs caused by surge noise, etc.

[0120] Pull-down resistor 56 is connected between the collector of third transistor 27 and the second terminal 11b of switch 11. Pull-down resistor 56, for example, makes the switch input signal SWin low (L) when the switch 11 is open and the second drive circuit 15 is on.

[0121] In the third variation, the switch input detection circuit 16A outputs the switch input signal SWin, which is related to the signal input to the switch 11, to the first signal input terminal 17c of the processing unit 17.

[0122] In the third variation, the switch input signal SWin is a voltage pulse signal based on a high level (H) and a low level (L) of voltage. The high level (H) of the switch input signal SWin is a voltage greater than the predetermined minimum high-level input voltage that the processing unit 17 can recognize as a high level of input voltage. The low level (L) of the switch input signal SWin is a voltage less than the maximum low-level input voltage that the processing unit 17 can recognize as a low level of input voltage.

[0123] Table 3 below shows the combinations of high and low levels of the switch input signal SWin, the on and off indication states of switch 11, the on and off states of the first drive circuit 14, and the on and off states of the second drive circuit 15.

[0124] As shown in Table 3 below, in the third variation, the switch input detection circuit 16A sets the switch input signal SWin to a low level when the switch 11 is in the off state and the second drive circuit 15 is in the on state (the fourth combination). When the switch 11 is in the on state, the first drive circuit 14 is in the off state, and the second drive circuit 15 is in the on state (the fifth combination), the switch input detection circuit 16A sets the switch input signal SWin to a low level. In combinations other than the fourth and fifth combinations listed in Table 3 below, the switch input detection circuit 16A sets the switch input signal SWin to a high level.

[0125] [Table 3]

[0126]

[0127] Figure 12 This is an example of the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, and the on / off state of the switch 11 in the state detection device 10B of the switch circuit in the third variation of the embodiment.

[0128] In the third variation, the processing unit 17 determines whether there is a fault in the electronic components of the switch circuit state detection device 10B based on the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, and the on / off state of the switch 11.

[0129] When determining whether there is a fault in the electronic components of the switching circuit status detection device 10B, the processing unit 17 makes the first pulse signal Pulse1 and the second pulse signal Pulse2 different. The processing unit 17 outputs each pulse signal Pulse1 and Pulse2 in such a way that the relationship between the first pulse signal Pulse1 and the second pulse signal Pulse2 is such that they have a common on-time. The common on-time is an on-time period in which at least a portion of the on-time of the first pulse signal Pulse1 overlaps with only a portion of the on-time of the second pulse signal Pulse2.

[0130] The processing unit 17 uses the low-level period of the switch input signal SWin, which indicates that the switch 11 is on, as a fourth condition, which is the same as the on-time obtained by subtracting the common on-time period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on-time period of the second pulse signal Pulse2. The processing unit 17 detects the on-state of the switch 11 under the fourth condition.

[0131] The processing unit 17 uses the low-level period of the switch input signal SWin, which indicates that switch 11 is open, being the same as the on-time period of the second pulse signal Pulse2 as a fifth condition. The processing unit 17 detects the open state of switch 11 under the fifth condition.

[0132] If at least one of the fourth and fifth conditions is not met, the processing unit 17 determines that there is a fault in the electronic components in the state detection device 10B of the switching circuit.

[0133] For example, Figure 12 The first pulse signal Pulse1 and the second pulse signal Pulse2 shown are pulse signals with the same period but different duty cycles. The common ON period of the first pulse signal Pulse1 and the second pulse signal Pulse2 is the period from time t1 to time t2 when the switch 11 is OFF, and the period from time t5 to time t6 when the switch 11 is ON.

[0134] If the state detection device 10B of the switching circuit is normal, the low level (L) period of the switch input signal SWin when the switch 11 is open (OFF) is the same as the on period of the second pulse signal Pulse2 (the period from time t1 to time t3) (fourth condition). The low level (L) period of the switch input signal SWin when the switch 11 is on (ON) is the same as the on period (the period from time t6 to time t7) obtained by subtracting the common on period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on period of the second pulse signal Pulse2 (fifth condition).

[0135] Furthermore, in the third modification described above, a circuit corresponding to the monitoring circuit 41 of the first modification described above may also be provided.

[0136] Figure 13 This is a structural diagram of the state detection device 40A of the switching circuit in the fourth variation of the embodiment. Figure 14 This is a circuit diagram of the state detection device 40A of the switching circuit in the fourth variation of the implementation.

[0137] like Figure 13 and Figure 14 As shown, the state detection device 40A of the switch circuit in the fourth variation of the embodiment includes, for example, a switch 11, a power supply 12, a reference potential point 13, a first drive circuit 14, a second drive circuit 15, a switch input detection circuit 16A, a processing unit 17, and a monitoring circuit 41A.

[0138] In the fourth variation, the monitoring circuit 41A is connected between the first terminal 11a of the switch 11 and the collector of the third transistor 27 (i.e., the output terminal of the second drive circuit 15) and the first drive circuit 14. The monitoring circuit 41A includes, for example, a pull-up resistor 57, an input protection resistor 58, and a pull-down resistor 59.

[0139] Pull-up resistor 57 is connected, for example, between power supply 12 and the second signal input terminal 17d of processing unit 17. Pull-up resistor 57 prevents the monitoring signal PMon from becoming an open circuit output when the potential of either power supply 12 or reference potential point 13 cannot be transmitted.

[0140] The input protection resistor 58 is connected between the second signal input terminal 17d of the processing unit 17 and the first terminal 11a of the switch 11. The input protection resistor 58 protects the processing unit 17, for example, against overvoltage inputs caused by surge noise, etc.

[0141] Pull-down resistor 59 is connected between the collector of third transistor 27 and the first terminal 11a of switch 11. Pull-down resistor 59, for example, causes the monitoring signal PMon to be low (L) when switch 11 is open, first drive circuit 14 is in a non-conducting state, and second drive circuit 15 is in a conducting state.

[0142] In the fourth variation, the monitoring circuit 41A outputs a monitoring signal PMon, corresponding to the on-state of the power supply 12 and the operation of the first drive circuit 14, to the second signal input terminal 17d of the processing unit 17. The monitoring signal PMon is a voltage pulse signal based on high (H) and low (L) voltage levels. The high level (H) of the monitoring signal PMon is a voltage greater than a predetermined minimum high-level input voltage that the processing unit 17 can recognize as a high-level input voltage. The low level (L) of the monitoring signal PMon is a voltage less than a maximum low-level input voltage that the processing unit 17 can recognize as a low-level input voltage.

[0143] Table 4 below shows the combinations of high and low levels of the monitoring signal PMon, the on and off states of the first drive circuit 14, and the on and off states of the second drive circuit 15.

[0144] As shown in Table 4 below, in the fourth variation, when the monitoring circuit 41A is in the off state of the first drive circuit 14 and the on state of the second drive circuit 15 (the sixth combination), the monitoring signal PMon is set to a low level. In combinations other than the sixth combination described in Table 4 below, the monitoring circuit 41A sets the monitoring signal PMon to a high level.

[0145] [Table 4]

[0146]

[0147] The operation of the state detection device 40A of the switching circuit in the fourth variation of the embodiment will be described below.

[0148] Figure 15 This example illustrates the correspondence between the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch 11 in the state detection device 40A of the switch circuit in the fourth variation of the embodiment. Figure 15 This is a diagram showing the first pulse signal Pulse1 and the second pulse signal Pulse2 as pulse signals with the same period but different duty cycles.

[0149] In the fourth variation, the processing unit 17 determines whether there is a fault in the electronic components of the switch circuit status detection device 40A based on the first pulse signal Pulse1, the second pulse signal Pulse2, the switch input signal SWin, the monitoring signal PMon, and the on / off state of the switch 11.

[0150] In the fourth variation, when determining whether there is a fault in the electronic components of the switching circuit state detection device 40A, the processing unit 17, similarly to the embodiment described above, makes the first pulse signal Pulse1 and the second pulse signal Pulse2 different. The processing unit 17 outputs each pulse signal Pulse1 and Pulse2 in such a way that the relationship between the first pulse signal Pulse1 and the second pulse signal Pulse2 is such that they have a common on-time. The common on-time is an on-time period in which at least a portion of the on-time of the first pulse signal Pulse1 overlaps with only a portion of the on-time of the second pulse signal Pulse2.

[0151] The processing unit 17 sets the low-level period of the monitoring signal PMon as the same as the turn-on period obtained by subtracting the common turn-on period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the turn-on period of the second pulse signal Pulse2 as the sixth condition.

[0152] If at least one of the fourth, fifth, and sixth conditions is not met, the processing unit 17 determines that there is a fault in the electronic components in the switching circuit status detection device 40A.

[0153] like Figure 15 As shown, the common ON period of the first pulse signal Pulse1 and the second pulse signal Pulse2 is the period from time t1 to time t2 when the switch 11 is OFF, and the period from time t5 to time t6 when the switch 11 is ON.

[0154] If the state detection device 40A of the switching circuit is normal, the low level (L) period of the monitoring signal PMon is the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal Pulse1 and the second pulse signal Pulse2 from the on-time period of the second pulse signal Pulse2 (the period from time t2 to time t3 and the period from time t6 to time t7) (sixth condition).

[0155] Furthermore, the detection methods for the fourth, fifth, and sixth conditions are not limited to detecting the same low-level (L) period during which the high and low levels of each signal SWin and PMon change. For example, it could be a method that detects the same low-level (L) period per unit time, or it could be a method that detects the same high-level (H) period other than the low-level (L) period.

[0156] Furthermore, in the above-described embodiments and variations, the state detection devices 10, 10A, 10B, 40, and 40A of the switch circuit include one switch 11, but are not limited to this. For example, the state detection devices 10, 10A, 10B, 40, and 40A of the switch circuit may also include multiple switches 11. In this case, for example, multiple switches 11 may each share a first drive circuit 14, a second drive circuit 15, a monitoring circuit 41, etc.

[0157] Furthermore, in the above-described embodiments and the second variation, the pull-up resistor 31 is connected to the collector of the second transistor 22, but this is not a limitation. For example, the pull-up resistor 31 can also be connected between the power supply 12 and the emitter of the second transistor 22.

[0158] Furthermore, in the third variation described above, the pull-down resistor 56 is connected to the collector of the third transistor 27, but this is not a limitation. For example, the pull-down resistor 56 can also be connected between the reference potential point 13 and the emitter of the third transistor 27.

[0159] Figure 13 This is a perspective view showing the structure of a shift lever device 60 having any one of the status detection devices 10, 10A, 10B, 40, and 40A of the switching circuit in the embodiments, the first modification, the second modification, the third modification, and the fourth modification.

[0160] The gear shift lever device 60 is mounted, for example, in a vehicle. The gear shift lever device 60 includes, for example, a gear shift lever 61, a lever bracket 62, a contact bracket 63, a base plate 71, and a plurality of contacts 72.

[0161] The shift lever 61 is, for example, a tilting type that tilts in two directions along a predetermined direction or a rotating type that rotates around an axis. The shift lever 61 is a so-called automatic return type, which automatically returns to the predetermined reference position or reference posture after the position or posture is changed by the operator from a predetermined reference position or reference posture.

[0162] The gear shift lever 61 has multiple states, such as switching between five states: reverse (R), neutral / reverse (NR), neutral (N), neutral / drive (ND), and drive (D). Reverse (R) is selected when the operator receives an instruction to reverse. Neutral / reverse (NR) is selected when the gear shift lever automatically returns to a predetermined reference position or posture after receiving an instruction to reverse. Drive (D) is selected when the gear shift lever automatically returns to a predetermined reference position or posture after receiving an instruction to drive forward. Neutral / drive (ND) is selected when the gear shift lever automatically returns to a predetermined reference position or posture after receiving an instruction to cut off power transmission.

[0163] The lever support 62 is connected to the base of the shift lever 61, for example, and moves in conjunction with the movement of the shift lever 61.

[0164] The contact bracket 63 holds the movable contact, for example, and is connected to the rod bracket 62, which moves the movable contact in conjunction with the movement of the rod bracket 62.

[0165] The substrate 71 has, for example, a plurality of contacts 72 arranged along a predetermined direction, such as five contacts 72 (R, NR, N, ND, D).

[0166] Any one of the multiple contacts 72, such as five contacts 72 (R, NR, N, ND, D), is connected to the movable contact of the contact bracket 63 by the displacement of the lever bracket 62 and the contact bracket 63 linked to the shift lever 61.

[0167] The multiple contacts 72 of the shift lever device 60 and the movable contact constitute the switch 11 in the state detection devices 10, 10A, 10B, 40, and 40A of the switching circuit. For example, the five contacts 72 (R, NR, N, ND, D) are the five first terminals 11a of the switch 11, and the movable contact is one second terminal 11b of the switch 11.

[0168] The embodiments disclosed herein are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention described in the patent protection scope and its equivalents.

[0169] The manner of this disclosure is as follows, for example.

[0170] <Postscript 1>

[0171] A state detection device for a switching circuit, comprising:

[0172] switch;

[0173] A first driving circuit is connected between the first terminal of the switch and the power supply, and switches the conduction state with the power supply according to the first pulse signal.

[0174] The second driving circuit is connected between the second terminal of the switch and the reference potential point, and switches the conduction state with the reference potential point according to the second pulse signal.

[0175] A switch input detection circuit, connected between the first terminal of the switch and the first drive circuit, outputs a switch input signal related to the signal input to the switch; and

[0176] The processing unit supplies the first pulse signal to the first driving circuit, supplies the second pulse signal to the second driving circuit, and receives the switch input signal from the switch input detection circuit.

[0177] The processing unit makes the first pulse signal different from the second pulse signal, and makes only a portion of the on-time of the first pulse signal and at least a portion of the on-time of the second pulse signal a common on-time that overlaps with each other.

[0178] The processing unit uses the condition that the high-level period of the switch input signal in the state indicating that the switch is on is the same as the on-time obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal.

[0179] The processing unit uses the fact that the high-level period of the switch input signal when the switch is in the off state is the same as the on period of the first pulse signal as a second condition.

[0180] If the first condition is met, the processing unit determines that the switch is in the ON state.

[0181] If the second condition is met, the processing unit determines that the switch is in the off state.

[0182] If at least one of the first condition and the second condition is not met, the processing unit determines that there is a fault in the electronic components.

[0183] <Appendix 2>

[0184] According to the state detection device of the switching circuit described in Appendix 1, wherein...

[0185] When the switch input detection circuit is in a first combination of the indication state of the switch being open and the indication state of the first drive circuit being on, the switch input signal is set to a high level.

[0186] The switch input detection circuit sets the switch input signal to a high level when the switch is in a second combination of the indicated state of the switch being on, the state of the first driving circuit being on, and the state of the second driving circuit being off.

[0187] When the combination of the switch's on / off indication state and the respective on / off states of the first and second driving circuits is a combination other than the first combination and the second combination, the switch input detection circuit sets the switch input signal to a low level.

[0188] <Appendix 3>

[0189] According to the state detection device of the switching circuit described in Appendix 1 or 2, wherein,

[0190] The state detection device includes a monitoring circuit connected between the second terminal of the switch and the output terminal of the first drive circuit and the second drive circuit, outputting a monitoring signal corresponding to the conduction state of the reference potential point, which corresponds to the operation of the second drive circuit.

[0191] The processing unit uses the fact that the high-level period of the monitoring signal received from the monitoring circuit is the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal as a third condition.

[0192] If at least one of the first, second, and third conditions is not met, the processing unit determines that there is a fault in the electronic components.

[0193] <Appendix 4>

[0194] According to the state detection device of the switching circuit described in Appendix 3, wherein...

[0195] When the monitoring circuit is in a third combination of the first driving circuit being in an on state and the second driving circuit being in an off state, the monitoring signal is set to a high level.

[0196] The monitoring circuit sets the monitoring signal to a low level when the combination of the on and off states of the first driving circuit and the second driving circuit is a combination other than the third combination.

[0197] <Appendix 5>

[0198] A state detection device for a switching circuit, comprising:

[0199] switch;

[0200] A first driving circuit is connected between the first terminal of the switch and the power supply, and switches the conduction state with the power supply according to the first pulse signal.

[0201] The second driving circuit is connected between the second terminal of the switch and the reference potential point, and switches the conduction state with the reference potential point according to the second pulse signal.

[0202] A switch input detection circuit, connected between the second terminal of the switch and the second drive circuit, outputs a switch input signal related to the signal input to the switch; and

[0203] The processing unit supplies the first pulse signal to the first driving circuit, supplies the second pulse signal to the second driving circuit, and receives the switch input signal from the switch input detection circuit.

[0204] The processing unit makes the first pulse signal different from the second pulse signal, and makes only a portion of the on-time of the second pulse signal and at least a portion of the on-time of the first pulse signal a common on-time that overlaps with each other.

[0205] The processing unit uses the condition that the low-level period of the switch input signal in the state indicating that the switch is on is the same as the on-time obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the second pulse signal.

[0206] The processing unit uses the fact that the low-level period of the switch input signal in the state indicating that the switch is open is the same as the on-time period of the second pulse signal as a second condition.

[0207] If the first condition is met, the processing unit determines that the switch is in the ON state.

[0208] If the second condition is met, the processing unit determines that the switch is in the off state.

[0209] If at least one of the first condition and the second condition is not met, the processing unit determines that there is a fault in the electronic components.

[0210] <Appendix 6>

[0211] According to the state detection device of the switching circuit described in Note 5, wherein...

[0212] When the switch input detection circuit is in a first combination of the indication state of the switch being open and the state of the second drive circuit being on, the switch input signal is set to a low level.

[0213] When the switch input detection circuit is in a second combination of the indicated state of the switch being on, the inactive state of the first driving circuit, and the on state of the second driving circuit, the switch input signal is set to a low level.

[0214] When the combination of the switch's on / off indication state and the respective on / off states of the first and second driving circuits is a combination other than the first combination and the second combination, the switch input detection circuit sets the switch input signal to a high level.

[0215] <Appendix 7>

[0216] According to the state detection device of the switching circuit described in Appendix 5 or 6, wherein...

[0217] The state detection device includes a monitoring circuit connected between the first terminal of the switch and the output terminal of the second drive circuit and the first drive circuit, outputting a monitoring signal corresponding to the conduction state of the power supply, which corresponds to the operation of the first drive circuit.

[0218] The processing unit uses the fact that the low-level period of the monitoring signal received from the monitoring circuit is the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal as a third condition.

[0219] If at least one of the first, second, and third conditions is not met, the processing unit determines that there is a fault in the electronic components.

[0220] <Appendix 8>

[0221] According to the state detection device of the switching circuit described in Appendix 7, wherein...

[0222] When the monitoring circuit is in a third combination of the first driving circuit being in a non-conducting state and the second driving circuit being in a conducting state, the monitoring signal is set to a low level.

[0223] The monitoring circuit sets the monitoring signal to a high level when the combination of the on and off states of the first driving circuit and the second driving circuit is a combination other than the third combination.

[0224] Explanation of reference numerals in the attached figures

[0225] 10, 10A, 10B, 40, 40A… Status detection device for switching circuits

[0226] 11…Switch

[0227] 12… power supply

[0228] 13…Reference Potential Point

[0229] 14…First driving circuit

[0230] 15…Second drive circuit

[0231] 16, 16A… Switch Input Detection Circuit

[0232] 17…Processing Department

[0233] 17a…First signal output terminal

[0234] 17b…Second signal output terminal

[0235] 17c…First signal input terminal

[0236] 17d…Second signal input terminal

[0237] 17A…First Processing Unit

[0238] 17B…Second Processing Unit

[0239] 41, 41A… Monitoring circuit

[0240] 60… Gear shift lever device.

Claims

1. A state detection device for a switching circuit, characterized in that, have: switch; A first driving circuit is connected between the first terminal of the switch and the power supply, and switches the conduction state with the power supply according to the first pulse signal. The second driving circuit is connected between the second terminal of the switch and the reference potential point, and switches the conduction state with the reference potential point according to the second pulse signal. A switch input detection circuit is connected between the first terminal of the switch and the first drive circuit, and outputs a switch input signal related to the signal input to the switch; as well as The processing unit supplies the first pulse signal to the first driving circuit, supplies the second pulse signal to the second driving circuit, and receives the switch input signal from the switch input detection circuit. The processing unit makes the first pulse signal different from the second pulse signal, and makes only a portion of the on-time of the first pulse signal and at least a portion of the on-time of the second pulse signal a common on-time that overlaps with each other. The processing unit uses the condition that the high-level period of the switch input signal in the state indicating that the switch is on is the same as the on-time obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal. The processing unit uses the fact that the high-level period of the switch input signal when the switch is in the off state is the same as the on period of the first pulse signal as a second condition. If the first condition is met, the processing unit determines that the switch is in the ON state. If the second condition is met, the processing unit determines that the switch is in the off state. If at least one of the first condition and the second condition is not met, the processing unit determines that there is a fault in the electronic components.

2. The state detection device for the switching circuit according to claim 1, characterized in that, When the switch input detection circuit is in a first combination of the indication state of the switch being open and the indication state of the first drive circuit being on, the switch input signal is set to a high level. The switch input detection circuit sets the switch input signal to a high level when the switch is in a second combination of the indicated state of the switch being on, the state of the first driving circuit being on, and the state of the second driving circuit being off. When the combination of the switch's on / off indication state and the respective on / off states of the first and second driving circuits is a combination other than the first combination and the second combination, the switch input detection circuit sets the switch input signal to a low level.

3. The state detection device for the switching circuit according to claim 1 or 2, characterized in that, The state detection device includes a monitoring circuit connected between the second terminal of the switch and the output terminal of the first drive circuit and the second drive circuit, outputting a monitoring signal corresponding to the conduction state of the reference potential point, which corresponds to the operation of the second drive circuit. The processing unit uses the fact that the high-level period of the monitoring signal received from the monitoring circuit is the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal as a third condition. If at least one of the first, second, and third conditions is not met, the processing unit determines that there is a fault in the electronic components.

4. The state detection device for the switching circuit according to claim 3, characterized in that, When the monitoring circuit is in a third combination of the first driving circuit being in an on state and the second driving circuit being in an off state, the monitoring signal is set to a high level. The monitoring circuit sets the monitoring signal to a low level when the combination of the on and off states of the first driving circuit and the second driving circuit is a combination other than the third combination.

5. A state detection device for a switching circuit, characterized in that, have: switch; A first driving circuit is connected between the first terminal of the switch and the power supply, and switches the conduction state with the power supply according to the first pulse signal. The second driving circuit is connected between the second terminal of the switch and the reference potential point, and switches the conduction state with the reference potential point according to the second pulse signal. A switch input detection circuit is connected between the second terminal of the switch and the second drive circuit, and outputs a switch input signal related to the signal input to the switch; as well as The processing unit supplies the first pulse signal to the first driving circuit, supplies the second pulse signal to the second driving circuit, and receives the switch input signal from the switch input detection circuit. The processing unit makes the first pulse signal different from the second pulse signal, and makes only a portion of the on-time of the second pulse signal and at least a portion of the on-time of the first pulse signal a common on-time that overlaps with each other. The processing unit uses the condition that the low-level period of the switch input signal in the state indicating that the switch is on is the same as the on-time obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the second pulse signal. The processing unit uses the fact that the low-level period of the switch input signal in the state indicating that the switch is open is the same as the on-time period of the second pulse signal as a second condition. If the first condition is met, the processing unit determines that the switch is in the ON state. If the second condition is met, the processing unit determines that the switch is in the off state. If at least one of the first condition and the second condition is not met, the processing unit determines that there is a fault in the electronic components.

6. The state detection device for a switching circuit according to claim 5, characterized in that, When the switch input detection circuit is in a first combination of the indication state of the switch being open and the state of the second drive circuit being on, the switch input signal is set to a low level. When the switch input detection circuit is in a second combination of the indicated state of the switch being on, the inactive state of the first driving circuit, and the on state of the second driving circuit, the switch input signal is set to a low level. When the combination of the switch's on / off indication state and the respective on / off states of the first and second driving circuits is a combination other than the first combination and the second combination, the switch input detection circuit sets the switch input signal to a high level.

7. The state detection device for a switching circuit according to claim 5 or 6, characterized in that, The state detection device includes a monitoring circuit connected between the first terminal of the switch and the output terminal of the second drive circuit and the first drive circuit, outputting a monitoring signal corresponding to the conduction state of the power supply, which corresponds to the operation of the first drive circuit. The processing unit uses the fact that the low-level period of the monitoring signal received from the monitoring circuit is the same as the on-time period obtained by subtracting the common on-time period of the first pulse signal and the second pulse signal from the on-time period of the first pulse signal as a third condition. If at least one of the first, second, and third conditions is not met, the processing unit determines that there is a fault in the electronic components.

8. The state detection device for the switching circuit according to claim 7, characterized in that, When the monitoring circuit is in a third combination of the first driving circuit being in a non-conducting state and the second driving circuit being in a conducting state, the monitoring signal is set to a low level. The monitoring circuit sets the monitoring signal to a high level when the combination of the on and off states of the first driving circuit and the second driving circuit is a combination other than the third combination.

Images