Max-min search circuit, median generation circuit, and application thereof

Abstract

The present application relates to in-memory computing field, especially to a maximum and minimum value search circuit, a median generation circuit and application thereof.The maximum and minimum value search circuit comprises N cascaded comparison units; each comparison unit is connected with an input unit, and each input unit is used for synchronously inputting respective input data to the respective connected comparison unit in descending order bit by bit. Each comparison unit comprises 2 PMOS tubes, 5 NMOS tubes, 2 AND gates, 2 OR gates and 1 inverter; and comprises a data control module, a larger value comparison module and a smaller value comparison module. The circuit can directly output the maximum value and the minimum value contained therein after the input unit completes data input. The maximum value search circuit is combined with the median generator based on the adder and the D flip-flop chain, and the median generation circuit is obtained. The two circuits provided by the present application can solve the problem that the working frequency and the area are limited in the existing floating point in-memory computing architecture.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing, and in particular to a maximum and minimum value search circuit, a median generation circuit, a median calculation circuit, and a CIM chip. Background Technology

[0002] In current SRAM floating-point in-memory computing (FP-CIM), the global maximum exponent and search are the core steps before mantissa normalization and alignment. However, the related circuits have multiple inherent limitations, such as hardware overhead, timing delay, array non-ideal effects, precision distortion and limited scalability, which seriously restrict the energy efficiency and computing power limit of floating-point in-memory computing.

[0003] First, implementing exponential parallel comparison in large-scale arrays relies heavily on multi-level digital comparison trees, global bit-line scanning, and global arbitration circuits. It also requires additional independent exponential storage macros, cross-column interconnect buses, and external decision logic. This encroaches on SRAM storage area and increases static leakage power consumption, contradicting the original design principle of high-density, low-overhead in-memory computing. Furthermore, global parallel traversal search has inherent timing bottlenecks; as the array size increases, the number of comparison levels grows exponentially, introducing long pipeline delays, disrupting the parallelism between exponential operations and array multiplication and accumulation, and reducing overall throughput.

[0004] Secondly, SRAM array device mismatch, bit line parasitic voltage drop, read noise and process deviations can disturb the exponent level sampling. High-bit exponent decisions are prone to misjudgment, causing the exponent and maximum value to be too small or offset. The subsequent mantissa is excessively shifted to the right, directly truncating the effective information of the low-bit, amplifying the multiplication and accumulation error and reducing the network inference accuracy. At the same time, soft errors in the exponent are much more sensitive to floating-point operations than those in the mantissa, and small decision deviations will be amplified by the normalization process.

[0005] Meanwhile, existing advanced exponents and processing mainly rely on the maximum exponent and alignment method. This is different from the fact that most advanced large model exponent data are concentrated on the exponent and the median value. If the exponent and the maximum value are aligned, it will lead to unnecessary power consumption. At the same time, due to the large number of alignment times, it is easy to cause data disorder, making it difficult to balance data accuracy and energy efficiency. Summary of the Invention

[0006] To address the problem that the exponent and search circuits in existing floating-point in-memory computing architectures mainly rely on complex comparator trees, which limits the overall frequency and area of ​​the chip, this invention provides a maximum and minimum value search circuit, a median generation circuit, a median calculation circuit, and a CIM chip.

[0007] The technical solution provided by this invention is as follows: A maximum and minimum value search circuit is used to identify the maximum and minimum values ​​of multiple input data. The circuit includes N cascaded comparison units. Each comparison unit is connected to an input unit, and each input unit is used to synchronously input its own input data bit by bit in descending order to its connected comparison unit.

[0008] Each comparator unit includes two PMOS transistors P1 and P2, five NMOS transistors N1 to N5, two AND gates AND1 and AND2, two OR gates OR1 and OR2, and one inverter INV. The circuit connections are as follows: the output of the input unit is connected to the input of INV, one of the inputs of AND1 and OR2, and the gate of N5. The output of INV is connected to the gate of N2; the other input of AND1 is connected to the drain of N3 and P1, with the connection point denoted as LQ. The output of AND1 is connected to one of the inputs of OR1; the source of N1 and the drain of P2 are grounded; the source of P2 is connected to the source of N4. The drain of N4 is connected to the source of N5 and the other input of OR2, with the connection point denoted as HQ. The output of OR2 is connected to one of the inputs of AND2; the drain of N5 and the source of P1 are connected to VDD. The drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3. The gates of P2 and N1 are connected to the enable signal EN; the gate of P1 is connected to the precharge signal Pre. The output of OR1 is used as the maximum value output port LB; the output of AND2 is used as the minimum value output port RB. In the first-stage comparator, one input of OR1 is grounded, and the other input of AND2 is connected to VDD. Between each stage of the comparator, the LB terminal of the previous stage comparator is connected to the other input of OR1 in the next stage comparator; the RB terminal of the previous stage comparator is connected to the other input of AND2 in the next stage comparator. The gate of N3 in each stage comparator is connected to the output of OR1 in the last stage, serving as the maximum value output port (Max). The gate of N3 in each stage comparator is connected to the output of AND2 in the last stage, serving as the minimum value output port (Min).

[0009] As a further improvement of the present invention, the operation logic of the maximum and minimum value search circuit for performing maximum and minimum value search on multiple input data includes: (1) Set Pre to low level and EN signal to high level. Control each input unit to input a high level signal to each level of the comparison unit so that the LQ node of each comparison unit is high level and the HQ node is low level.

[0010] (2) The input unit decomposes each input data of uniform length into multiple single-bit data bit by bit; and then inputs each single-bit data into its respective comparison unit in multiple clock cycles in order from high bit to low bit.

[0011] (3) In descending order, the Max and Min ports of the last comparison unit output one bit of the maximum and minimum values ​​in each clock cycle; and obtain the binary codes of the maximum and minimum values ​​after the last clock cycle.

[0012] As a further improvement of the present invention, the maximum data length supported by the input unit is M.

[0013] When the lengths of the input data in different input units are not the same, the input unit pads the higher bits of the shorter original data with zeros so that the length of all data is equal to the length of the longest original data; or it unifies the length of all data to M, thereby keeping the length of each input data uniform.

[0014] As a further improvement of the present invention, the number N of cascaded comparison units is equal to the number of channels of the maximum and minimum value search circuit; the maximum and minimum value search circuit with N channels supports processing N multi-bit numbers to output the maximum and minimum values.

[0015] As a further improvement of the present invention, the gates of N3 and N4 in the previous stage comparison unit, as well as the LB terminal and RB port, constitute four cascaded ports connecting to the next stage comparison unit. The four cascaded ports of the previous stage comparison unit are each connected to the next stage comparison unit through a controllable switch transmission element; the number of channels of the maximum and minimum value search circuit is adjusted by the switching signals of the transmission elements between each stage comparison unit.

[0016] As a further improvement of the present invention, the transmission element of the controllable switch includes a CMOS switch and a transmission gate.

[0017] The present invention also includes a median generation circuit for generating the median of multiple input data. This circuit includes: a maximum / minimum search circuit as described above, and a median generator.

[0018] The median generator includes two input terminals and one output terminal. The two input terminals of the median generator are connected to the Max port and Min port of the maximum and minimum value search circuit, respectively. The median generator is used to generate the median of the two data inputs to the Max port and the Min port, and outputs it to the outside through the output port.

[0019] As a further improvement of the present invention, when the data length supported by the median generation circuit is M, the median generator includes one full adder FA and M+1 D flip-flops D1~D2. M+1 .

[0020] The two input terminals of FA are connected to the Max and Min ports of the maximum-minimum search circuit, respectively; the CI terminal of FA is connected to the CO terminal; D1~DM+1 Cascade sequentially.

[0021] The output of FA is connected to the input of the first-stage D flip-flop via a unidirectional controllable transmission element; and the output of the previous-stage D flip-flop is connected to the input of the next-stage D flip-flop via a unidirectional controllable transmission element to form a backward transmission channel; the control terminal of each unidirectional controllable transmission element in the backward transmission channel is connected to the first enable signal EN1.

[0022] The output of the next stage D flip-flop is also connected to the input of the previous stage D flip-flop through a unidirectional controllable transmission element to form a feedforward transmission channel; the control terminal of each unidirectional controllable transmission element in the feedforward transmission channel is connected to the second enable signal EN2.

[0023] The control terminals of each D flip-flop are connected to the clock signal CLK. M-1 The output terminal is used as the output port Mid for the median.

[0024] As a further improvement of the present invention, the unidirectional controllable transmission element adopts a unidirectional transmission gate.

[0025] The median generation circuit implements the following operational logic for generating the median: Set the Pre signal in the maximum and minimum value search circuit to low level and the EN signal to high level; control each input unit to input a high-level signal to each stage of the comparison unit; so that the LQ node of each comparison unit is high level and the HQ node is low level; complete the initialization. In the median generator, EN1 and EN2 are set to high level. Simultaneously, in the maximum and minimum value search circuit, the input unit decomposes each input data of uniform length into multiple single-bit data. Then, in order from the most significant bit to the least significant bit, each single-bit data is sequentially input into its respective comparison unit over multiple clock cycles. After the second bit of the input data is input from the input unit, the median generator begins to output the most significant bit of the sum of the maximum and minimum values. In each clock cycle, the bits of the sum of the two values ​​are output sequentially from high to low.

[0026] After the maximum and minimum value search circuit completes the input of each bit of the input data, the EN1 and EN2 of the median generator are set to low level. At this time, when a new clk arrives, each bit of the sum of the maximum and minimum values ​​will be shifted to the left by one bit, which is equivalent to dividing the sum by 2, thus solving for the median.

[0027] The present invention also includes a median calculation circuit that employs the median generator as described above.

[0028] The present invention also includes a CIM chip that supports floating-point operations, which employs the aforementioned maximum and minimum value search circuit, or the aforementioned median generator, or the aforementioned median calculation circuit.

[0029] The present invention has the following beneficial effects: This invention presents a novel maximum and minimum value search circuit designed for exponential data processing in floating-point arithmetic. It can simultaneously search for the maximum and minimum values ​​from multiple input data. Compared to circuits with similar functions, this circuit has a simpler structure, a shorter time cycle for data search, and higher data processing efficiency, thus reducing area overhead and improving power consumption.

[0030] Based on the maximum-minimum search circuit, this invention also designs a median generator based on an adder and a D flip-flop chain. When used in conjunction with the maximum-minimum search circuit, it can simultaneously output the median of the maximum and minimum values ​​within the same time period, thus meeting the latest demands of neural network tasks for floating-point operations. This helps improve the accuracy of related operations and data processing efficiency, and has broad practical prospects. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the maximum and minimum value search circuit provided in Embodiment 1 of the present invention.

[0032] Figure 2 This is a circuit diagram of the maximum and minimum value search circuit provided in Embodiment 1 of the present invention.

[0033] Figure 3 This is a circuit diagram of a maximum / minimum value search circuit that includes two levels of comparison units.

[0034] Figure 4 This is a schematic diagram of a cascaded, reconfigurable multi-channel maximum / minimum value search circuit.

[0035] Figure 5 This is a schematic diagram of the median generation circuit provided in Embodiment 2 of the present invention.

[0036] Figure 6 This is a circuit diagram of the median generator used in the median generation circuit.

[0037] Figure 7 The signal timing diagram is shown for the maximum and minimum value search circuit in the simulation test.

[0038] Figure 8 This is the signal flow graph of the median generation circuit in the simulation test. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0041] Example 1 Technicians, in their research on optimizing in-memory computing circuits, discovered that traditional exponent and search circuits based on the number of adders generally suffer from large scale and complex computational logic, making it difficult to achieve optimal chip frequency and area. Furthermore, existing in-memory computing architectures primarily rely on shifting based on the exponent and maximum value, which contradicts the reality that most exponents in current neural networks are located near the middle of the exponent. To address these findings, this embodiment first provides a maximum-minimum value search circuit, which quickly identifies the maximum and minimum values ​​from multiple input data using a single circuit. This new circuit reduces the hardware scale of maximum value search, eliminates the need for complex external circuitry, and features simpler operating logic. Moreover, since it can simultaneously identify the maximum and minimum values ​​from multiple input data, it lays the foundation for median calculation, and the calculated median can then assist in shift operations in floating-point arithmetic. This aligns with the needs of current neural network-related data processing tasks, contributing to improved accuracy and efficiency in related calculations.

[0042] Specifically, such as Figure 1 As shown, the maximum and minimum value search circuit provided in this embodiment includes multiple cascaded comparison units; each comparison unit is connected to an input unit.

[0043] For a maximum-minimum search circuit containing N comparison units and N input circuits, the number of cascaded comparison units N equals the number of channels in the maximum-minimum search circuit. A maximum-minimum search circuit with N channels can identify the maximum and minimum values ​​from N different input data and output the corresponding search results. In practical applications, the number of channels in the maximum-minimum search circuit can be flexibly set according to the specific processing requirements of the circuit.

[0044] In the maximum / minimum value search circuit provided in this embodiment, each input unit synchronously inputs its own input data bit by bit into its connected comparison unit in descending order. During operation, in each clock cycle, the input unit inputs one bit of each input data to be compared into the comparison unit; the output ports Max and Min of the maximum and minimum values ​​in the last-stage comparison unit can also synchronously output one bit of the global maximum and global minimum values. Assuming that each input data has a length of M bits, after the Mth clock cycle, all input data has been input, and simultaneously, the output ports Max and Min of the last-stage comparison unit can complete the search and output of the global maximum and global minimum values.

[0045] For an input circuit capable of inputting the values ​​of each bit of the input data bit by bit in each clock cycle, this embodiment does not limit its circuit structure. It can use existing circuits that can achieve similar functions, or it can use new circuits with the same function. For example, in a typical scheme of this embodiment, the required input circuit can be constructed using ping-pong unit logic. The input circuit can ensure that in the subsequent data comparisons of each level of comparison unit, the high-order data comparison is performed first, until the lowest bit of the input data is matched.

[0046] Specifically, the comparison unit, capable of simultaneously comparing and outputting the maximum and minimum values ​​of multiple input data, is the core of the maximum-minimum value search circuit provided in this embodiment. In detail, in this embodiment, combined with... Figure 1 It can be seen that each comparator unit consists of 2 PMOS transistors P1 and P2, 5 NMOS transistors N1~N5, 2 AND gates AND1 and AND2, 2 OR gates OR1 and OR2, and 1 inverter INV. The circuit connection relationship between the components in each stage of the comparator unit is as follows: the output terminal of the input unit is connected to the input terminal of INV, one of the input terminals of AND1 and OR2, and the gate of N5. The output terminal of INV is connected to the gate of N2; the other input terminal of AND1 is connected to the drain of N3 and P1, and the connection point is denoted as LQ. The output terminal of AND1 is connected to one of the input terminals of OR1; the source of N1 and the drain of P2 are grounded; the source of P2 is connected to the source of N4. The drain of N4 is connected to the source of N5 and the other input terminal of OR2; the connection point is denoted as HQ. The output terminal of OR2 is connected to one of the input terminals of AND2; the drain of N5 and the source of P1 are connected to VDD. The drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3. The gates of P2 and N1 are connected to the enable signal EN; the gate of P1 is connected to the precharge signal Pre. The output of OR1 is used as the maximum value output port LB; the output of AND2 is used as the minimum value output port RB.

[0047] like Figure 2 As shown, in the first-stage comparator unit, one input terminal of OR1 is grounded, and the other input terminal of AND2 is connected to VDD. The connection relationships between the cascaded comparator units are as follows: the LB terminal of the previous stage comparator unit is connected to the other input terminal of OR1 in the next stage comparator unit; the RB terminal of the previous stage comparator unit is connected to the other input terminal of AND2 in the next stage comparator unit. The gate of N3 in each stage comparator unit is connected to the output terminal of OR1 in the last stage, serving as the output port Max for the maximum value. The gate of N3 in each stage comparator unit is connected to the output terminal of AND2 in the last stage, serving as the output port Min for the minimum value.

[0048] In the comparison unit designed in this embodiment, AND gate AND1 and OR gate OR1 together constitute a larger value comparison module, and AND gate AND2 and OR gate OR2 together constitute a smaller value comparison module; while PMOS transistors P1 and P2, NMOS transistors N1~N5 and inverter INV together constitute a data control module. When the circuit is working, the input units of each stage input the values ​​of each bit of the input data to the comparison unit; the data control module in each comparison unit determines which value is larger based on whether each bit of the input data is "1" or "0", and selects a portion of the data to discard.

[0049] For example, when finding the maximum value, if the highest bit of multiple sets of input data contains both "1" and "0", the data with the value "1" is larger. Therefore, the charge of the set of input data with a highest bit value of "0" is released, preventing new data from being written and discarding that set of data. The principle is similar when finding the minimum value: if the highest bit of multiple sets of input data contains both "1" and "0", the data with a highest bit value of "1" is discarded and no longer participates in subsequent comparisons.

[0050] Building upon this foundation, the larger value comparison modules at each level compare the values ​​of each bit in the input data and determine whether the data set should continue to participate in subsequent comparisons. Correspondingly, the smaller value comparison module functions similarly to the larger value comparison module, determining and comparing smaller values.

[0051] Specifically, in combination Figure 3 Taking the comparison of two sets of input data (denoted as SUM0 and SUM1, with the subscript number corresponding to the level of the comparison unit, the same below) as an example, a circuit with two channels is required, including two levels of comparison units and two input units. Based on this, when both input data SUM0 and SUM1 are 0, the outputs LB0 and LB1 are both 0, indicating that the maximum and minimum values ​​are both 0. When SUM0 is 0 and SUM1 is 1, LB0 is 0 and LB1 is 1, indicating that the maximum value output is 1 and the minimum value output is 0.

[0052] During circuit operation, the working logic of the larger value comparison module and the smaller value comparison module is as follows: The other data input port of AND1 in the larger value comparison module is connected to node LQ0 between N3 and P1. When LQ0 is low, AND1 will eventually output "0" regardless of whether the input data for that bit is "1" or "0", thus achieving low-bit latching. The other data input port of OR2 in the smaller value comparison module is connected to HQ0 between N4 and N5. When HQ0 is high, OR3 will eventually output "1" regardless of whether the input data for that bit is "1" or "0", thus achieving high-bit latching.

[0053] The data control module is used to select and eliminate certain levels of input data when comparing each bit of multiple sets of input data at each level, preventing them from participating in subsequent comparisons. Specifically, in the initial state, the Pre signal is set to low, turning on the pre-charge transistor P1. The voltages at the low-level latch signals LQ0 and LQ1 are set to high by VDD, and the EN signal is set to high, turning on N1 and setting HQ0 and HQ1 to low, completing the pre-charge. Subsequently, the Pre signal is set to high, the EN signal is set to low, and the pre-charge transistor is turned off.

[0054] During the comparison, when the current bit value of both sets of input data is 0, the outputs LB0, LB1, RB0, and RB1 are 0. At this time, LQ0 and LQ1 are still low, and HQ0 and HQ1 are still high. When the input data SUM0 is 0 and SUM1 is 1, N2 in the first-stage comparison unit is turned on, while N1 in the second-stage comparison unit remains off. With N3 in the first-stage comparison unit and N2 in the second-stage comparison unit turned on, the charge at HQ0 is released to ground, so the potential at that point will be low, while HQ1 remains high. At this time, the MAX output result is 1.

[0055] Under these conditions, N5 in the first-stage comparator is turned off, and N4 in the second-stage comparator is turned on. P1 in the second-stage comparator remains off. HQ0 is charged to a high level, while HQ1 remains low. Therefore, the minimum value (MIN) is output as 0. When the next set of exponents and data, SUM0 and SUM1, are 1 and 0 respectively, since LQ0 is low, even if the SUM0 input is 1, the LB0 output is still latched low. LQ1 is high, and since the SUM1 input is low, LAB1 is low, resulting in a maximum value (MAX) output of 0. Similarly, since HQ0 is low, even if the SUM0 input is 0, the RB0 output is still high. Since the SUM1 input is 1, HQ1 is high, so MIN is still output as 1. Under the control of the EN signal, N1 and P2 in the first-stage comparator are enabled once after each data bit is written.

[0056] In summary, the operation logic of the maximum and minimum value search circuit provided in this embodiment for performing maximum and minimum value searches on multiple input data includes: (1) Set Pre to low level and EN signal to high level. Control each input unit to input a high level signal to each level of the comparison unit so that the LQ node of each comparison unit is high level and the HQ node is low level.

[0057] (2) The input unit decomposes each input data of uniform length into multiple single-bit data bit by bit; and then inputs each single-bit data into its respective comparison unit in multiple clock cycles in order from high bit to low bit.

[0058] (3) In descending order, the Max and Min ports of the last comparison unit output one bit of the maximum and minimum values ​​in each clock cycle; and obtain the binary codes of the maximum and minimum values ​​after the last clock cycle.

[0059] Based on the above circuit working principle, in the maximum / minimum value search circuit provided in this embodiment, to ensure that the values ​​of bits with the same weight in different input data are compared in each round, the number of bits in each input data participating in the comparison needs to be the same. Assuming the maximum data length supported by the input unit is M, when the lengths of the input data from different input units are not the same, the input unit can pad the higher bits of the shorter original data with zeros so that the length of all data is equal to the length of the longest original data. Alternatively, when the number of bits in each input data is less than M, the higher bit padding operation can be used to unify the data length of all data to M, thereby ensuring that the length of each input data remains uniform.

[0060] As previously mentioned, the number of comparison units in the maximum / minimum value search circuit is equal to the number of channels in the circuit, and in each round, the circuit must perform the maximum and minimum value search task on the corresponding number of input data points, which is the same as the number of channels. Based on this, in order for the same circuit to simultaneously support the maximum and minimum value search task across different numbers of input data points, this embodiment modifies the circuit as follows: Figure 4 The improvement is illustrated below. Specifically, the gates of N3 and N4 in the previous stage comparator (which can be denoted as A2 and A2), as well as the LB terminal and RB port, constitute four cascaded ports connecting to the next stage comparator. The four cascaded ports of the previous stage comparator are each connected to the next stage comparator through a controllable switching transmission element (such as a CMOS switch, transmission gate, etc.); the number of channels in the maximum and minimum value search circuit is adjusted by the switching signals of the transmission elements (denoted as TG1, TG2, TG3, TG4) between each stage comparator.

[0061] By introducing controllable switching transmission elements between the comparison units, the cascading relationship between the comparison units can be reconfigured according to specific needs. Specifically, a circuit capable of searching for the maximum and minimum values ​​among four 8-bit input data should have four comparison units, namely Comparison Unit 1, Comparison Unit 2, Comparison Unit 3, and Comparison Unit 4. When the cascading relationship between Comparison Unit 1 and Comparison Unit 2 is "disconnected," the cascaded Comparison Units 2, 3, and 4 form a circuit capable of searching for the maximum and minimum values ​​among three 8-bit input data. Similarly, when the cascading relationship between Comparison Unit 2 and Comparison Unit 3 is "disconnected," the cascaded Comparison Units 3 and 4 form a circuit capable of searching for the maximum and minimum values ​​among two 8-bit input data, and so on.

[0062] Example 2 Building upon the minimum-maximum search circuit provided in Example 1, and addressing the current situation in neural network tasks where floating-point operations focus more on the median of the sum of exponents rather than the maximum value, this example further provides a median generation circuit for generating the median of multiple input data. Specifically, as shown... Figure 5 As shown, the circuit includes a maximum / minimum search circuit as in Embodiment 1 and a median generator. The median generator includes two input terminals and one output terminal; the two input terminals of the median generator are respectively connected to the Max port and Min port of the maximum / minimum search circuit; the median generator is used to generate the median of the two data inputs to the Max port and Min port, and outputs it to the outside through the output port.

[0063] Specifically, assuming the median generation circuit provided in this embodiment supports a data length of M, the median generator can consist of one full adder FA and M+1 D flip-flops D1~D1. M+1 The composition and corresponding circuit connection relationships are as follows: Figure 6 As shown. The two input terminals (A and B) of FA are connected to the Max and Min ports of the maximum / minimum search circuit, respectively; the CI terminal of FA is connected to the CO terminal; D1~D M+1 Cascade sequentially.

[0064] The output (S) of the FA is connected to the input (D) of the first-stage D flip-flop via a unidirectional controllable transmission element; and the output (Q) of the previous-stage D flip-flop is connected to the input (D) of the next-stage D flip-flop via a unidirectional controllable transmission element to form a backward transmission channel; the control terminals of each unidirectional controllable transmission element in the backward transmission channel are connected to the first enable signal EN1. The output (Q) of the next-stage D flip-flop is also connected to the input (D) of the previous-stage D flip-flop via a unidirectional controllable transmission element to form a feedforward transmission channel; the control terminals of each unidirectional controllable transmission element in the feedforward transmission channel are connected to the second enable signal EN2. The control terminals of each D flip-flop are connected to the clock signal CLK. M-1 The output terminal (Q) is used as the output port Mid for the median. In this embodiment, the unidirectional controllable transmission element can be a unidirectional transmission gate or other similar devices with specific unidirectional controllable signal transmission functions.

[0065] In this embodiment, the median generation circuit includes an adder with carry and a chain of D flip-flops that can control the direction of data transmission. This circuit can directly solve for the median value of two multi-bit input data through data shifting. Specifically, its operation logic for generating the median value based on two inputs is as follows: Set the Pre signal in the maximum and minimum value search circuit to low level and the EN signal to high level; control each input unit to input a high-level signal to each stage of the comparison unit; so that the LQ node of each comparison unit is high level and the HQ node is low level; complete the initialization. In the median generator, EN1 and EN2 are set to high level. Simultaneously, in the maximum and minimum value search circuit, the input unit decomposes each input data of uniform length into multiple single-bit data. Then, in order from the most significant bit to the least significant bit, each single-bit data is sequentially input into its respective comparison unit over multiple clock cycles. After the second bit of the input data is input from the input unit, the median generator begins to output the most significant bit of the sum of the maximum and minimum values. In each clock cycle, the bits of the sum of the two values ​​are output sequentially from high to low.

[0066] After the maximum and minimum value search circuit completes the input of each bit of the input data, the EN1 and EN2 of the median generator are set to low level. At this time, when a new clk arrives, each bit of the sum of the maximum and minimum values ​​will be shifted to the left by one bit, which is equivalent to dividing the sum by 2, thus solving for the median.

[0067] Based on the circuit structure of the median generation circuit, the circuit principle for generating the median using the above-mentioned operational logic is as follows: After calculating the maximum and minimum values ​​of the input data, each bit of the result is sequentially fed into adder FA for summation. Simultaneously, when EN1 is set high and EN2 is set low, the backward transmission channel is open, and the forward transmission channel is closed. A D flip-flop chain is used to perform shifting during the summation of the maximum and minimum values. Considering the potential carry, a carry-capable adder is used. Once all 8 bits of the input data have been summed, the highest bit of the sum of the maximum and minimum values ​​is stored in D9, and the next highest bit is stored sequentially.

[0068] After all data storage is completed, EN1 is set low and EN2 is set high, thus closing the backward transmission channel and opening the forward transmission channel. At this time, data is transmitted in reverse through the connection of D flip-flops, achieving a left shift of the data by one bit. For binary data, this is equivalent to dividing the value by 2. Therefore, the function of adding the maximum and minimum input values ​​and then dividing by 2 is realized, that is, to find the exponent and the intermediate value.

[0069] In practical applications, the median generator can be used either as part of a median generation circuit or as a standalone module with a mean calculation function. Therefore, this embodiment also provides a median calculation circuit, which employs the following... Figure 6 The median generator shown is used to calculate the average of two input data. In practical applications, by combining it with any other logic circuit that is different from the maximum and minimum value search circuit in Embodiment 1 and can also perform maximum and minimum value searches, another median generation circuit different from the scheme in Embodiment 2 can be obtained.

[0070] Example 3 In order to better utilize the various logic circuits with different functions provided in Embodiments 1 and 2, this embodiment further provides a CIM chip that supports floating-point operations, and the circuit adopts the maximum and minimum value search circuit as in Embodiment 2, or the median generator or median calculation circuit as in Embodiment 2.

[0071] Simulation test To verify the performance of the maximum / minimum value search circuit provided in this invention, technicians performed simulations in simulation software. Figure 2 The maximum and minimum value search circuit shown is Figure 5 The circuit function of the median generator shown is simulated.

[0072] 1. Maximum and minimum value search circuit The simulation is conducted on a circuit with two-stage comparison units, taking the input data SUM0 as 01101111 and SUM1 as 01010111 as an example. The waveforms of each key signal during the simulation are shown below. Figure 7 As shown. The task execution process is as follows. Figure 8 As shown, it includes the following steps: S1: Pre-charge phase: In the initial stage, the Pre signal is set to low and the EN signal is set to high; at the same time, high-level data is input to each channel before the exponent and data inputs, thus setting LQ0 and LQ1 to high and HQ0 and HQ1 to low.

[0073] S2: Data Comparison Phase When the first bit of both input data sets is 0, N2 and N1 in the first-level comparison unit are enabled. However, since the outputs of AND1 in the first-level comparison unit are 0, the outputs of OR1 in the first-level comparison unit and OR1 in the second-level comparison unit are also 0. At this time, N3 and N2 in the first-level comparison unit remain disabled, and LQ0 and LQ1 remain high. Similarly, since HQ0 and HQ1 remain low during the precharge phase, the outputs of OR2 in the first-level comparison unit and OR2 in the second-level comparison unit are low. At this time, the outputs of AND2 in the first-level comparison unit and AND2 in the second-level comparison unit are low, and N4 in the first-level comparison unit and P1 in the second-level comparison unit are disabled. At this time, HQ0 and HQ1 remain low.

[0074] When the second bit of both sets of data is 1, the outputs of AND1 in the first-level comparison unit and AND1 in the second-level comparison unit are high. Under this condition, the outputs of OR1 in the first-level comparison unit and OR1 in the second-level comparison unit are 1. At this time, N3 in the first-level comparison unit and N2 in the second-level comparison unit are in the enabled state. However, since N2 in the first-level comparison unit and N1 in the second-level comparison unit are in the disabled state, LQ0 and LQ1 are still in the high-level state. Similarly, since the input data of this bit is 1, N5 in the first-level comparison unit and N5 in the second-level comparison unit are turned on, and the potentials of HQ0 and HQ1 will be pulled high. At the same time, the outputs of OR2 in the first-level comparison unit and OR2 in the second-level comparison unit are high, which makes N4 in the first-level comparison unit and N4 in the second-level comparison unit turn on. Under the condition that EN is not enabled, P2 in the first-level comparison unit and P2 in the second-level comparison unit are turned on, pulling the potentials of HQ0 and HQ1, which were originally raised, low, waiting for the input of the next bit of data.

[0075] When both sets of data are SUM0=1 and SUM1=0, N2 in the first-stage comparator is turned on, while N2 in the second-stage comparator remains off. Simultaneously, AND1 in the first-stage comparator outputs 1, and AND1 in the second-stage comparator outputs 0. This causes OR1 in both the first and second-stage comparators to output 1, turning on N3 in both stages. Since N2 in the second-stage comparator remains off, LQ0 remains high. LQ1 will discharge during the EN enable phase, causing its potential to drop low. Because Pre is not turned on during the entire data comparison process, LQ1 will remain low. At this point, N5 in the first-stage comparator is turned on, pulling HQ0 high. HQ1, however, remains low because N5 in the second-stage comparator remains off. OR2 in the first-stage comparator outputs 1, but OR2 in the second-stage comparator outputs 0, resulting in a final output of 0.

[0076] S3: Data latching phase: When the next bit of the two sets of data is SUM0=0 and SUM1=1 respectively, the AND1 output of the first-level comparison unit is 0, and the OR1 output of the first-level comparison unit is also 0. Similarly, since LQ1 is low, the AND1 output of the first-level comparison unit is 0, and therefore the OR1 output of the second-level comparison unit is also 0. At this time, N3 in the first-level comparison unit and N3 in the second-level comparison unit remain closed, without changing the potentials of LQ0 and LQ1. That is, the SUM1 of the second set does not participate in finding the actual maximum value result, and the low level of LQ1 achieves latching of the second set of data. However, HQ0 remains high at this time, so the output data of AND2 and OR2 in the first-level comparison unit is 1. The potential of HQ1 is pulled high by VDD, and the output result of AND2 and OR2 in the first-level comparison unit is 1, that is, the smaller value comparison result is 1. The high level of HQ0 achieves latching of the data, eliminating the influence of the first set of data on the minimum value of the input data.

[0077] S4: Remaining data output stage: As can be seen from the previous data, when the current bit of any input data is 1, the corresponding HQ will be pulled high to achieve data latching, excluding the data after this group from the minimum value comparison. Similarly, when the current bit of any input data is 0, LQ will be pulled low to achieve data latching, excluding the data after this group from the subsequent larger value comparison.

[0078] In summary, after excluding the latched data, the remaining data is compared and output. For example, in this set of data, the maximum value is 01101111 and the minimum value is 01010111.

[0079] 2. Median Generator This experiment uses SUM0=1011, SUM1=0111, SUM2=1011, and SUM0=1010 as examples. It utilizes a median generator to search for the maximum and minimum values ​​in the four input data sets and generates the median based on the search results. The signal flow graph during circuit execution is shown below. Figure 8 As shown.

[0080] Based on the simulation results above, it can be seen that the maximum / minimum value search circuit and median generation circuit provided by this invention both achieve the expected computational functions and can be applied to floating-point in-memory calculation circuits. Furthermore, the circuit structures for both functions are significantly simpler than existing designs, with shorter computation time and higher computational efficiency. Therefore, this helps to reduce the hardware overhead and latency of floating-point in-memory calculation circuits.

[0081] The above-described embodiments are merely one implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A maximum / minimum value search circuit, characterized in that: It is used to identify the maximum and minimum values ​​of multiple input data; It consists of N cascaded comparison units; each comparison unit is connected to an input unit; Each comparator unit includes two PMOS transistors P1 and P2, five NMOS transistors N1 to N5, two AND gates AND1 and AND2, two OR gates OR1 and OR2, and one inverter INV; The output of the input unit is connected to the input of INV, one of the inputs of AND1 and OR2, and the gate of N5; the output of INV is connected to the gate of N2; the other input of AND1 is connected to the drain of N3 and P1, and the connection point is denoted as LQ; the output of AND1 is connected to one of the inputs of OR1; the source of N1 and the drain of P2 are grounded; the source of P2 is connected to the source of N4; the drain of N4 is connected to the source of N5 and the other input of OR2, and the connection point is denoted as HQ; the output of OR2 is connected to one of the inputs of AND2; the drain of N5 and the source of P1 are connected to VDD; the drain of N1 is connected to the source of N2; the drain of N2 is connected to the source of N3; the gates of P2 and N1 are connected to the enable signal EN; the gate of P1 is connected to the precharge signal Pre; the output of OR1 is used as the maximum value output port LB; the output of AND2 is used as the minimum value output port RB. In the first-stage comparator, the other input terminal of OR1 is grounded, and the other input terminal of AND2 is connected to VDD; the LB terminal of the previous-stage comparator is connected to the other input terminal of OR1 in the next-stage comparator; the RB terminal of the previous-stage comparator is connected to the other input terminal of AND2 in the next-stage comparator; the gate of N3 in each stage comparator is connected to the output terminal of OR1 in the last stage, and serves as the output port Max for the maximum value; the gate of N3 in each stage comparator is connected to the output terminal of AND2 in the last stage, and serves as the output port Min for the minimum value.

2. The maximum and minimum value search circuit according to claim 1, characterized in that: Its operation logic for performing maximum and minimum value searches on multiple input data includes: (1) Set Pre to low level and EN signal to high level; control each input unit to input high level signal to each level of comparison unit; so that the LQ node of each comparison unit is high level and the HQ node is low level; (2) The input unit decomposes each input data of uniform length into multiple single-bit data bit by bit; then, in order from the high bit to the low bit, each single-bit data is sequentially input into its respective comparison unit in multiple clock cycles; (3) In descending order, the Max and Min ports of the last comparison unit output one bit of the maximum and minimum values ​​in each clock cycle; and obtain the binary codes of the maximum and minimum values ​​after the last clock cycle.

3. The maximum and minimum value search circuit according to claim 2, characterized in that: The maximum data length supported by the input unit is M; When the lengths of the input data in different input units are not the same, the input unit pads the higher bits of the shorter original data with zeros so that the length of all data is equal to the length of the longest original data; or it unifies the length of all data to M, thereby keeping the length of each input data uniform.

4. The maximum and minimum value search circuit according to claim 1, characterized in that: The number N of cascaded comparison units is equal to the number of channels of the maximum and minimum value search circuit; the maximum and minimum value search circuit with N channels supports processing N multi-bit numbers to output the maximum and minimum values.

5. The maximum and minimum value search circuit according to claim 4, characterized in that: The gates of N3 and N4 in the previous stage comparison unit, as well as the LB terminal and RB port, constitute four cascaded ports connecting to the next stage comparison unit; the four cascaded ports of the previous stage comparison unit are respectively connected to the next stage comparison unit through a controllable switch transmission element; the number of channels of the maximum and minimum value search circuit is adjusted by the switching signals of the transmission elements between each stage comparison unit. And / or, the transmission element of the controllable switch includes a CMOS switch or a transmission gate.

6. A median generation circuit, characterized in that, It is used to generate the median of multiple input data, which includes: The maximum and minimum value search circuit as described in any one of claims 1-5; A median generator includes two input terminals and one output terminal; the two input terminals of the median generator are respectively connected to the Max port and Min port of the maximum and minimum value search circuit; the median generator is used to generate the median of the two data inputs to the Max port and the Min port, and outputs it to the outside through the output port.

7. The median generation circuit as described in claim 6, characterized in that: When the median generation circuit supports a data length of M, the median generator includes one full adder FA and M+1 D flip-flops D1~D2. M+1 ; The two input terminals of FA are connected to the Max and Min ports of the maximum-minimum search circuit, respectively; the CI terminal of FA is connected to the CO terminal; D1~D M+1 Cascade sequentially; The output of the FA is connected to the input of the first-stage D flip-flop through a unidirectional controllable transmission element; and the output of the previous-stage D flip-flop is connected to the input of the next-stage D flip-flop through a unidirectional controllable transmission element to form a backward transmission channel. The control terminal of each unidirectional controllable transmission element in the backward transmission channel is connected to the first enable signal EN1; The output of the next stage D flip-flop is also connected to the input of the previous stage D flip-flop through a unidirectional controllable transmission element to form a feedforward transmission channel; the control terminal of each unidirectional controllable transmission element in the feedforward transmission channel is connected to the second enable signal EN2. The control terminals of each D flip-flop are connected to the clock signal CLK; D M-1 The output terminal is used as the output port Mid for the median.

8. The median generation circuit as described in claim 6, characterized in that, The logic for generating the median is as follows: Set the Pre signal in the maximum and minimum value search circuit to low level and the EN signal to high level; control each input unit to input a high-level signal to each stage of the comparison unit; so that the LQ node of each comparison unit is high level and the HQ node is low level; complete the initialization. In the median generator, EN1 and EN2 are set to high. Simultaneously, in the maximum / minimum search circuit, the input unit decomposes each input data of uniform length into multiple single-bit data. Then, each single-bit data is sequentially input into its respective comparison unit over multiple clock cycles, from the most significant bit to the least significant bit. After the second bit of the input data is input from the input unit, the median generator begins to output the most significant bit of the sum of the maximum and minimum values. In each clock cycle, it sequentially outputs the bits of the sum from high to low. After the maximum and minimum value search circuit completes the input of each bit of the input data, the EN1 and EN2 of the median generator are set to low level. At this time, when a new clk arrives, each bit of the data of the sum of the maximum and minimum values ​​will be shifted to the left by one bit, which is equivalent to dividing the sum by 2, thus solving for the median. And / or, the unidirectional controllable transmission element adopts a unidirectional transmission gate.

9. A median calculation circuit, characterized in that: It employs the median generator as described in any one of claims 6-8.

10. A CIM chip that supports floating-point operations, characterized in that: It employs a maximum / minimum value search circuit as described in any one of claims 1-5, or a median generator as described in any one of claims 6-8, or a median calculation circuit as described in claim 9.

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