A level shifting circuit and control method

Abstract

The application belongs to the field of high-voltage driving circuit, and discloses a level shift circuit and a control method, the circuit comprising an input differential pair, a current limiting module, a load module, a voltage clamping module and a latch module, each module cooperates to complete the conversion of low-voltage signal to high-voltage domain. The input differential pair comprises first and second transistors, the gates of the two transistors receive two input signals respectively, and the sources are connected to the current limiting module; the upper end of the load module is connected to the high-side power supply, and the lower end is connected to the drains of the two transistors respectively; one end of the voltage clamping module is connected to the high-side power supply, and the other end is connected to the drains of the two transistors to form two nodes; the two input ends of the latch module are connected to the two nodes respectively, and the output end outputs the signal after level shift. The application inhibits the inrush current through the current limiting module, avoids the level mis-triggering through the pull-up node of the load unit, limits the node voltage through the voltage clamping unit to protect the low-voltage device from overvoltage breakdown, and shapes and latches the level through the latch module to eliminate the output glitch.

Description

Technical Field

[0001] This invention relates to the field of high-voltage drive circuits, and in particular to a level shifting circuit and control method. Background Technology

[0002] In the field of high-voltage drive technology, level shifting circuits are widely used to achieve signal interaction between different voltage domains. These circuits are typically paired with bootstrap circuits to drive high-side power transistors. Currently, most high-voltage level shifting circuits on the market employ general-purpose load structures and base voltage clamping designs, making it difficult to guarantee operational stability in low-supply-voltage applications. Furthermore, when the high-side power transistor experiences truncation, the bootstrap capacitor discharges too quickly, directly resulting in insufficient driving capability of the high-side power transistor. In addition, the switching action of the power transistor is accompanied by strong voltage change rate noise, and interference signals can easily cause glitches in the output of the level shifting circuit, inducing circuit malfunctions.

[0003] Currently, noise glitches are generally eliminated by adding pulse filter circuits. However, the filtering stage introduces additional transmission delay, making it impossible to balance signal transmission efficiency and anti-interference capability. Some circuits use resistors or diode-connected MOSFETs as pull-up loads. However, when using resistors as loads, large-value resistors must be configured to achieve low-current operating conditions, which significantly increases the chip layout area. Furthermore, their electrical characteristics are easily affected by factors such as process technology, voltage, and temperature. When using diode-connected MOSFETs as loads, the highest node level cannot reach the high-voltage power supply potential, easily leading to a floating intermediate level under low-voltage operating conditions, causing leakage and circuit mis-flipping problems.

[0004] After the circuit is turned off, the clamping device in the base voltage clamping design may operate in the reverse breakdown region due to process and temperature fluctuations, generating clamping discharge current, which will further increase standby power consumption. In addition, traditional current limiting methods cannot effectively suppress the inrush current at the moment of input transistor turn-on. The device is in a state of instantaneous high current for a long time, which not only affects its service life, but also reduces the reliability of the entire circuit. Summary of the Invention

[0005] The purpose of this invention is to provide a level shifting circuit and control method that is suitable for wide voltage domain operating scenarios, effectively solves the problem of excessively fast discharge of the bootstrap capacitor, suppresses interference caused by voltage change rate noise, reduces standby power consumption, and improves overall operational reliability.

[0006] To solve the above-mentioned technical problems, in one aspect, the present invention provides a level shifting circuit, comprising: The input differential pair includes a first transistor and a second transistor, wherein the gate of the first transistor receives a first input signal and the gate of the second transistor receives a second input signal; The load module includes a first load unit and a second load unit; A voltage clamping module includes a first voltage clamping unit and a second voltage clamping unit. One end of each of the first and second voltage clamping units is connected to a high-side power supply. The other end of the first voltage clamping unit is connected between the drain of the first transistor and the first load unit, forming a first node. The other end of the second voltage clamping unit is connected between the drain of the second transistor and the second load unit, forming a second node. The latch module has a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal that outputs a level-shifted signal. When the level shift circuit is in a non-high-side truncation state, the first input signal and the second input signal are out of phase, and a differential potential is output. The latch module is in a set state or a reset state, and outputs a level shift signal in real time. When the level shifting circuit is in the high-side truncation state, the first input signal and the second input signal are synchronously low, and the latch module enters the latch state.

[0007] Furthermore, one end of both the first load unit and the second load unit is connected to the high-side power supply, the other end of the first load unit is connected to the drain of the first transistor, and the other end of the first load unit is connected to the drain of the second transistor. The first load unit and the second load unit each independently include any one of the following: a resistor, a diode-connected MOSFET, and a cross-coupled MOSFET pair.

[0008] Furthermore, the first load unit includes a third transistor, and the second load unit includes a fourth transistor. The sources of both the third and fourth transistors are connected to the high-side power supply. The drain of the third transistor is connected to the drain of the first transistor, and the drain of the fourth transistor is connected to the drain of the second transistor.

[0009] Furthermore, the first voltage clamping unit and the second voltage clamping unit each independently include any one of the following structures: Zener diode, diode, and diode-connected MOSFET.

[0010] Furthermore, the first voltage clamping unit includes a first Zener diode, the second voltage clamping unit includes a diode and a second Zener diode, the cathode of the first Zener diode is connected to the high-side power supply, and the anode of the first Zener diode is connected to the gate of the fourth transistor. The cathode of the second Zener diode is connected to the high-side power supply, the anode of the second Zener diode is connected to the anode of the diode, and the cathode of the diode is connected to the gate of the third transistor.

[0011] Furthermore, the latch module includes any one of an RS flip-flop, a D flip-flop, and an inverter cross-coupled latch.

[0012] Furthermore, the latch module includes a first inverting Schmitt trigger, a second inverting Schmitt trigger, a first NOT gate, a second NOT gate, and a first inverter; The input terminal of the first inverting Schmitt trigger is connected to the first node, and the output terminal of the first inverting Schmitt trigger is connected to the second input terminal of the first NOT gate. The input terminal of the second inverting Schmitt trigger is connected to the second node, and the output terminal of the second inverting Schmitt trigger is connected to the first input terminal of the second NOT gate. The second input terminal of the second NOT gate is connected to the output terminal of the first NOT gate, and the output terminal of the second NOT gate is connected to the first input terminal of the first NOT gate. The output of the first NOT gate is also connected to the input of the first inverter, and the output of the first inverter outputs a level-shifted signal.

[0013] Furthermore, it also includes a current limiting module, one end of which is grounded and the other end is connected to the source of the first transistor and the second transistor; The current limiting module includes any one of the following: tail current source, resistor, and diode-connected MOSFET.

[0014] Furthermore, the current limiting module includes a fifth transistor, the drain of which is connected to the gates of the first and second transistors, and the source of which is grounded.

[0015] Furthermore, the current limiting module also includes a sixth transistor; the level shifting circuit also includes a bias circuit, which includes a second inverter, a constant current source, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; One end of the constant current source is connected to the low-side power supply, and the other end is connected to the drain of the eighth transistor; The gate of the eighth transistor is connected to an enable signal, and its source is connected to the drain and gate of the sixth transistor; the source of the sixth transistor is grounded. The gates of the seventh transistor, the fifth transistor, and the ninth transistor are all connected to the gate of the sixth transistor; the source of the seventh transistor is grounded. The input terminal of the second inverter is connected to the enable signal, the output terminal is connected to the gate of the ninth transistor, and the source of the ninth transistor is grounded. The gate of the tenth transistor is connected to an inverted enable signal, the source is grounded, and the drain is connected to the source of the second transistor.

[0016] Furthermore, it also includes the eleventh transistor, the twelfth transistor, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor; The source of the eleventh transistor is connected to the drain of the seventh transistor, the gate is connected to the enable signal, and the drain is connected to the drain and gate of the thirteenth transistor. The source and gate of the twelfth transistor are connected to the enable signal, and the drain is connected to the drain of the seventh transistor. The source of the thirteenth transistor is connected to the high-side power supply; The gates of the fourteenth transistor and the fifteenth transistor are both connected to the gate of the thirteenth transistor. The source of the fourteenth transistor is connected to the high-side power supply, and the drain is connected to the gate of the fourth transistor. The source of the fifteenth transistor is connected to the high-side power supply, and the drain is connected to the gate of the third transistor.

[0017] On the other hand, the present invention proposes a level shift control method, applied to the above-mentioned level shift circuit, comprising the following steps: The first transistor and the second transistor receive the first input signal and the second input signal, and the current limiting module limits the conduction current of the first transistor and the second transistor. The first and second nodes are pulled up by the load module, and the voltage of the first and second nodes is constrained to a safe range by the voltage clamping module. The latching module samples and latches the level signals of the first node and the second node, and outputs the level-shifted signal.

[0018] Compared with the prior art, the present invention has at least the following beneficial effects: This invention employs a differential input architecture, relying on a voltage clamping module to achieve node overvoltage protection and improve the reliability of high-voltage operation. The topologies of the current limiting, load, and clamping modules are selectable to adapt to various process and performance requirements. The latching module shapes and latches the signal, eliminating glitches for stable output. The circuit of this invention, through an enable-controlled bias branch, combined with an optimized bias circuit and current mirror, can stably complete high-to-low voltage signal conversion over a wide voltage range, improving reliability while ensuring transmission efficiency. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the level shifting circuit in one embodiment of the present invention; Figure 2 This is a detailed circuit diagram of a level shifting circuit in one embodiment of the present invention; Figure 3 This is a diagram of the truncated detection logic circuit in one embodiment of the present invention; Figure 4 This is a waveform timing diagram of a signal in one embodiment of the present invention.

[0020] Reference numerals: M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; M7, seventh transistor; M8, eighth transistor; M9, ninth transistor; M10, tenth transistor; M11, eleventh transistor; M12, twelfth transistor; M13, thirteenth transistor; M14, fourteenth transistor; M15, fifteenth transistor; Z1, first Zener diode; Z2, second Zener diode; D, diode; EN, enable signal; HP, high-side power supply; LP, low-side power supply; INP, first input signal; INN, second input signal; A, first node; B, second node; EN, enable signal; ENB, inverting enable signal. Detailed Implementation

[0021] Based on the teachings of this specification, those skilled in the art can form new technical solutions by combining different implementation methods without creating technical contradictions. Such variations should be considered to fall within the protection scope of this application.

[0022] The following is a more detailed description of a level shifting circuit and control method according to the present invention, with reference to schematic diagrams, illustrating preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0023] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0024] Example 1 like Figure 1 As shown, this embodiment of the invention proposes a level shifting circuit, including an input differential pair, a current limiting module, a load module, a voltage clamping module, and a latching module. The modules work together to convert the input signal in the low-voltage domain into the output signal in the high-voltage domain.

[0025] Specifically, such as Figure 2As shown, the input differential pair includes a first transistor M1 and a second transistor M2. The gate of the first transistor M1 receives a first input signal INP, and the gate of the second transistor M2 receives a second input signal INN, operating in the low-voltage domain. The input differential pair converts the input signal in the low-voltage domain into a current signal, driving the subsequent circuit to generate a corresponding voltage difference in the high-voltage domain, thereby realizing voltage domain conversion and making the level conversion transmission delay smaller and more symmetrical.

[0026] One end of the current limiting module is grounded, and the other end is connected to the source of the first transistor M1 and the second transistor M2. The current limiting module is used to limit the total current flowing through the input differential pair to prevent damage to the devices due to excessive current caused by differences in input signal levels. At the same time, by controlling the magnitude of the operating current, a reasonable balance is achieved between the circuit's operating speed and power consumption.

[0027] The load module includes a first load unit and a second load unit. One end of both the first and second load units is connected to the high-side power supply HP. The other end of the first load unit is connected to the drain of the first transistor M1, and the other end of the second load unit is connected to the drain of the second transistor M2. The load module provides independent high-voltage pull-up paths for the two differential output nodes, stabilizing the node potential to the high-side power supply when the transistors are turned off, thus avoiding leakage and false triggering problems caused by floating intermediate levels. The two independent loads can each form a differential amplification path with the transistors, completing the level conversion from low-voltage to high-voltage domains. Furthermore, the two node levels do not interfere with each other. This connection structure is compatible with the positive feedback mechanism of cross-coupled MOSFET loads, which can accelerate the node level switching speed and improve circuit response speed and output signal stability.

[0028] The voltage clamping module includes a first voltage clamping unit and a second voltage clamping unit. One end of both the first and second voltage clamping units is connected to the high-side power supply HP. The other end of the first voltage clamping unit is connected between the drain of the first transistor M1 and the first load unit, forming a first node A. The other end of the second voltage clamping unit is connected between the drain of the second transistor M2 and the second load unit, forming a second node B.

[0029] The voltage clamping module limits the voltage at the first node A and the second node B to a safe range. Specifically, it limits the voltage difference between the high-side power supply HP and the first node A, as well as the voltage difference between the high-side power supply HP and the second node B, to within the clamping voltage. This prevents the potential difference between the gate and source of the third transistor M3 and the fourth transistor M4 from exceeding the withstand voltage, effectively improving the reliability and lifespan of the circuit in high-voltage applications.

[0030] The latch module has its first input terminal connected to the first node A, its second input terminal connected to the second node B, and its output terminal outputting a level-shifted signal. The latch module latches and shapes the voltage signals at the first node A and the second node B, outputting a stable single-ended signal in the high-voltage domain. This eliminates glitches and uncertainties that may occur during level switching, making the output signal more stable and reliable.

[0031] When the level shifting circuit is in a non-high-side truncated state, the first input signal and the second input signal are out of phase, and a differential potential is output. The latching module is in a set state or a reset state, and outputs a level shifting signal in real time.

[0032] When the level shifting circuit is in the high-side truncation state, the first input signal and the second input signal are synchronously low, and the latch module enters the latch holding state, thereby avoiding the possibility of outputting an erroneous signal due to rapid changes in the high-side power supply HP.

[0033] In this embodiment, the first load unit and the second load unit each independently include any one of a resistor, a diode-connected MOSFET, and a cross-coupled load. When a resistor is used as the load unit, the circuit structure is simple and has high linearity. However, in the high-voltage domain, to consume less static power, a larger resistor value is required, resulting in a relatively larger chip area. Furthermore, the pull-up capability is greatly affected by process and temperature fluctuations, leading to insufficient circuit robustness. When a diode-connected MOSFET is used as the load unit, the nonlinear characteristics of the MOSFET are utilized to achieve a larger equivalent impedance, which helps to obtain sufficient voltage swing within a smaller area and facilitates circuit integration. When a cross-coupled load is used as the load unit, it can accelerate the differential node level switching, reduce signal transmission delay, enhance signal latching effect, effectively suppress level jitter and external interference, and improve output signal stability. The three methods can be flexibly selected according to specific process conditions and performance indicators.

[0034] In one specific embodiment, the first load unit includes a third transistor M3, and the second load unit includes a fourth transistor M4. The sources of both the third transistor M3 and the fourth transistor M4 are connected to the high-side power supply. The drain of the third transistor M3 is connected to the drain of the first transistor M1, and the drain of the fourth transistor M4 is connected to the drain of the second transistor M2.

[0035] The third transistor M3 and the fourth transistor M4 share a common high-side power supply HP at their sources, and their drains are respectively connected to the drains of the first transistor M1 and the second transistor M2. This connection method provides independent active pull-up loads for the first node A and the first node B, realizing the level conversion from low-voltage signals to high-voltage domains. Simultaneously, the third transistor M3 and the fourth transistor M4 can form a cross-coupled positive feedback structure, accelerating node level switching, improving circuit response speed, and the independence of the two loads avoids node signal crosstalk.

[0036] In this embodiment, the first voltage clamping unit and the second voltage clamping unit each independently include any one of the following: a Zener diode, a diode, and a diode-connected MOSFET structure. Zener diodes have stable reverse breakdown voltage characteristics, allowing for precise setting of the clamping voltage, making them suitable for applications requiring high clamping accuracy. Diodes achieve multi-level clamping through the superposition of the forward conduction voltages of multiple diodes, offering high design flexibility; the number of diodes connected in series can be adjusted to accommodate different clamping voltage requirements. Diode-connected MOSFET structures utilize the threshold voltage characteristics of MOSFETs for clamping, are fully compatible with standard CMOS processes, require no additional process support, and are suitable for fully integrated designs. These three methods can be flexibly selected based on specific process conditions and voltage levels, providing effective overvoltage protection for node voltages.

[0037] In one specific embodiment, the first voltage clamping unit includes a first Zener diode Z1, and the second voltage clamping unit includes a diode D and a second Zener diode Z2. The cathode of the first Zener diode Z1 is connected to the high-side power supply HP, and the anode of the first Zener diode Z1 is connected to the gate of the fourth transistor M4. The cathode of the second Zener diode Z2 is connected to the high-side power supply HP, and the anode of the second Zener diode Z2 is connected to the anode of the diode D. The cathode of the diode D is connected to the gate of the third transistor M3.

[0038] The first voltage clamping unit clamps the lowest level of the fourth transistor M4 at the level of the high-side power supply HP minus the regulated voltage value through the first Zener diode Z1, preventing the gate voltage of the fourth transistor M4 from dropping too low and protecting the fourth transistor M4, the third transistor M3, and the subsequent Schmitt trigger from overvoltage damage. The second voltage clamping unit provides a two-stage superimposed clamp at the gate of the third transistor M3 through the series combination of the second Zener diode Z2 and the diode D, avoiding reverse breakdown current during turn-off, increasing standby power consumption, and further improving the reliability of circuit operation.

[0039] In this embodiment, the latch module includes any one of an RS flip-flop, a D flip-flop, and an inverter cross-coupled latch. An RS flip-flop has set and reset functions, directly responding to voltage changes at the first node A and the second node B, generating a stable output state, suitable for processing differential asynchronous input signals. A D flip-flop is suitable for sampling the input signal at the clock edge, with the output signal synchronized with the system clock, suitable for synchronous digital systems. An inverter cross-coupled latch has a simple circuit structure, occupies a small chip area, and has low static power consumption, suitable for applications with high speed and area requirements. The three structures can be selected appropriately according to system design requirements.

[0040] In one specific embodiment, the latch module includes a first inverting Schmitt trigger, a second inverting Schmitt trigger, a first NOT gate, a second NOT gate, and a first inverter.

[0041] The input terminal of the first inverting Schmitt trigger is connected to the first node A, and the output terminal of the first inverting Schmitt trigger is connected to the second input terminal of the first NOT gate. The first inverting Schmitt trigger performs inversion shaping on the voltage signal at the first node A, eliminating glitches at the signal edges and improving the signal quality fed into the latch structure.

[0042] The input of the second inverting Schmitt trigger is connected to the second node B, and the output of the second inverting Schmitt trigger is connected to the first input of the second NOT gate. The second inverting Schmitt trigger and the first inverting Schmitt trigger form a symmetrical signal processing path, inverting and shaping the voltage signal at the second node B to maintain the timing consistency of the two signal processing paths.

[0043] The second input terminal of the second NOT gate is connected to the output terminal of the first NOT gate, and the output terminal of the second NOT gate is connected to the first input terminal of the first NOT gate. The first NOT gate and the second NOT gate form an SR latch structure through cross-coupling, which uses a positive feedback mechanism to accelerate the switching of the output signal, while keeping the output state unchanged during the switching transition phase of the input differential pair, avoiding uncertain state or brief erroneous output of the output signal, and keeping the output logic level stable at all times.

[0044] The output of the first NOT gate is also connected to the input of the first inverter, and the output of the first inverter outputs a level-shifted signal. The first inverter amplifies the latched signal, improving the driving capability of the output, enabling the level-shifting circuit to drive larger capacitive or resistive loads in the subsequent stage. Simultaneously, the shaping effect of the first inverter makes the rising and falling edges of the output signal steeper, improving the waveform quality of the output signal.

[0045] In this embodiment, the current limiting module includes any one of a tail current source, a resistor, and a diode-connected MOSFET. The tail current source is used to output a stable and constant current limiting value. Resistors have a simple structure and low implementation cost, but are relatively susceptible to process deviations and temperature changes, making them suitable for applications with low precision requirements. Diode-connected MOSFETs save chip area compared to resistors and are fully compatible with standard CMOS processes, making them suitable for applications with certain temperature characteristics requirements. By limiting the total current flowing through the input differential through the current limiting module, overall power consumption can be controlled while preventing excessive current from damaging devices, effectively extending the circuit's lifespan.

[0046] In one specific embodiment, the current limiting module includes a fifth transistor M5. The drain of the fifth transistor M5 is connected to the source of the first transistor M1 and the second transistor M2, and the source of the fifth transistor M5 is grounded. The fifth transistor M5 is equivalent to a current source controlled by the gate voltage. By adjusting the gate bias voltage of the fifth transistor M5, the magnitude of the tail current flowing through the input differential pair can be precisely set, thereby flexibly adjusting the circuit's operating current and power consumption while maintaining the circuit's stability under different operating conditions.

[0047] Furthermore, the current limiting module also includes a sixth transistor M6, and the level shifting circuit also includes a bias circuit, which includes a second inverter, a constant current source, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.

[0048] One end of the constant current source is connected to the low-side power supply LP, and the other end is connected to the drain of the eighth transistor M8. The gate of the eighth transistor M8 is connected to the enable signal EN, and its source is connected to the drain and gate of the sixth transistor M6, with the source of the sixth transistor M6 grounded. The eighth transistor M8 is controlled by the enable signal EN. When the enable signal EN is valid, the constant current source provides a stable bias current to the sixth transistor M6 through the eighth transistor M8, establishing a precise bias voltage at the gate of the sixth transistor M6.

[0049] The gates of the seventh transistor M7 and the fifth transistor M5 are both connected to the gate of the sixth transistor M6; the source of the seventh transistor M7 is grounded. The fifth transistor M5, the seventh transistor M7, and the sixth transistor M6 form a multi-path current mirror structure. If the device size ratio of the sixth transistor M6 to the seventh transistor M7 is 1:x, and the device size ratio of the sixth transistor M6 to the fifth transistor M5 is 1:y, then the branch current ratio of the sixth transistor M6, the seventh transistor M7, and the fifth transistor M5 corresponds to 1:x:y.

[0050] The inherent tracking characteristics of the current mirror structure enable the current in each branch to drift synchronously with process deviations and temperature changes, effectively suppressing the inconsistency of environmental factors on the operating points of each module and improving the stability and consistency of the entire circuit under different operating conditions.

[0051] The input of the second inverter is connected to the enable signal EN, and the output is connected to the gate of the ninth transistor M9, with the source of the ninth transistor M9 grounded. The second inverter inverts the enable signal EN, outputting an inverted enable signal ENB. When the enable signal EN is low, the second inverter outputs a high level, driving the ninth transistor M9 to conduct, quickly pulling down the relevant bias nodes, and rapidly disabling the circuit, reducing unnecessary static power consumption and achieving precise enable control.

[0052] When the enable signal EN is high, the eighth transistor M8 is turned on, while the ninth transistor M9 and the tenth transistor M10 are turned off. The sixth transistor M6 and the seventh transistor M7 remain on, generating a mirror current. The fifth transistor M5 outputs a current-limiting current based on the input differential to control the on / off states of the first transistor M1 and the second transistor M2, precisely suppressing the surge current generated when the transistors are turned on. When the enable signal EN is low, the eighth transistor M8 is turned off, while the ninth transistor M9 and the tenth transistor M10 are turned on. The gate potentials of the sixth transistor M6, the seventh transistor M7, and the fifth transistor M5 are pulled to ground by the ninth transistor M9, and the drain potential of the fifth transistor M5 is pulled to ground by the tenth transistor M10. The current mirror branch stops working.

[0053] The gate of the tenth transistor M10 is connected to the inverting enable signal ENB, its source is grounded, and its drain is connected to the source of the second transistor M2. When the enable signal EN is low, the inverting enable signal ENB is high, the first input signal INP is low, the second input signal INN is high, the second transistor M2 and the tenth transistor M10 pull down the second node B to ground, and the third transistor M3 pulls the first node A up to the high-side power supply HP. When the enable signal EN is low, the system pulls down the high-side power supply HP to the same potential as the low-side power supply LP. Therefore, there is no reverse breakdown current on the second Zener diode Z2, and the gate-source voltage and drain-source voltage of all transistors in the circuit will not exceed the overvoltage limit.

[0054] In this embodiment, the level shifting circuit further includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15.

[0055] The source of the eleventh transistor M11 is connected to the drain of the seventh transistor M7, and its gate is connected to the enable signal EN. The drain of the eleventh transistor M11 is also connected to the drain and gate of the thirteenth transistor M13. The source and gate of the twelfth transistor M12 are connected to the enable signal EN, and its drain is connected to the drain of the seventh transistor M7. The eleventh transistor M11 and the twelfth transistor M12 together constitute a level-shifting auxiliary structure across voltage domains, converting the current signal from the low-side power domain into an intermediate-level signal suitable for driving the gate of the high-voltage domain transistor. This solves the interface matching problem between the low-voltage domain control signal and the high-voltage domain load module, enabling effective signal transmission across power domains.

[0056] The source of the thirteenth transistor M13 is connected to the high-side power supply HP. The gates of the fourteenth transistor M14 and the fifteenth transistor M15 are both connected to the gate of the thirteenth transistor M13. The thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 form a current mirror structure in the high-side power supply HP domain. Using the thirteenth transistor M13 as a reference branch, a stable bias reference is established in the high-voltage domain, providing a stable operating current related to the high-side power supply HP for the subsequent high-voltage domain circuit.

[0057] The source of the fourteenth transistor M14 is connected to the high-side power supply HP, and its drain is connected to the gate of the fourth transistor M4; the source of the fifteenth transistor M15 is connected to the high-side power supply HP, and its drain is connected to the gate of the third transistor M3. When the first transistor M1 and the second transistor M2 are turned off, the fourteenth transistor M14 and the fifteenth transistor M15 can pull up the potential of the first node A and the second node B, causing the latch to enter a holding state and preventing erroneous output.

[0058] like Figure 3 As shown, the truncated detection logic circuit includes a D flip-flop, a NAND gate, and two inverters to generate the input signals required by the level shifting circuit (i.e., the first input signal INP and the second input signal INN). Combined with the triangular wave TRI, the integrator output signal INTO, the pulse width modulation signal PWM, and their timing waveforms, the timing waveform diagram is shown below. Figure 4 As shown, the complete working process of a level shifting circuit can be divided into the following three stages: The first stage is the normal modulation operation stage. The clock signal CLK level corresponds one-to-one with the edge of the triangular wave TRI. A low level of the clock signal CLK corresponds to the falling edge of the triangular wave TRI, and a high level of the clock signal CLK corresponds to the rising edge of the triangular wave TRI. The integrator output signal INTO is compared with the triangular wave TRI in real time. When the integrator output signal INTO is higher than the triangular wave TRI, the pulse width modulation signal PWM outputs a low level; when the integrator output signal INTO is lower than the triangular wave TRI, the pulse width modulation signal PWM outputs a high level. The high level of the pulse width modulation signal PWM is the high-side power transistor turn-on signal, and the low level of the pulse width modulation signal PWM is the low-side power transistor turn-on signal.

[0059] The D flip-flop samples the signal based on the clock signal CLK. The output signal of the D flip-flop and the pulse width modulation (PWM) signal are input to a NAND gate, and then through a single inverter to obtain the second input signal INN. The PWM signal is directly passed through another inverter to generate the first input signal INP. The first input signal INP and the second input signal INN form a periodic differential signal, which is input to the first transistor M1 and the second transistor M2.

[0060] When the first input signal INP is high and the second input signal INN is low, the first transistor M1 is turned on and the second transistor M2 is turned off. The current limiting module generates current that flows through the first transistor M1 and the first load unit. The potential of the first node A is pulled low, while the second node B remains high. The latch module outputs the corresponding high-voltage logic based on the potentials of the first node A and the second node B.

[0061] When the first input signal INP is low and the second input signal INN is high, the process is reversed: the potential of the second node B is pulled down, while the first node A remains high, and the output of the latch module flips synchronously. At this time, the fifth transistor M5 continuously provides a stable operating current, and the potentials of the first node A and the second node B dynamically switch with the differential input. The latch module updates its output state in real time following the input.

[0062] The second stage is the high-side truncation stage. The integrator output signal INTO remains higher than the triangular wave TRI, and the pulse width modulation signal PWM remains at a constant high level, continuously outputting the high-side power transistor turn-on command. When the rising edge of the next clock signal CLK arrives, the D flip-flop completes sampling and latching, and the output level flips, causing the second input signal INN to flip to a low level. At this time, the pulse width modulation signal PWM is at a high level, and the first input signal INP output by the inverter is also at a low level. The first input signal INP and the second input signal INN of the level shift circuit are simultaneously at a low level. The gates of the first transistor M1 and the second transistor M2 are both at a low potential, and the two input transistors are synchronously turned off with no current path. The fifth transistor M5 stops outputting operating current. The pull-up current source formed by the fourteenth transistor M14 and the fifteenth transistor M15 pulls the first node A and the second node B up to the high-side power supply HP potential. The inputs at both ends of the latch module are at a high level, entering the state-holding latching mode. At this time, there is only a small bias current flowing from the thirteenth transistor M13 to ground in the high-voltage domain branch, and the static power consumption of the circuit is significantly reduced.

[0063] The third stage is the post-truncation recovery switching stage. The integrator output signal INTO falls back below the triangular wave TRI, and the pulse width modulation signal (PWM) resumes its periodic high-low level alternation. On the rising edge of the next clock signal CLK, it triggers the D flip-flop to flip, and the output level of the D flip-flop switches synchronously. The second input signal INN resumes its periodic high-low transition, and the first input signal INP follows the PWM signal to flip synchronously. The first input signal INP and the second input signal INN re-form a periodic differential input signal. The first transistor M1 and the second transistor M2 alternately conduct with the differential input, and the fifth transistor M5 resumes outputting the current-limiting operating current. The first node A and the second node B are dynamically pulled down or pulled up according to the input differential signal. The latch module alternately outputs the corresponding high-voltage logic level according to the potential of the first node A and the second node B. The latch module exits the holding state and updates the output in real time, and the circuit returns to the cycle-by-cycle normal switching operation mode of the first stage.

[0064] The overall circuit generates a pulse width modulation (PWM) signal by comparing the clock signal CLK, the triangular wave TRI, and the integrator output signal INTO in real time. Relying on the timing latch logic of the D flip-flop, it identifies the high-side truncation condition and simultaneously pulls the first input signal INP and the second input signal INN to a low level, so that the level shifting circuit switches to the static low-power holding mode, realizing the detection of the high-side truncation state and the adaptation to low-power operation.

[0065] Example 2 This embodiment proposes a level shift control method, applied to the level shift circuit described in Embodiment 1, comprising the following steps: The first and second transistors receive the first and second input signals, respectively, and the current limiting module limits the input current. The first and second transistors each receive one of the two input signals; the differential input architecture results in shorter level transition transmission delays and closer proximity of positive and negative edge delays. The current limiting module restricts the branch conduction current, weakening the spike current generated when the transistor turns on, preventing device damage or breakdown caused by instantaneous large currents, and extending device lifespan.

[0066] The load module pulls up the first and second nodes, and the voltage clamping module constrains the voltages of the first and second nodes to a safe range. The load module pulls up the two signal branches respectively, raising the potentials of the first and second nodes to the high-side power supply potential when the transistors are turned off. This prevents node floating, leakage, and level inconsistencies, and avoids false triggering of downstream circuits. The voltage clamping module can constrain the voltages of the two nodes in real time, stabilizing the potentials within a safe operating range, preventing high-voltage potentials from impacting the transistors in the high-voltage and low-voltage domains, achieving continuous overvoltage protection, and improving the reliability of circuit operation in high-voltage scenarios.

[0067] The latch module acquires the level signals of the first node and the second node, and outputs the level-shifted signal. The latch module acquires the levels of the two differential nodes and filters out signal glitches and level jitter generated during transmission, eliminating signal instability and outputting a regular and reliable high-voltage level signal. Simultaneously, it relies on a positive feedback mechanism to accelerate the level switching speed, reduce signal transmission delay, and ensure output signal quality.

[0068] In summary, this invention, by incorporating a voltage clamping module, limits the input differential-to-drain voltage to a safe range, preventing damage to devices in both high-voltage and low-voltage domains from high-voltage voltage. This effectively achieves overvoltage protection and improves the circuit's operational reliability and device lifespan under high-voltage conditions. The load module, voltage clamping module, and current limiting module can be implemented using various circuit configurations, allowing for flexible selection based on actual process conditions, voltage levels, and performance specifications, resulting in greater circuit process adaptability and design versatility. The latching module, combined with cross-coupled NOT gates, inverters, and inverting amplifiers, latches and shapes the signals at the differential nodes, eliminating signal glitches and instability, and ensuring output signal quality. The entire circuit relies on the enable signal to control the bias circuit. With the assistance of optimized bias circuitry, current mirrors, and cross-domain level conversion auxiliary circuitry, stable cross-voltage level conversion can be achieved over a wide voltage range, adapting to various high- and low-voltage combinations and broadening its application scope.

[0069] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A level shifting circuit, characterized in that, include: The input differential pair includes a first transistor and a second transistor, wherein the gate of the first transistor receives a first input signal and the gate of the second transistor receives a second input signal; The load module includes a first load unit and a second load unit. The first load unit includes a third transistor, and the second load unit includes a fourth transistor. The sources of the third transistor and the fourth transistor are both connected to a high-side power supply. The drain of the third transistor is connected to the drain of the first transistor, and the drain of the fourth transistor is connected to the drain of the second transistor. A voltage clamping module includes a first voltage clamping unit and a second voltage clamping unit. One end of each of the first and second voltage clamping units is connected to a high-side power supply. The other end of the first voltage clamping unit is connected between the drain of the first transistor and the first load unit, forming a first node. The other end of the second voltage clamping unit is connected between the drain of the second transistor and the second load unit, forming a second node. The first voltage clamping unit includes a first Zener diode, the second voltage clamping unit includes a diode and a second Zener diode, the cathode of the first Zener diode is connected to the high-side power supply, and the anode of the first Zener diode is connected to the gate of the fourth transistor. The cathode of the second Zener diode is connected to the high-side power supply, the anode of the second Zener diode is connected to the anode of the diode, and the cathode of the diode is connected to the gate of the third transistor; The latch module has a first input terminal connected to the first node, a second input terminal connected to the second node, and an output terminal that outputs a level-shifted signal. The fourteenth and fifteenth transistors, the gates of the fourteenth and fifteenth transistors are both connected to the gate of the thirteenth transistor, the sources of the fourteenth and fifteenth transistors are connected to the high-side power supply, the drain of the fourteenth transistor is connected to the gate of the fourth transistor, and the drain of the fifteenth transistor is connected to the gate of the third transistor. When the level shift circuit is in a non-high-side truncation state, the first input signal and the second input signal are out of phase, and a differential potential is output. The latch module is in a set state or a reset state, and outputs a level shift signal in real time. When the level shifting circuit is in the high-side truncation state, the first input signal and the second input signal are synchronously low level. The pull-up current source formed by the fourteenth transistor and the fifteenth transistor pulls the first node and the second node up to the high-side power supply. The inputs at both ends of the latch module are high level, and the latch module enters the latch state.

2. The level shifting circuit as described in claim 1, characterized in that, One end of both the first load unit and the second load unit is connected to the high-side power supply, and the other end of the first load unit is connected to the drain of the first transistor and the other end of the first load unit is connected to the drain of the second transistor. The first load unit and the second load unit each independently include any one of the following: a resistor, a diode-connected MOSFET, and a cross-coupled MOSFET pair.

3. The level shifting circuit as described in claim 1, characterized in that, The first voltage clamping unit and the second voltage clamping unit each independently include any one of the following structures: Zener diode, diode, and diode-connected MOSFET.

4. The level shifting circuit as described in claim 1, characterized in that, The latch module includes any one of RS flip-flops, D flip-flops, and inverter cross-coupled latches.

5. The level shifting circuit as described in claim 4, characterized in that, The latch module includes a first inverting Schmitt trigger, a second inverting Schmitt trigger, a first NOT gate, a second NOT gate, and a first inverter; The input terminal of the first inverting Schmitt trigger is connected to the first node, and the output terminal of the first inverting Schmitt trigger is connected to the second input terminal of the first NOT gate. The input terminal of the second inverting Schmitt trigger is connected to the second node, and the output terminal of the second inverting Schmitt trigger is connected to the first input terminal of the second NOT gate. The second input terminal of the second NOT gate is connected to the output terminal of the first NOT gate, and the output terminal of the second NOT gate is connected to the first input terminal of the first NOT gate. The output of the first NOT gate is also connected to the input of the first inverter, and the output of the first inverter outputs a level-shifted signal.

6. The level shifting circuit as described in claim 1, characterized in that, It also includes a current limiting module, one end of which is grounded and the other end is connected to the source of the first transistor and the second transistor; The current limiting module includes any one of the following: tail current source, resistor, and diode-connected MOSFET.

7. The level shifting circuit as described in claim 6, characterized in that, The current limiting module includes a fifth transistor, the drain of which is connected to the gates of the first and second transistors, and the source of which is grounded.

8. The level shifting circuit as described in claim 7, characterized in that, The current limiting module further includes a sixth transistor; the level shifting circuit further includes a bias circuit, which includes a second inverter, a constant current source, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; One end of the constant current source is connected to the low-side power supply, and the other end is connected to the drain of the eighth transistor; The gate of the eighth transistor is connected to an enable signal, and its source is connected to the drain and gate of the sixth transistor; the source of the sixth transistor is grounded. The gates of the seventh transistor, the fifth transistor, and the ninth transistor are all connected to the gate of the sixth transistor; the source of the seventh transistor is grounded. The input terminal of the second inverter is connected to the enable signal, the output terminal is connected to the gate of the ninth transistor, and the source of the ninth transistor is grounded. The gate of the tenth transistor is connected to an inverted enable signal, the source is grounded, and the drain is connected to the source of the second transistor.

9. The level shifting circuit as described in claim 1, characterized in that, It also includes the eleventh, twelfth, thirteenth, fourteenth, and fifteenth transistors; The source of the eleventh transistor is connected to the drain of the seventh transistor, the gate is connected to the enable signal, and the drain is connected to the drain and gate of the thirteenth transistor. The source and gate of the twelfth transistor are connected to the enable signal, and the drain is connected to the drain of the seventh transistor. The source of the thirteenth transistor is connected to the high-side power supply; The gates of the fourteenth transistor and the fifteenth transistor are both connected to the gate of the thirteenth transistor. The source of the fourteenth transistor is connected to the high-side power supply, and the drain is connected to the gate of the fourth transistor. The source of the fifteenth transistor is connected to the high-side power supply, and the drain is connected to the gate of the third transistor.

10. A level shift control method, characterized in that, The application of the level shifting circuit according to any one of claims 1-9 includes the following steps: The first transistor and the second transistor receive the first input signal and the second input signal, and the current limiting module limits the conduction current of the first transistor and the second transistor. The first node and the second node are pulled up by the load module, and the voltage of the first node and the second node are constrained to a safe range by the voltage clamping module. The latching module samples and latches the level signals of the first node and the second node, and outputs the level-shifted signal.

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