A stacked system-in-package module and a welding method thereof

Abstract

The application provides a stacked system module and a welding method thereof. The system module comprises a first substrate, a carrier plate and a second substrate stacked in sequence along a first direction. The first substrate comprises a first surface and a second surface arranged oppositely, and the second surface is provided with a first pad. The second substrate comprises a third surface and a fourth surface arranged oppositely, wherein the third surface faces the second surface, and the third surface is provided with a second pad. The carrier plate comprises an opening and a connecting piece, wherein, along the first direction, projections of the first pad and the second pad are both located at the periphery of the projection of the opening, and the connecting piece is used for electrically connecting part of the first pad and part of the second pad through the connecting piece. The system module is beneficial to reducing the warping of the system module, reducing the failure rate of welding the first substrate and the second substrate on the carrier plate, facilitating heat dissipation of the first substrate and the second substrate, and improving the space utilization of the system module.

Description

Technical Field

[0001] This application relates primarily to the field of electronic circuit design, and more particularly to a stacked system module and its soldering method. Background Technology

[0002] A System on Module (SoM) is an embedded module design. The electronic components included in a SoM can be flexibly reduced or removed according to required functions. It typically includes a processor (CPU), storage components, power management circuitry, and clock circuitry. The SoM integrates all its electronic components onto a PCB (Printed Circuit Board), which is then soldered onto a carrier board. In some cases, the carrier board is also called the main board or system function board. Typically, the carrier board can include peripheral electronic components, such as detection circuits, amplification circuits, and circuit adapters; the carrier board may also include various interfaces that bring out CPU pins.

[0003] The various electronic components in a system module are typically composed of different materials with varying coefficients of thermal expansion. After soldering or surface mount technology (SMT) processes, the different coefficients of thermal expansion of these materials generate thermal stress, leading to microscopic strain and overall deformation, resulting in PCB warpage. The JEITA-7306 standard provides methods for measuring PCB warpage and formulas for calculating warpage degree; other aspects of PCB warpage can also be referenced in this standard. PCB warpage reduces the mechanical and electrical properties of the PCB to some extent. For example, increased mechanical stress makes it more prone to fracture under external force; poor soldering can lead to open circuits and other problems. Soldering the system module to the carrier board can also easily lead to soldering failures, such as open circuits and short circuits.

[0004] Therefore, there is an urgent need for a new system module to reduce or eliminate PCB warpage, improve the mechanical and electrical stability of the system module, and reduce the soldering failure rate between the system module and the carrier board. Summary of the Invention

[0005] This application addresses the technical problem of PCB warpage in system modules by providing a stacked system module and its soldering method, which can reduce PCB warpage and decrease the soldering failure rate between the system module and the carrier board.

[0006] To address the aforementioned technical problems, this application provides a stacked system module, comprising a first substrate, a carrier plate, and a second substrate stacked sequentially along a first direction. The first substrate includes a first surface and a second surface disposed opposite to each other, with a first pad disposed on the second surface. The second substrate includes a third surface and a fourth surface disposed opposite to each other, with the third surface facing the second surface and a second pad disposed on the third surface. The carrier plate includes an opening and a connector, wherein, along the first direction, the projections of the first pad and the second pad are both located outside the projection of the opening, and the connector is used to electrically connect a portion of the first pad and a portion of the second pad through the connector.

[0007] In some embodiments, along a first direction, the first projection of a portion of the first pad and the second projection of a portion of the second pad coincide.

[0008] In some embodiments, the connector extends along a first direction such that the conduction distance between a portion of the first pad and a portion of the second pad is minimized.

[0009] In some embodiments, a first electronic component is disposed on the first surface, the first electronic component including at least one of the following electronic components: a processor, a memory, and a clock oscillator.

[0010] In some embodiments, a second electronic component is disposed on the second surface, and a third electronic component is disposed on the third surface, both of which are located in the opening.

[0011] In some embodiments, a fourth electronic component is disposed on the fourth surface, the fourth electronic component including at least one of the following electronic components: a power management circuit and a clock oscillator.

[0012] In some embodiments, the stacked system module further includes metal pillars disposed at the opening, the first substrate further includes a first metal pillar pad, the second substrate further includes a second metal pillar pad, the first metal pillar pad and the second metal pillar pad are disposed opposite to each other, and the metal pillars are welded between the first metal pillar pad and the second metal pillar pad.

[0013] In some embodiments, the system module further includes a first heat sink and a second heat sink, wherein the first heat sink is disposed above the first substrate and the second heat sink is disposed below the second substrate along a first direction.

[0014] To address the aforementioned technical problems, this application also provides a welding method for a stacked system module, used in the stacked system module as described above. The welding method includes the following steps: welding a second electronic component to a second surface of a first substrate; welding a first electronic component to a first surface of the first substrate; welding a third electronic component to a third surface of a second substrate; welding a fourth electronic component to a fourth surface of the second substrate; welding the second substrate to a lower surface of a carrier plate, wherein the third surface is in contact with the carrier plate; and welding the first substrate to an upper surface of the carrier plate, wherein the second surface is in contact with the carrier plate.

[0015] In some embodiments, the welding method further includes: welding a metal pillar to a third surface while welding a second substrate to the lower surface of a carrier plate; and welding a metal pillar to a second surface while welding a first substrate to the upper surface of a carrier plate.

[0016] Compared with the prior art, this application has the following advantages: the first substrate, the carrier plate and the second substrate are stacked in sequence, and the warpage of the first substrate and the warpage of the second substrate can be offset to a certain extent, reducing the warpage of the entire system module and reducing the welding failure rate of the first substrate and the second substrate on the carrier plate; the carrier plate is provided with openings, which is conducive to heat dissipation of the first substrate and the second substrate and improves the space utilization of the system module. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings:

[0018] Figure 1 This is a schematic diagram of PCB warpage.

[0019] Figure 2 This is a schematic diagram of PCB concave warpage;

[0020] Figure 3 This is a schematic diagram showing that the PCB has not warped.

[0021] Figure 4 This is a cross-sectional schematic diagram of a stacked system module provided in an embodiment of this application;

[0022] Figure 5 This is a schematic diagram of the first surface of the first substrate in a system module provided in an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of the second surface of the first substrate in a system module provided in an embodiment of this application;

[0024] Figure 7This is a schematic diagram of the fourth surface of the second substrate in a system module provided in an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the third surface of the second substrate in a system module provided in an embodiment of this application;

[0026] Figure 9 This is a cross-sectional schematic diagram of a stacked system module provided in another embodiment of this application;

[0027] Figure 10 This is a schematic diagram of the second surface of the first substrate in a system module provided in another embodiment of this application;

[0028] Figure 11 This is a schematic diagram of the third surface of the second substrate in a system module provided in another embodiment of this application;

[0029] Figure 12 This is a cross-sectional schematic diagram of a stacked system module provided in another embodiment of this application;

[0030] Figure 13 This is an exemplary flowchart of a welding method for stacked system modules provided in an embodiment of this application.

[0031] Figure Labels

[0032] System module, 100;

[0033] First substrate, 110;

[0034] First surface, 111;

[0035] Second surface, 112;

[0036] First pad, 113;

[0037] First Electronic Components, 114;

[0038] Second electronic component, 115;

[0039] First area, 116;

[0040] Second substrate, 120;

[0041] Third surface, 121;

[0042] Fourth surface, 122;

[0043] Second pad, 123;

[0044] Third electronic component, 124;

[0045] Fourth electronic component, 125;

[0046] Second area, 126;

[0047] Carrier board, 130;

[0048] Opening, 131;

[0049] Connector, 132;

[0050] Metal column, 140;

[0051] First metal pillar pad, 141;

[0052] Second metal pillar pad, 142;

[0053] First heat sink component, 151;

[0054] Second heat sink, 152;

[0055] Thermal interface materials, 153;

[0056] Active electronic components, 201;

[0057] Passive electronic components, 202;

[0058] Pad, 203;

[0059] PCB, 204;

[0060] The top surface of the PCB, 205;

[0061] The bottom surface of the PCB is 206.

[0062] First direction, x. Detailed Implementation

[0063] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0064] As indicated in this application, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0065] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0066] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0067] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0068] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0069] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0070] Figure 1 This is a schematic diagram of PCB204 warping. Figure 2 This is a schematic diagram of the concave warpage of PCB204; Figure 3 This is a schematic diagram showing that PCB204 has not warped. Figure 1 In this context, the warpage of PCB204 is described as convex warpage, also known as a "crying face" pattern. Figure 2 In this context, the warpage of PCB204 is described as concave warpage, also known as a smiley face. Figure 3 In the middle, PCB204 is in a flat state and has not warped. Figures 1-3 In this design, the upper surface 205 of PCB 204 houses active electronic components 201 of the system module, such as processors, memory, and clock oscillators. The lower surface 206 of PCB 204 houses passive electronic components 202, such as resistors and capacitors. The lower surface 206 of PCB 204 also has pads 203. Active electronic components 201 are components that, when powered, can actively amplify, oscillate, control current, or distribute energy to electrical signals, and even perform data processing. Active electronic components 201 include various transistors, integrated circuits (ICs), image tubes, and displays. Passive electronic components 202, in contrast to active components, refer to components that do not have the function of amplifying, oscillating, or controlling electrical signals; their response to electrical signals is passive and compliant, and they do not affect the basic characteristics of the electrical signals. Common examples include resistors, capacitors, and inductors, which are passive electronic components 202.

[0071] The integrated circuit (IC) in active electronic component 201 and the passive electronic component 202 have different coefficients of thermal expansion (CTE). After reflow soldering heating in the surface mount process, the different degrees of expansion between the IC and the passive electronic component 202 lead to uneven stress distribution. During cooling, the IC contracts faster, while the passive electronic component 202 contracts slower. This uneven contraction causes the PCB 204 to warp. In this case, if the active electronic component 201 is located on the upper surface 205 of the PCB 204, the warping direction of the PCB 204 is convex. If the active electronic component 201 is located on the lower surface 206 of the PCB, the warping direction of the PCB 204 is concave.

[0072] Figure 4 This is a cross-sectional view of a stacked system module 100 according to an embodiment of this application. Figure 5 This is a schematic diagram of the first surface 111 of the first substrate 110 in a system module 100 provided in an embodiment of this application.

[0073] Figure 6 This is a schematic diagram of the second surface 112 of the first substrate 110 in a system module 100 provided in an embodiment of this application. Figure 7 This is a schematic diagram of the fourth surface 122 of the second substrate 120 in a system module 100 provided in an embodiment of this application. Figure 8 This is a schematic diagram of the third surface 121 of the second substrate 120 in a system module 100 provided in an embodiment of this application. The following is in conjunction with... Figures 4-8 This application describes a stacked system module 100 according to an embodiment of the present application.

[0074] like Figure 4 , Figure 6 and Figure 8 As shown, the system module 100 includes a first substrate 110, a carrier plate 130, and a second substrate 120 stacked sequentially along a first direction x. Figure 4 As shown, system module 100 can be used in practical applications according to... Figure 4The system module 100 is placed in the orientation shown, that is, the first direction x is a vertical direction from top to bottom. However, other placement orientations can be used in actual applications, therefore, this application does not limit the first direction x. The first substrate 110 includes a first surface 111 and a second surface 112 disposed opposite to each other, with a first pad 113 disposed on the second surface 112. The second substrate 120 includes a third surface 121 and a fourth surface 122 disposed opposite to each other, with the third surface 121 facing the second surface 112, and a second pad 123 disposed on the third surface 121. The carrier board 130 includes an opening 131 and a connector 132, wherein, along the first direction x, the projections of the first pad 113 and the second pad 123 are located outside the projection of the opening 131, and the connector 132 is used to electrically connect a portion of the first pad 113 and a portion of the second pad 123 through the connector 132.

[0075] Continue to refer to Figure 4 , Figure 6 and Figure 8 In some embodiments, compared with the prior art, this application splits the system module originally mounted on a single substrate into separate first substrate 110 and second substrate 120, and connects the first substrate 110 and the second substrate 120 together through connectors 132 on a carrier board 130. In this type of embodiment, the connector 132 can be a solder pad, respectively disposed on the upper and lower surfaces of the carrier board 130, and the connection between the first substrate 110 and the second substrate 120 is achieved by soldering, which is an electrical connection. The carrier board 130 can be a multilayer PCB board. In some embodiments, the connector 132 can be an internal trace, laser via, buried via, or through-hole of the PCB board, used to partially connect the first solder pad 113 on the upper surface of the carrier board 130 with the second solder pad 123 on the lower surface, thereby connecting the first substrate 110 and the second substrate 120. The laser via is formed by precisely drilling holes in the PCB board using a high-energy laser beam and depositing metal on the inner wall of the hole to achieve electrical connection between different layers. A buried via is a hole located inside a PCB, with metal deposited on its inner wall to achieve electrical connection between different layers. A via is a through-hole that penetrates the PCB board, typically with a conductive material (such as copper) plated on its inner wall to achieve electrical connection between different layers. In some embodiments, the connector 132 can also be a conductive pin penetrating the carrier board 130 to achieve electrical connection between the first substrate 110, the second substrate 120, and the carrier board 130.

[0076] Continue to refer to Figure 4 , Figure 6 and Figure 8 In some embodiments, the carrier board 130 further has an opening 131, and the projections of the first pad 113 and the second pad 123 on the carrier board 130 are both located outside the projection of the opening 131 on the carrier board 130. (See reference...) Figure 6 and Figure 8 As shown, the first substrate 110 has a first region 116 that is adapted to the size and position of the opening 131, and the second substrate 120 also has a second region 126 that is adapted to the size and position of the opening 131. The first pad 113 and the second pad 123 are respectively disposed around the first region 116 and the second region 126.

[0077] like Figure 5 As shown, in some embodiments, the first surface 111 is provided with a first electronic component 114, which includes at least one of the following electronic components: a processor, a memory, and a clock oscillator. In such embodiments, the first electronic component 114 is primarily an active electronic component of the system module 100. In some embodiments, the first electronic component 114 also includes passive electronic components such as resistors, inductors, and capacitors that match the processor, memory, and clock oscillator. In this application, the processor can be a microprocessor (MCU), a central processing unit (CPU), a system-on-a-chip (SOC), a field-programmable gate array (FPGA), a graphics processing unit (GPU), a digital signal processor (DSP), a programmable logic controller (PLC), and an application-specific integrated circuit (ASIC), etc. The processor can achieve logic control and data processing for specific tasks through clever programming or customized electronic circuits. The memory can be flash memory, electrically erasable programmable read-only memory (EEPROM), double data rate synchronous dynamic random access memory (SDRAM), and dynamic random access memory (DRAM), etc. The memory is primarily used to store various types of data in the system module 100, such as processor program code, pre-loaded data, and calculation results. A clock oscillator is a component in an electronic device used to generate a periodic clock signal. In this application, the clock oscillator can provide a periodic clock signal to electronic circuits such as processors, memory, and power management integrated circuits. In some embodiments, the clock oscillator can be a crystal oscillator, an RC oscillator, an LC oscillator, or a MEMS oscillator. In some embodiments, the clock oscillator can also be a combination of a crystal oscillator and a phase-locked loop (PLL), where the crystal oscillator generates a baseband signal, which is then multiplied or divided by the PLL before being output to other electronic circuits.

[0078] like Figure 7As shown, in some embodiments, the fourth surface 122 is provided with a fourth electronic component 125, which includes at least one of the following electronic components: a power management circuit and a clock oscillator. In such embodiments, the fourth surface 122 of the second substrate 120 is mainly provided with power control-related components, such as a power management integrated circuit (PMIC), a linear low-dropout regulator (LDO), and a switching regulator. The fourth electronic component 125 may also include a clock oscillator, which provides a stable clock signal to the power management integrated circuit, ensuring that the power management integrated circuit can operate and be controlled at predetermined time intervals. In some embodiments, the fourth electronic component 125 also includes passive electronic components such as capacitors, resistors, and inductors.

[0079] In some embodiments, the overall size of the first substrate 110 is larger than that of the second substrate 120, and the number of first pads 113 is greater than or equal to the number of second pads 123. This is because the first substrate 110 houses a processor, which has many signal pins, requiring more first pads 113 to connect to these pins. In some embodiments, the first pads 113 connected to the signal pins can also be connected to the carrier board 130 via connectors 132, thus connecting the signal pins to the carrier board 130.

[0080] like Figure 6 and Figure 8 As shown, the second electronic component 115 and the third electronic component 124 are mainly passive components, such as bypass capacitors, decoupling capacitors, inductors, and resistors. The bypass capacitors and decoupling capacitors have relatively large capacitance values, and the second electronic component 115 and the third electronic component 124 are relatively large in size. By placing the second electronic component 115 and the third electronic component 124 in the opening 131 and making reasonable use of the space in the opening 131, the space utilization rate of the system module 100 can be improved.

[0081] In some embodiments, to optimize the power distribution network (PDN), placing decoupling capacitors directly behind the power supply pins of the integrated circuit (IC) can achieve the shortest current path and obtain the optimal PDN result. A power distribution network (PDN) is a key component in an electronic system responsible for distributing and managing electrical energy. A PDN consists of power supplies, decoupling capacitors, power planes, and ground planes. Stable power supply and low-impedance circuit design can meet processor (CPU) design specifications. In some embodiments, optimal PDN design can be achieved on the PCB surface through reasonable stack-up design (e.g., power and ground are adjacent layers), reducing output-to-load impedance, optimizing capacitor selection, optimizing capacitor placement, and reducing parasitic inductance effects. In some embodiments, the first substrate 110 can be a multi-layer PCB. For electrical connections, if some first electronic components 114 and some second electronic components 115 are connected, vias and internal traces can be provided at corresponding positions on the first substrate 110 to connect the connected first electronic components 114 and some second electronic components 115. For example, the decoupling capacitor and bypass capacitor of the second electronic component 115 can be disposed at the projection of the power supply pin of the first electronic component 114 processor on the second surface 112, and connected by vias. In some embodiments, the second substrate 120 can be a multilayer PCB. In terms of electrical connection, if some of the fourth electronic components 125 and some of the third electronic components 124 are connected, vias and internal traces can be disposed at corresponding positions on the second substrate 120 to connect the connected fourth electronic components 125 and third electronic components 124. For example, the decoupling capacitor and bypass capacitor of the third electronic component 124 are disposed at the projection of the power supply pin of the power management integrated circuit on the third surface 121, and connected by vias. According to these embodiments, PDN optimization can be achieved, ensuring stable power supply, reducing power supply noise and parasitic inductance, and optimizing the position of capacitor placement.

[0082] In some embodiments, a second electronic component 115 is disposed on the second surface 112, and a third electronic component 124 is disposed on the third surface 121. Both the second electronic component 115 and the third electronic component 124 are located in the opening 131. Figure 4 and Figure 6 As shown, the second electronic component 115 is disposed in the first region 116 on the second surface 112. Corresponding pads are also provided on the second surface 112 for housing these second electronic components 115. For example... Figure 4 and Figure 8As shown, the third electronic component 124 is disposed in the second region 126 on the third surface 121. Corresponding pads are also provided on the third surface 121 to accommodate these third electronic components 124. Since both the first region 116 and the second region 126 correspond to the opening 131, the disposed second electronic component 115 and the third electronic component 124 can be located within the space of the opening 131, increasing the space utilization of the system module 100. The opening 131 also facilitates heat dissipation of the system module 100, improving its heat dissipation performance.

[0083] In some embodiments, the package types of the first electronic component 114, the second electronic component 115, the third electronic component 124, and the fourth electronic component 125 can be surface mount packages (SMT) such as LGA and BGA, or dual in-line packages (DIP), without limitation. In some embodiments, the materials of the first substrate 110 and the second substrate 120 can be High Tg FR4 circuit boards or substrate-like circuit boards, and the manufacturing process can be Any-layer PCB or HDIPCB, without limitation.

[0084] In some embodiments, a portion of the first electronic component 114 can be connected to the first pad 113 via internal PCB traces and vias, with some pins of the first electronic component 114 brought out to the first pad 113. A portion of the second electronic component 115 can be connected to the first pad 113 via internal PCB traces, with some pins of the second electronic component 115 brought out to the first pad 113. If a portion of the first electronic component 114 and a portion of the second electronic component 115 have the same electrical node, pins with the same electrical node can be connected together via internal traces and vias. In some embodiments, a portion of the fourth electronic component 125 can be connected to the second pad 123 via internal PCB traces and vias, with some pins of the fourth electronic component 125 brought out to the second pad 123. A portion of the third electronic component 124 can be connected to the second pad 123 via internal PCB traces, with some pins of the third electronic component 124 brought out to the second pad 123. If some third electronic components 124 and some fourth electronic components 125 have the same electrical nodes, the pins with the same electrical nodes can be connected together through internal traces and vias. For example, the bypass capacitor of the power management integrated circuit can be placed at the projection of the power management integrated circuit, and the pins of the bypass capacitor and the power management integrated circuit that have a connection relationship can be connected through vias to achieve the shortest path of the PDN.

[0085] In some embodiments, the first substrate 110 and the second substrate 120 are connected to the connector 132 of the carrier board 130 via the first pad 113 and the second pad 123, respectively. Since the first pad 113 leads out some of the pins of the first electronic component 114 and some of the second electronic component 115, and the second pad 123 leads out some of the pins of the third electronic component 124 and some of the fourth electronic component 125, the carrier board 130 can achieve electrical connection between the first substrate 110 and the second substrate 120 via the connector 132. As mentioned above, the connector can be a pad, conductive pin, laser via, buried via, or through-hole.

[0086] In some embodiments, the carrier board 130 is a multi-layer PCB, and peripheral electronic components are also provided on the carrier board 130. The peripheral electronic components include button circuits, signal transmission circuits, module expansion interfaces, and signal detection circuits. Electrical connections between the peripheral electronic components and the first substrate 110 and the second substrate 120 can be achieved through connectors 132 and traces and vias inside the carrier board 130.

[0087] Figure 9 This is a cross-sectional schematic diagram of a stacked system module 100 provided in another embodiment. In some embodiments, such as Figure 6 , Figure 8 and Figure 9 As shown, along the first direction x, the first projection of a portion of the first pad 113 and the second projection of a portion of the second pad 123 coincide. The first projection refers to the projection of the first pad 113 onto the carrier board 130, and the second projection refers to the projection of the second pad 123 onto the carrier board 130. That is, the size and setting area of ​​a portion of the first pad 113 are the same as the size and setting area of ​​a portion of the second pad 123. Through this setting method, partial pin compatibility of the first substrate 110 and the second substrate 120 can be achieved. For example, the projections of two rings of first pads 113 arranged around the first region 116 and two rings of second pads 123 arranged around the second region 126 coincide, and the pins of these two rings of first pads 113 and second pads 123 can achieve pin compatibility design.

[0088] In some embodiments, such as Figure 9The connector 132 extends along the first direction x, minimizing the conduction distance between a portion of the first pad 113 and a portion of the second pad 123. As mentioned earlier, in this embodiment, the connector 132 can be a via or lead penetrating the carrier board 130 along the first direction x; therefore, the connector 132 extends along the first direction x. The pins to be connected in the first pad 113 and the second pad 123 are arranged vertically opposite each other along the first direction x. One end of the connector 132 is connected to the first pad 113, and the other end of the connector 132 is soldered to the second pad 123, thus minimizing the conduction distance between the first pad 113 and the second pad 123. Assuming that a portion of the first pad 113 and a portion of the second pad 123 respectively lead out the power supply pins of the electronic components of the first substrate 110 and the second substrate 120, and that the power supply pins belong to the same electrical node in the circuit. The first pad 113 and the second pad 123 are arranged vertically opposite each other along the first direction x. The connector 132 connects the power supply pins of the first pad 113 and the second pad 123 to achieve the shortest path for power connection, which helps to reduce power supply noise and impedance. If the pins brought out from the first pad 113 and the second pad 123 are signal pins of electronic components on the substrate, this arrangement helps the system module 100 reduce signal delay and signal attenuation.

[0089] Figure 10 This is a schematic diagram of the second surface 112 of the first substrate 110 in a system module provided in an embodiment of this application. Figure 11 This is a schematic diagram of the third surface 121 of the second substrate 120 in a system module provided according to an embodiment of this application. In some embodiments, such as Figures 9-11As shown, the system module 100 includes a metal pillar 140 disposed at the opening 131. The first substrate 110 also includes a first metal pillar pad 141, and the second substrate 120 also includes a second metal pillar pad 142. The first metal pillar pad 141 and the second metal pillar pad 142 are disposed opposite to each other, and the metal pillar 140 is soldered between the first metal pillar pad 141 and the second metal pillar pad 142. In some embodiments, the height of the metal pillar 140 is slightly lower than the thickness of the carrier plate 130. If the metal pillar 140 is too high, it will affect the connection between the first substrate 110 and the carrier plate 130, causing a poor solder joint between the first substrate 110 and the carrier plate 130, resulting in connection failure; or it will affect the connection between the second substrate 120 and the carrier plate 130, causing a poor solder joint between the second substrate 120 and the carrier plate 130, resulting in connection failure. When the first substrate 110 and the second substrate 120 both warp, the metal pillar 140 can support the first substrate 110 and the second substrate 120, preventing electronic components from colliding and thus enhancing the mechanical structure of the system module 100. The metal pillar 140 can also be designed as ground (zero potential) or power to provide a low-impedance power path. When the metal pillar 140 is designed as ground, it can also disrupt the resonant cavity within the opening 131, reducing electromagnetic interference. In some embodiments, there can be multiple metal pillars 140.

[0090] Figure 12 This is a cross-sectional schematic diagram of a stacked system module 100 provided in another embodiment of this application. In some embodiments, such as Figure 12 As shown, the system module 100 also includes a first heat sink 151 and a second heat sink 152. Along the first direction x, the first heat sink 151 is disposed above the first substrate 110, and the second heat sink 152 is disposed below the second substrate 120. Electronic components such as processors, memory, and power management integrated circuits generate a large amount of heat. If the processor, memory, and power management integrated circuits are placed on the same plane, there is not enough space to avoid each other, resulting in poor heat dissipation performance. Moreover, heat-generating components are prone to mutual heating and interference due to heat conduction from the PCB surface. By placing the electronic components on the first substrate 110 and the second substrate 120, the heat-generating components can be effectively separated, avoiding mutual thermal interference. The carrier board also has an opening 131, because the opening 131 is a high thermal resistance conductor of air, further reducing heat transfer between the first substrate 110 and the second substrate 120. The first heat sink 151 and the second heat sink 152 are respectively disposed on the first surface 111 of the first substrate 110 and the fourth surface 122 of the second substrate 120, which can increase the heat dissipation performance of the system module 100. In some embodiments, applying thermal interface material 153 to the electronic components before setting the first heat sink 151 and the second heat sink 152 can further improve heat dissipation performance.

[0091] In the stacked system module 100 provided in this application, the first substrate 110, the carrier plate 130, and the second substrate 120 are stacked sequentially. The warpage of the first substrate 110 and the warpage of the second substrate 120 can be offset to a certain extent, reducing the warpage of the entire system module 100 and reducing the welding failure rate of the first substrate 110 and the second substrate 120 on the carrier plate 130. The carrier plate 130 is provided with an opening 131, which is beneficial for heat dissipation of the first substrate 110 and the second substrate 120 and improves the space utilization of the system module 100.

[0092] Figure 13 This is a flowchart illustrating a soldering method for a stacked system module 100 according to an embodiment of this application. This application also provides a soldering method for a stacked system module 100, used for soldering the stacked system module 100 as described above. Figure 13 As shown, the welding method includes the following steps:

[0093] S110, The second electronic component 115 is soldered to the second surface 112 of the first substrate 110;

[0094] S120, The first electronic component 114 is soldered to the first surface 111 of the first substrate 110;

[0095] S130, The third electronic component 124 is soldered to the third surface 121 of the second substrate 120;

[0096] S140, The fourth electronic component 125 is soldered to the fourth surface 122 of the second substrate 120;

[0097] S150, The second substrate 120 is soldered to the lower surface of the carrier plate 130, wherein the third surface 121 is in contact with the carrier plate 130.

[0098] S160, The first substrate 110 is soldered to the upper surface of the carrier plate 130, wherein the second surface 112 is in contact with the carrier plate 130.

[0099] In surface mount technology (SMT) processes, multiple heating steps are required to solder electronic components. Taking a double-sided PCB as an example, typically, electronic components on the first side are soldered first, and after the PCB cools, it is heated again to solder electronic components on the second side. The heating temperature for the first soldering is higher than that for the second soldering. That is, the electronic components soldered first undergo two heating cycles. If the electronic components on the first side are fragile, they are easily damaged after multiple heating cycles. In some embodiments of this application, the first electronic component 114 includes a processor, which is easily damaged after multiple heating cycles. Therefore, in some embodiments, the second electronic component 124 on the first substrate is soldered first, followed by the first electronic component 114 on the first substrate 110. Electronic components on the second substrate 120 can be soldered before, after, or simultaneously with the electronic components on the first substrate 110. During soldering on the second substrate 120, the fourth electronic component 125 is soldered first, followed by the third electronic component 124. In some embodiments, when welding the first substrate 110 and the second substrate 120 onto the carrier plate 130, the second substrate 120 is welded first and then the first substrate 110 is welded, so as to reduce the number of heating cycles of the first electronic component 114 and prevent damage to the first electronic component 114.

[0100] In some embodiments, while performing step S150, the metal pillar 140 is soldered onto the third surface 121; while performing step S160, the metal pillar 140 is soldered onto the second surface 112. The metal pillar 140 can serve as a third electronic component 124 on the second substrate 120. When the third electronic component 124 is soldered, it is soldered onto the third surface 121 together, which can reduce the soldering steps of the stacked system module 100 and improve production efficiency. In some embodiments, due to the mounting tolerance of the system module 100, the area of ​​the first metal pillar pad 141 of the first substrate 110 needs to be increased, and the spacing between the multiple first metal pillar pads 141 also needs to be appropriately increased to prevent poor contact during the soldering of the metal pillar 140.

[0101] This application uses specific terms to describe embodiments of the application. Terms such as "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that references to "an embodiment," "one embodiment," or "an alternative embodiment" in different locations throughout this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0102] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0103] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in this application are approximate values, which may be changed according to the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit preservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such numerical values ​​are set as precisely as feasible.

Claims

1. A stacked system module, characterized in that, It includes a first substrate, a carrier plate, and a second substrate stacked sequentially along a first direction, wherein, The first substrate includes a first surface and a second surface disposed opposite to each other, and the second surface is provided with a first pad; The second substrate includes a third surface and a fourth surface disposed opposite to each other, wherein the third surface faces the second surface and the third surface is provided with a second pad; The carrier board includes an opening and a connector, wherein, along the first direction, the projections of the first pad and the second pad are both located outside the projection of the opening, and the connector is used to electrically connect a portion of the first pad and a portion of the second pad through the connector.

2. The system module as described in claim 1, characterized in that, Along the first direction, the first projection of a portion of the first pad and the second projection of a portion of the second pad coincide.

3. The system module as described in claim 1, characterized in that, The connector extends along a first direction, such that the conductive distance between a portion of the first pad and a portion of the second pad is minimized.

4. The system module as described in claim 3, characterized in that, The first surface is provided with a first electronic component, which includes at least one of the following electronic components: a processor, a memory, and a clock oscillator.

5. The system module as described in claim 4, wherein the second surface is provided with a second electronic component, the third surface is provided with a third electronic component, and both the second electronic component and the third electronic component are located in the opening.

6. The system module as described in claim 5, characterized in that, The fourth surface is provided with a fourth electronic component, which includes at least one of the following electronic components: a power management circuit and a clock oscillator.

7. The system module as described in claim 6, characterized in that, It also includes a metal pillar disposed at the opening. The first substrate also includes a first metal pillar pad, and the second substrate also includes a second metal pillar pad. The first metal pillar pad and the second metal pillar pad are disposed opposite to each other, and the metal pillar is soldered between the first metal pillar pad and the second metal pillar pad.

8. The system module as described in claim 6, characterized in that, The system module further includes a first heat sink and a second heat sink. Along the first direction, the first heat sink is disposed above the first substrate, and the second heat sink is disposed below the second substrate.

9. A welding method for stacked system modules, characterized in that, For a system module as described in any one of claims 1-8, the welding method includes: The second electronic component is soldered onto the second surface of the first substrate; The first electronic component is soldered onto the first surface of the first substrate; The third electronic component is soldered onto the third surface of the second substrate; The fourth electronic component is soldered onto the fourth surface of the second substrate; The second substrate is welded to the lower surface of the carrier plate, wherein the third surface is in contact with the carrier plate; The first substrate is welded to the upper surface of the carrier plate, wherein the second surface is in contact with the carrier plate.

10. The welding method as described in claim 9, characterized in that, Also includes: While the second substrate is welded to the lower surface of the carrier plate, the metal pillar is welded to the third surface; While the first substrate is welded to the upper surface of the carrier plate, the metal pillar is welded to the second surface.

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