Flexible circuit substrate and flip chip package structure

Abstract

The present application provides a flexible circuit substrate, which includes a flexible substrate and a patterned circuit layer. The patterned circuit layer is disposed on the flexible substrate and includes a plurality of pins and two first mark patterns. A plurality of first inner pins of a plurality of inner pins of the pins extend into a chip disposing area of the flexible substrate and each corresponds to one of a plurality of first dummy bump disposing areas. The two first mark patterns are disposed in the chip disposing area and are perpendicular to a first long side of a dummy chip area. Two first extension lines of the two first mark patterns respectively pass through intersection points of two first inner pin center lines of two outermost first inner pins and two first bump center lines of two outermost first dummy bump disposing areas corresponding to the two outermost first inner pins. In addition, a film chip package structure including the flexible circuit substrate is also mentioned. The flexible circuit substrate and the film chip package structure of the present application can provide accurate distance reference.

Description

Technical Field

[0001] This invention relates to a circuit board and a packaging structure, and more particularly to a flexible circuit board and a thin-film flip-chip packaging structure including the flexible circuit board. Background Technology

[0002] Most thin-film flip-chip packages use thermocompression to electrically connect the chip bumps to the internal leads of the flexible circuit board. To determine whether the numerous and finely pitched internal leads on the flexible circuit board are indeed formed in the predetermined positions after the patterned metal layer process, and to determine whether the internal leads and bumps of the thin-film flip-chip package are accurately aligned and bonded after the thermocompression process, operators can measure the overall distance (i.e., the horizontal distance between the two outermost internal leads) of multiple internal leads arranged adjacent to each other along the long side of the chip placement area of ​​the flexible circuit board to confirm whether the internal leads have shifted or misaligned with the bumps.

[0003] However, when the extension direction of the two outermost inner pins of multiple inner pins arranged adjacent to each other along the long side of the chip setting area is oblique relative to this long side, it is difficult for the operator to grasp the measurement reference point of the two oblique inner pins, resulting in deviation of the measured distance and making it impossible to make an accurate judgment on whether the formation position of the inner pin and the engagement position with the bump are compliant. Summary of the Invention

[0004] This invention relates to a flexible circuit board and a thin-film flip-chip packaging structure that can provide accurate distance reference.

[0005] According to an embodiment of the present invention, a flexible circuit board includes a flexible substrate and a patterned circuit layer. The flexible substrate includes a chip placement area, wherein a virtual chip area is located within the chip placement area and has opposing first and second long sides. A plurality of virtual bump placement areas are located within the virtual chip area. The patterned circuit layer is disposed on the flexible substrate and includes a plurality of pins and two first marking patterns. Each of the plurality of pins has an inner pin extending into the chip placement area, each inner pin corresponding to one of the virtual bump placement areas. These inner pins include a plurality of first inner pins, which are arranged adjacently along the first long side, and at least the first inner pins adjacent to opposite ends of the first long side obliquely cross the first long side. The virtual bump placement areas include a plurality of first virtual bump placement areas, which are arranged adjacently along the first long side. Each of the first inner pins corresponds to one of the first virtual bump placement areas. Two first marking patterns are disposed within the chip placement area and perpendicular to the first long side. Two first extension lines extending from the two first marking patterns toward the first long side correspond to the two outermost first inner pins located at opposite ends of the first long side. The two outermost first inner pins have two equally spaced center lines, and the corresponding two outermost first virtual bump setting areas have two first bump center lines that equally bisect the two outermost first virtual bump setting areas in the direction perpendicular to the first long side. The two first extension lines pass through the intersection points of the two first inner pin center lines and the corresponding two first bump center lines.

[0006] In a flexible circuit board according to an embodiment of the present invention, the virtual chip region has a center line perpendicular to the first long side and the second long side, and the first internal pins are arranged in a mirror image on both sides of the center line.

[0007] In the flexible circuit board according to an embodiment of the present invention, each of the first inner pins has a first included angle of no more than 90 degrees with the first long side, and these first included angles of the first inner pins gradually decrease from the center line toward the direction away from the center line.

[0008] In a flexible circuit board according to an embodiment of the present invention, there is a gap between two first marking patterns and these first internal pins.

[0009] In the flexible circuit board according to an embodiment of the present invention, these inner pins further include a plurality of second inner pins arranged adjacently along the second long side, and at least the second inner pins adjacent to the opposite ends of the second long side obliquely cross the second long side. These virtual bump setting areas include a plurality of second virtual bump setting areas arranged adjacently along the second long side, and each of the second inner pins corresponds to one of the second virtual bump setting areas.

[0010] In the flexible circuit board according to an embodiment of the present invention, the patterned circuit layer further includes two second marking patterns. The two second marking patterns are disposed in the chip setting area and perpendicular to the second long side. Two second extension lines of the two second marking patterns extending toward the second long side correspond to the two outermost second inner pins located at opposite ends of the second long side. The two outermost second inner pins have two center lines of two second inner pins with equal widths. The corresponding two outermost second virtual bump setting areas have two second bump center lines that equally divide the two outermost first virtual bump setting areas in the direction perpendicular to the second long side. The two second extension lines pass through the intersection points of the two second inner pin center lines and the corresponding two second bump center lines.

[0011] In a flexible circuit board according to an embodiment of the present invention, there is a gap between the two second marking patterns and these second inner pins.

[0012] In a flexible circuit board according to an embodiment of the present invention, the virtual chip area has a center line perpendicular to the first long side and the second long side, and the second inner pins are arranged in a mirror image on both sides of the center line.

[0013] In the flexible circuit board according to an embodiment of the present invention, each of the second inner pins has a second included angle of no more than 90 degrees with the second long side, and these second included angles of the second inner pins gradually decrease from the center line toward the direction away from the center line.

[0014] According to an embodiment of the present invention, the thin-film flip-chip packaging structure includes the aforementioned flexible circuit substrate, chip, and encapsulating colloid. The chip is disposed on the flexible circuit substrate, located within a chip placement area and corresponding to a virtual chip area. The chip includes a plurality of bumps disposed in the virtual bump placement areas and electrically connected to the internal pins. The encapsulating colloid at least fills the space between the chip and the flexible circuit substrate.

[0015] Based on the above, the flexible circuit board of the thin-film flip-chip packaging structure of the present invention has two marking patterns perpendicular to the long side of the chip placement area within the chip placement area. The extension lines of these two marking patterns pass through the intersection points of the center lines of the two inner pins of the two outermost obliquely positioned inner pins located at opposite ends of this long side and the center lines of the two corresponding outermost bumps (or virtual bump placement areas). By directly measuring the horizontal distance between these two vertically positioned marking patterns, operators can not only confirm whether the inner pins of the flexible circuit board are deviated from their predetermined formation positions before the chip is bonded to the flexible circuit board, but also determine whether the inner pins and bumps are accurately aligned and connected after the chip is bonded to the flexible circuit board. Attached Figure Description

[0016] Figure 1This is a top view of a thin-film flip-chip packaging structure according to an embodiment of the present invention;

[0017] Figure 2 yes Figure 1 A magnified view of the chip placement area of ​​the flexible circuit board before chip placement in the thin-film flip-chip packaging structure.

[0018] Figure 3 yes Figure 2 A magnified view of a portion of the chip setup area;

[0019] Figure 4 yes Figure 1 A magnified view of the chip placement area of ​​the flexible circuit board after the chip is placed in the thin-film flip-chip packaging structure. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0021] Figure 1 This is a top view of a thin-film flip-chip packaging structure according to an embodiment of the present invention. It should be noted that... Figure 1 The thin-film flip-chip packaging structure 10 is shown in the form of a roll-to-roll conveyor operation, and only one thin-film flip-chip packaging structure 10 is schematically shown. The thin-film flip-chip packaging structure 10 includes a flexible circuit board 100, a chip 200, and an encapsulant 300. The chip 200 is disposed on the flexible circuit board 100. The encapsulant 300 at least fills the space between the chip 200 and the flexible circuit board 100. The flexible circuit board 100 includes a flexible substrate 110 and a patterned circuit layer 120. The flexible circuit board 100 also includes a solder resist layer 130. The solder resist layer 130 is disposed on the flexible substrate 110 and partially covers the patterned circuit layer 120 to prevent the patterned circuit layer 120 from being damaged or improperly bridged by external forces or foreign objects. Figure 1 The patterned circuit layer 120 is schematically represented by dots, and the solder resist layer 130, chip 200 and encapsulant 300 are shown in a perspective view.

[0022] Figure 2 yes Figure 1 A magnified view of the chip placement area of ​​the flexible circuit board before chip placement in the thin-film flip-chip packaging structure. Figure 3 yes Figure 2 A partial enlarged view of the chip placement area. The flexible substrate 110 of the flexible circuit board 100 includes a chip placement area 111, and the solder mask 130 has openings exposing the chip placement area 111. Please refer to... Figure 2 and Figure 3Before the chip 200 is disposed on the flexible circuit board 100, the virtual chip region 200' is located within the chip placement region 111 and has opposing first long sides LS1 and second long sides LS2. Multiple virtual bump placement regions S are located within the virtual chip region 200'. The virtual chip region 200' further has a center line CL1 perpendicular to the first long side LS1 and the second long side LS2. A patterned circuit layer 120 is disposed on the flexible substrate 110 and includes multiple pins 120a and two first marking patterns 120b. Each of these pins 120a has an inner pin 121 extending into the chip placement region 111. Each of these inner pins 121 corresponds to one of the virtual bump placement regions S. It should be noted that the chip 200 of the thin-film flip-chip package structure 10 is disposed within the chip placement region 111 of the flexible circuit board 100 by thermo-press bonding. Because the expansion and contraction of the flexible substrate 110 due to temperature changes is greater than that of the chip 200, when fabricating the flexible circuit board 100, the formation positions of these inner pins 121 must be pre-compensated with a compensation value (i.e., an offset relative to the predetermined bonding position) so that after the chip 200 is thermo-pressed and bonded, the contraction of the flexible substrate 110 causes these inner pins 121 to precisely align and bond to each bump 210 of the chip 200 (see reference). Figure 4 Therefore, Figure 2 and Figure 3 After the compensation value is added, the inner pin 121 may be misaligned with the corresponding virtual bump setting area S and not overlap or only partially overlap. In particular, the misalignment of the inner pin 121 is more obvious the further away from the center line CL1 (i.e. the larger the compensation value).

[0023] These internal pins 121 include a plurality of first internal pins 1211. These first internal pins 1211 are arranged adjacently along the first long side LS1, and at least the first internal pins 1211 adjacent to opposite ends of the first long side LS1 are diagonally across the first long side LS1. That is, some of these first internal pins 1211 are diagonally positioned. These virtual bump setting areas S include a plurality of first virtual bump setting areas S1, which are arranged adjacently along the first long side LS1. Each of these first internal pins 1211 corresponds to one of these first virtual bump setting areas S1. Two first marking patterns 120b are disposed within the chip setting area 111 and perpendicular to the first long side LS1. Specifically, two first extension lines L1 extending from the two first marking patterns 120b toward the first long side LS1 are perpendicular to the first long side LS1. That is, the two first marking patterns 120b are vertically positioned. The two first extension lines L1 respectively correspond to the two outermost first internal pins 1211e located at opposite ends of the first long side LS1. The two outermost first inner pins 1211e have two first inner pin center lines CL2 that equally divide the width W1 of the two outermost first inner pins 1211e. Corresponding to the two outermost first inner pins 1211e, the two outermost first virtual bump setting areas S1e have two first bump center lines CL3 that equally divide the two outermost first virtual bump setting areas S1e in the direction perpendicular to the first long side LS1. The two first extension lines L1 pass through the intersection points C1 and C2 of the two first inner pin center lines CL2 and the corresponding two first bump center lines CL3, respectively.

[0024] A gap G1 exists between the two first marking patterns 120b and the first inner pins 1211, 1211e. Specifically, the two first marking patterns 120b are disposed in a non-primary wiring area within the chip placement area 111, relatively far from the first long side LS1, to avoid affecting the wiring of the first inner pins 1211, 1211e. The width W2 of the first marking pattern 120b in the direction perpendicular to the first extension line L1 may be smaller than the width W1 of the corresponding outermost first inner pin 1211e, but is not limited thereto. In an embodiment not shown, the width W2 of the first marking pattern 120b may be equal to the width W1 of the corresponding outermost first inner pin 1211e.

[0025] Please refer to Figure 2 and Figure 3In this embodiment, the first inner pins 1211 are arranged in a mirror image on both sides of the center line CL1, and each has a first included angle A1 of no more than 90 degrees with the first long side LS1. These first included angles A1 of the first inner pins 1211 gradually decrease from the center line CL1 away from it. In this embodiment, the first inner pin 1211 located at or closest to the center line CL1 crosses the first long side LS1 perpendicularly, and the closer to the opposite ends of the first long side LS1, the more inclined the first inner pin 1211 becomes relative to the first long side LS1. That is, the first included angle A1 of the first inner pin 1211 located at or closest to the center line CL1 is 90 degrees, and these first included angles A1 decrease from the center line CL1 towards the opposite ends of the first long side LS1. In this embodiment, the extension direction of the first virtual bump setting area S1 follows the extension direction of the corresponding first inner pin 1211. That is, the first virtual bump setting area S1 located at or closest to the center line CL1 is perpendicular to the first long side LS1, and the first virtual bump setting area S1 becomes more inclined relative to the first long side LS1 in the direction from the center line CL1 to the opposite ends of the first long side LS1, but the present invention is not limited thereto.

[0026] In this embodiment, the first extension lines L1 of the two first marking patterns 120b are respectively aligned with the intersection points C1 and C2 of the center lines CL2 of the first inner pins 1211e of the two outermost first inner pins and the corresponding center lines CL3 of the first bumps. By judging whether the horizontal distance between the two vertically arranged first marking patterns 120b conforms to the preset distance range, the operator can conveniently and accurately confirm whether the first inner pins 1211 of the flexible circuit board 100 have shifted and deviated from the predetermined formation position during the manufacturing process, which is beneficial to subsequent processes.

[0027] Please continue to refer to this. Figure 2 and Figure 3 In this embodiment, the flexible circuit board 100 includes multiple second inner pins 1212 as well as multiple second virtual bump setting areas S2. These second inner pins 1212 are arranged adjacently along the second long side LS2, and at least the second inner pins 1212 adjacent to opposite ends of the second long side LS2 obliquely cross the second long side LS2. That is, some of these second inner pins 1212 are obliquely arranged. These second virtual bump setting areas S2 are arranged adjacently along the second long side LS2. Each of these second inner pins 1212 corresponds to one of these second virtual bump setting areas S2.

[0028] The patterned circuit layer 120 also includes two second marking patterns 120c. The two second marking patterns 120c are disposed within the chip setting area 111 and perpendicular to the second long side LS2. Specifically, two second extension lines L2 extending from the two second marking patterns 120c toward the second long side LS2 are perpendicular to the second long side LS2. That is, the two second marking patterns 120c are vertically positioned. The two second extension lines L2 correspond to the two outermost second inner pins 1212e located at opposite ends of the second long side LS2. These two outermost second inner pins 1212e have two second inner pin center lines CL4 that equally bisect the width W3 of these two second inner pins 1212e. Corresponding to these two outermost second inner pins 1212e, the two outermost second virtual bump setting areas S2e have two second bump center lines CL5 that equally bisect the two outermost second virtual bump setting areas S2e in the direction perpendicular to the second long side LS2. The two second extension lines L2 pass through the intersection points C3 and C4 of the center lines CL4 of the two second inner pins and the center lines CL5 of the corresponding two second bumps, respectively.

[0029] A gap G2 exists between the two second marking patterns 120c and the second inner pins 1212, 1212e. Specifically, the two second marking patterns 120c are disposed in a non-primary wiring area within the chip placement area 111, relatively far from the second long side LS2, to avoid affecting the wiring of the second inner pins 1212, 1212e. The width W4 of the second marking pattern 120c in the direction perpendicular to the second extension line L2 may be smaller than the width W3 of the corresponding outermost second inner pin 1212e, but is not limited thereto. In an embodiment not shown, the width W4 of the second marking pattern 120c may be equal to the width W3 of the corresponding outermost second inner pin 1212e.

[0030] In this embodiment, the second inner pins 1212 are arranged in a mirror image on both sides of the center line CL1, and each has a second included angle A2 of no more than 90 degrees with the second long side LS2. These second included angles A2 of the second inner pins 1212 gradually decrease from the center line CL1 away from it. In this embodiment, the second inner pin 1212 located at or closest to the center line CL1 crosses the second long side LS2 perpendicularly, and the second inner pin 1212 becomes increasingly inclined relative to the second long side LS2 towards the opposite ends of the second long side LS2. That is, the second included angle A2 of the second inner pin 1212 located at or closest to the center line CL1 is 90 degrees, while these second included angles A2 decrease in the direction from the center line CL1 towards the opposite ends of the second long side LS2. In this embodiment, the extension direction of the second virtual bump setting area S2 follows the extension direction of the corresponding second inner pin 1212. That is, the second virtual bump setting area S2 located at or closest to the center line CL1 is perpendicular to the second long side LS2, and the second virtual bump setting area S2 becomes more inclined relative to the second long side LS2 in the direction from the center line CL1 to the opposite ends of the second long side LS2, but the present invention is not limited thereto.

[0031] In this embodiment, the second extension lines L2 of the two second marking patterns 120c are respectively aligned with the intersection points C3 and C4 of the center lines CL4 of the second inner pins 1212e of the two outermost second inner pins and the corresponding center lines CL5 of the second bumps. By judging whether the horizontal distance between the two vertically arranged second marking patterns 120c conforms to the preset distance range, the operator can conveniently and accurately confirm whether the second inner pins 1212 of the flexible circuit board 100 have shifted from the predetermined formation position during the manufacturing process, which is beneficial to subsequent processes.

[0032] Figure 4 yes Figure 1 The image shows a partial enlarged view of the chip placement area on the flexible circuit board after the chip has been placed in the thin-film flip-chip packaging structure. Please also refer to... Figure 2 and Figure 4 When chip 200 is disposed on flexible circuit board 100, chip 200 is located within chip placement area 111 and corresponds to virtual chip area 200'. Chip 200 includes a plurality of bumps 210, which are disposed in these virtual bump placement areas S and electrically connected to these internal pins 121. The shape of these bumps 210 corresponds to these virtual bump placement areas S. Figure 4As shown, after the thermoforming bonding of the chip 200 and the flexible circuit board 100, each bump 210 of the chip 200 is precisely aligned and bonded to these inner pins 121. The first extension lines L1 of the two first marking patterns 120b pass through the intersection points C1 and C2 of the first inner pin center lines CL2 of the two outermost first inner pins 1211e and the first bump center lines CL3 of the bumps 210 disposed in the two outermost first virtual bump setting areas S1e. The second extension lines L2 of the two second marking patterns 120c pass through the intersection points C3 and C4 of the second inner pin center lines CL4 of the two outermost second inner pins 1212e and the second bump center lines CL5 of the bumps 210 disposed in the two outermost second virtual bump setting areas S2e. Therefore, after setting up the chip 200, the operator can measure the horizontal distance between the two first marking patterns 120b and the two second marking patterns 120c in the vertical direction to confirm whether the first inner pin 1211 and the second inner pin 1212 are offset when engaging the bump 210. This ensures that the inner pin 121 and the bump 210 are accurately connected, avoids electrical abnormalities or failures in the thin-film flip-chip package structure 10, and thus improves the reliability of the thin-film flip-chip package structure 10.

[0033] In summary, the flexible circuit board of the thin-film flip-chip packaging structure of the present invention has two marking patterns perpendicular to the long side of the chip placement area within the chip placement area. The extension lines of these two marking patterns pass through the intersection points of the center lines of the two inner pins of the two outermost obliquely positioned inner pins located at opposite ends of this long side and the center lines of the two corresponding outermost bumps (or virtual bump placement areas). By directly measuring the horizontal distance between these two vertically positioned marking patterns, operators can not only confirm whether the inner pins of the flexible circuit board are deviated from their predetermined positions before the chip is bonded to the flexible circuit board, but also determine whether the inner pins and bumps are accurately aligned and connected after the chip is bonded to the flexible circuit board.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flexible circuit board, characterized in that, include: A flexible substrate includes a chip mounting area, wherein a virtual chip area is located within the chip mounting area and has opposing first and second long sides, and a plurality of virtual bump mounting areas are located within the virtual chip area; as well as A patterned circuit layer, disposed on the flexible substrate, includes: A plurality of pins, each having an inner pin extending into the chip mounting area, each inner pin corresponding to one of the plurality of virtual bump mounting areas, wherein the plurality of inner pins includes a plurality of first inner pins, the plurality of first inner pins being arranged adjacently along the first long side, and at least the plurality of first inner pins adjacent to opposite ends of the first long side obliquely crossing the first long side; the plurality of virtual bump mounting areas includes a plurality of first virtual bump mounting areas, the plurality of first virtual bump mounting areas being arranged adjacently along the first long side, each of the plurality of first inner pins corresponding to one of the plurality of first virtual bump mounting areas; as well as Two first marking patterns are disposed within the chip setting area and perpendicular to the first long side. Two first extension lines of the two first marking patterns extending toward the first long side correspond to the two outermost plurality of first inner pins located at opposite ends of the first long side. The two outermost plurality of first inner pins have two center lines of equal width. The two outermost plurality of first virtual bump setting areas have two center lines of first bumps that equally divide the two outermost plurality of first virtual bump setting areas in the direction perpendicular to the first long side. The two first extension lines pass through the intersection points of the two center lines of the first inner pins and the corresponding two center lines of the first bumps.

2. The flexible circuit board according to claim 1, characterized in that, The virtual chip area has a center line perpendicular to the first long side and the second long side, and the plurality of first internal pins are arranged in a mirror image on both sides of the center line.

3. The flexible circuit board according to claim 2, characterized in that, Each of the plurality of first inner pins has a first included angle of no more than 90 degrees with the first long side, and the plurality of first included angles of the plurality of first inner pins gradually decrease from the center line in a direction away from the center line.

4. The flexible circuit board according to claim 1, characterized in that, There is a gap between the two first marking patterns and the plurality of first inner pins.

5. The flexible circuit board according to claim 1, characterized in that, The plurality of internal pins further includes a plurality of second internal pins, the plurality of second internal pins being arranged adjacently along the second long side, and the plurality of second internal pins at least adjacent to the opposite ends of the second long side diagonally crossing the second long side. The plurality of virtual bump setting areas include a plurality of second virtual bump setting areas, the plurality of second virtual bump setting areas being arranged adjacently along the second long side, and each of the plurality of second internal pins corresponding to one of the plurality of second virtual bump setting areas.

6. The flexible circuit board according to claim 5, characterized in that, The patterned circuit layer further includes two second marking patterns, which are disposed within the chip setting area and perpendicular to the second long side. Two second extension lines extending from the two second marking patterns toward the second long side correspond to the two outermost plurality of second inner pins located at opposite ends of the second long side. The two outermost plurality of second inner pins have two center lines of equal width. The corresponding two outermost plurality of second virtual bump setting areas have two center lines of second bumps that equally divide the two outermost plurality of first virtual bump setting areas in the direction perpendicular to the second long side. The two second extension lines pass through the intersection points of the two center lines of the second inner pins and the corresponding two center lines of the second bumps.

7. The flexible circuit board according to claim 6, characterized in that, There is a gap between the two second marking patterns and the plurality of second inner pins.

8. The flexible circuit board according to claim 5, characterized in that, The virtual chip area has a center line perpendicular to the first long side and the second long side, and the plurality of second inner pins are arranged in a mirror image on both sides of the center line.

9. The flexible circuit board according to claim 8, characterized in that, Each of the plurality of second inner pins has a second included angle of no more than 90 degrees with the second long side, and the plurality of second included angles of the plurality of second inner pins gradually decrease from the center line in a direction away from the center line.

10. A thin-film flip-chip packaging structure, characterized in that, include: Flexible circuit board as described in any one of claims 1 to 9; A chip is disposed on the flexible circuit board. The chip is located in the chip setting area and corresponds to the virtual chip area. The chip includes a plurality of bumps. The plurality of bumps are disposed in the plurality of virtual bump setting areas and are electrically connected to the plurality of internal pins. as well as An encapsulating colloid is used to fill at least the space between the chip and the flexible circuit substrate.

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