A read retry method for a flash memory chip and a data storage device

Abstract

This application belongs to the field of read retry optimization, specifically disclosing a read retry method and data storage device for flash memory chips. Based on the existing read retry table, this application introduces a flash memory chip temperature table and a data block health information table. When a read command fails, the interaction of these three tables determines the number of erase / write cycles of the block containing the chip page, the chip page write temperature, the current read temperature, the normalized hold time, and the read interference count. Then, a pre-trained read retry table prediction model is used to obtain a predicted read retry table entry, which is then accessed to perform the read retry operation. This application uses environmental information to quickly locate the read retry table entry, avoiding numerous unnecessary read retry operations, significantly reducing average read latency and worst-case tail latency, and improving the read retry efficiency of the data storage device. Furthermore, during training, the read retry table prediction model uses a training sample set covering various write and read temperatures, fully considering the large difference between write and read temperatures to avoid read retry errors.

Description

Technical Field

[0001] This application belongs to the field of read retry optimization of flash memory chips, and more specifically, relates to a read retry method and data storage device for flash memory chips. Background Technology

[0002] Flash memory, especially NAND flash memory, has been widely used in industrial control, automotive electronics, communication equipment, edge computing terminals, and various embedded systems due to its advantages such as non-volatility, high storage density, low power consumption, and relatively low cost. Each storage cell in flash memory represents different data states (such as "0 / 1" in SLC, and multiple levels in TLC / QLC) by capturing or releasing charge. The precise amount of charge determines the read threshold voltage. Factors such as charge leakage (natural aging), read disturbance, program disturbance, wear-out, and cell-to-cell interference can cause the charge amount to deviate from the expected value, leading to read errors.

[0003] Read retry mechanisms are a common method to mitigate read errors. When the raw bit error rate of a read operation exceeds the error correction module's capability, the firmware iterates through a predefined threshold voltage table. For each entry accessed, the read reference voltage of the flash memory is adjusted using the threshold voltage specified in that entry, and then the read command is reissued. If the error correction module successfully decodes the data, the read operation is complete; otherwise, the next entry is accessed.

[0004] However, conventional read retry techniques involve traversing invalid entries multiple times before a successful retry, increasing read operation latency. The entries determined through this traversal method may not be optimal, offering limited mitigation of read errors. Furthermore, in outdoor monitoring equipment in extremely cold or hot regions, the temperature difference between when writing data to industrial-grade solid-state drives and when transferring data from storage to the computer is significant. This large temperature difference between writing and reading increases the likelihood of read operations failing, making it more difficult to obtain the optimal read retry entries. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a read retry method and data storage device for flash memory chips, aiming to solve the problems of increased latency in determining entries through traversal in existing read retry methods and susceptibility to errors when faced with large temperature differences between writing and reading.

[0006] To achieve the above objectives, in a first aspect, this application provides a read retry method for flash memory chips. First, a retry table entry is predicted using the following method, then the predicted retry table entry is accessed to perform a retry operation: S1. Using the chip number corresponding to the read command as an index, the flash memory chip temperature table is searched to determine the current read temperature; using the chip block number corresponding to the read command as an index, the data block health information table is searched to determine the number of erase / write operations, the first page write temperature, the middle page write temperature, the last page write temperature, the normalized hold time, and the read interference count; S2. Combining the first page write temperature, the middle page write temperature, and the last page write temperature, the write temperature of the chip page corresponding to the read command is calculated, and the "number of erase / write operations of the block containing the chip page, chip page write temperature, current read temperature, normalized hold time, and read interference count" are used to determine the retry operation. The "count" is input into the pre-trained reread table prediction model, and the output is the reread table sequence number; S3. Using the reread table sequence number as the index, the reread table is searched to determine the predicted reread table entries; The column attributes of the reread table include the sequence number and the reread table entries, the column attributes of the flash memory chip temperature table include the chip number and the current read temperature, the number of rows is determined by the number of flash memory chips, and the data in the table is updated by overwriting; The column attributes of the data block health information table include the chip block number, the number of erase / write cycles, the first page write temperature, the middle page write temperature, the last page write temperature, the normalized hold time, and the read interference count, the number of rows is determined by the number of chip blocks, the data in the table is updated by overwriting, and the data is saved when power is off; The reread table, the flash memory chip temperature table, the data block health information table, and the pre-trained reread table prediction model are stored in the flash memory controller.

[0007] Preferably, the data in the reread table remains unchanged after leaving the factory; before leaving the factory, the current read temperature corresponding to each chip number in the flash memory chip temperature table is initialized to empty, and after leaving the factory, it is updated by overwriting after each power-on. The update rule is: all flash memory chips are read periodically, and the current read temperature corresponding to the chip number is updated after each read of the flash memory chip is completed; before leaving the factory, the "first page write temperature, middle page write temperature, and last page write temperature" corresponding to each chip block number are all initialized to empty, and the "erasing and writing count, normalized hold time, and read interference count" are all initialized to zero. After leaving the factory, it is updated by overwriting. The update rule is: ① each time an erasing and writing cycle of the memory chip block is completed, the current read temperature corresponding to the chip number is updated. ① Increment the "erased / written count" corresponding to the chip block number by 1, and set other attributes to zero; ② After each write operation to the flash memory chip block, update the "first page write temperature, middle page write temperature, and last page write temperature" corresponding to the chip block number, and keep other attributes unchanged; ③ After each read operation to the flash memory chip block, increment the "read interference count" corresponding to the chip block number by 1, and keep other attributes unchanged; ④ Whenever the flash memory chip temperature table is updated, calculate the normalized hold time based on the update time interval of the flash memory chip temperature table and the current read temperature corresponding to the updated chip number, and update the normalized hold time corresponding to all flash memory blocks corresponding to the updated chip number, while keeping other attributes unchanged.

[0008] Preferably, the formula for calculating the normalized retention time is as follows: ,in, It is the normalized retention time. It is the update time interval of the flash memory chip temperature gauge, and exp is the natural exponential function; It is the activation energy of the flash memory chip reaction; It is the Boltzmann constant; It is the preset target temperature; It is the current read temperature corresponding to the chip number that has been updated in the flash memory chip temperature table.

[0009] It should be noted that this application utilizes the normalized data hold time of real-time temperature calibration to improve the output accuracy of the reread table prediction model.

[0010] Preferably, the reread table prediction model is trained in the following way: Several blocks of flash memory chips of the same model are taken and divided into... Group; for the first Group flash chip block group execution The erase / write operation, among which... This represents the maximum number of erase / write cycles for a flash memory block. For each flash memory chip block in the same group, tests were conducted with different write temperatures, different data retention times, different read interference counts, and different read temperatures. During each test, all pages were read by traversing the reread table. After the test, the following data was saved: <number of erase / write cycles for the chip page block, chip page write temperature, read temperature, data retention time, number of read interference counts, and reread table index>. A training sample set was constructed using the combination of the number of erase / write cycles for the chip page block, chip page write temperature, read temperature, data retention time, and number of read interference counts as input data, and the reread table index as a label. The reread table prediction model was trained using the training sample set to obtain a pre-trained reread table prediction model.

[0011] Preferably, if the chip block is not completely written, the chip page write temperature is: If the chip block is completely written, then the chip page write temperature is fitted using a Bezier curve: ,in, This is an estimate of the data write temperature for the page number that currently needs to be reread. , , These are the page number and write temperature of the first page, the page number and write temperature of the middle page, and the page number and write temperature of the last page. This indicates the page number that needs to be reread. As an intermediate variable, , , , , .

[0012] It should be noted that this application solves the problem of excessive storage space consumption when using temperature difference as the input for reread table prediction by using the idea of ​​quadratic Bézier curve fitting.

[0013] Preferably, if the read command fails to execute a reread operation according to the predicted reread entry, a reread operation is performed near the predicted reread entry until the read is successful.

[0014] It should be noted that, considering insufficient training, inadequate model performance, or the absence of a read retry entry in Table 3 that can handle the current environmental conditions, relying on prediction results may lead to read retry failures. Repeatedly predicting to obtain the index for the next read retry could result in endless read retry failures. This application adds the aforementioned processing mechanism, allowing successful read retry processes to skip invalid read retry operations and ensuring that read retry processes that will ultimately fail end as early as possible, allowing the system to promptly employ other effective mechanisms for handling.

[0015] To achieve the above objectives, in a second aspect, this application provides a data storage device, comprising: at least one flash memory chip, each flash memory chip having multiple blocks for storing data, each block including multiple pages; at least one flash memory controller for receiving a master control read instruction from a host, converting the master control read instruction into a read operation instruction for the flash memory chip to perform a preset read operation to read one page of data, wherein the preset read operation has a preset read threshold voltage setting, and when the preset read operation fails, the flash memory controller executes the steps of the read retry method as described in the first aspect.

[0016] To achieve the above objectives, in a third aspect, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the read retry method as described in the first aspect.

[0017] To achieve the above objectives, in a fourth aspect, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the read retry method as described in the first aspect.

[0018] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0019] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: This application proposes a read retry method for flash memory chips. Based on the existing retry table, it introduces a flash memory chip temperature table and a data block health information table. When a read command fails, the three tables are linked to determine the current number of erase / write cycles of the block containing the chip page, the chip page write temperature, the current read temperature, the normalized hold time, and the read interference count. Then, a pre-trained retry table prediction model is used to obtain a predicted retry table entry, which is then accessed to perform the retry operation. This application utilizes environmental information to quickly locate the retry table entry, avoiding numerous unnecessary retry operations, significantly reducing average read latency and worst-case tail latency, and improving the read retry efficiency of the data storage device. Furthermore, during training, the retry table prediction model uses a training sample set covering various write and read temperatures, fully considering the large difference between write and read temperatures, which helps avoid read retry errors. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the solid-state drive hardware structure provided in the embodiments of this application.

[0021] Figure 2 This is a flowchart of a read retry method for a flash memory chip provided in an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] In this application, the term "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. In this application, the symbol " / " indicates that the related objects are in an "or" relationship, for example, A / B means A or B.

[0024] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0025] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0026] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0027] The embodiments of this application are described below with reference to the accompanying drawings.

[0028] At the core of an SSD (Solid State Drive) is an embedded controller, within which firmware manages data storage, access control, performance optimization, and lifespan assurance. The firmware coordinates modules such as the host interface, data cache, mapping table, flash transaction scheduling, flash block management, garbage collection, wear leveling, and multiple flash memory chips to jointly achieve efficient and reliable data read and write operations. Specifically, as follows... Figure 1 As shown.

[0029] Host Interface: The firmware receives read and write commands from the computer through the host interface (such as SATA, NVMe). The interface is responsible for protocol parsing and passing the host's Logical Address (LBA) request to the firmware for internal processing.

[0030] Data caching: Write data from the host is first temporarily stored in a data cache (usually DRAM). The cache can aggregate small writes, reduce direct operations on flash memory, and speed up read responses. The firmware determines when to actually write the cached data to flash memory.

[0031] Mapping Table: The firmware maintains a mapping table that maps logical addresses to physical addresses. Because flash memory cannot be overwritten, the firmware needs to dynamically map the host's logical block addresses to different physical pages on the flash memory chip. During a write operation, the firmware allocates a new page and updates the mapping table; during a read operation, it finds the latest data location based on the mapping table.

[0032] Flash Transaction Scheduling: This module is responsible for distributing read, write, and erase operations across multiple flash memory chips. It leverages multi-chip parallelism (interleaving and crossover) to improve bandwidth and optimizes the execution order based on priority and command queues to reduce latency.

[0033] Flash memory block management: Flash memory chips consist of blocks and pages. The firmware's flash memory block management module tracks the status of each block (free, written, awaiting reclamation, bad block, etc.), allocates new blocks for writing, and records the number of erases for each block.

[0034] Garbage Collection (GC): When valid data in flash memory is scattered across multiple blocks and the number of free blocks decreases, the firmware initiates garbage collection. It selects the block containing the most invalid data, copies the still valid pages from it to a new block, and then erases the original block. This process frees up available space but introduces write amplification.

[0035] Wear leveling: Flash memory blocks have a limited erase lifespan (typically a few thousand erase cycles). Wear leveling modules ensure that all blocks have approximately the same number of erase cycles, preventing some blocks from failing prematurely. Firmware prioritizes blocks with fewer erase cycles and selectively migrates blocks with higher erase cycles during garbage collection.

[0036] Flash memory chips: Multiple flash memory chips constitute the storage medium. The firmware sends read, write, and erase commands to the chips through the flash memory interface and handles low-level operations such as status checks and error correction (ECC).

[0037] like Figure 2 As shown, this application provides a read retry method for a flash memory chip, which is deployed in the "flash transaction scheduling" module of the firmware. Specifically, the retry table entry is predicted first, and then the predicted retry table entry is accessed to perform the retry operation.

[0038] S1. Using the chip number corresponding to the read command as an index, search the flash memory chip temperature table to determine the current read temperature. Using the chip block number corresponding to the read command as an index, search the data block health information table to determine the number of erase / write cycles, the first page write temperature, the middle page write temperature, the last page write temperature, the normalized hold time, and the read interference count.

[0039] S2. Combine the write temperatures of the first page, the middle page, and the last page to calculate the write temperature of the chip page corresponding to the read command. Input the "number of erase / write cycles of the chip page block, chip page write temperature, current read temperature, normalized hold time, and read interference count" into the pre-trained reread table prediction model and output the reread table sequence number.

[0040] S3. Using the reread table number as an index, search the reread table to determine the predicted reread table entries.

[0041] The reread table (corresponding to Table 1) includes column attributes such as serial number and reread entry. The content of each reread entry is the threshold voltage adjustment value used during a flash memory reread operation; this value is preset before firmware execution. Each reread entry typically corresponds to a voltage adjustment strategy. For SLC (Single-Level Cell), it contains only one voltage value; for MLC (Multi-Level Cell), it contains three reference voltage values; for TLC (Triple-Level Cell), it contains seven reference voltage values; and for QLC (Quadruple-Level Cell), it contains 15 reference voltage values. The data in the reread table remains unchanged after factory shipment.

[0042] The column attributes of the flash memory chip temperature table (corresponding to Table 2) include chip number and current read temperature. The number of rows is determined by the number of flash memory chips. The data in the table is updated using an overwrite method.

[0043] Preferably, before the flash memory chip temperature meter leaves the factory, the current reading temperature corresponding to each chip number is initialized to empty. After leaving the factory, it is updated in an overwrite manner after each power-on. The update rule is: all flash memory chips are read periodically, and the current reading temperature corresponding to the chip number is updated after each reading of the flash memory chip is completed.

[0044] The column attributes of the data block health information table (corresponding to Table 3) include chip block number, number of erase / write cycles, first page write temperature, middle page write temperature, last page write temperature, normalized hold time, and read interference count. The number of rows is determined by the number of chip blocks. The data in the table is updated by overwriting and is saved after power failure. The reread table, flash chip temperature table, data block health information table, and pre-trained reread table prediction model are stored in the flash controller.

[0045] It should be noted that if the data in Table 3 is not saved after power failure, when writing data (for example, writing one block A), after a power failure, if block A is reread and you want to perform prediction to speed up the reread, you will not be able to find the information of block A in Table 3.

[0046] Preferably, before the data block health information table leaves the factory, the "first page write temperature, middle page write temperature, and last page write temperature" corresponding to each chip block number are all initialized to empty, and the "erased / written count, normalized hold time, and read interference count" are all initialized to zero. After leaving the factory, it is updated in an overwrite manner, and the update rules are as follows: ① Whenever an erase / write cycle is completed for a memory chip block, the "erased / written count" corresponding to the chip block number is incremented by 1, and other attributes are set to zero; ② Whenever a write operation is completed for a flash memory chip block, the "first page write temperature, middle page write temperature, and last page write temperature" corresponding to the chip block number are updated, and other attributes remain unchanged; ③ Whenever a read operation is completed for a flash memory chip block, the "read interference count" corresponding to the chip block number is incremented by 1, and other attributes remain unchanged; ④ Whenever the flash memory chip temperature table is updated, the normalized hold time is calculated based on the update time interval of the flash memory chip temperature table and the current read temperature corresponding to the updated chip number, and the normalized hold time corresponding to all flash memory blocks corresponding to the updated chip number is updated at the same time, and other attributes remain unchanged.

[0047] Preferably, the formula for calculating the normalized retention time is as follows:

[0048] in, It is the normalized retention time. It is the update time interval of the flash memory chip temperature gauge, and exp is the natural exponential function; It is the activation energy of the flash memory chip reaction; It is the Boltzmann constant; It is the preset target temperature; It is the current read temperature corresponding to the chip number that has been updated in the flash memory chip temperature table.

[0049] It's important to note that "normalized retention time" refers to the time elapsed since the block was allocated a write time, given the current number of erase / write cycles for the written data. This is because data stored in flash memory may become unreadable after a certain period. The healthier the block, the longer it can be retained. Recording the retention time helps the management program remove data before it becomes corrupted and unreadable.

[0050] Preferably, the reread table prediction model is trained in the following way: Several blocks of flash memory chips of the same model are taken and divided into... Group; for the first Group flash chip block group execution The erase / write operation, among which... This represents the maximum number of erase / write cycles for a flash memory block. For each flash memory chip block in the same group, tests were conducted with different write temperatures, data retention times, read interference counts, and read temperatures. During each test, all pages were read by traversing the reread table. After the test, the following data was saved: <number of erase / write cycles for the chip page block, chip page write temperature, read temperature, data retention time, number of read interference counts, and reread table number>. A training sample set was constructed using the combination of these data as input data and the reread table number as the label. The reread table prediction model was then trained using this training sample set to obtain a pre-trained reread table prediction model. The optimal reread table number is the entry in the reread table that, under the input conditions of the prediction model, is most likely to result in a successful read retry operation.

[0051] Preferably, if the chip block is not completely written, the chip page write temperature is: If the chip block is completely written, then the chip page write temperature is fitted using a Bezier curve: ,in, This is an estimate of the data write temperature for the page number that currently needs to be reread. , , These are the page number and write temperature of the first page, the page number and write temperature of the middle page, and the page number and write temperature of the last page. This indicates the page number that needs to be reread. As an intermediate variable, , , , , .

[0052] Preferably, if the read command fails to execute a reread operation according to the predicted reread entry, a reread operation is performed near the predicted reread entry until the read is successful.

[0053] It is understood that the detailed functional implementation of each of the above units / modules can be found in the description in the aforementioned method embodiments, and will not be repeated here.

[0054] It should be understood that the above-described device is used to execute the methods in the above embodiments. The implementation principle and technical effect of the corresponding program modules in the device are similar to those described in the above methods. The working process of the device can be referred to the corresponding process in the above methods, and will not be repeated here.

[0055] Based on the methods in the above embodiments, this application provides an electronic device that may include a processor, a communications interface, a memory, and a communication bus, wherein the processor, communications interface, and memory communicate with each other via the communication bus. The processor may invoke logical instructions stored in the memory to execute the methods in the above embodiments.

[0056] Furthermore, the logical instructions in the aforementioned memory can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0057] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0058] Based on the methods in the above embodiments, this application provides a computer program product that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0059] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0060] The method steps in this application embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0061] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0062] It is understood that the various numerical designations used in the embodiments of this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application.

[0063] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A read retry method for a flash memory chip, characterized in that, First, predict the reread entries using the following method, then access the predicted reread entries and perform the reread operation: S1. Using the chip number corresponding to the read command as an index, search the flash memory chip temperature table to determine the current read temperature. Using the chip block number corresponding to the read command as an index, search the data block health information table to determine the number of erase / write cycles, the first page write temperature, the middle page write temperature, the last page write temperature, the normalized hold time, and the read interference count. S2. Combine the write temperature of the first page, the write temperature of the middle page, and the write temperature of the last page to calculate the write temperature of the chip page corresponding to the read command. Input the "number of erases and writes to the block where the chip page is located, the write temperature of the chip page, the current read temperature, the normalized hold time, and the read interference count" into the pre-trained reread table prediction model and output the reread table sequence number. S3. Using the reread table sequence number as an index, search the reread table to determine the predicted reread table entries; The reread table has columns including serial number and reread entries; the flash chip temperature table has columns including chip number and current read temperature, with the number of rows determined by the number of flash chips; the data in the table is updated using an overwrite method; the data block health information table has columns including chip block number, number of erase / write cycles, first page write temperature, middle page write temperature, last page write temperature, normalized hold time, and read interference count, with the number of rows determined by the number of chip blocks; the data in the table is updated using an overwrite method and is retained even after power loss; the reread table, flash chip temperature table, data block health information table, and pre-trained reread table prediction model are stored in the flash controller.

2. The read retry method as described in claim 1, characterized in that, The data in the table remains unchanged after the table leaves the factory. Before the flash memory chip temperature gauge leaves the factory, the current reading temperature corresponding to each chip number is initialized to empty. After leaving the factory, it is updated in an overwrite manner after each power-on. The update rule is: all flash memory chips are read periodically, and the current reading temperature corresponding to the chip number is updated after each reading of the flash memory chip is completed. Before leaving the factory, the data block health information table is initialized to empty for each chip block number, including "first page write temperature, middle page write temperature, and last page write temperature," and "erased / written count, normalized hold time, and read interference count." After leaving the factory, it is updated using an overwrite method, with the following update rules: ① Each time a memory chip block completes an erase / write cycle, the "erased / written count" for that chip block number is incremented by 1, while other attributes are set to zero; ② Each time a write operation is completed on a flash memory chip block, the "first page write temperature, middle page write temperature, and last page write temperature" for that chip block number are updated, while other attributes remain unchanged; ③ Each time a read operation is completed on a flash memory chip block, the "read interference count" for that chip block number is incremented by 1, while other attributes remain unchanged; ④ Whenever the flash memory chip temperature table is updated, the normalized hold time is calculated based on the update time interval of the flash memory chip temperature table and the current read temperature corresponding to the updated chip number. Simultaneously, the normalized hold time for all flash memory blocks corresponding to the updated chip number is updated, while other attributes remain unchanged.

3. The read retry method as described in claim 2, characterized in that, The formula for calculating the normalized retention time is as follows: in, It is the normalized retention time. It is the update time interval of the flash memory chip temperature gauge, and exp is the natural exponential function; It is the activation energy of the flash memory chip reaction; It is the Boltzmann constant; It is the preset target temperature; It is the current read temperature corresponding to the chip number that has been updated in the flash memory chip temperature table.

4. The read retry method as described in claim 1, characterized in that, The reread table prediction model is trained in the following way: Take several blocks of flash memory chips of the same model and divide them into... Group; For the Group flash chip block group execution The erase / write operation, among which... This represents the maximum number of erase / write cycles for a flash memory block. ; Test each flash memory chip block in the same group with different write temperatures, different data retention times, different read interference times, and different read temperatures. During each test, all pages are read by traversing the reread table. After the test, save <number of erase / write cycles of the chip page block, chip page write temperature, read temperature, data retention time, number of read interference times, and reread table sequence number>. The training sample set is constructed using a combination of the number of times the chip page block has been erased and written, the chip page writing temperature, the reading temperature, the data retention time, and the number of read interferences as input data, and the reread table sequence number as the label. The reread table prediction model is trained using the training sample set to obtain a pre-trained reread table prediction model.

5. The read retry method as described in claim 1, characterized in that, If the chip block is not completely written, the chip page write temperature is: ； If the chip block is completely written, the chip page writing temperature is fitted using a Bezier curve: in, This is an estimate of the data write temperature for the page number that currently needs to be reread. , , These are the page number and write temperature of the first page, the page number and write temperature of the middle page, and the page number and write temperature of the last page. This indicates the page number that needs to be reread. As an intermediate variable, , , , , .

6. The read retry method as described in claim 1, characterized in that, If a reread operation is performed according to the predicted reread entry and the read command fails, a reread operation will be performed near the predicted reread entry until the read is successful.

7. A data storage device, characterized in that, include: At least one flash memory chip, each flash memory chip having multiple blocks for storing data, each block including multiple pages; At least one flash memory controller is configured to receive a master control read instruction from a host, convert the master control read instruction into a read operation instruction for the flash memory chip, and perform a preset read operation to read a page of data, wherein the preset read operation has a preset read threshold voltage setting, and when the preset read operation fails, the flash memory controller executes each step of the read retry method as described in any one of claims 1 to 6.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements each step of the read retry method as described in any one of claims 1 to 6.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements each step of the read retry method as described in any one of claims 1 to 6.

Images