A fault self-diagnosis and isolation method and system for a ring network communication system

Abstract

This application belongs to the field of communication technology and discloses a fault self-diagnosis and isolation method and system for a ring network communication system. Multiple slave devices with dual communication interfaces and controlled switches are serially connected on a ring bus. The master unit is equipped with two RS485 ports connected to both ends of the ring bus. Under normal conditions, the controlled switches of the slave devices are turned on, and the slave devices are electrically connected in parallel to the bus. The master unit issues inspection commands according to a time sequence. The dual ports respectively complete signal transmission and reception and monitoring, and distinguish between open circuit and short circuit faults based on the combination logic of two types of status bits. In case of an open circuit, the break point is located by using the status bits of adjacent slave devices, and inspection is carried out on both sides to ensure communication of non-faulty slave devices. In case of a short circuit, the master unit first disconnects its own bus switch, and after the slave device times out and disconnects its internal controlled switch, it checks and locates the fault point one by one, disconnecting the internal controlled switches of the slave devices on both sides of the fault point to isolate the short circuit. Fault location and isolation can be achieved without shutting down the system, and other slave devices outside the fault point can still communicate normally, ensuring stable system operation.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a method and system for fault self-diagnosis and isolation of a ring network communication system. Background Technology

[0002] RS485 bus is an important bus structure in industrial field. This bus transmits information in a differential manner. It typically has one master and many slave devices. The master and slave devices are connected in parallel on the RS485 bus. The master and slave devices have unique communication addresses and use half-duplex communication mode, that is, only one device can send information on the bus at any given time, while other devices receive bus information.

[0003] The typical communication process is as follows: the master sends a inspection command to the slave. After sending, the master waits for a response from the addressed slave. All slaves can receive the master's inspection command, but only the addressed slave, upon receiving the command, sets itself to transmit mode, sends relevant information to the bus according to the command, and then resets to receive mode to continue receiving new master commands. After receiving a response from a slave, the master continues inspecting new slaves according to a predetermined logical sequence, and this process repeats continuously.

[0004] Due to the harsh conditions in industrial settings, communication lines are prone to open circuits and short circuits. In a parallel bus network, an open circuit will prevent devices downstream of the point of failure from communicating with the host, while a short circuit will paralyze the entire bus system or even damage the circuit. Summary of the Invention

[0005] To ensure that slave devices at other non-faulty line points can still communicate normally with the master when the bus line is short-circuited or open-circuited, thus guaranteeing the normal operation of the system; and especially to enable fault location and isolation without shutting down the system, this application provides a fault self-diagnosis and isolation method and system for a ring network communication system.

[0006] Firstly, this application provides a method for self-diagnosis and isolation of faults in a ring network communication system, employing the following technical solution: A method for fault self-diagnosis and isolation of a ring network communication system includes: According to the preset timing sequence, the host sends the first inspection command to the ring bus through the first communication port. Multiple slave devices are serially connected on the ring bus. Each slave device has two communication interfaces and a controlled switch. During normal operation, the controlled switch is in the on state, so that each slave device is electrically connected in parallel on the bus. The host receives the response information from the inspected slave device through the first communication port, and simultaneously listens to the communication signals on the bus through the second communication port, which is connected to the other end of the ring bus; both the first and second communication ports are RS485 communication ports; each communication port of the host has a control switch to control the connection between the communication port and the external wiring terminal. When the host does not receive the inspection command or the response information from the slave through the first communication port through the second communication port, the host inspects all slaves through the first communication port and the second communication port respectively, and obtains the first status bit and the second status bit corresponding to the slave. The first status bit indicates the result of the inspection through the first communication port, and the second status bit indicates the result of the inspection through the second communication port. Based on the combination logic of the first status bit and the second status bit of all slave devices, the fault type is determined to be either a line open circuit or a line short circuit. When a line is determined to be broken, the host determines the location of the break point according to the status bit logic relationship, and performs inspections on the slave devices on both sides of the break point through the first communication port and the second communication port respectively, maintaining normal communication with other slave devices outside the fault point. When a short circuit is detected, the host stops its inspection and disconnects the internal control switches connected to both ends of the ring bus. It waits for all slave devices to automatically disconnect their internal controlled switches if they do not receive a command from the host within a timeout period. Then, the host queries the slave devices one by one from the first communication port and the second communication port in physical order to determine the location of the short circuit fault point. The host then controls the controlled switches inside the slave devices on both sides of the fault point to be in the open state to isolate the short circuit point. At the same time, the host continues to inspect other slave devices outside the two sides of the short circuit point.

[0007] By adopting the above technical solution, after the host sends an inspection command through the first port, if the second port does not receive the inspection command signal sent by the host's first port or the slave's response command, it indicates that there is an open circuit or short circuit problem in the ring link. The host performs a complete inspection of all slaves from both the first and second ports, obtaining the first and second status bits of each slave, thereby quickly determining the fault type. Based on the logical relationship of the status bits, the fault location can be pinpointed. This fault analysis method using a status bit matrix is ​​equivalent to integrating a simple network topology identification capability into the communication protocol. If an open circuit occurs, the system will automatically split the ring network into two independent linear lines, with the host continuing to inspect the normal devices on both sides of the break point, preventing communication between slave devices from being affected by a single point break in the communication line. If a short circuit occurs, the system will first perform a full network electrical reset: the host disconnects the bus connection, and all slaves automatically disconnect their controlled switches due to communication timeout, achieving mutual isolation. The master unit then sequentially wakes up the slave units from both ends of the line. When communication is interrupted in one direction, the exact location of the short circuit can be determined. By disconnecting the controlled switches inside the slave units on both sides of the fault point, the faulty segment is completely isolated. This breaks the traditional RS485 bus's predicament of "one fault, the whole line paralyzed." The entire fault diagnosis, location, and isolation process is fully automated, requiring no manual intervention or specialized diagnostic equipment. It can be achieved solely through preset communication timing and switch control logic, reducing downtime losses in industrial settings and alleviating the pressure on on-site maintenance.

[0008] Optionally, the steps for determining whether the fault type is a line open circuit or a line short circuit based on the combination logic of the first status bit and the second status bit of all slave devices specifically include: When the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit equals the total number of slave devices, it is determined that the line is open and there is only one open circuit; or, When the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit is zero, it is determined that the line is short-circuited; or, When the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit is less than the total number of slave devices but greater than zero, it is determined that the line is broken and there are multiple breaks.

[0009] By adopting the above technical solution, and comparing the total number of logic 1s in the first and second status bits with the total number of slave devices, the fault type can be determined within milliseconds. This elevates fault diagnosis from qualitative description to quantitative analysis, enabling the host to simultaneously complete fault detection, fault classification, and fault severity assessment within a single inspection cycle.

[0010] Optionally, when a line break is detected, the steps for the host to determine the location of the break point based on the status bit logic relationship specifically include: When there is only one open circuit, check the combined status of the first status bit and the second status bit of the two adjacent slave devices; When the status bits of adjacent slave devices are opposite to each other, the circuit breaker point is determined to be located on the communication line between the two slave devices. When there are multiple circuit breaks, the point where the first and second status bits are both invalid, either in forward or reverse order, is the circuit break point.

[0011] Optionally, when a short circuit is determined, the steps to determine the location of the short circuit fault include: After waiting for the first preset time, all the controlled switches inside the slave device have been turned off and all communication interfaces have been set to receive mode. The master device also turns off the corresponding control switch inside and waits for the resettable fuse resistor to reset. The host turns on the first control switch, sends a fault identification command through the first communication port, and queries the slave devices in physical order; When the queried slave device responds correctly, the master sends a command to enable the controlled switch inside the queried slave device and continues to query the next slave device; When the queried slave device fails to respond, it is determined that the line between the current queried slave device and the previous slave device is short-circuited, and the master device immediately disconnects the first control switch. After the host waits for a second preset time, all the controlled switches inside the slave devices are disconnected again. Then the host turns on the second control switch and executes the same step-by-step query process through the second communication port. If the fault locations identified by the two queries are the same, it is determined that there is only one short circuit fault on the bus; if they are different, it is determined that there are multiple short circuit faults, and the host only identifies the fault point closest to its respective port.

[0012] Optionally, after identifying the short-circuit fault point, the steps to continue inspecting other slave devices besides those on both sides of the short-circuit point specifically include: The host stops bus inspection and waits for a third preset time. After that, all slave devices disconnect the internal controlled switches again. The host also disconnects the internal first control switch and second control switch and waits for the resettable fuse resistor to reset. The host inspects the slave devices on the side of the short-circuit fault point in physical order through the first communication port, turns on the controlled switch of the slave device away from the short-circuit fault point, and keeps the controlled switch inside the slave device close to the fault point off. The host inspects the slave devices on the other side of the short-circuit fault point in physical order through the second communication port, turns on the controlled switch of the slave device away from the short-circuit fault point, and keeps the controlled switch inside the slave device close to the fault point open.

[0013] By adopting the above technical solution and through this process, the internal controlled switches of the slave devices on both sides of the short-circuit fault point are used to isolate the short-circuit fault point. The master device inspects other slave devices on both sides of the fault point from two communication ports to achieve uninterrupted power isolation of the fault and normal communication with other slave devices outside the short-circuit fault point.

[0014] Optionally, the fault self-diagnosis and isolation method further includes an automatic addressing process during the power-on initialization phase: When the system is powered on, all the controlled switches inside the slave devices are in the open state, and the corresponding control switches inside the master device are also in the open state. The host sets the first communication port to transmit mode, the second communication port to receive mode, and turns on the two control switches inside the host. The host sends an addressing command through the first communication port. The addressing command can only reach the first slave connected to the host's first communication port. The corresponding slave receives the command and responds. After receiving the response information, the host's first communication port sends a control command again to turn on the controlled switch inside the corresponding slave. The response information includes at least the slave's own ID information code. The host sends an addressing command again. At this time, the second slave device can receive the addressing command and respond. The host sends a control command again to turn on the controlled switch inside the corresponding slave device. The host repeats the above process, turning on the controlled switches inside all the slave devices one by one, until the controlled switch of the last slave device is turned on, thus forming a closed-loop communication channel. When the host sends the addressing command again, all slave devices have been inspected and there is no response. The addressing command is received by the second communication port. The host determines that the addressing process is over and obtains the physical order of each slave device on the ring bus and the corresponding ID information code.

[0015] By adopting the above technical solution, through this process, the bus is divided into several segments by using the controlled switch inside the slave device to be in the open state at the beginning. Each inspection command of the master can only be advanced one by one, and then the physical order of each slave device on the bus is obtained by relying on the ID information code, and finally a smooth ring network is formed.

[0016] Optionally, the fault self-diagnosis and isolation method further includes an address reset step: After completing automatic addressing, the host will establish an association between the acquired slave ID information codes and the simplified address codes; The host sends a reset command through the first communication port. The reset command includes the slave ID information code and the corresponding simplified address code. After receiving the reset command, each slave device identifies whether the ID information code in the reset command matches its own ID. If so, it receives and stores the simplified address code and sends a response message. After receiving the response, the master sends the reset command to the next slave, until the address reset of all slaves is completed.

[0017] By adopting the above technical solution and through this process, the association between ID information code, physical sequence number and inspection address code is established.

[0018] Secondly, this application provides a fault self-diagnosis and isolation system for a ring network communication system, which adopts the following technical solution: A fault self-diagnosis and isolation system for a ring network communication system includes a master unit and multiple slave units. The master unit has two built-in double-pole control switches, and each slave unit has one built-in double-pole control switch. The master unit includes: Main processor; The first RS485 interface chip is controlled by the UART first interface of the main processor. Its output A terminal is serially connected to a first resettable fuse resistor PT1, and its output B terminal is serially connected to a second resettable fuse resistor PT2. The output A terminal and output B terminal of the first RS485 interface chip form an external RS485 port 1 after passing through the first double-pole control switch QK1. The second RS485 interface chip is controlled by the UART second interface of the main processor. Its output A terminal is serially connected to a third resettable fuse resistor PT3, and its output B terminal is serially connected to a fourth resettable fuse resistor PT4. The output A terminal and output B terminal of the second RS485 interface chip form an external RS485 port 2 after passing through the second double-pole control switch QK2. The RS485 port 1 and the RS485 port 2 are respectively connected to one side and the other side of the ring bus. The load resistor RL is connected in parallel at the connection points of the two resettable fuse resistors and the double control switch corresponding to the RS485 interface chip; the first double control switch QK1 and the second double control switch QK2 are controlled by the main processor. Multiple slave devices are serially connected end-to-end between the first communication port (RS485 port 1) and the second communication port (RS485 port 2) of the host via a ring bus. The slave devices include: From the processor; The first RS485 interface chip is controlled by the UART first interface of the slave processor. Its output A terminal is serially connected to a first resettable fuse resistor PT1 to form an external electrical interface A1, and its output B terminal is serially connected to a second resettable fuse resistor PT2 to form an external electrical interface B1. The second RS485 interface chip is controlled by the UART second interface of the slave processor. Its output A terminal is serially connected to a third resettable fuse resistor PT3 to form an external electrical interface A2, and its output B terminal is serially connected to a fourth resettable fuse resistor PT4 to form an external electrical interface B2. The dual-pole control switch QK inside the slave unit is controlled by the slave processor and is used to connect two external communication interfaces, so that A1 and A2, B1 and B2 are connected internally in the circuit. The dual-pole control switch QK is in the off state by default when powered on, so that the bus segments on both sides of the slave unit are isolated from each other. During normal operation, it is in the on state, so that the slave unit is electrically connected in parallel to the ring bus, and the two RS485 interface chips of each slave unit are connected to the bus.

[0019] Optionally, the fault self-diagnosis and isolation system further includes: Pull-up resistors, wherein the first pull-up resistor R1 in the master and slave devices is electrically connected to the output A terminal of the first RS485 interface chip in the master and slave devices respectively, and the second pull-up resistor R3 in the master and slave devices is electrically connected to the output A terminal of the second RS485 interface chip in the master and slave devices respectively; Pull-down resistors, wherein the first pull-down resistor R2 in the master and slave devices is electrically connected to the output B terminal of the first RS485 interface chip of the master and slave devices respectively, and the second pull-down resistor R4 in the master and slave devices is electrically connected to the output B terminal of the second RS485 interface chip of the master and slave devices respectively.

[0020] By adopting the above technical solution, pull-up and pull-down resistors ensure that the bus maintains a logic high level when static, in order to comply with the communication specifications of the UART interface.

[0021] In summary, this application includes at least one of the following beneficial technical effects: Automatic identification of the physical location sequence of slave devices on the ring bus was achieved; When the bus is open or short-circuited, the fault location is automatically identified online and isolated in the smallest possible area. The slave devices outside the fault location can still operate normally, thus avoiding downtime for troubleshooting and ensuring uninterrupted system operation. 3. The RS485 interface chip is protected by a resettable fuse resistor to prevent damage to the RS485 interface chip and the escalation of the fault in the event of a short circuit. Attached Figure Description

[0022] Figure 1This is a first flowchart of an embodiment of the method of this application; Figure 2 This is a second flowchart of an embodiment of the method of this application; Figure 3 This is a third flowchart of an embodiment of the method of this application; Figure 4 This is the fourth flowchart of an embodiment of the method of this application; Figure 5 The system embodiments in this application retain only the essential key content of the master and slave devices to show the system architecture diagram of the ring bus system; Figure 6 This is a system structure diagram illustrating the electrical connection between the master and slave devices in an embodiment of the system described in this application. Detailed Implementation

[0023] To make the purpose, technical solution, and advantages of this application clearer, the following description is provided in conjunction with the appendix. Figures 1-6 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the application.

[0024] The first embodiment of this application discloses a method for fault self-diagnosis and isolation of a ring network communication system. (Refer to...) Figure 1 The fault self-diagnosis and isolation methods include S110-S160: S110, according to the preset timing, the host sends the first inspection command to the ring bus through the first communication port. Multiple slave devices are serially connected on the ring bus. Each slave device has two communication interfaces and a controlled switch. During normal operation, the controlled switch is in the on state, so that each slave device is electrically connected in parallel on the bus. S120, the host receives the response information from the inspected slave through the first communication port, and at the same time listens to the communication signal on the bus through the second communication port, which is connected to the other end of the ring bus; both the first and second communication ports are RS485 communication ports; each communication port of the host has a control switch to control the connection between the communication port and the external wiring terminal. S130, when the host second communication port does not receive the inspection command issued by the first communication port or the response information of the slave, the host inspects all slaves through the first communication port and the second communication port respectively, and obtains the first status bit and the second status bit corresponding to the slave respectively. The first status bit indicates the result of the inspection through the first communication port, and the second status bit indicates the result of the inspection through the second communication port. S140, based on the combination logic of the first and second status bits of all slave devices, determine the fault type as a line open circuit or a line short circuit. S150, when the line is determined to be open, the host determines the location of the open circuit point according to the status bit logic relationship, and performs inspection on the slaves on both sides of the open circuit point through the first communication port and the second communication port respectively, maintaining normal communication with other slaves outside the fault point. S160: When a short circuit is detected, the host stops its inspection and disconnects the internal control switches connected to both ends of the ring bus. It waits for all slave devices to automatically cut off their internal controlled switches due to not receiving a timeout command from the host. Then, the host queries the slave devices one by one from the first communication port and the second communication port in physical order to determine the location of the short circuit fault point. It then controls the controlled switches inside the slave devices on both sides of the fault point to be in the open state to isolate the short circuit point. At the same time, it continues to inspect other slave devices outside the two sides of the short circuit point.

[0025] Specifically, in step S110, after the system enters normal operating mode, the main processor in the host computer periodically initiates communication according to a preset timing sequence. The host computer converts TTL serial data into differential signals through its internal first RS485 interface chip and sends a first inspection command to the ring bus via RS485 port 1 (the first communication port). At this time, the ring bus uses a daisy-chain connection between multiple slave devices. Since the controlled switches inside the slave devices are in the ON state during normal operation, the two electrical interfaces of each slave device are controllably connected within the slave device. Therefore, from the perspective of overall signal transmission, all slave devices are connected in parallel on the bus. When the host computer issues an inspection command, the differential signal propagates along the bus, ensuring that all slave devices on the bus receive the command simultaneously.

[0026] In step S120, the host computer adopts a dual-port collaborative working mode. The host computer not only receives the response information from the addressed slave device through RS485 port 1, but also simultaneously uses the second RS485 interface chip and RS485 port 2 (the second communication port) to listen for communication signals on the bus. RS485 port 2 is connected to the other end of the ring bus, and its core function is to receive the loop feedback signals.

[0027] When the bus is functioning correctly, the inspection commands sent by the master RS485 port 1 and the response information from the slave will be transmitted along the loop and received by RS485 port 2. This dual-port monitoring mechanism is entirely based on the RS485 communication port, enabling the master to compare the sent and received signals in real time, thereby keenly sensing any abnormalities in the bus status.

[0028] In step S130, when the host fails to receive the inspection command or slave response from RS485 port 1 via RS485 port 2, it can be determined that the bus line is malfunctioning. At this time, the host will switch its operating mode, and the two RS485 ports of the host will poll and diagnose all slaves one by one, obtaining and marking the inspection results of each slave via the two RS485 ports. Specifically, the host sets two status bits for each slave's response result: the first status bit ST1 indicates the inspection result via RS485 port 1, and the second status bit ST2 indicates the inspection result via RS485 port 2. In specific implementation, the host first sends an inspection command for a specific slave via RS485 port 1. If a response is correctly received from the slave, the corresponding first status bit ST1 is set to logic 1; otherwise, it is set to logic 0. Subsequently, the host sends an inspection command for the same slave via RS485 port 2. If a response is correctly received, the corresponding second status bit ST2 is set to logic 1; otherwise, it is set to logic 0. Through this bidirectional polling mechanism, the host can accurately record the connectivity status of each slave device on the bidirectional path.

[0029] In S140, the steps for determining whether the fault type is a line open circuit or a line short circuit based on the combination logic of the first and second status bits of all slave devices specifically include: When the sum of the number of logic 1s in the first state bit and the number of logic 1s in the second state bit equals the total number of slave devices, it is determined that the line is open and there is only one open circuit; or, When the sum of the number of logic 1s in the first state bit and the number of logic 1s in the second state bit is zero, a short circuit is determined; or, When the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit is less than the total number of slave devices but greater than zero (i.e., there is a slave device whose first status bit and second status bit are both 0), it is determined that the line is broken and there are multiple breaks.

[0030] Specifically, in step S140, the host intelligently determines the fault type based on the combined logic of the first and second status bits of all slave devices. If the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit equals the total number of slave devices, it indicates that although some slave devices do not respond to a single port, all slave devices can be accessed by at least one of the two ports. This situation can be identified as a line break with only one location. If the sum is zero, it indicates that no slave device can be accessed by any port. This extreme case of a complete network paralysis is identified as a line short circuit. If the sum is less than the total number of slave devices but greater than zero, it indicates that there are multiple breaks, causing the physical connection between some slave devices and both ports to be severed, resulting in a complete loss of connection.

[0031] In S150, when a line break is detected, the steps by which the host determines the location of the break point based on the status bit logic relationship specifically include: When there is only a single circuit break, check the combined status of the first and second status bits of the two adjacent slave devices. When the status bits of adjacent slave devices are opposite to each other, the circuit breaker point is determined to be located on the communication line between the two slave devices. When there are multiple circuit breaks, the point where the first and second status bits are both invalid, either in forward or reverse order, is the circuit break point.

[0032] Specifically, in step S150, when a line break is determined, the host will further pinpoint the break point based on the logical relationship of the status bits. If there is only a single break point, the host will check the combined status of the first and second status bits of the two adjacent slave devices. For example, if the status bits of two adjacent slave devices are 10 and 01 respectively, it means that one slave device can only be accessed by RS485 port 1 and the other can only be accessed by RS485 port 2. These two slave devices must be located on opposite sides of the break point, thus determining that the break point is located on the communication line between these two slave devices.

[0033] If multiple open circuits exist, causing some slave devices to have both their first and second status bits set to 0 (i.e., completely disconnected), the master traverses the circuit in either forward (towards the first communication port) or reverse (towards the second communication port) order. The first location where both the first and second status bits are invalid (00) is the open circuit point. It should be noted that this method can only identify the open circuit point closest to the master. For example, suppose there are 8 slave devices on the bus, with their first and second status bits set to 10, 10, 10, 00, 00, 00, 01, and 01 respectively. The master traverses from port 1; slave device #3 has a status bit of 10, while slave device #4 has a status bit of 00. Therefore, the first open circuit point is determined to be on the line between slave devices #3 and #4. Simultaneously, traversing from port 2, slave device #7 has a status bit of 01, while slave device #6 has a status bit of 00. Therefore, the second open circuit point is determined to be on the line between slave devices #6 and #7. In this situation, slave devices #4, #5, and #6 cannot be detected by either the first port or the second port.

[0034] After locating the circuit breaker point, the host computer independently inspects the slave computers on both sides of the circuit breaker point using RS485 port 1 and RS485 port 2 respectively. In this way, even if there is a circuit breaker, the other slave computers outside the fault point can still maintain normal communication and monitoring with the host computer.

[0035] Reference Figure 2 In S160, when a line short circuit is determined, the steps for determining the location of the short circuit fault specifically include S210-S260: S210, after waiting for the first preset time, all the controlled switches inside the slave unit have been turned off and all communication interfaces have been set to receive mode. The master unit also turns off the corresponding control switch inside and waits for the resettable fuse resistor to reset. S220: The host turns on the first control switch and sends a fault identification command through the first communication port to query the slave devices in physical order; S230: When the queried slave device responds correctly, the master sends a command to turn on the internal controlled switch of the queried slave device and continues to query the next slave device. S240, when the queried slave device fails to respond, it is determined that the line between the current queried slave device and the previous slave device is short-circuited, and the master immediately disconnects the first control switch; S250: After the master waits for the second preset time, all the controlled switches inside the slave are turned off again, and then the second control switch is turned on to execute the same step-by-step query process through the second communication port. S260: If the fault locations identified by the two queries are the same, it is determined that there is only one short circuit fault on the bus; if they are different, it is determined that there are multiple short circuit faults, and the host only identifies the fault point closest to its respective port.

[0036] After identifying the short-circuit fault point, it is necessary to continue inspecting other slave devices outside the two sides of the short-circuit point. This step specifically includes: The host stops bus inspection and waits for the third preset time. After that, all slave devices cut off their internal controlled switches again. The host also disconnects the first and second internal control switches and waits for the resettable fuse resistor to reset. The host inspects the slave units on the side of the short-circuit fault point in physical order through the first communication port, turns on the controlled switch inside the slave unit away from the short-circuit fault point, and keeps the controlled switch inside the slave unit close to the fault point off. The host inspects the slave devices on the other side of the short-circuit fault point in physical order through the second communication port, turns on the controlled switch inside the slave device away from the short-circuit fault point, and keeps the controlled switch inside the slave device close to the fault point off.

[0037] Specifically, in step S160, when a short circuit is detected, the differential signal of the entire RS485 bus is blocked due to the short circuit. At this time, the RS485 interface chip in the transmitting state is in a strong drive state. An external short circuit will trigger the resettable fuse resistor connected in series at its AB terminals to protect the interface chip from damage. When the host detects a bus short circuit, it immediately stops the inspection and disconnects the host control switches (QK1 and QK2) connected to both ends of the ring bus, cutting off the drive source to prevent the fault from escalating. Subsequently, the system enters a waiting period. After the first preset time T1, if all slave devices do not receive communication commands from the host within the predetermined time, their slave processors will trigger a protection mechanism, automatically disconnecting the internal controlled switches and setting both RS485 interface chips to a high-impedance receiving state. The host also simultaneously disconnects the corresponding internal control switches. Since no external energy is applied, no destructive large current flows through the short circuit point. At this time, the resettable fuse resistor, which is in short-circuit protection mode, will automatically return to its normal state, creating a safe electrical environment for subsequent fault diagnosis.

[0038] The specific location of the short-circuit fault is determined as follows: The master first turns on the first control switch (QK1 on the RS485 port 1 side) and sets RS485 port 1 to transmit mode. At this time, since all the internal controlled switches of the slave devices are open, the bus is physically divided into several independent segments. Starting from the first position in the bus physical location sequence, the master sequentially sends a fault identification command containing the address of the first slave device. Because only the first slave device has a direct physical path to the master's port 1, the command can only reach the first slave device.

[0039] If the first slave device being queried correctly receives the command and responds, it indicates that the communication line preceding that slave device is normal. After receiving the response, the master device sends a command to the slave device to turn on the controlled switch. Upon receiving this command, the queried slave device turns on its internal controlled switch. At this point, the communication channel is extended, and the master device then sets the address of the next slave device to be inspected in physical location sequence, continues to query the next slave device, and repeats the fault identification and controlled switch activation process, gradually advancing deeper into the bus.

[0040] When the queried slave device fails to respond, it indicates that the communication signal cannot reach that slave device. Since the previous slave device communicated normally with the master device, but its controlled switch was turned on, affecting the communication of the subsequent slave device, the fault must lie in the communication line between the previous slave device and the currently queried slave device, which is determined to be a short circuit fault point / location. To prevent the short circuit current from continuously affecting the master device, the master device will immediately disconnect the first control switch after determining the short circuit point / location, protecting the master device's RS485 interface chip and allowing the resettable fuse resistor to automatically reset.

[0041] To further verify whether other short circuits exist on the bus, the master will perform another fault identification from RS485 port 2. After waiting for a second preset time, the master ensures that all internal controlled switches of the slave devices are turned off again, then turns on the second control switch (i.e., QK2 on the RS485 port 2 side), and executes the same step-by-step polling process through RS485 port 2. That is, starting from the other end of the ring bus, the master checks the communication of each slave device and turns on its internal controlled switch one by one until it encounters a slave device that cannot respond.

[0042] The host compares and analyzes the fault locations identified in the two queries. If the fault locations are the same, it is determined that there is only one short-circuit fault on the bus; if the fault locations are different, it indicates that there are multiple short-circuit fault points on the bus, and the host can only identify the fault point closest to its respective port. The host displays the judgment result and issues an alarm to remind manual intervention.

[0043] After locating the short-circuit fault, the host needs to perform an isolation operation. The host stops bus inspection and waits for a third preset time. Then, all slave devices disconnect their internal controlled switches again, and the host also disconnects its internal first and second control switches, and waits again for the resettable fuse resistor to reset. This step aims to restore the bus to its initial safe state where all physical connections are disconnected (because during the short-circuit fault location process, some slave devices' internal controlled switches were turned on to extend the test channel, and they need to be disconnected again to clear this connection state), so as to reconstruct the communication network and physically avoid the short-circuit point.

[0044] The host system uses RS485 ports 1 and 2 to inspect the other slave devices on both sides of the fault point in sequence according to their physical locations. The host inspects the slave devices on the side of the short-circuit fault point via RS485 port 1. For slave devices outside the fault point, the host sends a command to activate their internal controlled switches to enable normal operation; for slave devices closer to the fault point, their internal controlled switches are kept open to physically disconnect them from the short-circuit point. Similarly, the host inspects the slave devices on the other side of the short-circuit fault point via RS485 port 2, activating the controlled switches of slave devices outside the fault point while keeping the controlled switches of slave devices closer to the fault point open. In this way, the short-circuit fault point is completely physically isolated, without affecting communication between other slave devices and the host, achieving normal inspection of slave devices outside the fault point and uninterrupted system operation.

[0045] Reference Figure 3 Furthermore, the fault self-diagnosis and isolation method also includes the automatic addressing process S310-S360 during the power-on initialization phase: S310, when the system is powered on, all the controlled switches inside the slave unit are in the off state, and the corresponding control switches inside the master unit are also in the off state; S320, the host sets the first communication port to transmit mode, the second communication port to receive mode, and turns on the two control switches inside the host. S330, the host sends an addressing command through the first communication port. The addressing command can only reach the first slave connected to the host's first communication port. The corresponding slave receives the command and responds. After receiving the response information, the host's first communication port sends a control command again to turn on the controlled switch inside the corresponding slave. The response information includes at least the slave's own ID information code. S340, the master sends the addressing command again. At this time, the second slave can receive the addressing command and respond. The master sends the control command again to turn on the controlled switch inside the corresponding slave. S350, the master repeats the above process, turning on the controlled switches inside all slaves one by one, until the controlled switch of the last slave is turned on, thus forming a closed-loop communication channel. When the host sends the addressing command again, all slave devices have been inspected and there is no response. The addressing command is received by the second communication port. The host determines that the addressing process is over and obtains the physical order of each slave device on the ring bus and the corresponding ID information code.

[0046] Specifically, when the system is first powered on, all controlled switches inside the slave devices are in the open state, and the control switches inside the master device are also in the open state. At this time, the ring bus has not yet formed a closed loop. The master device, as the communication initiator, sets RS485 port 1 to transmit mode and RS485 port 2 to receive mode, and controls the switches inside the master device to turn on. The master device sends an addressing communication command through RS485 port 1. Since the bus is divided into several independent segments, the command can only reach the first slave device. The first slave device receives the command and responds, and the response information includes its ID information code.

[0047] After receiving the response, the master sends a control command to activate the controlled switch inside the slave device, thus establishing communication between the slave device and the next slave device. The master then sends an addressing command, which the second slave device receives and responds to. The master then sends another control command to activate its internal controlled switch.

[0048] The master repeatedly executes the steps of sending addressing commands and control responses to the slave devices to turn on their internal controlled switches, turning on the controlled switches of all slave devices one by one, until the controlled switch of the last slave device is turned on, thus forming a closed-loop communication channel.

[0049] When the host sends the addressing command again, all slave devices have been inspected and therefore do not respond. The command is received by RS485 port 2. Based on this, the host determines that the addressing process is over and obtains the ID information codes of each slave device in sequence. This sequence is the physical location order of the slave devices in the ring network.

[0050] Reference Figure 4 Furthermore, the fault self-diagnosis and isolation method also includes address reset steps S410-S440: After completing automatic addressing, the S410 will establish an association between the ID information codes of each slave device and the simplified address codes obtained by the host. S420: The host sends a reset command through the first communication port. The reset command contains the slave ID information code and the corresponding simplified address code. S430: After receiving the reset command, each slave device identifies whether the ID information code in the reset command matches its own ID. If so, it receives and stores the simplified address code and sends a response. After receiving the response, the master sends the next slave reset command until the address reset of all slaves is completed.

[0051] Specifically, since ID information codes are generally quite long, direct use for inspection is inefficient; therefore, remapping is required (using simplified addresses, such as single-byte address codes). After automatic addressing, the host establishes an association between the acquired slave ID information codes and the simplified address codes. The host sends a reset command through RS485 port 1, which contains the slave ID information code and its corresponding simplified address code.

[0052] After receiving the reset command, each slave device checks whether the ID information code in the command matches its own ID. If they match, the slave device receives and stores the simplified address code and sends a response. After receiving the response, the master device sends the reset command to the next slave device. This process is repeated until the addresses of all slave devices are reset. During subsequent normal inspections, the master device can use the simplified address code for efficient communication.

[0053] Based on the above method embodiments, the second embodiment of this application discloses a fault self-diagnosis and isolation system for a ring network communication system. The fault self-diagnosis and isolation system for a ring network communication system of this application embodiment can implement any of the above-described fault self-diagnosis and isolation methods for ring network communication systems, and the specific working process of each module in the fault self-diagnosis and isolation system for ring network communication systems can refer to the corresponding process in the above method embodiments.

[0054] For ease of understanding, please refer to Figure 5 and Figure 6A fault self-diagnosis and isolation system for a ring network communication system includes a master unit, multiple slave units, and multiple pull-down and pull-up resistors corresponding to each RS485 interface. In this application, the master unit has two built-in double-pole control switches, and the slave units have one built-in double-pole control switch. The double-pole control switches are preferably double-pole linkage relays, which have extremely low mechanical contact resistance (typically about 50mΩ), will not affect the communication signal, and can also resist electrical interference such as lightning strikes and static electricity in the field.

[0055] The host unit includes a main processor, a first RS485 interface chip, a second RS485 interface chip, and a load resistor RL. The main processor has at least two UART interfaces to facilitate connection to the two RS485 interface chips.

[0056] The first RS485 interface chip is controlled by the UART first interface of the main processor. The output A terminal is serially connected to the first resettable fuse resistor PT1, and the output B terminal is serially connected to the second resettable fuse resistor PT2. The output A terminal and the output B terminal of the first RS485 interface chip form an external RS485 port 1 after passing through the first double-pole control switch QK1.

[0057] The second RS485 interface chip is controlled by the main processor's UART second interface. Output A is serially connected to a third resettable fuse resistor PT3, and output B is serially connected to a fourth resettable fuse resistor PT4. Output A and output B of the second RS485 interface chip form an external RS485 port 2 after passing through the second double-pole control switch QK2. RS485 port 1 and RS485 port 2 are respectively connected to one side and the other side of the ring bus.

[0058] The load resistor RL is connected in parallel at the connection points of the two resettable fuse resistors and the double-pole control switches corresponding to the RS485 interface chip. The load resistor RL is set to 120Ω. Because the two RS485 ports of the host serve as the beginning and end of a ring bus, this perfectly meets the requirement of setting load balancing resistors at both ends of the RS485 bus to avoid signal reflection and ensure communication effectiveness. The first double-pole control switch QK1 and the second double-pole control switch QK2 are controlled by the main processor.

[0059] Multiple slave devices are serially connected end-to-end via a ring bus between the master's first communication port (RS485 port 1) and second communication port (RS485 port 2). Each slave device includes a slave processor, a first RS485 interface chip, and a second RS485 interface chip. The slave processor has at least two UART interfaces to facilitate connection to the two RS485 interface chips.

[0060] The first RS485 interface chip is controlled by the UART first interface of the processor. Its output A terminal is serially connected to a first resettable fuse resistor PT1 to form an external electrical interface A1, and its output B terminal is serially connected to a second resettable fuse resistor PT2 to form an external electrical interface B1.

[0061] The second RS485 interface chip is controlled by the processor's UART second interface. Output A is serially connected to a third resettable fuse resistor PT3 to form an external electrical interface A2, and output B is serially connected to a fourth resettable fuse resistor PT4 to form an external electrical interface B2.

[0062] The dual-pole control switch QK (i.e., the controlled switch) inside the slave unit is controlled by the slave processor and is used to connect the two external RS485 electrical interfaces of the slave unit, so that A1 and A2, B1 and B2 are connected in the internal circuit of the slave unit. The dual-pole control switch QK is in the open state by default when powered on, so as to isolate the bus links on both sides of the slave unit. By receiving the control command from the master, the dual-pole control switch QK is turned on to ensure that the entire bus link is unobstructed. When neither of the two communication ports of the slave unit receives any inspection command from the master for a predetermined period of time, the dual-pole control switch QK automatically turns off to isolate the bus links on the left and right sides of the slave unit, and both RS485 interface chips are set to receive state.

[0063] When the internal controlled switch of the slave device is in the open state, the two RS485 interfaces of the slave device are equivalent to connecting to the left and right bus segments respectively. The slave device can receive bus commands from the left and right sides respectively. To elaborate further, it can receive communication commands sent from the first or second communication port of the master device. When the controlled switch is open, the RS485 communication port of the slave device that received the bus command is the same RS485 communication port that responds (when a local response is required). That is, receiving and sending must use the same RS485 interface to avoid incorrect data transmission direction affecting the master device's judgment.

[0064] When the controlled switch inside the slave device is in the ON state, its two RS485 interfaces are essentially connected in parallel. They are converted to TTL levels by two separate RS485 interface chips and input to different UART interfaces on the slave device. In this state, the slave device is connected to the ring bus in parallel. When there is an RS485 signal on the bus (regardless of which port of the master sends the communication command), both UART interfaces of the slave device can receive the RS485 bus communication command. If the information received by the two UART interfaces is consistent, when the slave device needs to respond, either RS485 communication interface can respond, while the other RS485 communication interface remains in receiving mode. By verifying the consistency of the information from the two UART interfaces, the normal operation of the two RS485 interface chips can be verified. This prevents the slave device's workflow when the controlled switch is off from being affected by the malfunction of one interface, thus ensuring system reliability.

[0065] With this design, during actual construction wiring, it is not necessary to distinguish which of the two external electrical interfaces (A1B1, A2B2) of the slave unit is the input and which is the output. Simply connect the RS485 bus on the same side according to the AB sequence. This effectively reduces the trouble caused by wiring errors. Moreover, this method effectively achieves minimum area isolation of the RS485 ring communication network when the line is short-circuited, while still ensuring the normal operation of the system communication.

[0066] In this configuration, the first pull-up resistor R1 in the master and slave devices is electrically connected to the output A terminal of the first RS485 interface chip in the master and slave devices, and the second pull-up resistor R3 in the master and slave devices is electrically connected to the output A terminal of the second RS485 interface chip in the master and slave devices.

[0067] The first pull-down resistor R2 in the master and slave devices is electrically connected to the output B terminal of the first RS485 interface chip of the master and slave devices, and the second pull-down resistor R4 in the master and slave devices is electrically connected to the output B terminal of the second RS485 interface chip of the master and slave devices.

[0068] The following is an application example illustrating the handling process for open circuits and short circuits that occur during normal inspections: Assume there are four slave devices on the bus, designated 1#, 2#, 3#, and 4#, and the master's inspection sequence is also 1#, 2#, 3#, and 4#. Slave devices 1# and 2# have the same wiring direction, while slave devices 3# and 4# have the same wiring direction but opposite directions. However, the system can automatically identify these and it does not affect the master's inspection.

[0069] Normal inspection procedure: (1) The host RS485 port 1 sends a command to inspect slave 1#. The host RS485 port 2 receives the command to inspect slave 1# from RS485 port 1. Slaves 1#, 2#, 3# and 4# all receive the command, but only slave 1# responds. The response from slave 1# is received by the host RS485 port 1 and the host RS485 port 2 respectively. (2) The host RS485 port 1 sends a command to inspect slave 2#. The host RS485 port 2 receives the command to inspect slave 2# from RS485 port 1. Slaves 1#, 2#, 3# and 4# all receive the command, but only slave 2# responds. The response from slave 2# is received by the host RS485 port 1 and the host RS485 port 2 respectively. (3) The host RS485 port 1 sends a command to inspect slave 3#. The host RS485 port 2 receives the command to inspect slave 3# from RS485 port 1. Slaves 1#, 2#, 3# and 4# all receive the command, but only slave 3# responds. The response from slave 3# is received by the host RS485 port 1 and the host RS485 port 2 respectively. (4) The host RS485 port 1 sends a command to inspect slave 4#. The host RS485 port 2 receives the command to inspect slave 4# from RS485 port 1. Slaves 1#, 2#, 3# and 4# all receive the command, but only slave 4# responds. The response from slave 4# is received by the host RS485 port 1 and the host RS485 port 2 respectively. (5) The host repeats the above process.

[0070] Assuming that the L2 line is open-circuited, when the host is executing process (3), the host RS485 port 2 does not receive the instruction to inspect slave 3# sent by the host RS485 port 1. Since the L2 line is open-circuited, slave 3# cannot receive the inspection instruction sent by the host, so slave 3# will not respond. Therefore, the host RS485 port 1 will not receive the response from slave 3#, and the host RS485 port 2 will not receive the response from slave 3#. At this time, it is preliminarily judged that there is a line fault.

[0071] Of course, it is also possible that when the host is executing process (4), the host RS485 port 2 does not receive the instruction to inspect slave 4# issued by the host RS485 port 1, and slave 4# cannot receive the inspection instruction issued by the host. Therefore, slave 4# will not respond, and the host RS485 port 1 will not receive the response from slave 4#, and the host RS485 port 2 will not receive the response from slave 4#. At this time, it is preliminarily judged that there is a line fault.

[0072] In other words, when the host inspects the slave unit behind the fault point, it will find that the line is faulty. The specific location of the fault point needs to be determined. The host internally sets up logical state tables ST1(2), ST2(2), ST3(2), and ST4(2), and the initial value is 0.

[0073] 1. The host RS485 port 1 queries slave device #1. Slave device #1 receives the inspection command and responds. The response information is received by the host RS485 port 1. The host sets ST1.0=1. 2. The host RS485 port 2 queries slave 1. Due to the L2 line being open, slave 1 does not receive the inspection command and therefore does not respond. The host RS485 port 2 does not receive the response information from slave 1 within the time limit, and the host sets ST1.1=0. 3. The host RS485 port 1 queries slave device #2. Slave device #2 receives the inspection command and responds. The response information is received by the host RS485 port 1, and the host sets ST2.0=1. 4. The host RS485 port 2 queries slave device #2. Due to the L2 line being open, slave device #2 does not receive the inspection command and therefore does not respond. The host RS485 port 2 does not receive the response information from slave device #2 within the time limit, and the host sets ST2.1=0. 5. The host RS485 port 1 queries slave 3. Due to the L2 line being open, slave 3 does not receive the inspection command and therefore does not respond. The host RS485 port 1 does not receive the response information from slave 3 within the time limit, and the host sets ST3.0=0. 6. The host RS485 port 2 queries slave device #3. Slave device #3 receives the inspection command and responds. The response information is received by the host RS485 port 2. The host sets ST3.1=1. 7. The host RS485 port 1 queries slave 4. Due to the L2 line being open, slave 4 cannot receive the inspection command and therefore does not respond. The host RS485 port 1 does not receive the response information from slave 4 within the time limit, and the host sets ST4.0=0. 8. The host RS485 port 2 queries slave device #4. Slave device #4 receives the inspection command and responds. The response information is received by the host RS485 port 2. The host sets ST4.1=1. The inspection statuses of slave devices 1#, 2#, 3#, and 4# are 10, 10, 01, and 01, respectively. The sum of the valid status bits is 4, which is consistent with the total number of slave devices, indicating that the fault is a line break. Furthermore, the statuses of slave devices 2# and 3# are reversed, indicating that the line break is located between slave devices 2# and 3#, corresponding to the L2 line.

[0074] The host's RS485 port 1 inspects slave devices #1 and #2 respectively, and the host's RS485 port 2 inspects slave devices #3 and #4 respectively. This ensures that all address points are inspected. At the same time, the host issues an L2 line open circuit fault warning to remind manual handling.

[0075] Assuming a short circuit fault occurs in line L2, when the host executes any of the steps (1), (2), (3), or (4), the host's RS485 port 2 will not receive the inspection command for slave device x# from host's RS485 port 1, and slave device x# will not receive the inspection command from the host. Therefore, slave device x# will not respond, and host's RS485 port 1 will not receive the response from slave device x#, nor will host's RS485 port 2 receive the response from slave device x#. At this point, a preliminary judgment is made that there is a short circuit fault in the line. The specific location of the fault needs to be further determined.

[0076] The host internally sets up logical state tables ST1(2), ST2(2), ST3(2), and ST4(2), with initial values ​​of 0. Due to a short circuit in the L2 line, all bus communication fails. Therefore: The host RS485 port 1 queries slave device #1 (its communication information cannot be effectively transmitted to the bus). Slave device #1 cannot perceive the bus information, so it will not respond. Therefore, the host RS485 port 1 will not receive information from slave device #1. After a time limit, the host sets ST1.0=0. The host RS485 port 2 queries slave device #1 (its communication information cannot be effectively transmitted to the bus). Slave device #1 cannot perceive the bus information, so slave device #1 will not respond. Therefore, the host RS485 port 2 will not receive information from slave device #1. After a time limit, the host sets ST1.1=0. The host RS485 port 1 queries slave device #2 (its communication information cannot be effectively transmitted to the bus). Slave device #2 cannot perceive the bus information, so it will not respond. Therefore, the host RS485 port 1 will not receive information from slave device #2. After a time limit, the host sets ST2.0=0. The host RS485 port 2 queries slave device #2 (its communication information cannot be effectively transmitted to the bus). Slave device #2 cannot perceive the bus information, so it will not respond. Therefore, the host RS485 port 2 will not receive information from slave device #2. After a time limit, the host sets ST2.1=0. The host RS485 port 1 queries slave device #3 (its communication information cannot be effectively transmitted to the bus). Slave device #3 cannot perceive the bus information, so slave device #3 will not respond. Therefore, the host RS485 port 1 will not receive information from slave device #3. After a time limit, the host sets ST3.0=0. The host RS485 port 2 queries slave device #3 (its communication information cannot be effectively transmitted to the bus). Slave device #3 cannot perceive the bus information, so slave device #3 will not respond. Therefore, the host RS485 port 2 will not receive information from slave device #3. After a time limit, the host sets ST3.1=0. The host RS485 port 1 queries slave device #4 (its communication information cannot be effectively transmitted to the bus). Slave device #4 cannot perceive the bus information, so slave device #4 will not respond. Therefore, the host RS485 port 1 will not receive information from slave device #4. After a time limit, the host sets ST4.0=0. The host RS485 port 2 queries slave device #4 (its communication information cannot be effectively transmitted to the bus). Slave device #4 cannot perceive the bus information, so slave device #4 will not respond. Therefore, the host RS485 port 2 will not receive information from slave device #4. After a time limit, the host sets ST4.1=0. The inspection statuses of slave units 1#, 2#, 3#, and 4# are 00, 00, 00, and 00 respectively. The sum of the valid status bits is 0, indicating that the fault is a short circuit.

[0077] The following is a detailed process for identifying the short circuit location, as well as the subsequent inspection process.

[0078] The host stops its inspection and waits for time T1. Each slave device automatically cuts off its internal controlled switch, and the host also cuts off QK1 and QK2. After a delay (usually less than 1 second), once the recoverable fuse resistor has been reset to normal, the host controls the QK1 switch to turn on, and the host RS485 port 1 is set to transmit mode.

[0079] The master RS485 port 1 inspects slave device 1#. Since the L0 line is normal (at this time, the controlled switch inside slave device 1# is in the open state), slave device 1# can correctly receive the inspection command sent by the master RS485 port 1# and respond accordingly. The master RS485 port 1# receives the response information from slave device 1#. The master then sends a control switch on command to slave device 1#, and slave device 1# controls the internal controlled switch to turn on after receiving the command. The master RS485 port 1 inspects slave device #2. Since both L0 and L1 lines are normal, slave device #2 correctly receives the inspection command sent by the master RS485 port 1 and responds accordingly. The master RS485 port 1 receives the response information from slave device #2. The master then sends a control switch activation command to slave device #2. Upon receiving the command, slave device #2 activates its internal control switch. When the controlled switch inside slave device #2 is turned on, a short circuit in line L2 causes a short circuit in lines L0 and L1 as well. The master's RS485 port 1 checks slave device #3, but its information cannot be effectively transmitted. Therefore, slave device #3 cannot receive valid bus information and will not respond. Since the master's RS485 port 1 cannot receive a response from slave device #3, the fault is located after slave device #2, most likely in line L2.

[0080] To further verify whether there are any other short circuits in the bus line, fault identification is performed again from the host RS485 port 2. After a T1 delay, all slave internal switches are turned off. The host also disconnects QK1 and QK2, and after a further delay (generally less than 1 second), once the recoverable fuse resistor has reset to normal, the host controls the QK2 switch to turn on, and the host RS485 port 2 is set to transmit mode.

[0081] The master RS485 port 2 inspects slave device #4. Since the L4 line is normal (the controlled switch inside slave device #4 is in the off state at this time), slave device #4 can correctly receive the inspection command sent by the master RS485 port 2 and respond accordingly. The master RS485 port 2 receives the response information from slave device #4. The master then sends a control switch on command to slave device #4. After receiving the command, slave device #4 controls the internal controlled switch to turn on. The master RS485 port 2 inspects slave device 3. Since both L4 and L3 lines are normal, slave device 3 can correctly receive the inspection command sent by the master RS485 port 2 and respond accordingly. The master RS485 port 2 receives the response information from slave device 3. The master then sends a control switch activation command to slave device 3. Upon receiving the command, slave device 3 activates its internal control switch. When the controlled switch inside slave unit #3 is turned on, a short circuit in line L2 causes lines L4 and L3 to also be short-circuited. The master's RS485 port 2 checks slave unit #2, but its information cannot be effectively transmitted. Therefore, slave unit #2 cannot receive valid bus information and naturally will not respond. Since the master's RS485 port 2 cannot receive a response from slave unit #2, the fault point is located after slave unit #3, most likely in line L2.

[0082] If both tests identify the L2 line as a short circuit fault, it means that the fault is only present on this part of the bus. The host displays the judgment result and issues an alarm, prompting manual intervention.

[0083] The host stops inspecting the bus and waits for time T1. Then, all slave devices disconnect their internal controlled switches again, and the host also disconnects switches QK1 and QK2. After a further delay (generally less than 1 second), once the recoverable fuse resistor has reset to normal, the host uses RS485 port 1 and RS485 port 2 to inspect the other slave devices on both sides of the fault point in sequence according to their physical location. Specifically, host RS485 port 1 inspects slave device #1 and controls its internal controlled switch to be on, while inspecting slave device #2 and disconnecting its internal controlled switch; host RS485 port 2 inspects slave device #4 and controls its internal controlled switch to be on, while inspecting slave device #3 and disconnecting its internal controlled switch. By disconnecting the internal controlled switches of slave devices #2 and #3, the L2 line is isolated. A short circuit in L2 does not affect communication between other slave devices and the host. Furthermore, utilizing the two communication ports of the slave devices, communication between slave devices #2 and #3, which are adjacent to the fault point, and the host is also unaffected.

[0084] After manually troubleshooting the short circuit fault, manually reset the main unit to return to normal operation.

[0085] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any feature disclosed in this specification (including the abstract and drawings) may be replaced by other equivalent or similar features unless specifically stated otherwise. That is, unless specifically stated otherwise, each feature is only one example of a series of equivalent or similar features.

Claims

1. A method for self-diagnosis and isolation of faults in a ring network communication system, characterized in that, include: According to the preset timing sequence, the host sends the first inspection command to the ring bus through the first communication port. Multiple slave devices are serially connected on the ring bus. Each slave device has two communication interfaces and a controlled switch. During normal operation, the controlled switch is in the on state, so that each slave device is electrically connected in parallel on the bus. The host receives the response information from the inspected slave device through the first communication port, and simultaneously listens to the communication signals on the bus through the second communication port, which is connected to the other end of the ring bus; both the first and second communication ports are RS485 communication ports; each communication port of the host has a control switch to control the connection between the communication port and the external wiring terminal. When the host does not receive the inspection command or the response information from the slave through the first communication port through the second communication port, the host inspects all slaves through the first communication port and the second communication port respectively, and obtains the first status bit and the second status bit corresponding to the slave. The first status bit indicates the result of the inspection through the first communication port, and the second status bit indicates the result of the inspection through the second communication port. Based on the combination logic of the first status bit and the second status bit of all slave devices, the fault type is determined to be either a line open circuit or a line short circuit. When a line is determined to be broken, the host determines the location of the break point according to the status bit logic relationship, and performs inspections on the slave devices on both sides of the break point through the first communication port and the second communication port respectively, maintaining normal communication with other slave devices outside the fault point. When a short circuit is detected, the host stops its inspection and disconnects the host control switch connected to both ends of the ring bus. It waits for all slave devices to automatically disconnect their internal controlled switches if they do not receive a command from the host due to timeout. Then, the host queries the slave devices one by one from the first communication port and the second communication port in physical order to determine the location of the short circuit fault point. It then controls the controlled switches inside the slave devices on both sides of the fault point to be in the open state to isolate the short circuit point. At the same time, it continues to inspect other slave devices outside the two sides of the short circuit point.

2. The fault self-diagnosis and isolation method for a ring network communication system according to claim 1, characterized in that, Based on the combination logic of the first and second status bits of all slave devices, the specific steps for determining whether the fault type is a line open circuit or a line short circuit include: When the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit equals the total number of slave devices, it is determined that the line is open and there is only one open circuit; or, When the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit is zero, it is determined that the line is short-circuited; or, When the sum of the number of logic 1s in the first status bit and the number of logic 1s in the second status bit is less than the total number of slave devices but greater than zero, it is determined that the line is broken and there are multiple breaks.

3. The fault self-diagnosis and isolation method for a ring network communication system according to claim 2, characterized in that, When a line break is detected, the host determines the location of the break point based on the status bit logic relationship. The specific steps include: When there is only one open circuit, check the combined status of the first status bit and the second status bit of the two adjacent slave devices; When the status bits of adjacent slave devices are opposite to each other, the circuit breaker point is determined to be located on the communication line between the two slave devices. When there are multiple circuit breaks, the point where the first and second status bits are both invalid, either in forward or reverse order, is the circuit break point.

4. The fault self-diagnosis and isolation method for a ring network communication system according to claim 2, characterized in that, When a short circuit is detected in the line, the specific steps for determining the location of the short circuit fault include: After waiting for the first preset time, all the controlled switches inside the slave device have been turned off and all communication interfaces have been set to receive mode. The master device also turns off the corresponding control switch inside and waits for the resettable fuse resistor to reset. The host turns on the first control switch, sends a fault identification command through the first communication port, and queries the slave devices in physical order; When the queried slave device responds correctly, the master sends a command to enable the controlled switch inside the queried slave device and continues to query the next slave device; When the queried slave device fails to respond, it is determined that the line between the current queried slave device and the previous slave device is short-circuited, and the master device immediately disconnects the first control switch. After the host waits for a second preset time, all the controlled switches inside the slave devices are disconnected again. Then the host turns on the second control switch and executes the same step-by-step query process through the second communication port. If the fault locations identified by the two queries are the same, it is determined that there is only one short circuit fault on the bus; if they are different, it is determined that there are multiple short circuit faults, and the host only identifies the fault point closest to its respective port.

5. The fault self-diagnosis and isolation method for a ring network communication system according to claim 4, characterized in that, After identifying the short-circuit fault point, the specific steps for inspecting other slave devices besides those on both sides of the short-circuit point include: The host stops bus inspection and waits for a third preset time. After that, all slave devices disconnect the internal controlled switches again. The host also disconnects the internal first control switch and second control switch and waits for the resettable fuse resistor to reset. The host inspects the slave devices on the side of the short-circuit fault point in physical order through the first communication port, turns on the controlled switch of the slave device away from the short-circuit fault point, and keeps the controlled switch inside the slave device close to the fault point off. The host inspects the slave devices on the other side of the short-circuit fault point in physical order through the second communication port, turns on the controlled switch of the slave device away from the short-circuit fault point, and keeps the controlled switch inside the slave device close to the fault point open.

6. The fault self-diagnosis and isolation method for a ring network communication system according to claim 1, characterized in that, The fault self-diagnosis and isolation method also includes an automatic addressing process during the power-on initialization phase: When the system is powered on, all the controlled switches inside the slave devices are in the open state, and the corresponding control switches inside the master device are also in the open state. The host sets the first communication port to transmit mode, the second communication port to receive mode, and turns on the two control switches inside the host. The host sends an addressing command through the first communication port. The addressing command can only reach the first slave connected to the host's first communication port. The corresponding slave receives the command and responds. After receiving the response information, the host's first communication port sends a control command again to turn on the controlled switch inside the corresponding slave. The response information includes at least the slave's own ID information code. The host sends an addressing command again. At this time, the second slave device can receive the addressing command and respond. The host sends a control command again to turn on the controlled switch inside the corresponding slave device. The host repeatedly executes the steps of sending addressing commands and control responses to the slave devices to turn on their internal controlled switches, turning on the controlled switches of all slave devices one by one, until the controlled switch of the last slave device is turned on, thus forming a closed-loop communication channel. When the host sends the addressing command again, all slave devices have been inspected and there is no response. The addressing command is received by the second communication port. The host determines that the addressing process is over and obtains the physical order of each slave device on the ring bus and the corresponding ID information code.

7. The fault self-diagnosis and isolation method for a ring network communication system according to claim 6, characterized in that, The fault self-diagnosis and isolation method also includes an address reset step: After completing automatic addressing, the host will establish an association between the acquired slave ID information codes and the simplified address codes; The host sends a reset command through the first communication port. The reset command includes the slave ID information code and the corresponding simplified address code. After receiving the reset command, each slave device identifies whether the ID information code in the reset command matches its own ID. If so, it receives and stores the simplified address code and sends a response message. After receiving the response, the master sends the reset command to the next slave, until the address reset of all slaves is completed.

8. A fault self-diagnosis and isolation system for a ring network communication system, characterized in that, The fault self-diagnosis and isolation method for the ring network communication system as described in any one of claims 1 to 7 includes a master unit and multiple slave units, wherein the master unit has two built-in double-pole control switches and each slave unit has one built-in double-pole control switch; wherein the master unit includes: Main processor; The first RS485 interface chip is controlled by the UART first interface of the main processor. Its output A terminal is serially connected to a first resettable fuse resistor PT1, and its output B terminal is serially connected to a second resettable fuse resistor PT2. The output A terminal and output B terminal of the first RS485 interface chip form an external RS485 port 1 after passing through the first double-pole control switch QK1. The second RS485 interface chip is controlled by the UART second interface of the main processor. Its output A terminal is serially connected to a third resettable fuse resistor PT3, and its output B terminal is serially connected to a fourth resettable fuse resistor PT4. The output A terminal and output B terminal of the second RS485 interface chip form an external RS485 port 2 after passing through the second double-pole control switch QK2. The RS485 port 1 and the RS485 port 2 are respectively connected to one side and the other side of the ring bus. The load resistor RL is connected in parallel at the connection points of the two resettable fuse resistors and the double control switch corresponding to the RS485 interface chip; the first double control switch QK1 and the second double control switch QK2 are controlled by the main processor. Multiple slave devices are serially connected end-to-end between the first communication port (RS485 port 1) and the second communication port (RS485 port 2) of the host via a ring bus. The slave devices include: From the processor; The first RS485 interface chip is controlled by the UART first interface of the slave processor. Its output A terminal is serially connected to a first resettable fuse resistor PT1 to form an external electrical interface A1, and its output B terminal is serially connected to a second resettable fuse resistor PT2 to form an external electrical interface B1. The second RS485 interface chip is controlled by the UART second interface of the slave processor. Its output A terminal is serially connected to a third resettable fuse resistor PT3 to form an external electrical interface A2, and its output B terminal is serially connected to a fourth resettable fuse resistor PT4 to form an external electrical interface B2. The dual-pole control switch QK inside the slave unit is controlled by the slave processor and is used to connect two external communication interfaces, so that A1 and A2, B1 and B2 are connected internally in the circuit. The dual-pole control switch QK is in the off state by default when powered on, so that the bus segments on both sides of the slave unit are isolated from each other. During normal operation, it is in the on state, so that the slave unit is electrically connected in parallel to the ring bus, and the two RS485 interface chips of each slave unit are connected to the bus.

9. The fault self-diagnosis and isolation system for a ring network communication system according to claim 8, characterized in that, The fault self-diagnosis and isolation system also includes: Pull-up resistors, wherein the first pull-up resistor R1 in the master and slave devices is electrically connected to the output A terminal of the first RS485 interface chip in the master and slave devices respectively, and the second pull-up resistor R3 in the master and slave devices is electrically connected to the output A terminal of the second RS485 interface chip in the master and slave devices respectively; Pull-down resistors, wherein the first pull-down resistor R2 in the master and slave devices is electrically connected to the output B terminal of the first RS485 interface chip of the master and slave devices respectively, and the second pull-down resistor R4 in the master and slave devices is electrically connected to the output B terminal of the second RS485 interface chip of the master and slave devices respectively.

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