Bonded wafer and method of making the same

Abstract

This invention provides a bonding wafer and its fabrication method. The bonding wafer fabrication method includes: providing a support substrate, wherein a first oxide layer and a second oxide layer are respectively formed on two opposing surfaces of the support substrate; forming a protective layer on the surface of the first oxide layer, the protective layer covering the first oxide layer; providing a device substrate, wherein a buried oxide layer is formed on the surface of the device substrate; bonding the support substrate and the device substrate, with the second oxide layer facing the buried oxide layer; performing a lift-off process to remove a portion of the device substrate, such that the remaining device substrate, support substrate, first oxide layer, and second oxide layer constitute the bonding wafer; and performing a cleaning process and a heat treatment process on the bonding wafer using the protective layer as a mask. Because the surface of the first oxide layer is covered by the protective layer, the first oxide layer is protected, thereby preventing a reduction in the thickness of the first oxide layer and avoiding any impact on the warpage of the bonding wafer due to a reduction in the thickness of the first oxide layer.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a bonding wafer and its fabrication method. Background Technology

[0002] Silicon-on-Insulator (SOI) is a core material architecture for photonic integrated circuits, playing a crucial role in integrated optical systems. This structure consists of three layers: a top layer of single-crystal silicon film, used to construct core photonic components such as optical waveguides, modulators, and photodetectors; a middle layer of buried silicon dioxide (BOX), which provides both electrical insulation and optical isolation, effectively blocking light signal leakage to the substrate; and a bottom layer of silicon substrate, providing necessary mechanical support. This high refractive index difference design enables highly localized propagation of light energy in submicron-scale silicon waveguides, thus driving the miniaturization and high-density integration of photonic devices. However, in current manufacturing processes, SOI wafers typically employ back-side thinning or implantation lift-off techniques. In actual production, nanometer-level precision control is required for key processes such as photolithography, etching, deposition, and bonding. Among these, wafer warp is a core indicator affecting the quality of large-size wafers. However, after multilayer thin film deposition or high-temperature processes, uneven thermal stress can easily lead to overall deformation. Excessive warpage not only threatens the safety of automated transmission systems but may also cause the photolithography process to exceed the depth of field, resulting in pattern defocusing and increased overlay errors. This, in turn, leads to waveguide size deviations and mode mismatches, severely affecting optical performance. Furthermore, warpage can also cause problems such as poor local contact, uneven film thickness, or interface delamination, directly restricting production yield.

[0003] Currently, providing an oxide layer on the back side can effectively suppress the warpage degradation caused by SOI structures. However, this also means that silicon photonics SOI processes are not compatible with conventional SOI processes, especially in the cleaning process. The back side of SOI wafers with a back oxide layer should be kept away from acidic cleaning solutions (such as hydrofluoric acid) as much as possible, otherwise there is a risk of particle shedding and warpage degradation. Summary of the Invention

[0004] The purpose of this invention is to provide a bonding wafer and a method for preparing the same, so as to improve the warpage of the bonding wafer.

[0005] To achieve the above objectives, the present invention provides a method for preparing a bonding wafer, comprising:

[0006] A support substrate is provided, wherein a first oxide layer and a second oxide layer are respectively formed on two opposing surfaces of the support substrate;

[0007] A protective layer is formed on the surface of the first oxide layer, the protective layer covering the first oxide layer;

[0008] A device substrate is provided, wherein a buried oxide layer is formed on the surface of the device substrate;

[0009] The supporting substrate is bonded to the device substrate, with the second oxide layer facing the buried oxide layer;

[0010] A stripping process is performed to remove a portion of the device substrate, leaving the remaining device substrate, the support substrate, the first oxide layer, the second oxide layer, and the buried oxide layer to form a bonding wafer.

[0011] Using the protective layer as a mask, a cleaning process and a heat treatment process are performed on the bonding wafer.

[0012] Optionally, in the method for fabricating the bonded wafer, the material of the protective layer is Si. x N y The ratio of x to y is 0.7 to 0.9.

[0013] Optionally, in the method for preparing the bonding wafer, the gases used when forming the protective layer include SiH4 and NH3, and the ratio of the gas flow rate of SiH4 to the gas flow rate of NH3 is 1:3.5 to 1:6.

[0014] Optionally, in the method for fabricating the bonded wafer, the temperature during the formation of the protective layer is 350℃~400℃, the gas pressure is 530 Pa~1060 Pa, and the RF power density is 1.2 W / cm². 2 ~1.8W / cm 2 .

[0015] Optionally, in the method for preparing the bonded wafer, the gas flow rate of SiH4 is 50 sccm to 80 sccm, and the gas flow rate of NH3 is 250 sccm to 350 sccm.

[0016] Optionally, in the method for preparing the bonded wafer, the thickness of the protective layer is 50 nm to 150 nm.

[0017] Optionally, in the method for preparing the bonding wafer, after performing the heat treatment process, the method further includes:

[0018] An etching process is performed on the bonding wafer to remove the protective layer.

[0019] Optionally, in the method for preparing the bonding wafer, the etching process uses hot phosphoric acid with a concentration of 60% to 85%, a temperature of 155°C to 165°C, and a spraying time of 3 to 5 minutes.

[0020] Optionally, in the method for preparing the bonded wafer, the temperature of the heat treatment process is 800℃~950℃.

[0021] Based on the same inventive concept, the present invention also provides a bonding wafer, comprising:

[0022] A bonding wafer is formed using the bonding wafer fabrication method described above. The thickness of the first oxide layer in the bonding wafer is 1000 nm to 4500 nm, the warpage of the bonding wafer is less than or equal to 13.8 μm, and the number of particles with a diameter greater than 90 nm on the surface of the bonding wafer is less than 32.

[0023] The method for fabricating a bonding wafer provided by this invention includes: providing a support substrate, wherein a first oxide layer and a second oxide layer are respectively formed on two opposing surfaces of the support substrate; forming a protective layer on the surface of the first oxide layer, the protective layer covering the first oxide layer; providing a device substrate, wherein a buried oxide layer is formed on the surface of the device substrate; bonding the support substrate and the device substrate, with the second oxide layer facing the buried oxide layer; performing a peeling process to peel off a portion of the device substrate, such that the remaining device substrate, support substrate, first oxide layer, and second oxide layer constitute a bonding wafer; and performing a cleaning process and a heat treatment process on the bonding wafer using the protective layer as a mask. Because the surface of the first oxide layer is covered by the protective layer, the protective layer can protect the first oxide layer during the cleaning and heat treatment processes, preventing damage to the first oxide layer and thus preventing a reduction in the thickness of the first oxide layer. This prevents the reduction in the thickness of the first oxide layer from affecting the warpage of the bonding wafer, thereby improving the warpage of the bonding wafer and mitigating the problem of first oxide layer particles falling off due to high temperatures during the heat treatment process. Attached Figure Description

[0024] Figure 1 This is a schematic flowchart of the bonding wafer fabrication method provided in an embodiment of the present invention.

[0025] Figures 2 to 7 This is a schematic diagram of the structure formed in the bonding wafer preparation method provided in the embodiments of the present invention.

[0026] Figure 8 This is a schematic diagram of the particles on the surface of the bonded wafer before performing the planarization process in Embodiment 1 of the bonding wafer fabrication method provided by the present invention.

[0027] Figure 9 This is a schematic diagram of the particles on the surface of the bonded wafer after the planarization process in Embodiment 1 of the bonding wafer fabrication method provided by the present invention.

[0028] Figure 10This is a schematic diagram of the particles on the surface of the bonded wafer before the planarization process, in a comparative example of the bonding wafer fabrication method provided in this embodiment of the invention.

[0029] Figure 11 This is a schematic diagram of the particles on the surface of the bonded wafer after the planarization process, in a comparative example of the bonding wafer fabrication method provided in this embodiment of the invention.

[0030] Figure 12 This is a schematic diagram of the particles on the surface of the bonded wafer before the planarization process in Comparative Example 2 of the bonding wafer fabrication method provided in this embodiment of the invention.

[0031] Figure 13 This is a schematic diagram of the particles on the surface of the bonded wafer after the planarization process in Comparative Example 2 of the bonding wafer fabrication method provided in this embodiment of the invention.

[0032] The reference numerals in the attached figures are explained as follows:

[0033] 100 - Bonded wafer; 110 - Supporting substrate; 111 - First oxide layer; 112 - Second oxide layer; 113 - Protective layer; 120 - Device substrate; 121 - Buried oxide layer; 122 - Ion implantation layer. Detailed Implementation

[0034] The bonding wafer and its fabrication method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0035] Figure 1 This is a schematic flowchart of the bonding wafer fabrication method provided in an embodiment of the present invention. Figure 1 The method for preparing the bonding wafer provided in this embodiment includes:

[0036] Step S1: Provide a support substrate, wherein a first oxide layer and a second oxide layer are respectively formed on two opposing surfaces of the support substrate;

[0037] Step S2: A protective layer is formed on the surface of the first oxide layer, the protective layer covering the first oxide layer;

[0038] Step S3: Provide a device substrate, wherein a buried oxide layer is formed on the surface of the device substrate;

[0039] Step S4: Bond the support substrate to the device substrate, with the second oxide layer facing the buried oxide layer;

[0040] Step S5: Perform a stripping process to remove a portion of the device substrate, leaving the remaining device substrate, the support substrate, the first oxide layer, and the second oxide layer to form a bonding wafer;

[0041] Step S6: Using the protective layer as a mask, perform cleaning and heat treatment processes on the bonding wafer.

[0042] The method for preparing the bonding wafer provided in this embodiment will be described in more detail below with reference to the accompanying drawings.

[0043] First, such as Figure 2 As shown, in step S1, a support substrate 110 is provided. A first oxide layer 111 and a second oxide layer 112 are formed on two opposing surfaces of the support substrate 110. Specifically, the support substrate 110 can be a silicon substrate. The first oxide layer 111 and the second oxide layer 112 can be formed by a thermal oxidation process at an oxidation temperature of 800℃~1000℃, for example, 900℃ or 950℃. The thickness of both the first oxide layer 111 and the second oxide layer 112 can be 1000nm~4500nm.

[0044] Then, proceed with step S2, as follows: Figure 3 As shown, a protective layer 113 is formed on the surface of the first oxide layer 111. The protective layer 113 covers the first oxide layer 111, that is, the protective layer 113 is located on the surface of the first oxide layer 111. The protective layer 113 can protect the first oxide layer 111 in the subsequent cleaning process, avoid damage to the first oxide layer 111, thereby avoiding a reduction in the thickness of the first oxide layer 111, and can improve the warpage of the bonded wafer 100.

[0045] In this embodiment, the material of the protective layer 113 is Si. x N y The ratio of x to y is 0.7 to 0.9, which means that the ratio of silicon atoms to nitrogen atoms is 0.7 to 0.9, for example, 0.8. In this way, the cleaning solution can be prevented from etching the first oxide layer 111 in the subsequent cleaning process.

[0046] It should be noted that if the ratio of silicon to nitrogen atoms is small, for example, less than 0.7, it is more likely to cause problems in subsequent cleaning and etching processes. Therefore, in this embodiment, the ratio of silicon to nitrogen atoms (i.e., the ratio of x to y) is 0.7 to 0.9. Furthermore, the presence of the nitrogen-containing protective layer itself can generate stress on the silicon wafer, leading to deterioration and warping. This application strictly controls the number of nitrogen atoms to minimize warping caused by the protective layer. Based on this, it ensures the thickness of the first oxide layer and avoids deterioration, warping, and surface particle shedding caused by subsequent high-temperature processes. Therefore, the number of nitrogen atoms is crucial in this process.

[0047] Specifically, when forming the protective layer 113, the gases used include SiH4, NH3 and N2, wherein N2 is used as a carrier gas, and the gas flow rate of SiH4 to the gas flow rate of NH3 is 1:3.5 to 1:6.

[0048] For example, the SiH4 gas flow rate can be 50 sccm to 80 sccm, such as 60 sccm or 70 sccm; the NH3 gas flow rate can be 250 sccm to 350 sccm, such as 280 sccm, 290 sccm or 300 sccm; and the N2 gas flow rate can be 1500 sccm to 3000 sccm, such as 2000 sccm, 2500 sccm or 2800 sccm.

[0049] In this embodiment, the protective layer 113 can be formed using a plasma-enhanced chemical vapor deposition (PECVD) process. During the formation of the protective layer 113, the temperature can be 350°C to 400°C, for example, 350°C; the gas pressure can be 530 Pa to 1060 Pa; and the RF power density can be 1.2 W / cm². 2 ~1.8W / cm 2 .

[0050] In this embodiment, the thickness of the protective layer 113 can be 50 nm to 150 nm, for example, 100 nm, 110 nm, 120 nm or 130 nm.

[0051] Next, as Figure 4 As shown, in step S3, a device substrate 120 is provided, and a buried oxide layer 121 is formed on the surface of the device substrate 120. Specifically, the device substrate 120 can be a silicon substrate, and the buried oxide layer 121 is formed by a thermal oxidation process or a PECVD process. The thickness of the buried oxide layer 121 can be 20 nm to 500 nm.

[0052] After that, as Figure 5As shown, an ion implantation process is performed along the surface of the buried oxide layer 121 to form an ion implantation layer 122 in the device substrate 120.

[0053] In this embodiment, the ion implantation process uses hydrogen ions, or a combination of hydrogen and helium ions. The implantation energy for hydrogen ions is 30 keV to 70 keV, and the implantation energy for helium ions is 50 keV to 80 keV. The dose is 1E16cm. -2 ~6E16cm -2 .

[0054] Next, as Figure 5 As shown, in step S4, the support substrate 110 is bonded to the device substrate 120, with the second oxide layer 112 facing the buried oxide layer 121. The bonding method can be vacuum bonding or atmospheric pressure bonding.

[0055] Subsequently, plasma activation treatment is performed on the surfaces of the device substrate 120 and the support substrate 110, respectively. The plasma source used for plasma activation treatment can be Ar or O2.

[0056] Next, as Figure 6 As shown, a stripping process is performed to strip a portion of the thickness of the device substrate 120 along the ion implantation layer 122, such that the remaining device substrate 120, the support substrate 110, the first oxide layer 111, the second oxide layer 112, and the buried oxide layer 121 constitute a bonding wafer 100.

[0057] During the lift-off process, the Si-H bonds formed by hydrogen ion implantation in the ion-implanted layer 122 break. The broken H atoms diffuse and accumulate in the device substrate 120, forming hydrogen molecules (H2) and creating tiny gas cavities within the substrate 120. As the pressure inside these gas cavities continues to increase, when the pressure exceeds the local strength threshold of the device substrate 120, delamination is triggered, forming a potential lift-off interface. Simultaneously, helium ions are distributed as interstitial sites in the silicon lattice of the device substrate 120. Due to the low migration energy of helium atoms, they can migrate and form clusters even at low temperatures, promoting the nucleation and growth of hydrogen bubbles, resulting in a more uniform lift-off interface and thus reducing surface roughness.

[0058] In this embodiment, the stripping process is a low-temperature stripping process, which can be achieved through a furnace tube process. The temperature of the stripping process can be 300℃~500℃, for example, 350℃ or 400℃, and the time can be 3 minutes to 20 minutes.

[0059] After the stripping process is performed, the remaining device substrate 120 has a thickness of 400nm to 600nm, for example, 450nm or 500nm.

[0060] Next, step S6 is executed, using the protective layer 113 as a mask to perform a cleaning process and a heat treatment process on the bonding wafer 100. Specifically, the protective layer 113 can be used as a mask to first perform a cleaning process on the bonding wafer 100, and then perform a heat treatment process; or, a heat treatment process can be performed first, and then a cleaning process; or, two cleaning processes can be performed first, and then a heat treatment process can be performed; or, a heat treatment process can be performed between two cleaning processes.

[0061] Specifically, a standard cleaning process can be performed on the bonding wafer 100 to remove residual silicon shavings on the surface of the bonding wafer 100. Due to the presence of the protective layer 113, the first oxide layer 111 can be protected, thereby avoiding damage to the first oxide layer 111 during the cleaning process and thus preventing a reduction in the thickness of the first oxide layer 111.

[0062] Then, a heat treatment process is performed on the bonding wafer 100 to strengthen the bonding between the device substrate 120 and the support substrate 110. Specifically, the wafer is transferred into a reactor for a heat treatment process at a temperature of 800°C to 950°C in an atmosphere of O2 or a mixture of O2 and H2O. During the heat treatment process, the presence of the protective layer 113 protects the first oxide layer 111, thereby preventing a reduction in the thickness of the first oxide layer 111. This, in turn, avoids changes in the warpage of the bonding wafer 100 caused by a reduction in the thickness of the first oxide layer 111, improves the warpage of the bonding wafer 100, and mitigates the problem of particles of the first oxide layer 111 falling off due to high temperatures during the heat treatment process.

[0063] Next, the bonded wafer 100 is cleaned using an acid pickling process to remove the surface oxide layer formed on the bonded wafer 100 during the heat treatment process. The cleaning solution used can be a 10% volume concentration hydrofluoric acid solution.

[0064] After performing the heat treatment process, a planarization process is performed on the bonding wafer 100. The planarization process can be at least one of rapid thermal annealing, argon thermal annealing, and hydrogen-argon mixed gas annealing. Specifically, the annealing temperature can be 1100℃~1200℃, the annealing time can be 30min~40min, and the atmosphere can be Ar. During this process, the first protective layer 113 can protect the first oxide layer and prevent the particles of the first oxide layer 111 from falling off due to high temperature during the planarization process.

[0065] After that, as Figure 7As shown, an etching process is performed on the bonding wafer 100 to remove the protective layer 113. The etching process uses hot phosphoric acid with a concentration of 60%~85%, a temperature of 155℃~165℃, and a spraying time of 3min~5min.

[0066] It should be noted that the presence of the protective layer 113 will generate stress, which may affect the warpage of the bonding wafer 100 and cause the warpage of the bonding wafer 100 to deteriorate. Therefore, in this embodiment, after performing the planarization process, the protective layer 113 is removed, thereby effectively protecting the balancing effect of the second oxide layer 112 on the warpage of the bonding wafer 100 on the surface of the device substrate 120.

[0067] The following provides an embodiment and two comparative examples to further illustrate the effectiveness of the bonding wafer fabrication method provided in this embodiment.

[0068] Table 1 Comparison of the Embodiments and the Comparative Examples

[0069]

[0070] Example 1, as Figure 2 As shown, a support substrate 110 is provided, and a first oxide layer 111 and a second oxide layer 112 are respectively formed on two opposing surfaces of the support substrate 110; wherein, the oxidation temperature of the first oxide layer 111 and the second oxide layer 112 is 900℃, and the oxidation thickness is 1700nm; Figure 3 As shown, a protective layer 113 is formed on the surface of the first oxide layer 111, and the protective layer 113 covers the first oxide layer 111; wherein, the material of the protective layer 113 is Si. x N y The ratio of x to y is 0.8; Specifically, during the formation of protective layer 113, the SiH4 gas flow rate is 60 sccm, the NH3 gas flow rate is 240 sccm, the N2 carrier gas flow rate is 3000 sccm, the deposition temperature is 400℃, the gas pressure is 1000 Pa, and the RF power density is 1.65 W / cm². 2 .

[0071] Next, as Figure 4 As shown, a device substrate 120 is provided, on the surface of which a buried oxide layer 121 is formed. Further, an ion implantation layer 122 is formed in the device substrate 120. The ion implantation layer 122 is formed by an ion implantation process using hydrogen and helium ions. The hydrogen ion implantation energy is 60 keV, and the dose is 1E16cm⁻¹. -2 The helium ion implantation energy was 60 keV, and the dose was 1E16cm. -2 ; then, as Figure 5As shown, the support substrate 110 is bonded to the device substrate 120, and the second oxide layer 112 faces the buried oxide layer 121.

[0072] Next, as Figure 6 As shown, a stripping process is performed to remove a portion of the device substrate 120, leaving the remaining device substrate 120, the support substrate 110, the first oxide layer 111, the second oxide layer 112, and the buried oxide layer 121 forming a bonding wafer 100. During the stripping process, a portion of the device substrate 120 is stripped along the ion implantation layer 122. Using the protective layer 113 as a mask, a cleaning process and a heat treatment process are performed on the bonding wafer 100. The heat treatment process is performed at a temperature of 900°C in a mixed atmosphere of O2 and H2O. Afterwards, a planarization process is performed on the bonding wafer; then, as... Figure 7 As shown, an etching process is performed on the bonding wafer to remove the protective layer.

[0073] As shown in Table 1 above, in Example 1, the thickness of the first oxide layer 111 is 19998.6 angstroms, and the warpage (BOW) of the bonded wafer 100 is 13.8 μm. Figure 8 and Figure 9 As shown, before the planarization process, the number of particles with a surface diameter greater than 90 nm on the bonding wafer 100 was 25, and after the planarization process, the number of particles with a surface diameter greater than 90 nm on the bonding wafer 100 was 32.

[0074] Comparative Example 1, such as Figure 2 As shown, a support substrate 110 is provided, and a first oxide layer 111 and a second oxide layer 112 are formed on two opposing surfaces of the support substrate 110, respectively; wherein the oxidation temperature of the first oxide layer 111 and the second oxide layer 112 is 900°C and the oxide thickness is 1700 nm; then, a device substrate 120 is provided, and a buried oxide layer 121 is formed on the surface of the device substrate 120. The thickness of the buried oxide layer 121 is 300 nm. Next, the support substrate 110 and the device substrate 120 are bonded, with the second oxide layer 112 facing the buried oxide layer 121; then, a stripping process is performed to remove a portion of the device substrate 120, such that the remaining device substrate 120, the support substrate 110, the first oxide layer 111, and the second oxide layer 112 constitute a bonded wafer 100. Using the protective layer 113 as a mask, a cleaning process and a heat treatment process are performed on the bonded wafer 100. The cleaning process uses a 10% (by volume) hydrofluoric acid solution, the heat treatment temperature is 900°C, and the atmosphere is a mixture of O2 and H2O. Afterwards, a planarization process is performed on the bonded wafer.

[0075] As shown in Table 1 above, in Comparative Example 1, the thickness of the first oxide layer 111 is 19956.8 angstroms, and the warpage (BOW) of the bonded wafer 100 is 30.63 μm. Figure 10 and Figure 11 As shown, before the planarization process, the number of particles with a diameter greater than 90 nm on the surface of the bonding wafer 100 was 17, and after the planarization process, the number of particles with a diameter greater than 90 nm on the surface of the bonding wafer 100 was 465.

[0076] Comparative Example 2 provides a support substrate 110, on which two opposing surfaces are formed a first oxide layer 111 and a second oxide layer 112, respectively; wherein the oxidation temperature of the first oxide layer 111 and the second oxide layer 112 is 900℃ and the oxidation thickness is 1700nm; a protective layer 113 is formed on the surface of the first oxide layer 111, the protective layer 113 covering the first oxide layer 111; wherein the material of the protective layer 113 is Si. x N y The ratio of x to y is 0.6; the SiH4 gas flow rate is 60 sccm, the NH3 gas flow rate is 350 sccm, the N2 carrier gas flow rate is 3000 sccm, the deposition temperature is 400℃, the gas pressure is 1000 Pa, and the RF power density is 1.65 W / cm². 2 .

[0077] Next, a device substrate 120 is provided, on the surface of which a buried oxide layer 121 is formed. Further, an ion implantation layer 122 is formed in the device substrate 120. The ion implantation layer 122 is formed by an ion implantation process using hydrogen and helium ions. The hydrogen ion implantation energy is 60 keV, and the dose is 1E16cm. -2 The helium ion implantation energy was 60 keV, and the dose was 1E16cm. -2 Next, the support substrate 110 is bonded to the device substrate 120, with the second oxide layer 112 facing the buried oxide layer 121. Then, a stripping process is performed to remove a portion of the device substrate 120, leaving the remaining device substrate 120, support substrate 110, first oxide layer 111, second oxide layer 112, and buried oxide layer 121 forming a bonded wafer 100. During the stripping process, a portion of the device substrate 120 is stripped along the ion implantation layer 122. Using the protective layer 113 as a mask, a cleaning process and a heat treatment process are performed on the bonded wafer 100. The heat treatment process temperature is 900°C, and the atmosphere is a mixture of O2 and H2O. Afterward, a planarization process is performed on the bonded wafer; then, as... Figure 7 As shown, an etching process is performed on the bonding wafer to remove the protective layer.

[0078] As shown in Table 1 above, in Comparative Example 2, the thickness of the first oxide layer 111 is 19975.3 angstroms, and the warpage (BOW) of the bonded wafer 100 is 20.64 μm. Figure 12 and Figure 13 As shown, before the planarization process, the number of particles with a diameter greater than 90 nm on the surface of the bonding wafer 100 was 20, and after the planarization process, the number of particles with a diameter greater than 90 nm on the surface of the bonding wafer 100 was 467.

[0079] Comparing the above embodiment with the two comparative examples, it can be seen that, using the bonding wafer fabrication method provided in this embodiment (Embodiment 1), after performing the planarization process, the warpage of the bonding wafer 100 is less than or equal to 13.8 μm, and the number of particles with a surface diameter greater than 90 nm on the bonding wafer 100 is less than or equal to 32. Therefore, the bonding wafer 100 fabrication method provided in this embodiment avoids damage to the first oxide layer 111, thereby avoiding a reduction in the thickness of the first oxide layer 111, which can improve the warpage of the bonding wafer 100 and improve the problem of particle shedding of the first oxide layer 111 caused by high temperature during the heat treatment process.

[0080] like Figure 7 As shown, this embodiment also provides a bonding wafer, which is formed using the bonding wafer preparation method provided in this embodiment. The thickness of the first oxide layer 111 in the bonding wafer 100 is 1000nm~4500nm, the warpage of the bonding wafer is less than or equal to 13.8μm, and the number of particles with a diameter greater than 90nm on the surface of the bonding wafer 100 is less than or equal to 32.

[0081] In this embodiment, the bonding wafer can be a silicon-on-insulator (SOI) structure.

[0082] In summary, the bonding wafer and its fabrication method provided by this invention include the following steps: providing a support substrate, wherein a first oxide layer and a second oxide layer are formed on two opposing surfaces of the support substrate; forming a protective layer on the surface of the first oxide layer, the protective layer covering the first oxide layer; providing a device substrate, wherein a buried oxide layer is formed on the surface of the device substrate; bonding the support substrate and the device substrate together, with the second oxide layer facing the buried oxide layer; performing a peeling process to peel off a portion of the device substrate, such that the remaining device substrate, support substrate, first oxide layer, and second oxide layer constitute the bonding wafer. Using the protective layer as a mask, a cleaning process and a heat treatment process are performed on the bonding wafer. Because the surface of the first oxide layer is covered by the protective layer, the protective layer can protect the first oxide layer during the cleaning and heat treatment processes, preventing damage to the first oxide layer and thus preventing a reduction in the thickness of the first oxide layer. This prevents the reduction in the thickness of the first oxide layer from affecting the warpage of the bonding wafer, thereby improving the problem of particle shedding of the first oxide layer due to high temperature during the heat treatment process.

[0083] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0084] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for preparing a bonding wafer, characterized in that, include: A support substrate is provided, wherein a first oxide layer and a second oxide layer are respectively formed on two opposing surfaces of the support substrate; A protective layer is formed on the surface of the first oxide layer, the protective layer covering the first oxide layer; A device substrate is provided, wherein a buried oxide layer is formed on the surface of the device substrate; The supporting substrate is bonded to the device substrate, with the second oxide layer facing the buried oxide layer; A stripping process is performed to remove a portion of the device substrate, leaving the remaining device substrate, the support substrate, the first oxide layer, the second oxide layer, and the buried oxide layer to form a bonding wafer. Using the protective layer as a mask, a cleaning process and a heat treatment process are performed on the bonding wafer.

2. The method for preparing a bonding wafer as described in claim 1, characterized in that, The protective layer is made of Si. x N y The ratio of x to y is 0.7 to 0.

9.

3. The method for preparing a bonding wafer as described in claim 1, characterized in that, When forming the protective layer, the gases used include SiH4 and NH3, and the ratio of the gas flow rate of SiH4 to the gas flow rate of NH3 is 1:3.5 to 1:

6.

4. The method for preparing a bonding wafer as described in claim 3, characterized in that, The protective layer is formed at a temperature of 350°C to 400°C, an air pressure of 530 Pa to 1060 Pa, and an RF power density of 1.2 W / cm². 2 ~1.8W / cm 2 .

5. The method for preparing a bonding wafer as described in claim 3, characterized in that, The gas flow rate of SiH4 is 50 sccm to 80 sccm, and the gas flow rate of NH3 is 250 sccm to 350 sccm.

6. The method for preparing a bonding wafer as described in claim 1, characterized in that, The thickness of the protective layer is 50 nm to 150 nm.

7. The method for preparing a bonding wafer as described in claim 1, characterized in that, After performing the heat treatment process, the process further includes: An etching process is performed on the bonding wafer to remove the protective layer.

8. The method for preparing a bonding wafer as described in claim 7, characterized in that, The etching process uses hot phosphoric acid with a concentration of 60% to 85%, a temperature of 155°C to 165°C, and a spraying time of 3 to 5 minutes.

9. The method for preparing a bonding wafer as described in claim 1, characterized in that, The temperature of the heat treatment process is 800℃~950℃.

10. A bonding wafer, characterized in that, include: A bonding wafer is formed using the bonding wafer fabrication method described in any one of claims 1 to 9, wherein the thickness of the first oxide layer in the bonding wafer is 1000 nm to 4500 nm, the warpage of the bonding wafer is less than or equal to 13.8 μm, and the number of particles with a diameter greater than 90 nm on the surface of the bonding wafer is less than or equal to 32.

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