Method for predicting fundamental thermal cycle amplitude of vehicle-mounted rectifier based on low heat capacity characteristic of si c device

Abstract

The application discloses a vehicle-mounted rectifier fundamental frequency thermal cycle amplitude prediction method based on SiC device low heat capacity characteristics, and relates to the technical field of power electronic thermal management. The method obtains device characteristic parameters, transient thermal impedance discrete data and operation condition parameters of an SiC power module; multi-order thermal network parameters are fitted based on the transient thermal impedance discrete data, and are decoupled into a chip heat capacity dominant section parameter subset and a package thermal resistance dominant section parameter subset in the time scale; frequency domain response verification is performed on the chip section according to a target fundamental frequency, and an effective participating order set is determined; a power pulsation amplitude corresponding to the frequency is extracted, a frequency domain transfer function is constructed in combination with the effective participating order set, a junction temperature fluctuation amplitude is calculated, and output is performed. The application completes physical layer decoupling by using inherent time constant gaps of the device, cooperates with frequency domain contribution rate adaptive verification, reduces unified thermal network order reduction error, and improves the prediction precision of the fundamental frequency thermal cycle amplitude under multiple working conditions.

Description

Technical Field

[0001] This invention relates to the field of thermal management and reliability assessment technology for power electronic devices, and in particular to a method for predicting the fundamental frequency thermal cycling amplitude of an on-board rectifier based on the low thermal capacity characteristics of SiC devices. Background Technology

[0002] In the electric drive systems of new energy vehicles, silicon carbide (SiC) power devices are widely used in key power conversion equipment such as on-board rectifiers due to their high voltage resistance and high-frequency switching characteristics. During actual vehicle operation, frequent acceleration and deceleration, as well as sudden load changes, subject the power devices to high-frequency pulsating thermal stress. This type of periodic temperature fluctuation, closely related to the fundamental frequency of the motor operation—known as fundamental frequency thermal cycling—is a major factor leading to fatigue degradation and failure of the device packaging materials.

[0003] Currently, for predicting transient junction temperatures of power devices, the industry typically employs a unified RC thermal network model based on one-dimensional heat conduction theory, such as the Foster or Cauer model. This involves constructing an equivalent circuit composed of multiple thermal resistances and capacitive values ​​by performing multi-order exponential fitting on the transient thermal impedance test curves of the device's junction-case. In practical engineering, the instantaneous power loss waveform during rectifier operation is usually used as the input excitation for the unified thermal network, and the dynamic response curve of the device's junction temperature is calculated using time-domain convolution or frequency-domain transfer functions. However, existing methods fail to effectively isolate the thermal dynamic response scales spanning multiple orders of magnitude within wide-bandgap semiconductor devices with high switching frequencies and thin chip structures. When evaluating the steady-state fluctuation amplitude of millisecond-level high-frequency thermal excitation, uncontrollable phase distortion and amplitude attenuation errors are easily introduced. Summary of the Invention

[0004] Purpose of the invention: To provide a method for predicting the fundamental frequency thermal cycling amplitude of an on-board rectifier based on the low thermal capacity characteristics of SiC devices, in order to solve the above-mentioned technical problems.

[0005] Technical solution: A method for predicting the fundamental frequency thermal cycling amplitude of an on-board rectifier based on the low thermal capacity characteristics of SiC devices, comprising:

[0006] Obtain the device characteristic parameters, transient thermal impedance discrete data, and operating condition parameters of the vehicle rectifier for the SiC power module, including the target fundamental frequency.

[0007] Based on the transient thermal impedance discrete data, the parameters of the multi-order thermal network are fitted and decoupled on the time scale. They are divided into a chip thermal capacity-dominated parameter subset that characterizes the internal heat transfer process of the chip and a package thermal resistance-dominated parameter subset that characterizes the heat transfer process of the package layer.

[0008] Based on the target fundamental frequency, frequency domain response verification is performed on the decoupled subset to determine the effective set of participating orders for fundamental frequency thermal cycling calculation.

[0009] Based on the operating condition parameters and device characteristic parameters, the power pulsation amplitude corresponding to the target fundamental frequency is extracted. The frequency domain transfer function is constructed by combining the effective participation order set, the junction temperature fluctuation amplitude is calculated, and the result is output as the prediction result of the fundamental frequency thermal cycling amplitude of the vehicle rectifier.

[0010] According to one aspect of this application, extracting the power ripple amplitude at a corresponding frequency based on operating condition parameters includes:

[0011] The instantaneous power loss waveform of the power module during the fundamental frequency period is calculated based on the operating condition parameters.

[0012] A frequency domain transformation is performed on the instantaneous power loss waveform, and the magnitude of the complex coefficients corresponding to the fundamental frequency is extracted as the fundamental frequency power pulsation amplitude, and the magnitude of the complex coefficients corresponding to the second harmonic is extracted as the second harmonic power pulsation amplitude.

[0013] According to one aspect of this application, the parameters of a multi-order thermal network are decoupled over a time scale, and a subset of parameters dominated by chip thermal capacity and a subset of parameters dominated by package thermal resistance are divided, including:

[0014] Extract the time constant sequence and thermal resistance sequence of each order from the parameters of the multi-order thermal network;

[0015] The boundary time constant is determined based on the distribution characteristics of the time constant sequences of each order;

[0016] Parameters with time constants less than the boundary time constant are assigned to the chip thermal capacity-dominated parameter subset, while parameters with time constants greater than the boundary time constant are assigned to the package thermal resistance-dominated parameter subset.

[0017] According to one aspect of this application, the boundary time constant is determined based on the distribution characteristics of time constant sequences of each order, including:

[0018] Arrange the time constant sequences of each order in ascending order of their numerical values;

[0019] Calculate the logarithmic ratio of the ratios of adjacent time constants after arrangement to obtain the logarithmic gap ratio sequence;

[0020] The position corresponding to the maximum value in the logarithmic gap ratio sequence is determined as the boundary position;

[0021] The boundary time constant is obtained by calculating the geometric mean of the adjacent time constants on both sides of the boundary position.

[0022] According to one aspect of this application, the boundary time constant is determined based on the distribution characteristics of the time constant sequences of each order, specifically through the following method:

[0023] Obtain the pre-configured frequency domain participation threshold, where frequency domain participation characterizes the ratio of the thermal impedance amplitude of a single-order thermal network under AC operation to its DC thermal resistance.

[0024] Based on the frequency domain participation threshold, calculate the square root of the difference between the reciprocal of the square of the frequency domain participation threshold and one, and then divide it by twice pi to obtain the boundary coefficient.

[0025] The product of the dividing coefficient and the period corresponding to the target fundamental frequency is determined as the dividing time constant.

[0026] According to one aspect of this application, the chip thickness of the SiC power module is within a preset thickness range; and among the multi-order thermal network parameters, there is at least an order of magnitude gap between the minimum time constant belonging to the subset of parameters dominated by package thermal resistance and the maximum time constant belonging to the subset of parameters dominated by chip thermal capacity.

[0027] According to one aspect of this application, a frequency domain transfer function is constructed by combining the effective participation order set, and the junction temperature fluctuation amplitude is calculated, including:

[0028] A complex thermal impedance model is constructed based on the effective participation order set, and the thermal impedance amplitude corresponding to the target fundamental frequency is calculated.

[0029] The fundamental frequency junction temperature fluctuation amplitude is obtained by multiplying the power pulsation amplitude at the corresponding frequency with the thermal impedance amplitude.

[0030] According to one aspect of this application, the step of pre-constructing a multi-condition mapping table is also included:

[0031] Traverse the preset fundamental frequency range and extract multiple discrete frequency points;

[0032] Each discrete frequency point is taken as the target fundamental frequency. Based on the preset reference operating condition parameters, the steps of determining the effective participation order set and calculating the junction temperature fluctuation amplitude are performed to obtain the reference junction temperature fluctuation amplitude corresponding to each discrete frequency point.

[0033] By associating discrete frequency points with reference junction temperature fluctuation amplitudes, a pre-built frequency-temperature fluctuation amplitude mapping table is generated.

[0034] According to one aspect of this application, fitting multi-order thermal network parameters based on transient thermal impedance discrete data includes:

[0035] Set an initial fitting order, use the initial fitting order to perform curve fitting on the transient thermal impedance discrete data, and calculate the fitting residual;

[0036] Gradually increase the fitting order until the current fitting residual is less than the preset residual threshold. Then, determine the corresponding order as the target fitting order and output the multi-order thermal network parameters under the target fitting order.

[0037] According to one aspect of this application, after outputting the junction temperature fluctuation amplitude, the method further includes:

[0038] Input the junction temperature fluctuation amplitude into the pre-configured device lifetime assessment model to calculate the fatigue damage degree of the SiC power module;

[0039] And / or, when the junction temperature fluctuation amplitude exceeds the preset safety fluctuation threshold, the derating operation control strategy of the vehicle rectifier is triggered.

[0040] Beneficial effects: Physical layer decoupling is achieved by utilizing the inherent time constant gap of the device, and adaptive verification of the frequency domain contribution rate is combined to reduce the order reduction error of the unified thermal network and improve the prediction accuracy of the fundamental frequency thermal cycling amplitude under multiple operating conditions. Attached Figure Description

[0041] Figure 1 This is a flowchart of the method for predicting the fundamental frequency thermal cycling amplitude of an on-board rectifier based on the low thermal capacity characteristics of SiC devices, according to the present invention.

[0042] Figure 2 This is a flowchart illustrating the parameter subsets for dividing the chip thermal capacity-dominant segment and the package thermal resistance-dominant segment in this invention.

[0043] Figure 3 This is a flowchart of the first method for determining the boundary time constant according to the present invention.

[0044] Figure 4 This is a flowchart of the second method for determining the boundary time constant in this invention.

[0045] Figure 5 This is a flowchart of the pre-constructed multi-condition mapping table in this invention. Detailed Implementation

[0046] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first," "second," etc., in the specification and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein are implemented in a sequence other than those illustrated or described herein. Furthermore, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to the process, method, product, or apparatus.

[0048] As mentioned in the background section, when evaluating the steady-state fluctuation amplitude of millisecond-level high-frequency thermal excitation, uncontrollable phase distortion and amplitude attenuation errors are easily generated. The applicant's research also revealed that under the complex and variable electrical load frequencies of the automotive environment, it is difficult for the thermal network parameters of a fixed structure to maintain stable prediction accuracy across the entire operating range. In other words, when dealing with high-frequency thermal excitation with a wide timescale, existing power device thermodynamic prediction methods struggle to balance model simplification requirements with response accuracy under different frequency bands.

[0049] To solve these problems, combined with Figures 1 to 5 The present invention will be specifically described through the following embodiments.

[0050] Example 1

[0051] According to one aspect of this application, this embodiment provides a method for predicting the fundamental frequency thermal cycling amplitude of an automotive rectifier based on the low thermal capacity characteristics of SiC devices. The method includes the following steps:

[0052] Step 101: Obtain the device characteristic parameters, transient thermal impedance discrete data of the SiC power module, and the operating condition parameters of the vehicle rectifier, wherein the operating condition parameters include the target fundamental frequency.

[0053] In this embodiment, the device characteristic parameters include key geometric and thermal properties of the chip layer and the packaging layer. Specifically, the chip layer parameters include the effective chip area, chip thickness, thermal conductivity of silicon carbide material, and specific heat capacity; the packaging layer parameters include solder layer thickness, copper layer thickness and ceramic layer thickness of the direct-bonded copper substrate, and substrate thickness. Transient thermal impedance discrete data are used to characterize the change of thermal impedance from junction to case over time. Operating parameters, in addition to the target fundamental frequency, include switching frequency, DC bus voltage, output power, and coolant temperature.

[0054] To obtain the power input excitation required for subsequent frequency domain calculations, the instantaneous power loss waveform of the power module within the fundamental period is calculated based on operating parameters and device characteristic parameters. This instantaneous power loss waveform is composed of the superposition of conduction loss and switching loss. Conduction loss can be calculated based on the product of the device's on-resistance and the square of the instantaneous current, while switching loss can be estimated based on the product of the switching energy and switching frequency provided in the device datasheet. This power loss calculation method is a conventional technique in this field, and a fast Fourier transform can be used to perform a frequency domain transformation on the instantaneous power loss waveform.

[0055] Next, the magnitude of the complex coefficients corresponding to the fundamental frequency is extracted as the fundamental frequency power ripple amplitude, which is the power ripple amplitude at the corresponding frequency. The magnitude of the complex coefficients corresponding to the second harmonic is extracted and used as the second harmonic power ripple amplitude for subsequent junction temperature fluctuation amplitude correction. This decouples the complex time-domain loss waveform into independent frequency-domain excitation components.

[0056] Step 102 involves fitting multi-order thermal network parameters based on transient thermal impedance discrete data, and decoupling these parameters over time, dividing them into a subset of chip thermal capacity-dominant parameters characterizing the internal heat transfer process of the chip, and a subset of package thermal resistance-dominant parameters characterizing the heat transfer process of the package layer. In this embodiment, an initial fitting order is set, which can be selected by those skilled in the art based on the complexity of the thermal impedance curve. The transient thermal impedance discrete data is then curve-fitted using the initial fitting order; that is, based on the initial fitting order, a nonlinear least squares method is used to perform curve fitting on the transient thermal impedance discrete data, and the fitting residual is calculated.

[0057] The fitting order is gradually increased until the current fitting residual is less than a preset residual threshold. The residual threshold can be determined by those skilled in the art based on the measurement accuracy of the thermal impedance curve and the requirements for fitting fidelity in frequency domain calculations. For example, a value is selected that makes the normalized root mean square error less than a preset percentage. The corresponding order is determined as the target fitting order, and the multi-order thermal network parameters at this target fitting order are output for decoupling the time scale.

[0058] Based on this, utilizing the natural time constant gap characteristic brought about by the extremely low heat capacity of silicon carbide chips, the thermal network model is decomposed into two parameter subsets with clear physical meanings. The parameter subset with the smaller time constant is assigned to the chip heat capacity-dominated segment, which is used to respond to millisecond-level fundamental frequency temperature fluctuations; the parameter subset with the larger time constant is assigned to the package thermal resistance-dominated segment, whose response within the fundamental frequency period is approximately a constant bias.

[0059] Step 103: Based on the target fundamental frequency, perform frequency domain response verification based on the chip thermal capacity dominant segment parameter subset and the package thermal resistance dominant segment parameter subset to determine the effective participating order set for fundamental frequency thermal cycling calculation.

[0060] This addresses the issue of potential accuracy degradation caused by fixed physical boundaries under low-frequency operating conditions. At lower target fundamental frequencies, the thermal response of the encapsulation layer may intrude into the fundamental frequency cycle.

[0061] At the current frequency, this embodiment dynamically determines whether to include some orders of the packaging layer in the calculation by evaluating the frequency domain contribution ratio of a subset of parameters dominant by the chip's thermal capacity. After verification, the set of valid participating orders is determined, thereby maintaining the stability of prediction accuracy across the entire operating frequency range.

[0062] Step 104: Extract the power ripple amplitude corresponding to the target fundamental frequency based on the operating condition parameters and device characteristic parameters, and construct the frequency domain transfer function by combining the effective participation order set to calculate the junction temperature fluctuation amplitude.

[0063] In this embodiment, a complex-domain thermal impedance mapping model is constructed using the thermal resistance and time constant parameters contained in the effective participation order set. Specifically, the fundamental frequency power pulsation amplitude is used as the input excitation of the frequency domain transfer function. By multiplying the amplitudes and superimposing the phases, the fluctuation amplitude of the chip junction temperature within the fundamental period is calculated, thereby reducing the cumbersome iterative process of traditional time-domain simulation.

[0064] It should be noted that, for the junction temperature fluctuation amplitude, in the simplified scenario that only considers the fundamental frequency component, it refers to the product of the power pulsation amplitude and the thermal impedance amplitude; in the extended multi-frequency synthesis, the peak-to-peak value is extracted from the time-domain reconstructed waveform as the final output junction temperature fluctuation amplitude.

[0065] Step 105: Output the junction temperature fluctuation amplitude as the predicted result of the fundamental frequency thermal cycling amplitude of the vehicle rectifier.

[0066] Accordingly, the junction temperature fluctuation amplitude is input into a pre-configured device lifetime assessment model, and the fatigue damage degree of the silicon carbide power module is calculated by combining the material fatigue characteristic curve. When the junction temperature fluctuation amplitude is detected to exceed the preset safety fluctuation threshold, the derating operation control strategy of the on-board rectifier is triggered, that is, by actively reducing the output power or adjusting the switching frequency to suppress the thermal cycling amplitude and extend the service life of the device. In this embodiment, the output prediction result reflects the high-frequency thermal stress level of the power device under preset operating conditions.

[0067] Example 2

[0068] Based on the above embodiment one, this embodiment describes the process of decoupling the parameters of a multi-stage thermal network on a time scale.

[0069] In this embodiment, the chip thickness of the silicon carbide power module is within a preset thickness range. For example, a typical automotive-grade silicon carbide MOSFET chip is selected, with a thickness between 100 and 200 micrometers. Within this thickness range, the thermal diffusion time constant of the chip layer is in the sub-millisecond range, which is orders of magnitude different from the time constant of the packaging layer, which is in the tens of milliseconds to seconds range. Those skilled in the art can determine whether this gap condition is met based on the actual chip thickness and packaging structure of the target device.

[0070] Among the multi-order thermal network parameters, there is a numerical gap of at least one order of magnitude between the smallest time constant belonging to the subset of parameters dominated by package thermal resistance and the largest time constant belonging to the subset of parameters dominated by chip thermal capacity. Because silicon carbide chips have low thermal capacity, their thermal response is in the sub-millisecond to millisecond range, while the thermal response of the package layer, including solder, substrate, and baseplate, is in the tens of milliseconds to seconds range. Based on this inherent time constant distribution characteristic, decoupling the multi-order thermal network parameters is equivalent to grouping the frequency domain behavior. That is, using the aggregated response of multi-order parameters in the frequency domain, the thermal dynamic behavior at the chip level and the package level can be characterized separately, without requiring a direct numerical mapping between individual order parameters and specific physical structure layers.

[0071] In one possible implementation, the process of dividing the data into a chip thermal capacity-dominant subset of parameters characterizing the internal heat transfer process of the chip, and a package thermal resistance-dominant subset of parameters characterizing the heat transfer process of the package layer, includes the following steps:

[0072] Step 201: Extract the time constant sequence and thermal resistance sequence of each order from the multi-order thermal network parameters.

[0073] Based on the output results corresponding to the target fitting order, a set of time constants characterizing thermal dynamic delay characteristics and a set of thermal resistances characterizing steady-state temperature rise resistance are separated for subsequent identification of physical layer boundaries.

[0074] Furthermore, the boundary time constants are determined based on the distribution characteristics of the time constant sequences of each order, specifically including:

[0075] Step 202: Arrange the time constant sequences of each order in ascending order of their values.

[0076] In order to find clustering features of time constants in the logarithmic domain, a sorting operation is performed on the extracted time constant sequences of each order, arranging the elements in the sequence in order from the smallest time scale to the largest time scale.

[0077] Step 203: Calculate the logarithmic value of the ratio of adjacent time constants after arrangement to obtain the logarithmic gap ratio sequence.

[0078] This embodiment uses a logarithmic scale to reduce the dimensional influence caused by the large absolute value range of the time constant, and to characterize the degree of separation between adjacent orders on the time scale.

[0079] Specifically, the logarithm (base 10) of the ratio of the time constant of the next adjacent position to the time constant of the current position is calculated to generate a sequence reflecting the gap width. The corresponding calculation relationship is as follows:

[0080] Gap _i =log10(τ_(i+1) / τ_i);

[0081] Among them, Gap _i τ_i represents the logarithmic gap ratio at the i-th position in the logarithmic gap ratio sequence, log10 represents the logarithmic operation with base 10, τ_i represents the i-th order time constant after sorting, and τ_(i+1) represents the (i+1)-th order time constant after sorting.

[0082] Step 204: Determine the position corresponding to the maximum value in the logarithmic gap ratio sequence as the boundary position.

[0083] The calculated logarithmic gap ratio sequence is iterated through, and the maximum value is extracted. The sequence index corresponding to this maximum value represents the physical isolation band between the thermal response of the chip layer and the thermal response of the package layer in the silicon carbide power module. This index is defined as the boundary position to guide the subsequent parameter set partitioning.

[0084] Step 205: Calculate the geometric mean of the adjacent time constants on both sides of the boundary position to obtain the boundary time constant.

[0085] To determine the specific numerical boundary at the dividing point, this embodiment extracts the smaller and larger time constants corresponding to the dividing point, calculates their product, and then takes the square root. The geometric mean can evenly bisect the gap distance in the logarithmic domain, providing an unbiased cutting boundary. The corresponding calculation relationship is as follows:

[0086] τ_split=(τ_k×τ_(k+1)) 1 / 2 ;

[0087] Where τ_split is the dividing time constant, τ_k is the smaller time constant at the dividing position, and τ_(k+1) is the larger time constant at the dividing position.

[0088] Step 206: Classify the order parameters whose time constant is less than the boundary time constant into the chip thermal capacity-dominant parameter subset, and classify the order parameters whose time constant is greater than the boundary time constant into the package thermal resistance-dominant parameter subset.

[0089] Based on the boundary time constant, the original multi-order thermal network parameters are binary-divided. The order of parameters assigned to the chip thermal capacity-dominated subset has a smaller time constant and is used to characterize the heat transfer process that generates periodic temperature fluctuations within the fundamental frequency cycle. The order of parameters assigned to the package thermal resistance-dominated subset has a larger time constant and exhibits an approximately constant temperature bias within the fundamental frequency cycle, thus completing the decoupling of the thermal resistance model on the time scale.

[0090] In some alternative implementations, this embodiment provides an alternative physical layer demarcation method that does not rely on logarithmic gap detection.

[0091] Specifically, the density, specific heat capacity, thermal conductivity, and chip thickness of silicon carbide material are extracted. Based on one-dimensional thermal diffusion theory, the characteristic thermal diffusion time of a single layer of material is calculated and used as the chip's characteristic time constant. Elements in each order of time constant sequence are sequentially compared with the chip's characteristic time constant. Parameters with values ​​less than or equal to a preset multiple of the chip's characteristic time constant are assigned to the chip's thermal capacity-dominated parameter subset, while other orders are assigned to the packaging thermal resistance-dominated parameter subset. This method incorporates prior material physics information to achieve time-scale decoupling.

[0092] In another optional embodiment, based on the low thermal capacity physical characteristics of SiC devices, the transient thermal impedance is decoupled into a chip thermal capacity-dominated segment and a package thermal resistance-dominated segment according to a time constant, including the following steps:

[0093] Curve fitting is performed on the discrete data of transient thermal impedance, and a multi-order Foster thermal network model is used to express the transient thermal impedance. The corresponding calculation formula is as follows:

[0094] Z _th (t)=∑ _(i=1) n R _i (1-e -t / τ_i );

[0095] Among them, Z _th (t) is the transient thermal impedance, R _i Let τ_i be the i-th order thermal resistance, τ_i be the i-th order time constant, n be the model order, i be the order number of the multi-order Foster thermal network, t be the time variable, and e be the natural constant. Through nonlinear least squares optimization, with the objective of minimizing the fitting residual, the set of thermal network parameters is obtained, containing the thermal resistance value sequences of each order and the corresponding time constant sequences.

[0096] Accordingly, based on the principles of thermal diffusion physics, heat transfer from the chip surface outwards requires passing through multiple material layers, and the thermal time constant of each layer is determined by the product of its thermal resistance and thermal capacity. The correspondence between each order of time constants and the physical structure layers is established: According to the one-dimensional thermal diffusion theory, the formula for calculating the characteristic thermal diffusion time of a single-layer material is:

[0097] τ_layer=d 2 / α=(ρ×c _p ×d 2 ) / k;

[0098] Where τ_layer is the characteristic thermal diffusion time of a single-layer material, d is the layer thickness, α is the thermal diffusivity, ρ is the material density, and c _p is the specific heat capacity, and k is the thermal conductivity.

[0099] The characteristic thermal diffusion time of the chip layer is calculated using the set of physical parameters of the SiC chip, and is denoted as the chip characteristic time constant.

[0100] By comparing the time constants of each order in the Foster thermal network parameter set with the characteristic time constant of the chip, a time constant-physical layer mapping table is established: the order of time constants that are less than or close to the characteristic time constant of the chip corresponds to the internal heat transfer process of the chip; the order of time constants that are greater than the characteristic time constant of the chip corresponds to the heat transfer process of the packaging layer.

[0101] Next, we define the criteria for determining the boundary time constant, assuming the fundamental period is:

[0102] T _0 =1 / f0;

[0103] Among them, T _0 f0 is the fundamental frequency, where f is the fundamental period and f0 is the fundamental frequency of the motor.

[0104] Define the boundary time constant as:

[0105] τ_split=β×T _0

[0106] Wherein, β is the boundary coefficient, which means that for thermal networks with a time constant less than the boundary time constant, their thermal response can fully develop within the fundamental frequency period and contribute to the fundamental frequency temperature fluctuation; for thermal networks with a time constant greater than the boundary time constant, their thermal response is approximately constant within the fundamental frequency period and does not produce temperature fluctuations.

[0107] Based on this, the boundary time constant is calculated according to the fundamental frequency in the operating condition parameter set and the selected boundary coefficient. The parameters of each order in the Foster thermal network are sorted according to the size of the time constant, and divided into a chip thermal capacity-dominated parameter subset and a package thermal resistance-dominated parameter subset, with the boundary time constant as the boundary.

[0108] Example 3

[0109] Based on Example 2, this example describes the process of determining the effective set of participating orders for fundamental frequency thermal cycle calculation.

[0110] In one possible implementation, the following steps are included:

[0111] Step 301: At the target fundamental frequency, calculate the complex thermal impedance amplitude of the chip thermal capacity dominant segment parameter subset, and calculate the full network thermal impedance amplitude based on all order parameters of the chip thermal capacity dominant segment parameter subset and the package thermal resistance dominant segment parameter subset. The ratio of the complex thermal impedance amplitude of the chip thermal capacity dominant segment parameter subset to the full network thermal impedance amplitude is used to obtain the chip segment frequency domain contribution rate.

[0112] Specifically, the target fundamental frequency is converted to a fundamental angular frequency. Using the thermal resistances and time constants of the parameter subset dominated by the chip's thermal capacity, the equivalent thermal impedance amplitude of this subset at the fundamental angular frequency is calculated in the complex domain. Correspondingly, using all multi-order thermal network parameters, including both the chip segment and the package segment, the total thermal impedance amplitude of the entire network at the same frequency is calculated. By calculating the ratio of these two values, the frequency domain contribution of the chip segment to the total thermal impedance is calculated at the current operating frequency. The corresponding calculation relationships are as follows:

[0113] CR=Z _chip_mag / Z _total_mag ;

[0114] Where CR is the chip segment frequency domain contribution rate, and Z _chip_mag Z represents the complex thermal impedance magnitude of the subset of parameters dominated by the chip's thermal capacity. _total_mag This represents the amplitude of the thermal impedance of the entire network.

[0115] Step 302: Compare and verify the chip segment frequency domain contribution rate with the pre-configured contribution rate threshold.

[0116] A pre-configured contribution rate threshold is obtained to define the acceptable error range when using only chip segment parameters for thermal cycling prediction. The value of the contribution rate threshold can be adaptively adjusted by those skilled in the art based on actual engineering accuracy requirements. The chip segment frequency domain contribution rate is compared with the value of this contribution rate threshold. This comparison operation serves as a decision-making node in the subsequent adaptive adjustment process, used to determine whether the currently fixed physical layer boundary at the preset fundamental frequency meets the engineering calculation requirements.

[0117] Step 303: If the chip segment frequency domain contribution rate is greater than or equal to the contribution rate threshold, then the order contained in the chip thermal capacity dominant segment parameter subset is determined as the effective participating order set.

[0118] When the target fundamental frequency is high, causing the chip segment thermal response to dominate, the comparison results show that the chip segment frequency domain contribution rate is greater than or equal to the pre-configured contribution rate threshold. This indicates that within the fundamental period, the thermal response of the packaging layer does not substantially intrude, and the original chip segment parameters are sufficient to meet the prediction requirements. Accordingly, the order adjustment operation is stopped, and an initial subset of chip thermal capacity dominant segment parameters is obtained based on logarithmic gap detection. This subset is then locked as the final effective set of participating orders for subsequent junction temperature calculations.

[0119] Step 304: If the chip segment frequency domain contribution rate is less than the contribution rate threshold, calculate the frequency domain thermal impedance amplitude of each order in the package thermal resistance dominant segment parameter subset at the target fundamental frequency, and add the package layer order into the chip thermal capacity dominant segment parameter subset one by one in descending order of amplitude until the updated chip segment frequency domain contribution rate reaches the contribution rate threshold, and determine the updated order set as the effective participating order set.

[0120] When the target fundamental frequency is low, causing the thermal response of the packaging layer to intrude into the fundamental frequency period, the comparison results show that the chip segment frequency domain contribution rate is less than the pre-configured contribution rate threshold. To compensate for the prediction error under low-frequency conditions, an adaptive order adjustment process is initiated. For each order in the package thermal resistance dominant segment parameter subset, its frequency domain thermal impedance amplitude at the target fundamental frequency is calculated. Based on the calculated amplitude, the orders within the packaging layer are sorted in descending order. According to the sorting order, the packaging layer order with the largest amplitude is extracted and assigned to the chip thermal capacity dominant segment parameter subset, forming an updated parameter subset. The chip segment frequency domain contribution rate is recalculated accordingly. The order borrowing and contribution rate recalculation process is repeated until the chip segment frequency domain contribution rate is greater than or equal to the contribution rate threshold. After the condition is met, the updated order set is used as the effective participating order set for subsequent calculation processes.

[0121] This embodiment introduces a frequency domain contribution rate verification mechanism. At the current operating frequency, the impedance ratio of the evaluation chip segment is calculated, and the order of high-amplitude packaging layers is dynamically and adaptively incorporated into the calculation set. This flexible adjustment strategy can compensate for the response loss caused by thermal intrusion of the packaging layer at low frequencies, enabling the model to maintain stable evaluation reliability across the entire operating frequency band.

[0122] Example 4

[0123] Based on the above embodiment three, this embodiment further explains the process of constructing a frequency domain transfer function by combining the effective participation order set and calculating the junction temperature fluctuation amplitude.

[0124] In this embodiment, the frequency domain response of the multi-order RC network includes the superposition of amplitudes and phases of each order. When the time constants of each order differ significantly, weighting the multi-order parameters to form a single-order model may result in the loss of phase information of high-frequency orders, causing the synthesized thermal impedance amplitude and phase to deviate from the true frequency domain characteristics. To reduce this deviation, this embodiment retains each independent order within the set of valid participating orders.

[0125] In one possible implementation, the following steps are included:

[0126] Step 401: Construct a complex thermal impedance model based on the effective participation order set, and calculate the thermal impedance amplitude corresponding to the target fundamental frequency.

[0127] Further, the thermal impedance amplitude corresponding to the target fundamental frequency is calculated, specifically including:

[0128] Step 4011: Retain all order parameters in the effective participating order set, and calculate the real part and imaginary part in the frequency domain for each order parameter for the target fundamental frequency.

[0129] Unlike compressing multi-order parameters into a single-order parameter through weighted averaging, this embodiment retains each independent order within the effective participating order set, reducing the frequency domain characteristic deviation introduced by model order reduction. The target fundamental frequency is converted into the fundamental angular frequency. For each order in the set, the complex impedance component of that order at the fundamental angular frequency is calculated using its thermal resistance and time constant parameters.

[0130] Step 4012: Summate the real parts of the frequency domain for all orders, and sum the imaginary parts of the frequency domain for all orders.

[0131] The calculated real components are summed, and the calculated imaginary components are summed. This superposition operation integrates the thermal dynamic responses of multiple time constant branches in the complex domain. The corresponding computational relationships are as follows:

[0132] Re=∑(R _i / (1+(ω _0 ×τ_i) 2 ));

[0133] Im=∑(-R _i ×ω _0 ×τ_i / (1+(ω _0 ×τ_i) 2 ));

[0134] Where Re is the total real part of the summation, Im is the total imaginary part of the summation, ∑() is the summation function, and R _i To effectively participate in the thermal resistance of the i-th order in the order set, τ_i is the time constant of the i-th order, and ω _0 ω is the fundamental angular frequency.

[0135] Step 4013: Based on the summed total real part and total imaginary part, synthesize the complex modulus value to obtain the thermal impedance amplitude corresponding to the target fundamental frequency.

[0136] After obtaining the total real and imaginary parts, the magnitude of the corresponding vector is calculated in the complex plane. This magnitude is used to characterize the system's steady-state resistance to thermal power excitation at this frequency band. The corresponding calculation relationship is as follows:

[0137] Z _mag =(Re 2 +Im 2 ) 1 / 2 ;

[0138] Among them, Z _mag Let Re be the thermal impedance amplitude corresponding to the target fundamental frequency, and let Im be the total real part and Im be the total imaginary part.

[0139] Step 402: Multiply the power pulsation amplitude and thermal impedance amplitude at the corresponding frequency to obtain the fundamental frequency junction temperature fluctuation amplitude.

[0140] Based on the extracted fundamental frequency power pulsation amplitude, it is multiplied by the thermal impedance amplitude to reflect the peak value of the chip junction temperature fluctuating around the steady-state average under a single fundamental frequency excitation. For the second harmonic frequency, following the same method as calculating the fundamental frequency, the real and imaginary parts of the parameters of each order in the effective participating order set at the second harmonic are calculated. The real parts of the frequency domain for all orders are summed, and the imaginary parts of the frequency domain for all orders are summed to synthesize the complex modulus and obtain the second harmonic thermal impedance amplitude. The corresponding calculation relationship is as follows:

[0141] Δ _T_f0 =P _amp_f0 ×Z _mag ;

[0142] Where, Δ _T_f0 P represents the amplitude of the fundamental frequency junction temperature fluctuation. _amp_f0 Z represents the fundamental frequency power ripple amplitude. _mag This represents the thermal impedance amplitude.

[0143] Furthermore, when performing frequency domain transformation on the instantaneous power loss waveform, the modulus of the complex coefficients corresponding to the second harmonic is extracted as the second harmonic power ripple amplitude; after obtaining the fundamental frequency junction temperature fluctuation amplitude, the following is also included:

[0144] Step 403: For the second harmonic frequency, in the same way as calculating the fundamental frequency, calculate the real and imaginary parts of the frequency domain of each order parameter in the effective participating order set at the second harmonic. Summate the real parts of the frequency domain of all orders and sum the imaginary parts of the frequency domain of all orders to synthesize the complex modulus and obtain the second harmonic thermal impedance amplitude. Multiply the second harmonic power pulsation amplitude and the second harmonic thermal impedance amplitude to obtain the second harmonic junction temperature fluctuation amplitude.

[0145] During rectifier operation, the power loss waveform contains not only the fundamental frequency component but also a second harmonic component. To improve the reliability of the prediction results, the second harmonic angular frequency is extracted and substituted into the calculation logic of the real and imaginary parts to obtain the total real and imaginary parts corresponding to the second harmonic, which are then synthesized into the second harmonic thermal impedance amplitude. Based on this, the second harmonic power pulsation amplitude is multiplied by the second harmonic thermal impedance amplitude to calculate the junction temperature fluctuation component at the preset frequency.

[0146] Step 404: Calculate the phase lag corresponding to the fundamental frequency response and the second harmonic response, respectively. That is, calculate the phase lag corresponding to the fundamental frequency response based on the total real part and the total imaginary part at the fundamental frequency, and calculate the phase lag corresponding to the second harmonic response based on the total real part and the total imaginary part at the second harmonic frequency.

[0147] Due to the delay effect in heat transfer, the temperature fluctuation waveform will have a phase shift relative to the power pulsation waveform. In this embodiment, the phase lag angle of the fundamental frequency and the second harmonic is calculated using the ratio of the imaginary part to the real part in the complex domain, respectively, for subsequent time-domain waveform alignment. The corresponding calculation relationship is as follows:

[0148] θ = arctan(Im / Re);

[0149] Where θ is the phase lag, arctan() is the arctangent function, Im is the total imaginary part, and Re is the total real part.

[0150] Step 405: Based on the fundamental frequency junction temperature fluctuation amplitude, the second harmonic junction temperature fluctuation amplitude, and their respective phase lags, reconstruct the temperature fluctuation waveform in the time domain, extract the difference between the maximum and minimum values ​​of the waveform, and obtain the peak-to-peak value of the temperature fluctuation as the junction temperature fluctuation amplitude.

[0151] The calculated fundamental and second harmonic responses are transformed to the time domain and superimposed. Based on their respective junction temperature fluctuation amplitudes and phase lag parameters, a time-domain temperature fluctuation function containing dual-frequency components is constructed. Within a single fundamental period, the reconstructed waveform is discretized, and the maximum and minimum values ​​in the discrete sequence are extracted, with the difference between them calculated. This difference represents the peak-to-peak temperature fluctuation after comprehensively considering multi-frequency excitation and phase delay, and is used as the final output junction temperature fluctuation amplitude. The corresponding calculation relationships are as follows:

[0152] Δ_T_pk-pk =max(Δ _T (t))-min(Δ _T (t));

[0153] Where, Δ _T_pk-pk The peak-to-peak value of the temperature fluctuation, max() is the function to extract the maximum value, min() is the function to extract the minimum value, Δ _T (t) is the time-domain reconstruction function for temperature fluctuation waveforms, where t is the time variable.

[0154] Accordingly, a time-domain temperature fluctuation function is constructed, and the corresponding calculation formula is as follows:

[0155] ΔT(t)=ΔT _f0 ×cos(ω _0 ×t+θ1)+ΔT _2_f0 ×cos(2×ω _0 ×t+θ2);

[0156] Where, ΔT _f0 The fundamental frequency junction temperature fluctuation amplitude, ΔT _2_f0 The amplitude of the second harmonic junction temperature fluctuation, ω _0 θ is the fundamental angular frequency, θ1 is the fundamental frequency phase lag, θ2 is the second harmonic phase lag, and t is the time variable.

[0157] In another possible embodiment, based on the time-scale segmentation results, a simplified fundamental frequency temperature fluctuation prediction model is established using only the chip thermal capacity-dominant segment parameters, including the following steps:

[0158] Equivalent thermal parameters for fundamental frequency thermal cycling analysis are extracted from the subset of parameters representing the chip's thermal capacity-dominant segment. The equivalent thermal resistance of the chip segment is defined as the sum of the thermal resistances of all orders within this subset, and the equivalent time constant of the chip segment is defined as the weighted average of the time constants of all orders. The corresponding calculation formula is as follows:

[0159] R _chip =∑ _(i∈Ω_chip )R _i ;

[0160] τ_chip=(∑ _(i∈Ω_chip) R _i ×τ_i) / (∑ _(i∈Ω_chip) R _i );

[0161] Among them, R _chip Ω_chip is the equivalent thermal resistance of the chip segment, τ_chip is the set of order indices of the chip's thermal capacity-dominant segments, and τ_chip is the equivalent time constant of the chip segment.

[0162] Next, the ratio of the equivalent time constant to the equivalent thermal resistance is calculated, which is the equivalent thermal capacity of the chip segment. The calculation results are combined into a set of equivalent thermal parameters for the chip segment, including three parameters: equivalent thermal resistance, equivalent time constant, and equivalent thermal capacity.

[0163] Furthermore, based on frequency domain analysis, a direct mapping relationship between power pulsation and temperature fluctuation is established. The instantaneous power loss waveform is decomposed into DC and AC components, and the corresponding calculation formula is as follows:

[0164] P(t) = P _avg +P _ac (t);

[0165] Where P(t) is the instantaneous power loss, P _avg For average power loss, P _ac (t) represents the AC pulsation component. For typical operating conditions of an on-board rectifier, the main components of power pulsation are the fundamental frequency and its second harmonic. The fundamental frequency power pulsation amplitude is extracted and denoted as the fundamental frequency power pulsation amplitude.

[0166] Accordingly, the frequency domain transfer function of the chip segment thermal impedance is constructed. For the single-order equivalent model, the calculation formula is:

[0167] Z _chip (jω)=R _chip / (1+jωτ_chip);

[0168] ω _0 =2πf0;

[0169] Among them, Z _chip (jω) is the frequency domain transfer function of the thermal impedance of the chip segment, where j is the imaginary unit and ω represents the angular frequency. _0 f0 represents the fundamental angular frequency, where f0 is the fundamental frequency of the motor, i.e., the target fundamental frequency.

[0170] Next, the thermal impedance amplitude at the fundamental angular frequency is calculated using the following formula:

[0171] |Z _chip (jω _0 )∣=R _chip / sqrt(1+(ω _0 ×τ_chip) 2 );

[0172] Among them, |Z _chip (jω _0 )∣ represents the thermal impedance modulus of the chip segment at the fundamental angular frequency, and sqrt represents the square root operation.

[0173] Based on this, the fundamental frequency fluctuation amplitude of the junction temperature is calculated using the fundamental frequency power pulsation amplitude and the fundamental frequency thermal impedance amplitude. The corresponding calculation formula is as follows:

[0174] ΔT _f0 =P _amp_f0 ×∣Z _chip (jω _0 )∣=(P _amp_f0 ×R _chip ) / sqrt(1+(2π×f0×τ_chip) 2 );

[0175] Among them, P _amp_f0 The fundamental frequency power ripple amplitude, ΔT _f0 The amplitude of the junction temperature fluctuation is the peak-to-peak value of the junction temperature within the fundamental frequency period. The phase lag of the temperature fluctuation relative to the power fluctuation is calculated using the following formula:

[0176] θ=arctan(2π×f0×τ_chip);

[0177] Where θ is the phase lag of the junction temperature fluctuation relative to the power pulsation at the fundamental frequency. The amplitude of the junction temperature fluctuation at the fundamental frequency and the phase lag are integrated into the prediction result of the fundamental frequency thermal cycling.

[0178] Example 5

[0179] Unlike Embodiment 2 described above, this embodiment provides another method for determining the boundary time constant based on the distribution characteristics of time constant sequences of each order. This embodiment does not rely on logarithmic gap detection; instead, it introduces a frequency domain cutoff criterion and performs mathematical derivation for rapid scenario estimation. The remaining steps are the same as in Embodiment 2 and can be referred to the foregoing description, and will not be repeated here.

[0180] In one possible implementation, the following steps are included:

[0181] Step 501: Obtain the pre-configured frequency domain participation threshold, where frequency domain participation characterizes the ratio of the thermal impedance amplitude of a single-order thermal network under AC operation to its DC thermal resistance.

[0182] Under AC thermal excitation, the contribution of the thermal network order to temperature fluctuations is related to its time constant and excitation frequency. At the target frequency, the ratio of the amplitude of the complex thermal impedance of a single order to the DC steady-state thermal resistance of that order is defined as the frequency domain participation degree. This is used to characterize the degree of response attenuation of the preset order under AC operating conditions.

[0183] Obtain a pre-configured frequency domain participation threshold, which is used to set the attenuation boundary and define the order that is considered to have an effective contribution to the fundamental frequency fluctuation. This order is regarded as a constant bias.

[0184] The frequency domain participation threshold is set, which means that when the thermal impedance amplitude of a single-order thermal network decreases to a percentage below the corresponding threshold of its DC thermal resistance under AC operation, for example, when the frequency domain participation threshold is set to 0.1, and the thermal impedance amplitude decreases to less than 10% of its DC thermal resistance, it is determined that the order has no contribution to temperature fluctuation. Those skilled in the art can adjust this threshold according to the prediction accuracy requirements.

[0185] Step 502: Based on the frequency domain participation threshold, calculate the square root of the difference between the reciprocal of the square of the frequency domain participation threshold and one, and then divide it by twice pi to obtain the derived boundary coefficient.

[0186] Based on the definition of frequency domain participation, a nonlinear mapping relationship is established between it and the boundary coefficient. A lower frequency domain participation threshold allows more deeply decaying orders to be included in the effective calculation range, and the derived boundary coefficient will increase accordingly. Specifically, the reciprocal of the square of the frequency domain participation threshold is calculated, 1 is subtracted from this reciprocal, and the square root of the result is taken. The ratio of this square root to twice the constant pi is then calculated to obtain the boundary coefficient, whose calculation formula is as follows:

[0187] β=(1 / (2×π))×((1 / (α _th) 2 )-1) 1 / 2 ;

[0188] Where β is the dividing coefficient, π is the constant of pi, and α _th This is the preset frequency domain participation threshold.

[0189] Step 503: The product of the boundary coefficient and the period corresponding to the target fundamental frequency is determined as the boundary time constant.

[0190] After deriving the boundary coefficient, it is bound to a specific time scale under the current operating conditions. The fundamental period is obtained by calculating the reciprocal of the target fundamental frequency. The boundary coefficient is multiplied by this fundamental period; the product is used to characterize the cutoff point of the time constant that dynamically changes with the operating frequency. Through this process, the empirical constant value is transformed into a dynamic boundary index physically bound to the system cutoff frequency. The corresponding calculation formula is as follows:

[0191] τ_split=β×T _0 ;

[0192] Where τ_split is the boundary time constant, β is the boundary coefficient, and T _0 The period corresponding to the target fundamental frequency.

[0193] Correspondingly, when using the frequency domain cutoff boundary method, the contribution rate verification process can be omitted in most operating conditions because the boundary time constant is dynamically adjusted with the target fundamental frequency. In application scenarios with higher requirements for prediction accuracy, contribution rate verification can also be superimposed on the dynamic boundary to form a double guarantee.

[0194] Example 6

[0195] Unlike Embodiment 4 above, this embodiment provides another method for constructing a frequency domain transfer function by combining the effective participating order set to calculate the junction temperature fluctuation amplitude. This embodiment uses parameter compression to construct a single-order equivalent model as a simplified alternative to direct calculation of multiple orders. The remaining steps are the same as in Embodiment 4 and can be referred to the foregoing description, and will not be repeated here.

[0196] Before performing equivalent compression of parameters, the distribution characteristics of time constants within the effective participation order set are evaluated. The ratio of the maximum to the minimum time constant within the set is calculated. When it is less than a preset multiple, the amplitude and phase errors introduced by the single-order equivalent model are within the allowable range of engineering calculations, triggering the simplified calculation process of this embodiment.

[0197] In one possible implementation, the following steps are included:

[0198] Step 601: Summing up the thermal resistances of each order in the effective participating order set to obtain the equivalent thermal resistance of the chip segment, and using the proportion of each order thermal resistance in the equivalent thermal resistance of the chip segment as the weight, the time constants of each order are weighted and averaged to obtain the equivalent time constant of the chip segment.

[0199] Multiple discrete resistor-capacitor network branches are compressed into a unified representation node. All thermal resistance values ​​within the set are linearly summed, and their sum is defined as the chip segment equivalent thermal resistance. To characterize the overall thermal delay effect, the proportion of each order of thermal resistance in the chip segment equivalent thermal resistance is used as a weighting coefficient. The time constants of each order are then weighted and summed to calculate the chip segment equivalent time constant. The calculation relationship is as follows:

[0200] R _eq =∑(R _i );

[0201] τ_eq=∑(R _i ×τ_i) / R _eq ;

[0202] Among them, R _eq Let R be the equivalent thermal resistance of the chip segment, ∑() be the summation function, and R be the summation value. _i To effectively participate in the thermal resistance of the i-th order in the order set, τ_eq is the equivalent time constant of the chip segment, and τ_i is the time constant of the i-th order.

[0203] Step 602: Calculate the equivalent thermal capacity of the chip segment based on the equivalent thermal resistance and equivalent time constant of the chip segment, and generate a set of single-order equivalent parameters.

[0204] Based on the correspondence between thermal resistance, heat capacity, and time constant in the thermal network model, the heat storage characteristics of a single node are reconstructed using equivalent indices. The ratio of the equivalent time constant to the equivalent thermal resistance is calculated to obtain the equivalent heat capacity of the chip segment. The equivalent thermal resistance, equivalent time constant, and equivalent heat capacity of the chip segment are combined to form a single-order equivalent parameter set for subsequent frequency domain mapping. The corresponding calculation formula is as follows:

[0205] C _eq =τ_eq / R _eq ;

[0206] Among them, C _eq R is the equivalent heat capacity of the chip segment, τ_eq is the equivalent time constant of the chip segment, and R _eq This is the equivalent thermal resistance of the chip segment.

[0207] Step 603: Construct a single-order frequency domain transfer function based on the single-order equivalent parameter set, and calculate the thermal impedance amplitude corresponding to the target fundamental frequency.

[0208] By utilizing the standard frequency domain response characteristics of a single-order low-pass filter, a mapping relationship from power input to temperature output is established. Specifically, the target fundamental frequency is converted to the fundamental angular frequency. The square of the product of the fundamental angular frequency and the equivalent time constant of the chip segment is calculated. One is added to this square, and the square root is taken. The ratio of the equivalent thermal resistance of the chip segment to this square root is then calculated, yielding the thermal resistance amplitude of the single-order model at the current frequency. The calculation formula is as follows:

[0209] Z _mag_single =R _eq / (1+(ω _0 ×τ_eq) 2 ) 1 / 2 ;

[0210] Among them, Z _mag_single R is the thermal impedance amplitude corresponding to the target fundamental frequency. _eq For the equivalent thermal resistance of the chip segment, ω _0 τ is the fundamental angular frequency, and τ_eq is the equivalent time constant of the chip segment.

[0211] After obtaining the thermal impedance amplitude, multiplying it by the power pulsation amplitude corresponding to the target fundamental frequency yields the predicted fundamental frequency junction temperature fluctuation amplitude. Under preset operating conditions, this simplified scheme can reduce the computational power required for complex number operations.

[0212] Example 7

[0213] Based on the fundamental frequency thermal cycling prediction principle provided in Embodiments 1 to 4 above, this embodiment further provides an engineering solution for the computationally limited characteristics of the vehicle environment. This solution transfers complex model decoupling, frequency domain verification, and multi-order complex number operations to the offline stage, and achieves rapid invocation in the online environment by constructing a multi-condition mapping table.

[0214] In one possible implementation, a multi-condition mapping table is pre-built, specifically including the following steps:

[0215] Step 701: Traverse the preset fundamental frequency range and extract multiple discrete frequency points.

[0216] The fundamental frequency variation range of the motor under typical operating conditions of the on-board rectifier is obtained. Discrete sampling is performed within this range according to a preset frequency step size or logarithmic distribution law, generating a test sequence containing multiple specific frequency values. This discrete frequency point covers the characteristic electrical load frequencies that may occur when the vehicle is traveling at low, medium, and high speeds.

[0217] Step 702: Take each discrete frequency point as the target fundamental frequency, and perform the steps of determining the effective participation order set and calculating the junction temperature fluctuation amplitude based on the preset reference operating condition parameters to obtain the reference junction temperature fluctuation amplitude corresponding to each discrete frequency point.

[0218] In the offline computing environment, the physical parameters of the silicon carbide devices, the fitted multi-order thermal network parameters, and the rated power loss baseline values ​​are configured identically to those in the actual vehicle. For each discrete frequency point in the test sequence, adaptive adjustment and frequency domain mapping calculations are iteratively invoked. Specifically, for the currently selected frequency point, physical layer partitioning based on the logarithmic gap ratio is performed. The contribution rate is verified using the complex thermal impedance ratio at that frequency to determine the effective participation order set. Correspondingly, the total thermal impedance amplitude and phase at that frequency are calculated, and the peak-to-peak value of the junction temperature fluctuation is output in conjunction with the power pulsation excitation. The result of each loop output is recorded, which is the reference junction temperature fluctuation amplitude at that frequency point.

[0219] Step 703: Associate the discrete frequency points with the reference junction temperature fluctuation amplitude to generate a pre-built frequency-temperature fluctuation amplitude mapping table.

[0220] Specifically, the input and output data of all cyclic tests are integrated to establish a mapping relationship between discrete frequency point sequences and reference junction temperature fluctuation amplitude sequences. This mapping relationship is stored as a structured data table or matrix, i.e., a frequency-temperature fluctuation amplitude mapping table. This mapping table solidifies the thermal dynamic response characteristics of the device at different time scales, freeing the subsequent prediction process from real-time dependence on complex mathematical models. The completed mapping table is then distributed and stored in the local control unit of the automotive rectifier.

[0221] Accordingly, the frequency domain transfer function is constructed by combining the effective participation order set, and the junction temperature fluctuation amplitude is calculated, specifically through the following method:

[0222] Step 704: Based on the target fundamental frequency in the real-time acquired operating condition parameters, query the pre-built frequency-temperature fluctuation amplitude mapping table, and extract the corresponding value as the junction temperature fluctuation amplitude through precise matching or linear interpolation.

[0223] During actual vehicle operation, the onboard control unit acquires the motor's operating status information in real time via the communication bus, and parses the current target fundamental frequency. Using this target fundamental frequency as a lookup index, a table of frequency-temperature fluctuation amplitudes is retrieved locally. If the current frequency coincides with a discrete frequency point in the table, the corresponding reference junction temperature fluctuation amplitude is extracted and used as the prediction result for the current operating condition. If the current frequency lies between two adjacent discrete frequency points, a linear interpolation algorithm is used to calculate the appropriate value as the prediction result. Through this combination of table lookup and interpolation, the state assessment of high-frequency thermal cycling stress can be completed within a microsecond-level time window.

[0224] In this embodiment, the intensive multi-order complex number mapping and waveform reconstruction operations are performed in advance, and a multi-condition mapping matrix is ​​constructed through offline traversal. During online monitoring of actual vehicles, the complex algebraic operations are reduced in dimensionality and transformed into a simple feature addressing and linear interpolation process, which can reduce the computing power of single thermal cycle prediction and complete the deployment of high-precision thermal monitoring on the engineering computing platform.

[0225] In one alternative implementation, an offline mapping table can be constructed based on rated operating conditions. During online lookup, if the actual operating power deviates from the rated power, the reference junction temperature fluctuation amplitude obtained from the lookup table is linearly scaled according to the ratio of the actual power fluctuation amplitude to the rated power fluctuation amplitude to obtain the corrected junction temperature fluctuation amplitude under the current operating conditions. This linear scaling relationship stems from the linear mapping characteristic between the junction temperature fluctuation amplitude and the power fluctuation amplitude.

[0226] According to one aspect of this application, the thermal impedance model is decoupled into a chip thermal capacity-dominated segment and a package thermal resistance-dominated segment by utilizing the logarithmic gap characteristic of the device's inherent time constant distribution. During the calculation, the conventional single-order weighted average order reduction operation is abandoned; instead, multi-order parameters of the chip segment are retained for complex domain synthesis, and a second harmonic thermal response component is superimposed. This mechanism can reduce the truncation error caused by model parameter compression and improve the accuracy of junction temperature peak-to-peak prediction within a preset frequency band.

[0227] Based on the above embodiments, this application also provides a system for predicting the fundamental frequency thermal cycling amplitude of an on-board rectifier based on the low thermal capacity characteristics of SiC devices. The system includes a processor coupled to a memory, which stores instructions. When the processor executes the instructions, it implements the methods executed in the above method embodiments.

[0228] This application also provides an electronic device, including: one or more processors and a memory, wherein the one or more processors are coupled to the memory, the memory is used to store computer program code, the computer program code including computer instructions, and when the one or more processors execute the computer instructions, the electronic device executes the methods executed in the above-described method embodiments.

[0229] This application also provides a chip, including: a processor and a communication interface, wherein the processor calls a computer program or instruction through the communication interface to execute the methods executed in the above-described method embodiments.

[0230] It should be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. A method for predicting the fundamental frequency thermal cycling amplitude of an on-board rectifier based on the low thermal capacity characteristics of SiC devices, characterized in that, include: Obtain the device characteristic parameters, transient thermal impedance discrete data, and operating condition parameters of the vehicle rectifier for the SiC power module, including the target fundamental frequency. Based on the transient thermal impedance discrete data, the parameters of the multi-order thermal network are fitted and decoupled on the time scale. They are divided into a chip thermal capacity-dominated parameter subset that characterizes the internal heat transfer process of the chip and a package thermal resistance-dominated parameter subset that characterizes the heat transfer process of the package layer. Parameters of multi-order thermal networks are fitted based on transient thermal impedance discrete data, including: Set an initial fitting order, use the initial fitting order to perform curve fitting on the transient thermal impedance discrete data, and calculate the fitting residual; Gradually increase the fitting order until the current fitting residual is less than the preset residual threshold, then determine the corresponding order as the target fitting order, and output the multi-order thermal network parameters under the target fitting order. Based on the target fundamental frequency, frequency domain response verification is performed on the decoupled subset to determine the effective set of participating orders for fundamental frequency thermal cycling calculation. Based on the operating condition parameters and device characteristic parameters, the power ripple amplitude corresponding to the target fundamental frequency is extracted, and the frequency domain transfer function is constructed by combining the effective participation order set. The junction temperature fluctuation amplitude is calculated and output as the prediction result of the fundamental frequency thermal cycling amplitude of the vehicle rectifier. After outputting the junction temperature fluctuation amplitude, it also includes: Input the junction temperature fluctuation amplitude into the pre-configured device lifetime assessment model to calculate the fatigue damage degree of the SiC power module; And / or, when the junction temperature fluctuation amplitude exceeds the preset safety fluctuation threshold, the derating operation control strategy of the vehicle rectifier is triggered; It also includes the step of pre-building a multi-condition mapping table: Traverse the preset fundamental frequency range and extract multiple discrete frequency points; Each discrete frequency point is taken as the target fundamental frequency. Based on the preset reference operating condition parameters, the steps of determining the effective participation order set and calculating the junction temperature fluctuation amplitude are performed to obtain the reference junction temperature fluctuation amplitude corresponding to each discrete frequency point. By associating discrete frequency points with reference junction temperature fluctuation amplitudes, a pre-built frequency-temperature fluctuation amplitude mapping table is generated.

2. The method according to claim 1, characterized in that, Extract the power ripple amplitude corresponding to the target fundamental frequency, including: The instantaneous power loss waveform of the power module during the fundamental frequency period is calculated based on the operating condition parameters. A frequency domain transformation is performed on the instantaneous power loss waveform. The magnitude of the complex coefficients corresponding to the fundamental frequency is extracted as the fundamental frequency power pulsation amplitude, and the magnitude of the complex coefficients corresponding to the second harmonic is extracted as the second harmonic power pulsation amplitude.

3. The method according to claim 1, characterized in that, The parameters of the multi-order thermal network are decoupled on a time scale, and the parameters are divided into a subset dominated by chip thermal capacity and a subset dominated by package thermal resistance, including: Extract the time constant sequence and thermal resistance sequence of each order from the parameters of the multi-order thermal network; The boundary time constant is determined based on the distribution characteristics of the time constant sequences of each order; Parameters with time constants less than the boundary time constant are assigned to the chip thermal capacity-dominated parameter subset, while parameters with time constants greater than the boundary time constant are assigned to the package thermal resistance-dominated parameter subset.

4. The method according to claim 3, characterized in that, The boundary time constants are determined based on the distribution characteristics of time constant sequences of each order, including: Arrange the time constant sequences of each order in ascending order of their numerical values; Calculate the logarithmic ratio of the ratios of adjacent time constants after arrangement to obtain the logarithmic gap ratio sequence; The position corresponding to the maximum value in the logarithmic gap ratio sequence is determined as the boundary position; The boundary time constant is obtained by calculating the geometric mean of the adjacent time constants on both sides of the boundary position.

5. The method according to claim 3, characterized in that, The boundary time constants are determined based on the distribution characteristics of the time constant sequences of each order, specifically through the following methods: Obtain the pre-configured frequency domain participation threshold, where frequency domain participation characterizes the ratio of the thermal impedance amplitude of a single-order thermal network under AC operation to its DC thermal resistance. Based on the frequency domain participation threshold, calculate the square root of the difference between the reciprocal of the square of the frequency domain participation threshold and one, and then divide it by twice pi to obtain the boundary coefficient. The product of the dividing coefficient and the period corresponding to the target fundamental frequency is determined as the dividing time constant.

6. The method according to claim 3, characterized in that, The chip thickness of the SiC power module is within a preset thickness range; and among the multi-order thermal network parameters, there is at least an order of magnitude gap between the minimum time constant belonging to the parameter subset dominated by the thermal resistance of the package and the maximum time constant belonging to the parameter subset dominated by the thermal capacity of the chip.

7. The method according to claim 1, characterized in that, By constructing a frequency domain transfer function using the effective participation order set, the junction temperature fluctuation amplitude is calculated, including: A complex thermal impedance model is constructed based on the effective participation order set, and the thermal impedance amplitude corresponding to the target fundamental frequency is calculated. The fundamental frequency junction temperature fluctuation amplitude is obtained by multiplying the power pulsation amplitude at the corresponding frequency with the thermal impedance amplitude.

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