A bipolar transport antiferroelectric field effect transistor and applications thereof

Abstract

The application provides a bipolar transport antiferroelectric field effect transistor and application thereof, and belongs to the field of novel memory. The application adopts a semiconductor channel or a semiconductor p-i-n junction with bipolar transport characteristics, uses hafnium-zirconium-oxygen antiferroelectric material or zirconium oxide material with self-recovery endurance characteristics as a gate stack, and forms an antiferroelectric field effect transistor with bipolar transport characteristics. The antiferroelectric field effect transistor is used as a memory, and by periodically and alternately using the hysteresis of two different polarities of the antiferroelectric material and applying different reading gate voltages during data writing, super-high endurance characteristics are achieved, and a potential solution is provided for end-side artificial intelligence equipment.

Description

Technical Field

[0001] This invention relates to the field of novel memory, specifically to a bipolar transport antiferroelectric field-effect transistor and its applications. Background Technology

[0002] The deployment of AI on edge devices is becoming a mainstream trend due to its faster response times, better privacy, and lower operating costs. To adapt to changing or network-connected environments and meet personalized user needs while protecting user privacy, edge AI devices need to continuously and lightweightly perform on-chip training based on collected data, allowing the model to evolve. On-chip training based on the traditional von Neumann architecture requires significant data transfer between computing and storage units. In-memory computing (CIM) technology, by directly performing generalized matrix-vector multiplication (GEMV) operations within the storage unit, overcomes the energy efficiency and latency bottlenecks caused by data transfer. Among various CIM paradigms, FeFET-based CIM has received widespread attention in recent years. FeFETs are made by integrating hafnium oxide-based ferroelectric materials into a MOSFET gate stack. Compared to traditional volatile static random access memory (SRAM), they have smaller cell areas, multi-value storage capabilities, and help reduce the hardware overhead of computing systems. Furthermore, they avoid the static power consumption or refresh power consumption required for data retention and the data loading power consumption during system startup, making them highly suitable for edge devices. Compared to other emerging two-terminal non-volatile memories such as resistive random access memory (RRAM), phase-change memory (PCM), and magnetic random access memory (MRAM), FeFETs, in addition to having the advantages of high switching ratio and three-terminal structure, also have the advantage of low write power consumption due to field-induced low power consumption, making them particularly suitable for on-chip training scenarios that require frequent weight updates.

[0003] However, the high coercivity of hafnium oxide-based ferroelectric materials in FeFETs requires high operating voltages, leading to reliability issues such as fatigue effects and limiting the improvement of FeFET durability. Some studies have replaced the ferroelectric layer in FeFETs with an antiferroelectric (AFE) layer, utilizing the lower coercivity of each of the two hysteresis branches of the AFE material to reduce the operating voltage and improve the FeFET's durability. However, since the fatigue effect still exists in the single hysteresis branch of the AFE material, the optimized FeFET still struggles to meet the durability requirements of on-chip training for neural network weight devices.

[0004] Recent research (K.-Y. Hsiang, et al., Novel Opposite Polarity Cycling Recovery (OPCR) of HfZrO2 Antiferroelectric-RAM with an Access Scheme TowardUnlimited Endurance, in 2022 IEEE International Electron Devices Meeting (IEDM)) indicates that the durability characteristics of the two unipolar hysteresis loops in highly zirconium-doped hafnium zirconium oxide (HZO) AFE materials are independent of each other. That is, positive (negative) polarity electric field cycling only causes fatigue in the positive (negative) polarity hysteresis, while the negative (positive) polarity hysteresis remains unaffected. Furthermore, the material exhibits a self-recovery effect in its durability characteristics. After fatigue occurs in the positive (negative) polarity hysteresis, if a negative (positive) polarity electric field cycle is applied, the negative (positive) polarity hysteresis begins to fatigue, and the polarization intensity of the positive (negative) polarity hysteresis recovers to its initial state. Through this cyclical process, the material can achieve ultra-high durability characteristics. However, current research on improving the durability of FeFETs using AFE materials is limited by the unipolar transport characteristics of conventional transistors, restricting the use of single-branch hysteresis and making it difficult to leverage the self-healing effect to enhance durability. These limitations hinder the application of FeFET-based CIMs in edge-side artificial intelligence devices. Summary of the Invention

[0005] To address the problems in the prior art described above, the present invention aims to propose a bipolar transport antiferroelectric field-effect transistor, comprising a semiconductor channel (or semiconductor pin junction) with bipolar transport characteristics and a hafnium zirconium oxide antiferroelectric material with a self-healing effect, which is expected to achieve ultra-high durability characteristics and provide a promising solution for edge-side artificial intelligence devices based on FeFET-based CIM.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A bipolar transport antiferroelectric field-effect transistor (AAFET) includes a gate, a source, a drain, an antiferroelectric gate stack, and a semiconductor layer, wherein the antiferroelectric gate stack is made of hafnium zirconium oxide antiferroelectric material or zirconium oxide material with a zirconium doping ratio of more than 50%, and the semiconductor layer is a semiconductor channel or semiconductor pin junction with bipolar transport characteristics.

[0008] Furthermore, the antiferroelectric field-effect transistor adopts a metal-antiferroelectric-semiconductor structure (MFS), a metal-antiferroelectric-channel-side dielectric-semiconductor structure (MFIS), or a metal-antiferroelectric-metal-channel-side dielectric-semiconductor structure (MFMIS).

[0009] In the antiferroelectric field-effect transistor of the present invention, the hafnium zirconium oxide antiferroelectric material or zirconium oxide material constituting the antiferroelectric gate stack with a zirconium doping ratio of more than 50% has a self-healing effect.

[0010] In the antiferroelectric field-effect transistor of the present invention, the semiconductor channel or semiconductor pin junction has bipolar transport characteristics. The bipolar transport characteristics refer to the semiconductor forming a conductive state with electrons as the majority carriers in the gate voltage range above the off-state voltage, and a conductive state with holes as the majority carriers in the gate voltage range below the off-state voltage, under transistor gate voltage regulation; the off-state voltage of the bipolar transport characteristics is 0.

[0011] Furthermore, the semiconductor channel may be one or more of the following materials: oxide semiconductor material, two-dimensional semiconductor material, carbon nanotube material, semiconductor nanowire material, quantum dot semiconductor material, perovskite semiconductor material, organic semiconductor material, or coordination polymer semiconductor material. The oxide semiconductor material can be tin monoxide (SnO); the two-dimensional semiconductor material can be molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), molybdenum distelluride (MoTe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), rhenium diselenide (ReSe2), palladium diselenide (PdSe2), black phosphorus, phosphorene, indium selenide (InSe), or two-dimensional tellurium; the carbon nanotube material can be a semiconductor-type single-walled carbon nanotube; the semiconductor nanowire material can be silicon nanowires, indium arsenide nanowires, indium antimonide nanowires, indium gallium arsenide nanowires, or lead selenide nanowires; the quantum dot semiconductor material can be lead sulfide quantum dots, lead selenide quantum dots, or black phosphorus quantum dots; the perovskite semiconductor material can be methylammonium lead iodide perovskite (MAPbI3), chlorine-doped methylammonium lead iodide perovskite (MAPbI3), or chlorine-doped methylammonium lead iodide perovskite (MAPbI3). 3-x Cl x ), formamidinium / methylammonium / cesium trication lead halide perovskite (FA / MA / Cs mixed cationic perovskite) or phenethylamine tin iodide perovskite ((PEA)2SnI4); the organic semiconductor material can be pentacene, rubrene, fullerene (C 60 The coordination polymer semiconductor material may be a copper-benzene hexathiol coordination polymer (Cu-BHT).

[0012] In the semiconductor pin junction, the p region is heavily p-type doped, the i region is lightly p-type or lightly n-type doped, and the n region is heavily n-type doped.

[0013] Furthermore, during a wide range of forward and reverse scans of the gate voltage (-V W → V W → -V W V W (For the erase / write gate voltage amplitude), the transport characteristics (transfer curve) of the AAFET have one hysteresis in each of the first and second quadrants, and the two hysteresis branches are independent and do not overlap (see...). Figure 1 It has the following characteristics:

[0014] 1) The counterclockwise hysteresis in the first quadrant corresponds to the positive polarity hysteresis of the AFE and the n-branch in the bipolar transport characteristics; in the positive polarity hysteresis of the AFE, the high polarization state corresponds to the threshold of the AAFET being V. th,H+ The threshold value of the AAFET corresponding to the low polarization state is V. th,L+ When V is applied to the gate of an AAFET m Time (V) m > 0 (a voltage parameter), the on-state current I corresponds to the high polarization state with positive hysteresis. on (Stored data "1"), the low polarization state of positive polarity hysteresis corresponds to the off-state current I. off (Store data "0"), satisfying ;

[0015] 2) The clockwise hysteresis in the second quadrant corresponds to the negative polarity hysteresis of the AFE and the p-branch in the bipolar transport characteristics; in the negative polarity hysteresis of the AFE, the high polarization state corresponds to the threshold of the AAFET being V. th,H- The threshold value of the AAFET corresponding to the low polarization state is V. th,L- When -V is applied to the gate of an AAFET m At that time, the high polarization state with negative hysteresis corresponds to the off-state current I. off (Stored data "0"), the low polarization state with negative hysteresis corresponds to the on-state current I. on (Store data "1");

[0016] The voltage parameters described above satisfy -V W < V th,H- < -V m < V th,L- < 0 < V th,H+ < V m < V th,L+ < V W .

[0017] Furthermore, when the antiferroelectric field-effect transistor is used as a memory, it periodically alternates between two hysteresis loops during data writing. Utilizing the self-recovery effect of the AFE material, it is expected to achieve ultra-high durability characteristics (see...). Figure 2First, apply a positive erase / write gate voltage (biased to V). m The overall range is 0 ~ V W Using first-quadrant hysteresis for data writing, after N1 cycles, the first-quadrant hysteresis becomes fatigued, causing V to... th,H+ or V th,L+ This causes drift, making V m Current switching ratio under gate voltage I on / I off Degradation occurs; thereafter, a negative polarity erase / write gate voltage (biased to -V) is applied. m The overall range is -V W ~0) Using second-quadrant hysteresis for data writing, after applying N2 cycles, the second-quadrant hysteresis becomes fatigued, causing V to... th,H- or V th,L- This causes a drift, making -V m Current switching ratio under gate voltage I on / I off Degeneration occurs, and V th,H+ With V th,L+ All values ​​have been restored to their initial values; thereafter, a positive polarity erase / write gate voltage (biased to V) is applied. m The overall range is 0 ~ V W Using first-quadrant hysteresis for data writing, after applying N3 cycles, the first-quadrant hysteresis becomes fatigued, causing V to... th,H+ or V th,L+ This causes drift, making V m Current switching ratio under gate voltage I on / I off Degeneration occurs, and V th,H- With V th,L- All have been restored to their initial values... and so on. N1, N2, and N3 are all positive integers.

[0018] Furthermore, when the antiferroelectric field-effect transistor is used as a memory for data readout: if the first quadrant hysteresis is being used, a V0 is applied at the gate terminal. m A constant voltage V is applied to the drain terminal. DD Ground the source terminal and sense the source leakage current. If the current is I... on The stored data is "1" if the current is I. off The stored data is "0"; if second quadrant hysteresis is being used, -V is applied at the gate. m A constant voltage V is applied to the drain terminal. DD Ground the source terminal and sense the source leakage current. If the current is I... on The stored data is "1" if the current is I. off Then the stored data is "0".

[0019] Based on the above methods, the AAFET memory device is expected to achieve ultra-high durability characteristics and can be used to form ferroelectric transistors or embedded dynamic random access memory. In-memory computing technology based on this type of memory can enable on-chip training tasks of edge artificial intelligence devices.

[0020] The beneficial technical effects of this invention are as follows:

[0021] This invention employs a semiconductor channel or semiconductor pin junction with bipolar transport characteristics, and uses hafnium zirconium oxide (AFE) material with self-healing durability as the gate layer to construct an antiferroelectric field-effect transistor (AAFET) with bipolar transport characteristics. By periodically alternating the use of two hysteresis loops of different polarities of the AFE material and applying different read gate voltages during data writing, this invention is expected to achieve ultra-high durability characteristics, providing a highly promising solution for edge-side artificial intelligence devices. Attached Figure Description

[0022] Figure 1 This is a schematic diagram illustrating the structure and principle of the bipolar transport antiferroelectric field-effect transistor described in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram illustrating the principle of the bipolar transport antiferroelectric field-effect transistor described in this embodiment of the invention, which periodically alternates between two hysteresis loops during data writing. Detailed Implementation

[0024] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.

[0025] The structure and principle of the bipolar transport antiferroelectric field-effect transistor (AAFET) in this embodiment are as follows: Figure 1 As shown: This AAFET employs a metal-antiferroelectric-semiconductor structure; its antiferroelectric (AFE) gate stack uses hafnium zirconium oxide material with a zirconium doping ratio higher than 50%; the semiconductor layer is a semiconductor channel or semiconductor pin junction with bipolar transport characteristics; the off-state voltage of the bipolar transport characteristics is 0. When performing gate voltage (V... g During a wide range of forward and reverse scans (-V) W → V W → -V W V W (For the erase / write gate voltage amplitude), the transfer curve of the AAFET has one hysteresis in the first quadrant and one in the second quadrant, and the two hysteresis branches are independent and do not overlap; the counterclockwise hysteresis in the first quadrant corresponds to the positive polarity hysteresis of the AFE and the nth branch in the bipolar transport characteristic; in the positive polarity hysteresis of the AFE, the high polarization state corresponds to the threshold of the AAFET being V. th,H+ The threshold value of the AAFET corresponding to the low polarization state is V. th,L+ When V is applied to the gate of an AAFETm Time (V) m > 0 (a voltage parameter), the on-state current I corresponds to the high polarization state with positive hysteresis. on (Stored data "1"), the low polarization state of positive polarity hysteresis corresponds to the off-state current I. off (Store data "0"), satisfying The clockwise hysteresis in the second quadrant corresponds to the negative polarity hysteresis of the AFE and the p-branch in the bipolar transport characteristic; in the negative polarity hysteresis of the AFE, the high polarization state corresponds to the threshold V of the AAFET. th,H- The threshold value of the AAFET corresponding to the low polarization state is V. th,L- When -V is applied to the gate of an AAFET m At that time, the high polarization state with negative hysteresis corresponds to the off-state current I. off (Stored data "0"), the low polarization state with negative hysteresis corresponds to the on-state current I. on (Store data "1"); The voltage parameters mentioned above satisfy -V W < V th,H- < -V m < V th,L- < 0 < V th,H+ < V m < V th,L+ < V W .

[0026] The principle of the bipolar transport antiferroelectric field-effect transistor in this embodiment, which periodically alternates between the two hysteresis loops during data writing, is as follows: Figure 2 As shown: First, a positive erase / write gate voltage (biased to V) is applied to the AAFET. m The overall range is 0 ~ V W Using first-quadrant hysteresis for weight updates, after N1 iterations, first-quadrant hysteresis becomes fatigued, causing V to... th,H+ or V th,L+ This causes drift, making the current switch more sensitive than I. on / I off Degradation occurs; thereafter, a negative polarity erase / write gate voltage (biased to -V) is applied. m The overall range is -V W ~0) Using second-quadrant hysteresis for weight updates, after applying N2 cycles, the second-quadrant hysteresis becomes fatigued, leading to V th,H- or V th,L- This causes drift, making the current switch more sensitive than I. on / I off Degeneration occurs, and V th,H+ With V th,L+ All values ​​have been restored to their initial values; thereafter, a positive polarity erase / write gate voltage (biased to V) is applied. mThe overall range is 0 ~ V W Using first-quadrant hysteresis for weight updates, after applying N3 cycles, the first-quadrant hysteresis becomes fatigued, leading to V... th,H+ or V th,L+ This causes drift, making the current switch more sensitive than I. on / I off Degeneration occurs, and V th,H- With V th,L- All have been restored to their initial values... and so on. N1, N2, and N3 are all positive integers.

[0027] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A bipolar transport antiferroelectric field-effect transistor, comprising a gate terminal, a source terminal, a drain terminal, an antiferroelectric gate stack, and a semiconductor layer, characterized in that, The antiferroelectric gate stack is made of hafnium zirconium oxide antiferroelectric material or zirconium oxide material with a zirconium doping ratio of more than 50%. The semiconductor layer is a semiconductor channel or semiconductor pin junction with bipolar transport characteristics. The transfer characteristic curve of the antiferroelectric field-effect transistor has one hysteresis in the first quadrant and one in the second quadrant, and the two hysteresis branches are independent of each other and do not overlap.

2. The antiferroelectric field-effect transistor as described in claim 1, characterized in that, Under the gate voltage regulation of the transistor, the semiconductor layer forms a conductive state with electrons as the majority carriers in the gate voltage range above the off-state voltage, and a conductive state with holes as the majority carriers in the gate voltage range below the off-state voltage; the off-state voltage is 0.

3. The antiferroelectric field-effect transistor as described in claim 1, characterized in that, The antiferroelectric field-effect transistor adopts a metal-antiferroelectric-semiconductor structure, a metal-antiferroelectric-channel-side dielectric-semiconductor structure, or a metal-antiferroelectric-metal-channel-side dielectric-semiconductor structure.

4. The antiferroelectric field-effect transistor as described in claim 1, characterized in that, The semiconductor channel is made of one or more of the following materials: oxide semiconductor material, two-dimensional semiconductor material, carbon nanotube material, semiconductor nanowire material, quantum dot semiconductor material, perovskite semiconductor material, organic semiconductor material, or coordination polymer semiconductor material.

5. The antiferroelectric field-effect transistor as described in claim 4, characterized in that, The oxide semiconductor material is tin monoxide; the two-dimensional semiconductor material is molybdenum disulfide, molybdenum diselenide, molybdenum distelluride, tungsten disulfide, tungsten diselenide, rhenium diselenide, palladium diselenide, black phosphorus, phosphorene, indium selenide, or two-dimensional tellurium; the carbon nanotube material is a semiconductor-type single-walled carbon nanotube; the semiconductor nanowire material is silicon nanowire, indium arsenide nanowire, indium antimonide nanowire, indium gallium arsenide nanowire, or lead selenide nanowire; the quantum dot semiconductor material is lead sulfide quantum dots, lead selenide quantum dots, or black phosphorus quantum dots. The perovskite semiconductor material is methylammonium lead-iodide perovskite, chlorine-doped methylammonium lead-iodide perovskite, formamidinium / methylammonium / cesium trication lead halide perovskite, or phenethylamine tin-iodide perovskite; the organic semiconductor material is pentacene, rubrene, fullerene, fullerene derivatives, copper phthalocyanine, iron phthalocyanine, indigo, Thiol violet, diketopyrrolopyrroles, isoindigo compounds, naphthimides, perylene diimides, or benzodifurandione organic semiconductors; the coordination polymer semiconductor material is a copper-benzenehexathiol coordination polymer.

6. The antiferroelectric field-effect transistor as described in claim 1, characterized in that, In the semiconductor pin junction, the p region is heavily p-type doped, the i region is lightly p-type or lightly n-type doped, and the n region is heavily n-type doped.

7. The antiferroelectric field-effect transistor as described in claim 1, characterized in that, During the wide range of gate voltage -V W →V W → -V W During forward and reverse scanning, the transfer characteristic curves of the antiferroelectric field-effect transistor have the following characteristics: 1) The counterclockwise hysteresis in the first quadrant corresponds to the n-branch of the positive polarity hysteresis and bipolar transport characteristics of antiferroelectricity; in the positive polarity hysteresis of antiferroelectricity, the high polarization state corresponds to the threshold voltage of the antiferroelectric field-effect transistor being V. th,H+ The threshold voltage of the antiferroelectric transistor corresponding to the low polarization state is V. th,L+ When V is applied to the gate terminal of an antiferroelectric field-effect transistor m At that time, the highly polarized state with positive polarity hysteresis corresponds to the on-state current I. on The low polarization state of positive polarity hysteresis corresponds to the off-state current I. off ,satisfy ; 2) The clockwise hysteresis in the second quadrant corresponds to the negative polarity hysteresis of antiferroelectricity and the p-branch in the bipolar transport characteristic; in the negative polarity hysteresis of antiferroelectricity, the high polarization state corresponds to the threshold voltage of the antiferroelectric field-effect transistor being V. th,H- The threshold voltage of the antiferroelectric transistor corresponding to the low polarization state is V. th,L- When a -V is applied to the gate terminal of an antiferroelectric transistor m At that time, the high polarization state with negative hysteresis corresponds to the off-state current I. off The low polarization state with negative hysteresis corresponds to the on-state current I. on ; Among them, V W V represents the erase / write grid voltage amplitude. m > 0 indicates a voltage parameter; -V W < V th,H- < -V m < V th,L- < 0 <V th,H+ < V m < V th,L+ < V W .

8. The application of the antiferroelectric field-effect transistor according to any one of claims 1 to 7 as a memory, characterized in that, During data writing, the antiferroelectric field-effect transistor periodically alternates between the two hysteresis loops, utilizing the self-recovery effect of the antiferroelectric gate stack material to achieve high durability.

9. The application as described in claim 8, characterized in that, Apply bias V m The overall range is 0 ~ V W The positive polarity erase / write gate voltage uses first-quadrant hysteresis for data writing. After N1 cycles, the first-quadrant hysteresis becomes fatigued, causing the threshold voltage V of the antiferroelectric transistor corresponding to the high polarization state in the positive polarity hysteresis to decrease. th,H+ Or the threshold voltage V of the antiferroelectric field-effect transistor corresponding to the low polarization state th,L+ This causes drift, making V m Current switching ratio under gate voltage I on / I off Degradation occurs; thereafter, the bias is changed to -V. m The overall range is -V W A negative polarity erase / write gate voltage of ~0 is used for data writing with second-quadrant hysteresis. After N2 cycles, fatigue occurs in the second-quadrant hysteresis, causing the threshold voltage V of the antiferroelectric transistor corresponding to the high polarization state in the negative polarity hysteresis to decrease. th,H- Or the threshold voltage V of the antiferroelectric field-effect transistor corresponding to the low polarization state th,L- This causes a drift, making -V m Current switching ratio under gate voltage I on / I off Degeneration occurs, and V th,H+ With V th,L+ All have been restored to their initial values; thereafter, a bias of V is applied instead. m The overall range is 0 ~ V W The positive polarity erase / write gate voltage uses first-quadrant hysteresis for data writing. After N3 cycles, the first-quadrant hysteresis fatigues, causing V to... th,H+ or V th,L+ This causes drift, making V m Current switching ratio under gate voltage I on / I off Degeneration occurs, and V th,H- With V th,L- All have been restored to their initial values...and so on, where N1, N2, and N3 are all positive integers; V W V represents the erase / write grid voltage amplitude. m > 0 indicates a voltage parameter; -V W < V th,H- < -V m < V th,L- < 0 < V th,H+ < V m < V th,L+ <V W .

10. The application as described in claim 9, characterized in that, When reading data, if the antiferroelectric transistor is using first-quadrant hysteresis, a V0 is applied at the gate terminal. m A constant voltage V is applied to the drain terminal. DD Ground the source terminal and sense the source leakage current. If the current is I... on The stored data is "1" if the current is I. off The stored data is "0"; if the antiferroelectric field-effect transistor is using second quadrant hysteresis, then -V is applied to the gate terminal. m A constant voltage V is applied to the drain terminal. DD Ground the source terminal and sense the source leakage current. If the current is I... on The stored data is "1" if the current is I. off The stored data is "0".

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