Preparation process of high-temperature-resistant and corrosion-resistant high-sensitivity inverted pressure resistance type pressure sensor for vehicle

Abstract

The application relates to a preparation process of a high-temperature-resistant and corrosion-resistant high-sensitivity inverted pressure resistance type pressure sensor for vehicles. The application comprises the following steps: providing an SOI silicon wafer; growing a thin oxide layer on the surface of the SOI silicon wafer, and forming a light-doped P-type pressure-sensitive resistor and a heavy-doped P+ structure in contact on the upper part of the SOI silicon wafer through boron ion implantation; forming a pre-window hole on the surface of the thin oxide layer; depositing a metal layer for electrical connection on the surface of the thin oxide layer; depositing a SiO dielectric film on the surface of the thin oxide layer; preparing top silicon and a recess absolute pressure cavity on the top silicon, and bonding the top silicon and the SiO dielectric film; preparing a TSV through hole extending to the surface of the metal layer on the top silicon; growing an insulating layer on the inner wall of the TSV through hole, and preparing a PAD electrical connection structure electrically connected with the metal layer on the surface of the insulating layer; forming a pressure receiving cavity on the back surface of the SOI silicon wafer; and inversely packaging the micro sensor chip on a PCB substrate through micro tin balls to form electrical connection. The application realizes high-reliability, corrosion-resistance and high-pressure-resistant pressure sensor detection.

Description

Technical Field

[0001] This invention relates to the field of micro pressure sensor chips and semiconductor packaging technology, and in particular to a manufacturing process for a high-temperature resistant, corrosion-resistant, and highly sensitive flip-chip piezoresistive pressure sensor for automotive applications. Background Technology

[0002] Piezoresistive pressure sensors, with their advantages of simple structure, high sensitivity, fast response speed, and controllable cost, are widely used in industrial fluid detection, medical equipment, and intelligent sensing. With the rapid development of interventional medicine, miniature precision pneumatics, and hydraulic systems, the market has placed extremely high demands on the miniaturization, corrosion resistance, and high-pressure resistance of pressure sensors. This is especially true for interventional medical catheters and miniature precision pipelines, where the sensor chip diameter must be strictly controlled within 0.5mm. Furthermore, these sensors must be able to withstand long-term contact with human bodily fluids and corrosive fluid media, and withstand high-pressure fluid impacts to ensure detection stability and service life. Meanwhile, automotive applications place high demands on the overall performance of pressure sensors. Limited installation space within automobiles necessitates compact sensor mounting locations, requiring pressure sensors with small package sizes and high integration.

[0003] Currently, traditional piezoresistive pressure sensor chips generally adopt a structure design with front-side wiring and front-side pads, where both the electrode metal wiring and pads are located on the front side of the sensor's sensitive membrane. This structure has significant technical drawbacks: Firstly, the front-side wiring and pads occupy a large amount of the chip's effective area, significantly compressing the space for the sensitive film layout. The effective sensitive area accounts for less than 60%, which limits chip miniaturization. The diameter of conventional chips is difficult to break through the 0.5mm limit, making it impossible to adapt to the installation requirements of ultra-micro conduits and micro pipes. Secondly, the exposed metal electrodes are prone to oxidation, corrosion, and electrochemical erosion when in contact with bodily fluids or corrosive acid and alkali media, leading to electrode open circuits, signal drift, and sensor failure. To solve the corrosion problem, traditional solutions require depositing an insulating protective layer on the front side. However, the insulating layer will cover the surface of the sensitive film, reducing the pressure sensing sensitivity, while increasing the process complexity and manufacturing cost. Moreover, the insulating layer is prone to peeling and cracking after long-term use, resulting in poor protection reliability. Third, traditional sensors use wire bonding packaging technology. The gold wire leads have parasitic parameters that can interfere with the detection of weak pressure electrical signals. At the same time, the leads are susceptible to breakage due to vibration and bending. They also have poor high pressure resistance and fatigue resistance, making them unsuitable for micro high pressure and high frequency operating scenarios. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problems of front-side wiring of micro pressure sensor chips, large area occupied by solder pads, high difficulty in miniaturization, easy damage to exposed electrodes by body fluids and corrosive media, and the need for additional insulating protective layers in the prior art.

[0005] To solve the above-mentioned technical problems, the present invention provides a manufacturing process for a high-temperature resistant, corrosion-resistant, and highly sensitive flip-chip piezoresistive pressure sensor for automobiles, comprising: The SOI silicon wafer includes a support silicon wafer, a buried oxide insulating layer and a donor silicon wafer arranged sequentially from bottom to top. A thin oxide layer is grown on the surface of the SOI silicon wafer, and a lightly doped P-type varistor and a heavily doped P+ structure are formed in contact on the upper part of the SOI silicon wafer by boron ion implantation. Pre-opened windows are formed on the surface of the thin oxide layer; A metal layer for electrical connection is deposited on the surface of the thin oxide layer, and the metal layer is in contact with the heavily doped P+ structure through the pre-opened window; A SiO dielectric film is deposited on the surface of the thin oxide layer; A top silicon and a grooved pressure-absorbing cavity located on the top silicon are prepared, and the top silicon is bonded to the SiO dielectric film; TSV vias extending to the surface of the metal layer are formed on the top silicon layer; An insulating layer is grown on the inner wall of the TSV via, and a PAD electrical connection structure electrically connected to the metal layer is prepared on the surface of the insulating layer. The pressure-sensitive layer is released by etching on the back side of the SOI silicon wafer, and the buried oxide insulating layer is used as the etching stop layer to form a pressure-bearing cavity through patterning. Micro-solder balls are fabricated on the PAD electrical connection structure, and a micro-sensor chip is flip-chip packaged onto a PCB substrate through the micro-solder balls to form an electrical connection.

[0006] In one embodiment of the present invention, the preparation steps of the SOI silicon wafer include: A support silicon wafer with atomic-level polishing precision is provided. The support silicon wafer is subjected to high-temperature thermal oxidation to form a SiO2 layer on the surface of the support silicon wafer. The SiO2 layer serves as a buried oxide insulating layer and as a barrier layer for subsequent backside ICP etching. The thickness of the SiO2 layer is 2μm to 30μm. A donor silicon wafer with an atomic-level polishing precision is provided. The donor silicon wafer is then polished and thinned to a preset thickness, wherein the thickness of the thinned donor silicon wafer is between 5 μm and 80 μm. The supporting silicon wafer and the donor silicon wafer are cleaned to remove surface particles, metallic impurities and organic contaminants, and to ensure a clean bonding interface. Hydrogen ions are implanted into the donor silicon wafer at a predetermined depth to form a hydrogen-rich damage layer inside the wafer. This hydrogen-rich damage layer serves as a predetermined fracture surface for subsequent peeling. The hydrogen ion implantation energy is between 10 keV and 100 keV, and the implantation dose is 1 × 10⁻⁶. 15 cm -2 ~1×10 20 cm -2 The thickness of the subsequently formed top silicon layer ranges from 2μm to 50μm; The injection surface of the donor silicon wafer is bonded to the surface of the buried oxide insulating layer on the supporting silicon wafer at room temperature, and a pre-bonded structure is formed by van der Waals forces. The pre-bonded structure is subjected to low-temperature annealing, which causes hydrogen ions in the hydrogen enrichment damage layer to aggregate and form microbubbles. The stress generated after the microbubbles grow and merge along the hydrogen enrichment damage layer peels off the excess substrate of the donor silicon wafer, resulting in an SOI initial product with a rough top silicon layer. The low-temperature annealing temperature is between 200°C and 500°C. The top silicon layer of the SOI precursor is subjected to wet etching to remove the residual damage layer on the surface of the top silicon layer, and then the top silicon layer is subjected to chemical mechanical polishing to obtain an SOI silicon wafer. The surface roughness of the top silicon layer after chemical mechanical polishing is less than or equal to 0.1 nm, and the thickness deviation is controlled within ±5 nm. The SOI silicon wafer is sequentially cleaned, defect-detected, and thinned. During cleaning, the SOI silicon wafer is ultrasonically treated in anhydrous ethanol, acetone, and deionized water for 30 to 60 minutes respectively. Then, the SOI silicon wafer is placed on a hot plate and heated at 100°C for 30 minutes. After the thinning treatment, the thickness of the SOI silicon wafer is 350 μm to 450 μm.

[0007] In one embodiment of the present invention, a thin oxide layer is grown on the surface of the SOI silicon wafer, and a lightly doped P-type varistor and a heavily doped P+ structure in contact are formed on the upper part of the SOI silicon wafer by boron ion implantation, including: SOI silicon wafers are placed in an oxidation furnace and a thin oxide layer is formed by dry oxidation growth. The dry oxidation temperature is 700℃~1200℃, the time is 30 minutes~90 minutes, and the thickness of the thin oxide layer is 10nm~100nm. Boron ions are implanted into an SOI silicon wafer with the thin oxide layer to form the lightly doped P-type varistor, wherein the boron ion implantation energy is between 50 keV and 130 keV, and the implantation dose is 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 ; Boron ions are implanted into an SOI silicon wafer on which the lightly doped P-type varistor is formed to form a heavily doped P+ structure in contact with the lightly doped P-type varistor. The implantation energy of the boron ions is between 30 keV and 80 keV, and the implantation dose is 3 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 .

[0008] In one embodiment of the present invention, pre-opened windows are formed on the surface of the thin oxide layer, including: The cavity is pretreated by evacuating the etching cavity and then purging it with argon gas to remove residual impurities and stabilize the etching environment. The vacuum level of the etching cavity is between 5 mTorr and 10 mTorr. Before the process gas ignition is prepared, the main etching gas CF4 and the auxiliary gas O2 are introduced into the etching chamber to form a process atmosphere suitable for the etching of the thermal oxidative layer. The gas flow rate of CF4 is 80 sccm~120 sccm, the gas flow rate of O2 is 10 sccm~20 sccm, and the chamber pressure is 15 mTorr~30 mTorr. Radio frequency (RF) ignition etching is performed to form plasma from CF4 and O2 under RF action. The plasma is used to perform anisotropic etching on the thermo-oxidative layer. The etching endpoint is controlled by an endpoint detection system to prevent over-etching of the silicon substrate while forming pre-opened holes. The RF power is 300W~500W and the etching rate is 80Å / min~120Å / min. After purging the chamber and shutting off the process gas, high-purity nitrogen is introduced into the etching chamber to purge it and remove the byproducts generated during the etching process.

[0009] In one embodiment of the present invention, a metal layer for electrical connection is deposited on the surface of the thin oxide layer, comprising: The deposition chamber is evacuated to obtain the background vacuum environment required for metal layer deposition, wherein the background vacuum of the deposition chamber is 5 × 10⁻⁶. -7 Torr; High-purity Ar is introduced into the deposition chamber as a process gas, and the chamber pressure is kept stable. The flow rate of the high-purity Ar is 30 sccm to 60 sccm, and the chamber pressure is 3 mTorr to 8 mTorr. Turn on the RF power supply or DC power supply and perform pre-sputtering treatment on the metal target to clean the surface of the metal target and remove the oxide layer and impurities on the surface of the metal target. The pre-sputtering treatment time is 5 min to 10 min. The wafer is moved to the process position and formal sputtering deposition is performed on the surface of the thin oxide layer to form the metal layer, wherein the DC power is 800W~1200W, the substrate temperature is 25℃~80℃, the deposition rate is 300Å / min~500Å / min, and the deposition time is 1min~30min. After deposition is complete, the power supply and Ar gas are turned off, and high-purity nitrogen is introduced into the deposition chamber for purging to remove residual plasma and dust.

[0010] In one embodiment of the present invention, a SiO dielectric film is deposited on the surface of the thin oxide layer, comprising: The wafer is fed into the PECVD deposition chamber, and the PECVD deposition chamber is subjected to vacuuming and heating treatment, wherein the vacuum degree of the PECVD deposition chamber reaches 10. -6 Torr level, chamber temperature is 350℃~400℃; SiH4, NH3 and O2 are introduced into the PECVD deposition chamber as a mixed process gas, wherein the flow rate of SiH4 is controlled at 20 sccm to 40 sccm, the flow rate of NH3 is controlled at 30 sccm to 50 sccm, and the flow rate of O2 is controlled at 50 sccm to 80 sccm. The mixed process gas is reacted under the action of plasma and a SiO dielectric film is deposited on the surface of the thin oxide layer. The cavity pressure of the PECVD deposition chamber is 2 Torr~5 Torr and the radio frequency power is 200W~400W. The deposition process of the SiO dielectric film is controlled to achieve the target thickness, wherein the deposition rate of the SiO dielectric film is between 100 Å / min and 200 Å / min, and the thickness of the SiO dielectric film is between 0.1 μm and 5 μm.

[0011] In one embodiment of the present invention, the fabrication of a top silicon layer and a recessed pressure-absorbing cavity located on the top silicon layer includes: A silicon wafer is provided, and the silicon wafer is cleaned and dried. A photoresist coating process is performed, in which positive photoresist is uniformly coated on the surface of the silicon wafer, wherein the coating speed is 3000rpm~4000rpm and the photoresist layer thickness is 1.2μm~1.8μm; The silicon wafer after uniformly coating with positive photoresist is pre-baked to remove the solvent in the positive photoresist. The pre-baking temperature is 100℃~110℃ and the pre-baking time is 90s. The positive photoresist is exposed using a recessed absolute pressure cavity pattern to form an exposure pattern corresponding to the recessed absolute pressure cavity, wherein the exposure dose is 120 mJ / cm².2 ~180mJ / cm 2 ; After exposure, the silicon wafer is subjected to a post-bake treatment, wherein the post-bake treatment temperature is 110°C and the post-bake treatment time is 60s; The silicon wafer, after post-baking, is immersed in a developing solution for development, and then rinsed with deionized water and dried to transfer the groove absolute pressure cavity pattern to the surface of the silicon wafer. The development time is 40s to 60s.

[0012] In one embodiment of the present invention, a TSV via extending to the surface of the metal layer is formed on the top silicon, comprising: The top silicon is pretreated by evacuating the etching chamber and then introducing argon gas for short-term plasma cleaning to remove microparticles and the native oxide layer on the surface of the top silicon. The vacuum degree of the etching chamber is within 8 mTorr. A thick photoresist is spin-coated onto the top silicon surface and then pre-baked. The spin-coating speed is 2500 rpm to 3500 rpm, the photoresist layer thickness is 3.0 μm to 5.0 μm, the pre-baking temperature is 105℃, and the pre-baking time is 120 s. The thick photoresist is exposed according to the TSV via pattern using a stepper lithography machine, and then post-baking and developing are performed to form the TSV via windows. The exposure dose is 150 mJ / cm². 2 ~200mJ / cm 2 The post-baking temperature is 110℃, the post-baking time is 90s, and the developing time is 50s~70s; The wafer with the TSV via window formed is transferred to the DRIE etching process, and the top silicon is etched using the Bosch alternating etching process, wherein the cavity pressure of the Bosch alternating etching process is 18 mTorr~28 mTorr. SF6 is introduced during the etching stage, and C4F8 is introduced during the passivation stage. By alternating between the etching and passivation stages, TSV vias extending to the surface of the metal layer are formed on the top silicon. The flow rate of SF6 is 120 sccm to 180 sccm, the RF power of the etching stage is 500W to 700W, the flow rate of C4F8 is 80 sccm to 120 sccm, the aspect ratio of the TSV via is greater than or equal to 1:3, and the aperture of the TSV via is 10μm to 200μm. After etching, the wafer is subjected to wet photoresist removal and plasma residue removal to remove residual photoresist and etching residue inside and outside the TSV vias.

[0013] In one embodiment of the present invention, an insulating layer is grown on the inner wall of the TSV via, and a PAD electrical connection structure electrically connected to the metal layer is prepared on the surface of the insulating layer, including: Dry oxygen is introduced into the furnace tube to grow an insulating layer on the inner wall of the TSV through-hole, wherein the dry oxidation temperature is 950℃~1050℃ and the thickness of the insulating layer is 0.5μm~1μm. SnAg alloy metal is prepared by evaporation process and then patterned by photolithography to form PAD electrical connection structure, which is electrically connected to the metal layer.

[0014] In one embodiment of the present invention, micro-solder balls are fabricated on the PAD electrical connection structure, and a micro-sensor chip is flip-chip packaged onto a PCB substrate through the micro-solder balls to form an electrical connection, including: The wafers that have completed the previous process are cleaned and dried, and then sent to the ball-mounting process. The chip pad area where the PAD electrical connection structure is located is subjected to surface pretreatment to remove the oxide layer and organic impurities on the surface of the chip pad area and improve the adhesion of the subsequent plating layer. The surface pretreatment is carried out by Ar atmosphere plasma cleaning with a cleaning power of 200W, a chamber pressure of 10mTorr, and a cleaning time of 60s. A passivation layer is formed on the PAD electrical connection structure and the surrounding dielectric surface, and the passivation layer is photolithographically windowed to expose the pad window corresponding to the PAD electrical connection structure. Selective electroplating is performed on the pad windows to deposit a tin layer on the PAD electrical connection structure. The selective electroplating uses a tin methanesulfonate plating solution at a temperature of 25±2℃ and a current density of 1.5A / dm³. 2 ~2.5A / dm 2 The electroplating time is 80s~150s; After electroplating, the photoresist is wet-stripped and the tin layer is pre-melted by hot air leveling to preliminarily adjust the morphology of the tin layer. The wafer is fed into a reflow oven for reflow processing, causing the tin layer to shrink into a spherical shape under the action of surface tension, thereby forming micro tin balls. The reflow process includes passing through a preheating zone, a constant temperature zone, and a peak temperature zone in sequence. The temperature of the preheating zone is 120℃~150℃ and the holding time is 90s. The temperature of the constant temperature zone is 180℃~200℃ and the holding time is 60s. The temperature of the peak temperature zone is 230℃~240℃ and the holding time is 40s. Nitrogen gas is introduced as a protective gas during the reflow process to suppress high-temperature oxidation of the tin layer and to form standard spherical micro-tin balls. The wafer with the micro-solder balls formed is subjected to flux cleaning and drying treatment to remove residual flux from the surface; The micro-sensor chip is reflow soldered to the PCB substrate through the micro-solder balls, so that the PAD electrical connection structure forms a leadless electrical connection with the PCB substrate through the micro-solder balls.

[0015] The technical solution of the present invention has the following advantages compared with the prior art: This invention discloses a manufacturing process for a high-temperature, corrosion-resistant, and highly sensitive flip-chip piezoresistive pressure sensor for automotive applications. The TSV vertical interconnect allows the electrical signal to be led out from the back side, eliminating the need for wiring and metal pads on the sensitive front side. This increases the effective sensitive area ratio and reduces the impact of corrosive media on the metal electrodes. The leadless packaging method avoids the risk of gold wire breakage associated with traditional gold wire bonding packaging. By leading the electrodes out from the back of the chip through the TSV vertical interconnect structure, and eliminating wiring and pads on the front side, the effective area of ​​the chip is completely freed up, increasing the effective sensitive area ratio to over 95%, a significant improvement compared to the traditional ratio of less than 60%. This perfectly adapts to the ultra-small installation space requirements of interventional medical catheters and miniature precision tubes.

[0016] This invention addresses the high reliability requirements of the automotive industry by employing a leadless packaging structure, which reduces package size and is more suitable for compact, high-reliability automotive applications. Attached Figure Description

[0017] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0018] Figure 1 This is a flowchart illustrating the manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles, as described in this invention.

[0019] Figure 2 This is a schematic diagram of the structure of the SOI silicon wafer formed in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure formed by the thin oxide layer, lightly doped P-type varistor, heavily doped P+ structure, and pre-opened window in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the structure after the metal layer, SiO dielectric film, top silicon, and groove pressure relief cavity are formed in an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure after the TSV through-hole, SiO2 insulating layer and PAD electrical connection structure are formed in an embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the structure after the pressure cavity is released and flipped and packaged in an embodiment of the present invention.

[0024] Explanation of reference numerals on the accompanying drawings: 1. Supporting silicon wafer; 2. Buried oxide insulating layer; 3. Donor silicon wafer; 4. Thin oxide layer; 5. Lightly doped P-type varistor; 6. Heavily doped P+ structure; 7. Pre-opened window; 8. Metal layer; 9. SiO dielectric film; 10. Top silicon; 11. Groove pressure relief cavity; 12. TSV via; 13. Insulating layer; 14. PAD electrical connection structure; 15. Pressure-bearing cavity; 16. Micro solder ball; 17. PCB substrate. Detailed Implementation

[0025] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0026] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0027] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0028] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0029] Reference Figure 1 As shown, a manufacturing process for a high-temperature, corrosion-resistant, and highly sensitive flip-chip piezoresistive pressure sensor for automotive applications includes: S1. Provide an SOI silicon wafer, comprising, from bottom to top, a support silicon wafer 1, a buried oxide insulating layer 2, and a donor silicon wafer 3. (Refer to...) Figure 2 As shown, this step specifically includes: A support silicon wafer 1 with an atomic-level polishing precision is provided. The support silicon wafer 1 is subjected to high-temperature thermal oxidation to form a SiO2 layer on the surface of the support silicon wafer 1. The SiO2 layer serves as a buried oxide insulating layer 2 and as a barrier layer for subsequent backside ICP etching. The thickness of the SiO2 layer is 2μm to 30μm.

[0030] A donor silicon wafer 3 with atomic-level polishing precision is provided. The donor silicon wafer 3 is then polished and thinned to a preset thickness, wherein the thickness of the thinned donor silicon wafer 3 is between 5μm and 80μm. It should be noted that the thickness of the donor silicon wafer 3 determines the voltage withstand capability of the chip. Therefore, by polishing and thinning the donor silicon wafer 3 to a thickness of 5μm to 80μm, the thicker the top silicon wafer, the greater the voltage withstand capability of the chip.

[0031] The supporting silicon wafer 1 and the donor silicon wafer 3 are cleaned to remove surface particles, metallic impurities and organic contaminants, and to ensure that the bonding interface is clean.

[0032] Hydrogen ions are implanted into the donor silicon wafer 3 at a predetermined depth to form a hydrogen-rich damage layer inside the donor silicon wafer 3. This hydrogen-rich damage layer serves as a predetermined fracture surface for subsequent peeling. The hydrogen ion implantation energy is between 10keV and 100keV, and the implantation dose is 1×10⁻⁶. 15 cm -2 ~1×10 20 cm -2 The thickness of the top silicon layer formed subsequently ranges from 2μm to 50μm; after implantation, hydrogen ions form a continuous hydrogen-rich damage layer inside the silicon wafer, which serves as the pre-set fracture surface for subsequent peeling.

[0033] The implantation surface of the donor silicon wafer 3 is bonded to the surface of the buried oxygen insulating layer 2 on the supporting silicon wafer 1 at room temperature, and a pre-bonding structure is formed by van der Waals forces. Subsequently, the pre-bonding structure is subjected to low-temperature annealing, which causes hydrogen ions in the hydrogen-rich damaged layer to aggregate and form microbubbles. The stress generated by the growth and merging of the microbubbles peels off the excess substrate of the donor silicon wafer 3 along the hydrogen-rich damaged layer, resulting in a rough SOI preliminary product with a top silicon layer. The low-temperature annealing temperature is between 200°C and 500°C. The above process can improve the interfacial bonding strength and promote the aggregation of hydrogen ions in the hydrogen-damaged layer to form microbubbles.

[0034] The top silicon layer of the SOI precursor is subjected to wet etching to remove the residual damage layer on the surface of the top silicon layer, and then the top silicon layer is subjected to chemical mechanical polishing to obtain an SOI silicon wafer. The surface roughness of the top silicon layer after chemical mechanical polishing is less than or equal to 0.1 nm, and the thickness deviation is controlled within ±5 nm. The SOI silicon wafer is sequentially cleaned, defect-detected, and thinned. During cleaning, the SOI silicon wafer is ultrasonically treated in anhydrous ethanol, acetone, and deionized water for 30 to 60 minutes respectively. Then, the SOI silicon wafer is placed on a hot plate and heated at 100°C for 30 minutes. After the thinning treatment, the thickness of the SOI silicon wafer is 350 μm to 450 μm.

[0035] It's important to note that the core reason SOI substrates withstand high temperatures is the 8.9 eV bandgap of the buried SiO2 layer, significantly higher than the 1.12 eV of single-crystal silicon. At high temperatures, this bandgap blocks minority carrier injection from the substrate into the top silicon active region, suppressing the exponential increase in leakage current with temperature. Simultaneously, the buried oxide layer cuts off the thermal crosstalk path between the active region and the substrate, greatly reducing the risk of high-temperature latch-up. Besides high-temperature resistance, SOI substrates offer the following advantages: First, parasitic capacitance is much lower than that of bulk silicon substrates, resulting in a more than 30% increase in device switching speed and a 40% reduction in power consumption, making them suitable for high-frequency, low-power applications. Second, they provide natural dielectric isolation, eliminating the need for additional well isolation and achieving complete device isolation, leading to higher integration density. Third, they exhibit excellent radiation resistance and low leakage current, making them suitable for extreme environments such as aerospace.

[0036] S2. A thin oxide layer 4 is grown on the surface of the SOI silicon wafer, and a lightly doped P-type varistor 5 and a heavily doped P+ structure 6 are formed in contact on the upper part of the SOI silicon wafer by boron ion implantation. (Refer to...) Figure 3 As shown, this step specifically includes: The SOI silicon wafer is placed in an oxidation furnace and a thin oxide layer 4 is formed by dry oxidation growth. The dry oxidation temperature is 700℃~1200℃ and the time is 30 minutes~90 minutes. The thickness of the thin oxide layer 4 is 10nm~100nm.

[0037] The thin oxide layer 4 prevents channeling during subsequent ion implantation. Channeling refers to the phenomenon where the projected range of some impurity ions in the crystal increases significantly during ion implantation. Since the implanted ions are highly likely to be scattered by atoms in the crystal, the projected range is determined by the implantation energy. When ions are implanted into a silicon wafer at a specific angle, the silicon crystal structure exhibits some channels. At this point, the probability of some implanted ions being scattered by atoms in the crystal decreases, leading to a significantly greater implantation depth for these ions. The concentration distribution of the implanted impurity ions along the projected range does not follow a Gaussian distribution, causing the ion implantation result to deviate from the predicted result. Therefore, by adding a very thin and dense oxide layer to the silicon wafer surface, the implanted ions are first scattered through the thin oxide layer 4, making the incident angle of the implanted ions randomized, thereby avoiding the channeling effect.

[0038] Boron ions are implanted into the SOI silicon wafer on which the thin oxide layer 4 is formed to form the lightly doped P-type varistor 5, wherein the boron ion implantation energy is between 50 keV and 130 keV, and the implantation dose is 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 ; Boron ions are implanted into the SOI silicon wafer on which the lightly doped P-type varistor 5 is formed to form a heavily doped P+ structure 6 in contact with the lightly doped P-type varistor 5. The implantation energy of the boron ions is between 30 keV and 80 keV, and the implantation dose is 3 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 .

[0039] Through the above steps, a heavily doped P+ structure 6 is formed, interconnecting with the lightly doped P-type varistors 5. This internal interconnect structure connects several P-type varistors together, forming a Wheatstone bridge with the subsequent metal layer 8 (e.g., aluminum). To reduce resistance errors in the circuit, the resistance value of the internal interconnect structure should be as small as possible; to ensure ohmic contact with the aluminum, the doping concentration of the internal interconnect structure needs to be sufficiently high to reduce the width of the Schottky barrier between silicon and aluminum. Therefore, the heavily doped P+ structure 6 is implanted with a large dose of dopant.

[0040] S3. Pre-opened windows 7 are formed on the surface of the thin oxide layer 4. This step specifically includes: The cavity is pretreated by evacuating the etching cavity and then purging it with argon gas to remove residual impurities and stabilize the etching environment. The vacuum level of the etching cavity is between 5 mTorr and 10 mTorr. Before the process gas ignition is prepared, the main etching gas CF4 and the auxiliary gas O2 are introduced into the etching chamber to form a process atmosphere suitable for the etching of the thermal oxidative layer. The gas flow rate of CF4 is 80 sccm~120 sccm, the gas flow rate of O2 is 10 sccm~20 sccm, and the chamber pressure is 15 mTorr~30 mTorr. Radio frequency (RF) ignition etching is performed to form plasma from CF4 and O2 under RF action. The plasma is used to perform anisotropic etching on the thermal oxide layer. The etching endpoint is controlled by an endpoint detection system to prevent over-etching of the silicon substrate while forming the pre-opened aperture 7. The RF power is 300W~500W and the etching rate is 80Å / min~120Å / min. After purging the etching chamber and shutting off the process gas, high-purity nitrogen is introduced into the etching chamber to purge it and remove byproducts generated during the etching process. The wafer temperature is maintained at 20℃~30℃ throughout the process to ensure etching uniformity and sidewall perpendicularity, forming pre-opened holes 7 to prepare for subsequent electrical connections.

[0041] S4. A metal layer 8 for electrical connection is deposited on the surface of the thin oxide layer 4. The metal layer 8 contacts the heavily doped P+ structure 6 through the pre-opened window 7. (Refer to...) Figure 4 As shown, this step specifically includes: The deposition chamber is evacuated to obtain the background vacuum environment required for the deposition of metal layer 8, wherein the background vacuum of the deposition chamber is 5 × 10⁻⁶. -7 Torr; High-purity Ar is introduced into the deposition chamber as a process gas, and the chamber pressure is kept stable. The flow rate of the high-purity Ar is 30 sccm to 60 sccm, and the chamber pressure is 3 mTorr to 8 mTorr. Turn on the RF power supply or DC power supply and perform pre-sputtering treatment on the metal target to clean the surface of the metal target and remove the oxide layer and impurities on the surface of the metal target. The pre-sputtering treatment time is 5 min to 10 min. In this embodiment, the metal layer 8 is made of aluminum. In other embodiments, copper, silver or other metal materials suitable for forming electrical connections can also be used.

[0042] The wafer is moved to the process position and formal sputtering deposition is performed on the surface of the thin oxide layer 4 to form the metal layer 8, wherein the DC power is 800W~1200W, the substrate temperature is 25℃~80℃, the deposition rate is 300Å / min~500Å / min, and the deposition time is 1min~30min. After deposition is complete, the power supply and Ar gas are turned off, and high-purity nitrogen is introduced into the deposition chamber for purging to remove residual plasma and dust.

[0043] S5. Deposit a SiO dielectric film 9 on the surface of the thin oxide layer 4. This step specifically includes: The wafer is fed into the PECVD deposition chamber, and the PECVD deposition chamber is subjected to vacuuming and heating treatment, wherein the vacuum degree of the PECVD deposition chamber reaches 10. -6 Torr level, chamber temperature is 350℃~400℃; SiH4, NH3 and O2 are introduced into the PECVD deposition chamber as a mixed process gas, wherein the flow rate of SiH4 is controlled at 20 sccm to 40 sccm, the flow rate of NH3 is controlled at 30 sccm to 50 sccm, and the flow rate of O2 is controlled at 50 sccm to 80 sccm. The mixed process gas is reacted under the action of plasma and SiO dielectric film 9 is deposited on the surface of the thin oxide layer 4. The cavity pressure of the PECVD deposition chamber is 2 Torr~5 Torr and the radio frequency power is 200W~400W. The deposition process of the SiO dielectric film 9 is controlled to achieve the target thickness, wherein the deposition rate of the SiO dielectric film 9 is 100 Å / min to 200 Å / min, and the thickness of the SiO dielectric film 9 is 0.1 μm to 5 μm.

[0044] CMP polishing is then performed using silica polishing slurry at a pressure of 2 psi to 4 psi and a polishing disc speed of 50 rpm to 80 rpm to remove excess film and achieve global planarization.

[0045] S6. Prepare a top silicon layer 10 and a recessed pressure-absorbing cavity 11 located on the top silicon layer 10, and bond the top silicon layer 10 to the SiO dielectric film 9. (Refer to...) Figure 4 As shown, this step specifically includes: A silicon wafer is provided, and the silicon wafer is cleaned and dried. A photoresist coating process is performed, in which positive photoresist is uniformly coated on the surface of the silicon wafer, wherein the coating speed is 3000rpm~4000rpm and the photoresist layer thickness is 1.2μm~1.8μm; The silicon wafer after uniformly coating with positive photoresist is pre-baked to remove the solvent in the positive photoresist. The pre-baking temperature is 100℃~110℃ and the pre-baking time is 90s. The positive photoresist is exposed using the groove absolute pressure cavity 11 pattern to form an exposure pattern corresponding to the groove absolute pressure cavity 11, wherein the exposure dose is 120 mJ / cm². 2 ~180mJ / cm 2 ; After exposure, the silicon wafer is subjected to a post-bake treatment, wherein the post-bake treatment temperature is 110°C and the post-bake treatment time is 60s; The silicon wafer, after post-baking, is immersed in a developing solution for development, and then rinsed with deionized water and dried to transfer the groove absolute pressure cavity 11 pattern to the surface of the silicon wafer. The development time is 40s to 60s.

[0046] In addition, the top silicon 10 of the above-mentioned prepared groove pressure relief cavity 11 is bonded to the lower SOI silicon wafer at low temperature using the SI-O-SI bonding method.

[0047] S7. A TSV via 12 extending to the surface of the metal layer 8 is formed on the top silicon 10. (Refer to...) Figure 5 As shown, this step specifically includes: The top silicon 10 is pretreated by evacuating the etching chamber and then introducing argon gas for short-term plasma cleaning to remove microparticles and native oxide layer on the surface of the top silicon 10. The vacuum degree of the etching chamber is within 8 mTorr. Thick photoresist is spin-coated onto the top silicon 10 surface and pre-baked. The spin-coating speed is 2500 rpm to 3500 rpm, the photoresist layer thickness is 3.0 μm to 5.0 μm, the pre-baking temperature is 105℃, and the pre-baking time is 120 s. The thick photoresist was exposed according to the TSV via 12 pattern using a stepper lithography machine, and then post-baking and developing were performed to form the TSV via 12 windows. The exposure dose was 150 mJ / cm². 2 ~200mJ / cm 2 The post-baking temperature is 110℃, the post-baking time is 90s, and the developing time is 50s~70s; The wafer with the TSV via 12 window is transferred to the DRIE etching process, and the top silicon 10 is etched using the Bosch alternating etching process, wherein the cavity pressure of the Bosch alternating etching process is 18 mTorr to 28 mTorr. SF6 is introduced during the etching stage and C4F8 is introduced during the passivation stage. By alternating between the etching and passivation stages, TSV vias 12 extending to the surface of the metal layer 8 are formed on the top silicon 10. The flow rate of SF6 is 120 sccm to 180 sccm, the RF power of the etching stage is 500W to 700W, and the flow rate of C4F8 is 80 sccm to 120 sccm. The alternating cycle achieves the etching of TSV vias 12 with an aspect ratio greater than or equal to 1:3. The target aperture of the TSV vias 12 is 10μm to 200μm. After etching, the wafer is subjected to wet photoresist removal and plasma residue removal to remove residual photoresist and etching residue inside and outside the TSV via 12.

[0048] S8. An insulating layer 13 is grown on the inner wall of the TSV via 12, and a PAD electrical connection structure 14 electrically connected to the metal layer 8 is formed on the surface of the insulating layer 13. This step specifically includes: Dry oxygen is introduced into the furnace tube to grow an insulating layer 13 (SiO2) on the inner wall of the TSV through-hole 12. The dry oxidation temperature is 950℃~1050℃, and the thickness of the insulating layer 13 is 0.5μm~1μm. This is used to prevent sidewall leakage and ensure the reliability of TSV vertical interconnection. SnAg alloy metal is prepared by evaporation process and then patterned by photolithography to form PAD electrical connection structure 14, which is electrically connected to the metal layer 8.

[0049] S9. The pressure-sensitive layer is released by etching on the back side of the SOI silicon wafer, and the buried oxide insulating layer 2 is used as the etching stop layer to form a pressure-bearing cavity 15 through patterning. This step specifically includes: KOH alkaline etching solution is used at an etching temperature of 75℃~85℃ to precisely etch and release the pressure-sensitive layer. The etched stop layer is the buried oxygen insulating layer 2, which is then patterned to form a pressure-bearing cavity 15. By cooperating with the grooved pressure-absorbing cavity 11, pressure can be applied to the pressure-sensitive layer, and a corresponding pressure feedback signal can be output by a Wheatstone bridge.

[0050] It is understood that the pressure-receiving cavity 15 and the grooved pressure-absolute cavity 11 are arranged opposite each other in the thickness direction. The pressure-receiving cavity 15 is used to receive the pressure of the fluid to be measured and transmit the pressure to the pressure-sensitive region corresponding to the lightly doped P-type varistor 5. Since the pressure-receiving cavity 15 uses the buried oxygen insulating layer 2 as the cutoff layer, the uniformity of the cavity thickness and the uniformity of the varistor structure can be improved. The grooved pressure-absolute cavity 11 is formed by the top silicon 10 and the SiO dielectric film 9 to form a sealed reference cavity. The sealed reference cavity is used to provide a pressure detection reference environment, making the sensor suitable for absolute pressure detection or stable reference pressure detection scenarios.

[0051] S10. Micro-solder balls 16 are fabricated on the PAD electrical connection structure 14, and the micro-sensor chip is flip-chip packaged onto the PCB substrate 17 through the micro-solder balls 16 to form an electrical connection. (Refer to...) Figure 6 As shown, this step specifically includes: The wafers that have completed the previous process are cleaned and dried, and then sent to the ball-mounting process. The chip pad area where the PAD electrical connection structure 14 is located is subjected to surface pretreatment to remove the oxide layer and organic impurities on the surface of the chip pad area and improve the adhesion of the subsequent plating layer. The surface pretreatment is carried out by Ar atmosphere plasma cleaning with a cleaning power of 200W, a chamber pressure of 10mTorr, and a cleaning time of 60s. A passivation layer is formed on the PAD electrical connection structure 14 and the surrounding dielectric surface, and the passivation layer is photolithographically windowed to expose the pad window corresponding to the PAD electrical connection structure 14. Selective electroplating is performed on the pad windows to deposit a tin layer on the PAD electrical connection structure 14. The selective electroplating uses a tin methanesulfonate plating solution at a temperature of 25±2℃ and a current density of 1.5A / dm³. 2 ~2.5A / dm 2 The electroplating time is 80s~150s; After electroplating, the photoresist is wet-stripped and the tin layer is pre-melted by hot air leveling to preliminarily adjust the morphology of the tin layer. The wafer is fed into a reflow oven for reflow treatment, causing the tin layer to shrink into a spherical shape under the action of surface tension, thereby forming micro tin balls 16. The reflow treatment includes passing through a preheating zone, a constant temperature zone, and a peak temperature zone in sequence. The temperature of the preheating zone is 120℃~150℃ and the holding time is 90s. The temperature of the constant temperature zone is 180℃~200℃ and the holding time is 60s. The temperature of the peak temperature zone is 230℃~240℃ and the holding time is 40s. Nitrogen gas is introduced as a protective gas during the reflow process to suppress high-temperature oxidation of the tin layer and prevent the tin material from oxidizing at high temperatures, so that the tin layer shrinks into a standard spherical shape due to surface tension. The wafer on which the micro solder balls 16 are formed is subjected to flux cleaning and drying treatment to remove residual flux on the surface; The micro-sensor chip is reflow soldered to the PCB substrate 17 via the micro solder balls 16, so that the PAD electrical connection structure 14 forms a leadless electrical connection with the PCB substrate 17 via the micro solder balls 16. This meets the requirements of ultra-small product design and leadless packaging, improves product reliability, and prevents the problem of broken wires in traditional gold wire connections.

[0052] Multiple micro-solder balls 16 can correspond one-to-one with multiple PAD electrical connection structures 14, thereby realizing a leadless flip-chip electrical connection between the sensor chip and the PCB substrate 17. This structure can avoid the gold wire breakage problem in traditional gold wire bonding and reduce the influence of gold wire parasitic parameters on weak pressure electrical signals. When the sensor is working, the pressure to be measured is applied to the pressure-sensitive area through the pressure-receiving cavity 15. The pressure-sensitive area deforms under the reference environment provided by the pressure-receiving cavity 11, and the resistance value of the lightly doped P-type varistor 5 changes. This resistance change is converted into an electrical signal by a Wheatstone bridge and transmitted to the PCB substrate 17 in sequence through the heavily doped P+ structure 6, the metal layer 8, the PAD electrical connection structure 14, and the micro-solder balls 16. Since the sensitive surface has fewer exposed metal wiring and pads, it can improve corrosion resistance and release more effective sensitive area for chip miniaturization.

[0053] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A manufacturing process for a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for automotive applications, characterized in that... include: SOI silicon wafers are provided, including a support silicon wafer (1), a buried oxide insulating layer (2) and a donor silicon wafer (3) arranged sequentially from bottom to top. A thin oxide layer (4) is grown on the surface of the SOI silicon wafer, and a lightly doped P-type varistor (5) and a heavily doped P+ structure (6) are formed in contact on the upper part of the SOI silicon wafer by boron ion implantation. Pre-opened windows (7) are formed on the surface of the thin oxide layer (4); A metal layer (8) for electrical connection is deposited on the surface of the thin oxide layer (4), and the metal layer (8) is in contact with the heavily doped P+ structure (6) through the pre-opened window (7); A SiO dielectric film (9) is deposited on the surface of the thin oxide layer (4); Prepare a top silicon (10) and a groove pressure relief cavity (11) located on the top silicon (10), and bond the top silicon (10) to the SiO dielectric film (9); TSV vias (12) extending to the surface of the metal layer (8) are formed on the top silicon (10). An insulating layer (13) is grown on the inner wall of the TSV via (12), and a PAD electrical connection structure (14) electrically connected to the metal layer (8) is prepared on the surface of the insulating layer (13). The pressure-sensitive layer is released by etching on the back side of the SOI silicon wafer, and the buried oxide insulating layer (2) is used as the etching stop layer to form a pressure-bearing cavity (15) by patterning. Micro-solder balls (16) are fabricated on the PAD electrical connection structure (14), and the micro-sensor chip is flip-chip packaged on the PCB substrate (17) through the micro-solder balls (16) to form an electrical connection.

2. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, The SOI silicon wafer fabrication steps include: A support silicon wafer (1) with an atomic-level polishing precision is provided. The support silicon wafer (1) is subjected to high-temperature thermal oxidation to form a SiO2 layer on the surface of the support silicon wafer (1). The SiO2 layer serves as a buried oxide insulating layer (2) and as a barrier layer for subsequent backside ICP etching. The thickness of the SiO2 layer is 2μm to 30μm. Provide a donor silicon wafer (3) with a surface polishing precision of atomic level, and perform polishing and thinning treatment on the donor silicon wafer (3) to reduce the donor silicon wafer (3) to a preset thickness, wherein the thickness of the thinned donor silicon wafer (3) is 5μm~80μm; The supporting silicon wafer (1) and the donor silicon wafer (3) are cleaned to remove surface particles, metal impurities and organic contaminants, and to ensure that the bonding interface is clean. Hydrogen ions are implanted into the donor silicon wafer (3) at a predetermined depth to form a hydrogen-rich damage layer inside the donor silicon wafer (3). The hydrogen-rich damage layer is used as a predetermined fracture surface for subsequent peeling. The hydrogen ion implantation energy is between 10keV and 100keV, and the implantation dose is 1×10⁻⁶. 15 cm -2 ~1×10 20 cm -2 The thickness of the subsequently formed top silicon layer ranges from 2μm to 50μm; The injection surface of the donor silicon wafer (3) is bonded to the surface of the buried oxygen insulating layer (2) on the supporting silicon wafer (1) at room temperature, and a pre-bonded structure is formed by van der Waals forces; The pre-bonded structure is subjected to low-temperature annealing, which causes hydrogen ions in the hydrogen enrichment damage layer to aggregate and form microbubbles. The stress generated after the microbubbles grow and merge along the hydrogen enrichment damage layer peels off the excess substrate of the donor silicon wafer (3) to obtain SOI initial product with rough top silicon. The low-temperature annealing temperature is 200℃~500℃. The top silicon layer of the SOI precursor is subjected to wet etching to remove the residual damage layer on the surface of the top silicon layer, and then the top silicon layer is subjected to chemical mechanical polishing to obtain an SOI silicon wafer. The surface roughness of the top silicon layer after chemical mechanical polishing is less than or equal to 0.1 nm, and the thickness deviation is controlled within ±5 nm. The SOI silicon wafer is sequentially cleaned, defect-detected, and thinned. During cleaning, the SOI silicon wafer is ultrasonically treated in anhydrous ethanol, acetone, and deionized water for 30 to 60 minutes respectively. Then, the SOI silicon wafer is placed on a hot plate and heated at 100°C for 30 minutes. After the thinning treatment, the thickness of the SOI silicon wafer is 350 μm to 450 μm.

3. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, A thin oxide layer (4) is grown on the surface of the SOI silicon wafer, and a lightly doped P-type varistor (5) and a heavily doped P+ structure (6) are formed in contact on the upper part of the SOI silicon wafer by boron ion implantation, including: The SOI silicon wafer is placed in an oxidation furnace and a thin oxide layer (4) is formed by dry oxidation growth. The dry oxidation temperature is 700℃~1200℃ and the time is 30 minutes~90 minutes. The thickness of the thin oxide layer (4) is 10nm~100nm. Boron ions are implanted into the SOI silicon wafer on which the thin oxide layer (4) is formed to form the lightly doped P-type varistor (5), wherein the implantation energy of the boron ions is between 50 keV and 130 keV, and the implantation dose is between 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 ; Boron ions are implanted into an SOI silicon wafer on which the lightly doped P-type varistor (5) is formed to form a heavily doped P+ structure (6) in contact with the lightly doped P-type varistor (5), wherein the implantation energy of the boron ions is between 30 keV and 80 keV and the implantation dose is 3 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 .

4. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, Pre-opened windows (7) are formed on the surface of the thin oxide layer (4), including: The cavity is pretreated by evacuating the etching cavity and then purging it with argon gas to remove residual impurities and stabilize the etching environment. The vacuum level of the etching cavity is between 5 mTorr and 10 mTorr. Before the process gas ignition is prepared, the main etching gas CF4 and the auxiliary gas O2 are introduced into the etching chamber to form a process atmosphere suitable for the etching of the thermal oxidative layer. The gas flow rate of CF4 is 80 sccm~120 sccm, the gas flow rate of O2 is 10 sccm~20 sccm, and the chamber pressure is 15 mTorr~30 mTorr. Radio frequency ignition etching is performed to form plasma by CF4 and O2 under radio frequency action. The plasma is used to perform anisotropic etching on the thermal oxide layer. The etching endpoint is controlled by the endpoint detection system to prevent over-etching of the silicon substrate while forming the pre-opened window (7). The radio frequency power is 300W~500W and the etching rate is 80Å / min~120Å / min. After purging the chamber and shutting off the process gas, high-purity nitrogen is introduced into the etching chamber to purge it and remove the byproducts generated during the etching process.

5. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, A metal layer (8) for electrical connection is deposited on the surface of the thin oxide layer (4), including: The deposition chamber is evacuated to obtain the background vacuum environment required for the deposition of the metal layer (8), wherein the background vacuum of the deposition chamber is 5 × 10⁻⁶. -7 Torr; High-purity Ar is introduced into the deposition chamber as a process gas, and the chamber pressure is kept stable. The flow rate of the high-purity Ar is 30 sccm to 60 sccm, and the chamber pressure is 3 mTorr to 8 mTorr. Turn on the RF power supply or DC power supply and perform pre-sputtering treatment on the metal target to clean the surface of the metal target and remove the oxide layer and impurities on the surface of the metal target. The pre-sputtering treatment time is 5 min to 10 min. The wafer is moved to the process position and formal sputtering deposition is performed on the surface of the thin oxide layer (4) to form the metal layer (8), wherein the DC power is 800W~1200W, the substrate temperature is 25℃~80℃, the deposition rate is 300Å / min~500Å / min, and the deposition time is 1min~30min. After deposition is complete, the power supply and Ar gas are turned off, and high-purity nitrogen is introduced into the deposition chamber for purging to remove residual plasma and dust.

6. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, A SiO dielectric film (9) is deposited on the surface of the thin oxide layer (4), comprising: The wafer is fed into the PECVD deposition chamber, and the PECVD deposition chamber is subjected to vacuuming and heating treatment, wherein the vacuum degree of the PECVD deposition chamber reaches 10. -6 Torr level, chamber temperature is 350℃~400℃; SiH4, NH3 and O2 are introduced into the PECVD deposition chamber as a mixed process gas, wherein the flow rate of SiH4 is controlled at 20 sccm to 40 sccm, the flow rate of NH3 is controlled at 30 sccm to 50 sccm, and the flow rate of O2 is controlled at 50 sccm to 80 sccm. The mixed process gas is reacted under the action of plasma and a SiO dielectric film (9) is deposited on the surface of the thin oxide layer (4), wherein the cavity pressure of the PECVD deposition chamber is 2 Torr~5 Torr and the radio frequency power is 200W~400W; The deposition process of the SiO dielectric film (9) is controlled to achieve the target thickness, wherein the deposition rate of the SiO dielectric film (9) is 100 Å / min to 200 Å / min and the thickness of the SiO dielectric film (9) is 0.1 μm to 5 μm.

7. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, Fabricating a top silicon (10) and a recessed pressure-absorbing cavity (11) located on the top silicon (10) includes: A silicon wafer is provided, and the silicon wafer is cleaned and dried. A photoresist coating process is performed, in which positive photoresist is uniformly coated on the surface of the silicon wafer, wherein the coating speed is 3000rpm~4000rpm and the photoresist layer thickness is 1.2μm~1.8μm; The silicon wafer after uniformly coating with positive photoresist is pre-baked to remove the solvent in the positive photoresist. The pre-baking temperature is 100℃~110℃ and the pre-baking time is 90s. The positive photoresist is exposed using the recessed pressure chamber (11) pattern to form an exposure pattern corresponding to the recessed pressure chamber (11), wherein the exposure dose is 120 mJ / cm². 2 ~180mJ / cm 2 ; After exposure, the silicon wafer is subjected to a post-bake treatment, wherein the post-bake treatment temperature is 110°C and the post-bake treatment time is 60s; The silicon wafer after post-baking is immersed in a developing solution for development, and then rinsed and dried with deionized water to transfer the pattern of the groove absolute pressure cavity (11) to the surface of the silicon wafer. The development time is 40s to 60s.

8. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, Forming a TSV via (12) extending to the surface of the metal layer (8) on the top silicon (10) includes: The top silicon (10) is pretreated by evacuating the etching chamber and then passing argon gas through it for short-term plasma cleaning to remove microparticles and natural oxide layer on the surface of the top silicon (10). The vacuum degree of the etching chamber is within 8 mTorr. Thick photoresist is spin-coated onto the top silicon (10) surface and pre-baked. The spin-coating speed is 2500 rpm to 3500 rpm, the photoresist layer thickness is 3.0 μm to 5.0 μm, the pre-baking temperature is 105 °C, and the pre-baking time is 120 s. The thick photoresist was exposed according to the TSV via (12) pattern using a stepper lithography machine, and then post-baking and developing were performed to form the TSV via (12) window. The exposure dose was 150 mJ / cm². 2 ~200mJ / cm 2 The post-baking temperature is 110℃, the post-baking time is 90s, and the developing time is 50s~70s; The wafer with the TSV via (12) window formed is transferred to the DRIE etching process, and the top silicon (10) is etched using the Bosch alternating etching process, wherein the cavity pressure of the Bosch alternating etching process is 18 mTorr~28 mTorr. SF6 is introduced during the etching stage and C4F8 is introduced during the passivation stage. By alternating the etching stage and the passivation stage, a TSV via (12) extending to the surface of the metal layer (8) is formed on the top silicon (10). The flow rate of SF6 is 120 sccm to 180 sccm, the RF power of the etching stage is 500 W to 700 W, the flow rate of C4F8 is 80 sccm to 120 sccm, the aspect ratio of the TSV via (12) is greater than or equal to 1:3, and the aperture of the TSV via (12) is 10 μm to 200 μm. After etching, the wafer is subjected to wet photoresist removal and plasma residue removal to remove the photoresist and etching residues remaining inside and outside the TSV via (12).

9. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, An insulating layer (13) is grown on the inner wall of the TSV via (12), and a PAD electrical connection structure (14) electrically connected to the metal layer (8) is prepared on the surface of the insulating layer (13), comprising: Dry oxygen is introduced into the furnace tube to grow an insulating layer (13) on the inner wall of the TSV through hole (12), wherein the dry oxidation temperature is 950℃~1050℃ and the thickness of the insulating layer (13) is 0.5μm~1μm; SnAg alloy metal is prepared by evaporation process and then patterned by photolithography to form PAD electrical connection structure (14), which is electrically connected to the metal layer (8).

10. The manufacturing process of a high-temperature resistant, corrosion-resistant, and highly sensitive inverted piezoresistive pressure sensor for vehicles according to claim 1, characterized in that, Micro-solder balls (16) are fabricated on the PAD electrical connection structure (14), and a micro-sensor chip is flip-chip packaged on a PCB substrate (17) through the micro-solder balls (16) to form an electrical connection, including: The wafers that have completed the previous process are cleaned and dried, and then sent to the ball-mounting process. The surface of the chip pad area where the PAD electrical connection structure (14) is located is pretreated to remove the oxide layer and organic impurities on the surface of the chip pad area and improve the adhesion of the subsequent plating layer. The surface pretreatment is carried out by Ar atmosphere plasma cleaning with a cleaning power of 200W, a chamber pressure of 10mTorr, and a cleaning time of 60s. A passivation layer is formed on the PAD electrical connection structure (14) and the surrounding dielectric surface, and the passivation layer is photolithographically windowed to expose the pad window corresponding to the PAD electrical connection structure (14). Selective electroplating is performed on the pad windows to deposit a tin layer on the PAD electrical connection structure (14). The selective electroplating uses a tin methanesulfonate system electroplating solution, the electroplating temperature is 25±2℃, and the current density is 1.5A / dm³. 2 ~2.5A / dm 2 The electroplating time is 80s~150s; After electroplating, the photoresist is wet-stripped and the tin layer is pre-melted by hot air leveling to preliminarily modify the morphology of the tin layer. The wafer is sent into a reflow oven for reflow treatment, so that the tin layer shrinks into a spherical shape under the action of surface tension, thereby forming micro tin balls (16). The reflow treatment includes passing through a preheating zone, a constant temperature zone and a peak temperature zone in sequence. The temperature of the preheating zone is 120℃~150℃ and the holding time is 90s. The temperature of the constant temperature zone is 180℃~200℃ and the holding time is 60s. The temperature of the peak temperature zone is 230℃~240℃ and the holding time is 40s. Nitrogen gas is introduced as a protective gas during the reflow process to suppress high-temperature oxidation of the tin layer and to form standard spherical micro tin balls (16). The wafer on which the micro-solder balls (16) are formed is subjected to flux cleaning and drying treatment to remove residual flux on the surface; The micro-sensor chip is reflow soldered to the PCB substrate (17) through the micro solder ball (16) so that the PAD electrical connection structure (14) forms a leadless electrical connection with the PCB substrate (17) through the micro solder ball (16).

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