A light-load adaptive load current sampling circuit

Abstract

The embodiment of the application discloses a kind of light load adaptive load current sampling circuits, the load current sampling circuit includes power MOS tube, light load detection circuit, light load determination circuit and minimum drain-source voltage circuit, wherein: light load detection circuit, for sampling the current output by power MOS tube according to preset proportion, light load determination circuit, for comparing the current output by light load detection circuit with second reference current, generate control signal, and according to control signal control the working state of minimum drain-source voltage circuit;Minimum drain-source voltage circuit is in working state, for comparing the source voltage of power MOS tube with preset voltage reference, obtain voltage comparison result;According to voltage comparison result, the gate voltage of power MOS tube is adjusted, to maintain the drain-source voltage of power MOS tube at preset minimum drain-source voltage.Using the embodiment of the application, the current of power tube can be accurately sampled under light load condition.

Description

Technical Field

[0001] This invention relates to the field of dedicated chip and logic circuit technology, and in particular to a light-load adaptive load current sampling circuit. Background Technology

[0002] In high-side driver (HSD) applications, the current sampling ratio of the power transistor is a critical parameter, directly determining the accuracy of the chip's monitoring of the power transistor's current. This requires that the sampling ratio be as accurate as possible across the entire load range, from light load to full load, and that the corresponding tests also cover all load conditions.

[0003] Existing technologies typically employ a sampling transistor sharing a common gate and common drain with the power transistor to proportionally replicate the load current for sampling. However, to support larger load currents and reduce conduction losses, current HSD products generally have a low on-resistance for the power transistor, typically below a few hundred milliohms. This results in an extremely small voltage drop across the power transistor under light load conditions, close to the offset voltage of the sampling circuit itself. Consequently, the actual voltage drop across the power transistor cannot be accurately detected, leading to inaccurate load current acquisition and affecting the current sampling accuracy under light load conditions.

[0004] Another existing technical solution is to discard the sampled data directly under light load conditions and circumvent the problem of inaccurate sampling under light load by increasing the test load until the sampled values ​​meet the accuracy requirements. However, this solution essentially abandons the current monitoring capability under light load conditions, and there is still a sampling blind zone in the light load range, making it impossible to achieve accurate current sampling across the entire load range.

[0005] In view of the technical problems existing in the above-mentioned prior art, there is an urgent need for a load current sampling scheme that can accurately sample under light load conditions. Summary of the Invention

[0006] This application provides a light-load adaptive load current sampling circuit that can accurately sample the current of the power transistor under light-load conditions.

[0007] This application provides a light-load adaptive load current sampling circuit, which includes a power MOSFET, a light-load detection circuit, a light-load determination circuit, and a minimum drain-source voltage circuit, wherein: The first input terminal of the light load detection circuit is connected to the gate of the power MOSFET, the second input terminal of the light load detection circuit is connected to the source of the power MOSFET, the output terminal of the light load detection circuit is connected to the input terminal of the light load determination circuit, the output terminal of the light load determination circuit is connected to the enable terminal of the minimum drain-source voltage circuit, the input terminal of the minimum drain-source voltage circuit is connected to the source of the power MOSFET, and the output terminal of the minimum drain-source voltage circuit is connected to the gate of the power MOSFET. The light load detection circuit is used to sample the current output by the power MOSFET according to a preset ratio. The light load determination circuit is used to compare the current output by the light load detection circuit with a second reference current, generate a control signal, and control the operating state of the minimum drain-source voltage circuit according to the control signal. When the minimum drain-source voltage circuit is in the operating state, it is used to compare the source voltage of the power MOSFET with a preset voltage reference to obtain a voltage comparison result. The gate voltage of the power MOSFET is adjusted according to the voltage comparison result to maintain the drain-source voltage of the power MOSFET at a preset minimum drain-source voltage.

[0008] Optionally, the light-load detection circuit includes a sampling MOSFET, a second operational amplifier, a scaling MOSFET, a first sampling resistor, a second sampling resistor, and a fourth current mirror, wherein: The source of the sampling MOS transistor is connected to one end of the first sampling resistor and the non-inverting input of the second operational amplifier. One end of the second sampling resistor is connected to the inverting input of the second operational amplifier and the source of the scaling MOS transistor. The output of the second operational amplifier is connected to the gate of the scaling MOS transistor. The drain of the scaling MOS transistor is connected to the input of the fourth current mirror. The first input terminal of the light load detection circuit is the gate of the sampling MOS transistor, the second input terminal of the light load detection circuit is the other end of the first sampling resistor and the second sampling resistor, and the output terminal of the light load detection circuit is the output terminal of the fourth current mirror.

[0009] Optionally, the light load determination circuit includes a second reference current source, a Schmitt trigger, and an inverter, wherein: The input terminal of the light load determination circuit is the positive terminal of the second reference current source and the input terminal of the Schmitt trigger. The light load determination circuit includes a first output terminal and a second output terminal. The first output terminal of the light load determination circuit is the output terminal of the Schmitt trigger and the input terminal of the inverter. The second output terminal of the light load determination circuit is the output terminal of the inverter.

[0010] Optionally, the minimum drain-source voltage circuit includes a first operational amplifier, a first current mirror, a second current mirror, a third current mirror, a first switch, a second switch, a fifth switch, a pull-up current source, and a pull-down current source; wherein: The non-inverting input of the first operational amplifier is used to input a preset voltage reference. The inverting input of the first operational amplifier is connected to one end of the first switch and one end of the second switch. The other end of the first switch is connected to the source of the power MOSFET. The output of the first operational amplifier is connected to the input of the first current mirror. The output of the first current mirror is connected to the input of the second current mirror and one end of the fifth switch. The other end of the fifth switch is connected to the drive pull-down current source. The output of the second current mirror is connected to the input of the third current mirror. The input terminal of the minimum drain-source voltage circuit is the power supply terminal of the third current mirror, and the output terminal of the minimum drain-source voltage circuit is the output terminal of the third current mirror and the negative terminal of the driving pull-up current source.

[0011] Optionally, the load current sampling circuit further includes a first power supply, a second power supply, and a first reference ground; the minimum drain-source voltage circuit further includes a third switch, a fourth switch, and a first reference current source; the power supply terminal of the first current mirror is connected to one end of the third and fourth switches, and the other end of the third switch is connected to the positive terminal of the first reference current source, wherein: The first power supply is connected to the drain of the power MOSFET, the drain of the sampling MOSFET, and the positive power supply terminal of the first operational amplifier, respectively, for supplying power to the power MOSFET, the sampling MOSFET, and the first operational amplifier; the first power supply is also connected to the other end of the second switch; The second power supply is connected to the positive terminal of the drive pull-up current source, the power supply terminal of the second current mirror, and the power supply of the fourth current mirror, and is used to supply power to the drive pull-up current source, the second current mirror, and the fourth current mirror. The first reference ground is connected to the negative terminal of the second reference current source, the negative power supply terminal of the first operational amplifier, the negative terminal of the first reference current source, and the other end of the fourth switch; The voltage output by the second power supply is higher than the voltage output by the first power supply, and the voltage output by the first power supply is higher than the voltage of the first reference ground.

[0012] Optionally, the sampling MOSFET replicates the current output by the power MOSFET at a first scale, where the first scale is: , The current output from the sampling MOSFET is scaled by the second operational amplifier, the scaling MOSFET, the first sampling resistor, and the second sampling resistor according to a second ratio before being fed into the input terminal of the fourth current mirror. The second ratio is: .

[0013] Optionally, the current output by the second reference current source is the second reference current, wherein: If the current output by the light load detection circuit is less than the second reference current, then the control signal is logic signal 1, the first switch receives logic signal 1 and closes, logic signal 1 is flipped to logic signal 0 by the inverter, the second switch receives logic signal 0 and opens, and the minimum drain-source voltage circuit is in working state. If the current output by the light load detection circuit is greater than or equal to the second reference current, then the control signal is logic signal 0, the first switch receives logic signal 0 and opens, logic signal 0 is flipped into logic signal 1 by the inverter, the second switch receives logic signal 1 and closes, and the minimum drain-source voltage circuit is in a non-operating state.

[0014] Optionally, if the voltage comparison result indicates that the source voltage of the power MOSFET is less than the preset voltage reference, the first operational amplifier outputs current; if the voltage comparison result indicates that the source voltage of the power MOSFET is greater than or equal to the preset voltage reference, the first operational amplifier does not output current. The smaller the source voltage of the power MOSFET is compared to the preset voltage reference, the larger the pull-down current output by the third current mirror to control the gate voltage of the power MOSFET becomes, thereby causing the power MOSFET to enter a saturation state. When the power MOSFET is in a saturation state, the on-resistance and source voltage of the power MOSFET increase until the source voltage of the power MOSFET is maintained near the preset voltage reference, and the minimum drain-source voltage circuit reaches a balance state.

[0015] Optionally, the current output by the drive pull-up current source and the current output by the drive pull-down current source are the drive currents under normal non-light load operating conditions, wherein: When the minimum drain-source voltage circuit is in operation, the current output by the drive pull-up current source remains unchanged. The fifth switch changes from the closed state during the normal non-light load operation to the open state. The current path output by the drive pull-down current source is cut off. The current output by the first current mirror after cascading through the second and third current mirrors replaces the current output by the drive pull-down current source.

[0016] Optionally, when the minimum drain-source voltage circuit is in the initial stage of operation, the third switch is open, the fourth switch is closed, the power supply terminal of the first current mirror is connected to the first reference ground, and the total current of the first current mirror has no upper limit, so that the current output by the first current mirror increases, which is used to quickly pull down the gate voltage of the power MOSFET. When the minimum drain-source voltage circuit is in the steady-state phase of operation, the third switch is closed and the fourth switch is open. The power supply terminal of the first current mirror is connected to the first reference ground through the first reference current source. The upper limit of the total current of the first current mirror is the first reference current output by the first reference current source, which reduces the current output by the first current mirror to maintain the stability of the adjustment loop with a small current. The adjustment loop is composed of the first operational amplifier, the first current mirror, the second current mirror, the third current mirror and the power MOSFET.

[0017] Compared with the prior art, the embodiments of this application have the following beneficial effects: (1) The drain-source voltage of the power MOSFET is maintained at the preset minimum drain-source voltage by the minimum drain-source voltage circuit, so that the drain-source voltage of the power MOSFET will not be too low under light load conditions, and the light load detection circuit can still sample the current output by the power MOSFET according to the preset ratio under light load conditions.

[0018] (2) The light load determination circuit compares the current output by the light load detection circuit with the second reference current and generates a control signal. The working state of the minimum drain source voltage circuit is controlled according to the control signal, so as to realize the adaptive activation or deactivation of the minimum drain source voltage regulation according to the load current.

[0019] (3) The minimum drain-source voltage circuit compares the source voltage of the power MOSFET with a preset voltage reference and adjusts the gate voltage of the power MOSFET according to the comparison result, thereby adjusting the drain-source voltage of the power MOSFET and keeping it at the preset minimum drain-source voltage. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram of a light-load adaptive load current sampling circuit according to an embodiment of this application is shown. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0023] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0024] Please refer to Figure 1 This diagram illustrates a structural schematic of a light-load adaptive load current sampling circuit according to an embodiment of this application. The load current sampling circuit includes a power MOSFET, a light-load detection circuit, a light-load determination circuit, and a minimum drain-source voltage circuit, wherein: The first input terminal of the light load detection circuit is connected to the gate of the power MOSFET, the second input terminal of the light load detection circuit is connected to the source of the power MOSFET, the output terminal of the light load detection circuit is connected to the input terminal of the light load determination circuit, the output terminal of the light load determination circuit is connected to the enable terminal of the minimum drain-source voltage circuit, the input terminal of the minimum drain-source voltage circuit is connected to the source of the power MOSFET, and the output terminal of the minimum drain-source voltage circuit is connected to the gate of the power MOSFET. The light load detection circuit is used to sample the current output by the power MOSFET according to a preset ratio; the light load determination circuit is used to compare the current output by the light load detection circuit with a second reference current, generate a control signal, and control the operating state of the minimum drain-source voltage circuit according to the control signal; when the minimum drain-source voltage circuit is in the operating state, it is used to compare the source voltage of the power MOSFET with a preset voltage reference to obtain a voltage comparison result; and adjust the gate voltage of the power MOSFET according to the voltage comparison result to maintain the drain-source voltage of the power MOSFET at a preset minimum drain-source voltage.

[0025] A MOSFET is a voltage-controlled semiconductor switching device that uses the gate voltage to control the conductivity of the conductive channel between the drain and source, thereby controlling the amount of current flowing through it. A MOSFET consists of three electrodes: the drain (D) is the current inflow terminal; the gate (G) is the control terminal, which is controlled by voltage (VGATE); and the source (S) is the current outflow terminal, connected to the load (VOUT).

[0026] The enable terminal is the port on the circuit module that receives control signals and determines whether the module enters the working state. Usually, when the control signal is logic signal 1, the module enters the working state; when the control signal is logic signal 0, the module enters the non-working state.

[0027] Compared with the prior art, the embodiments of this application have the following beneficial effects: (1) The drain-source voltage (VDS) of the power MOSFET is maintained at the preset minimum drain-source voltage by the minimum drain-source voltage circuit, so that the drain-source voltage of the power MOSFET will not be too low under light load conditions, and the light load detection circuit can still sample the current output by the power MOSFET according to the preset ratio under light load conditions.

[0028] (2) The light load determination circuit compares the current output by the light load detection circuit with the second reference current and generates a control signal. The working state of the minimum drain source voltage circuit is controlled according to the control signal, so as to realize the adaptive activation or deactivation of the minimum drain source voltage regulation according to the load current.

[0029] (3) The minimum drain-source voltage circuit compares the source voltage of the power MOSFET with a preset voltage reference and adjusts the gate voltage of the power MOSFET according to the comparison result, thereby adjusting the drain-source voltage of the power MOSFET and keeping it at the preset minimum drain-source voltage.

[0030] See also Figure 1 In a specific embodiment provided in this application, the light-load detection circuit includes a sampling MOSFET, a second operational amplifier, a scaling MOSFET, a first sampling resistor, a second sampling resistor, and a fourth current mirror, wherein: The source of the sampling MOS transistor is connected to one end of the first sampling resistor and the non-inverting input of the second operational amplifier. One end of the second sampling resistor is connected to the inverting input of the second operational amplifier and the source of the scaling MOS transistor. The output of the second operational amplifier is connected to the gate of the scaling MOS transistor. The drain of the scaling MOS transistor is connected to the input of the fourth current mirror. The first input terminal of the light load detection circuit is the gate of the sampling MOS transistor, the second input terminal of the light load detection circuit is the other end of the first sampling resistor and the second sampling resistor, and the output terminal of the light load detection circuit is the output terminal of the fourth current mirror.

[0031] Among them, the sampling MOSFET is used to replicate the power MOSFET current to achieve the first-stage scaling ( The second operational amplifier is a closed-loop error amplifier used to compare the voltages across the first sampling resistor R1 and the second sampling resistor R2; the scaling MOSFET is an actuator driven by the second operational amplifier to implement the second-stage scaling ( R1 is connected to the source circuit of the sampling MOS to sense the sampling current; R2 is connected to the source circuit of the scaling MOS to sense the scaled current; the fourth current mirror is used to mirror the output scaled current.

[0032] In this circuit, the sampling MOSFET current Isample flows through resistor R1, creating a voltage drop across R1. The voltage at the non-inverting input of the second operational amplifier is V2+ = VOUT + Isample × R1. The scaling MOSFET current Iscaled flows through resistor R2, creating a voltage drop across R2. The voltage at the inverting input of the second operational amplifier is V2- = VOUT + Iscaled × R2. The second operational amplifier drives the gate of the scaling MOSFET based on the voltage difference between the non-inverting and inverting inputs, adjusting its conduction level. The scaled current is output from the drain of the scaling MOSFET and fed into a fourth current mirror for reflection.

[0033] Wherein, the sampling MOSFET replicates the current output by the power MOSFET at a first scale, where the first scale is: , The current output from the sampling MOSFET is scaled by the second operational amplifier, the scaling MOSFET, the first sampling resistor, and the second sampling resistor according to a second ratio before being fed into the input terminal of the fourth current mirror. The second ratio is: .

[0034] The embodiments of this application have the following beneficial effects: (1) By using a two-stage scaling structure of sampling MOSFET and scaling MOSFET, the large current output by the power MOSFET is gradually reduced to a small current signal suitable for comparison with the reference current.

[0035] (2) The second ratio is determined by the resistance ratio of the first sampling resistor to the second sampling resistor. The resistance ratio has high matching accuracy in integrated circuit technology, which makes the current scaling ratio stable and accurate.

[0036] (3) The second operational amplifier uses the voltage on the sampling current side as a reference and the voltage on the scaling current side as feedback to drive the gate of the scaling MOS transistor to form a negative feedback closed loop, so that the scaling current automatically follows the sampling current and changes in a fixed proportion without external adjustment.

[0037] See also Figure 1 The light load determination circuit includes a second reference current source, a Schmitt trigger, and an inverter, wherein: The input terminal of the light load determination circuit is the positive terminal of the second reference current source and the input terminal of the Schmitt trigger. The light load determination circuit includes a first output terminal and a second output terminal. The first output terminal of the light load determination circuit is the output terminal of the Schmitt trigger and the input terminal of the inverter. The second output terminal of the light load determination circuit is the output terminal of the inverter.

[0038] The second reference current source Iref2 provides the current threshold for light load determination. A Schmitt trigger shapes the comparison result between the sampled current output from the fourth current mirror and the second reference current output from the second reference current source into a digital logic signal. The difference between a Schmitt trigger and a conventional comparator lies in its hysteresis characteristic. When the current difference between the sampled current output from the fourth current mirror and the second reference current output from the second reference current source decreases from a large value to a small value, it must fall below the lower threshold before flipping to "1" to determine a light load. When the current difference between the sampled current output from the fourth current mirror and the second reference current output from the second reference current source increases from a small value to a large value, it must rise above the upper threshold before flipping to "0" to determine a non-light load. Between the upper and lower thresholds, the output remains unchanged from the previous state. This avoids frequent start-stop of the minimum drain-source voltage circuit due to repeated switching of the control signal when the current fluctuates near the threshold. The Schmitt trigger outputs only one logic signal (light_load_det), but there may be multiple control nodes in the minimum drain-source voltage circuit. The inverter inverts the logic signal output by the Schmitt trigger to obtain another logic signal (light_load_detz), which can control another control node in the minimum drain-source voltage circuit.

[0039] The embodiments of this application have the following beneficial effects: (1) By connecting the positive terminal of the second reference current source and the input terminal of the Schmitt trigger to the same node, the sampling current and the second reference current can be directly compared at this node without the need for an additional independent current comparator, and the circuit structure is simple.

[0040] (2) The Schmitt trigger has hysteresis characteristics. When the sampled current fluctuates near the second reference current, the output remains unchanged from the previous state. It flips only when it exceeds the upper threshold or falls below the lower threshold, thus avoiding the frequent start and stop of the minimum drain-source voltage circuit caused by the control signal switching repeatedly when the load current fluctuates near the light load judgment threshold.

[0041] (3) The output of the Schmitt trigger is converted into a complementary second signal by the inverter. The control signals output from the first and second output terminals are always complementary, which ensures that the two switches controlled by the two control signals will not close or open at the same time.

[0042] See also Figure 1 The minimum drain-source voltage circuit includes a first operational amplifier, a first current mirror, a second current mirror, a third current mirror, a first switch, a second switch, a fifth switch, a pull-up current source, and a pull-down current source; wherein: The non-inverting input of the first operational amplifier is used to input a preset voltage reference. The inverting input of the first operational amplifier is connected to one end of the first switch and one end of the second switch. The other end of the first switch is connected to the source of the power MOSFET. The output of the first operational amplifier is connected to the input of the first current mirror. The output of the first current mirror is connected to the input of the second current mirror and one end of the fifth switch. The other end of the fifth switch is connected to the drive pull-down current source. The output of the second current mirror is connected to the input of the third current mirror. The input terminal of the minimum drain-source voltage circuit is the power supply terminal of the third current mirror, and the output terminal of the minimum drain-source voltage circuit is the output terminal of the third current mirror and the negative terminal of the driving pull-up current source.

[0043] The preset voltage reference Vref is the target clamping voltage of the minimum drain-source voltage circuit, and is a preset value. The first operational amplifier acts as an error amplifier. When the first switch is closed, it compares Vref with the output voltage VOUT of the power MOSFET; when the second switch is closed, it compares Vref with the output voltage of the first power supply VBB. The first, second, and third current mirrors form a three-stage cascaded current mirror system, pulling the output current down to VGATE. When the pull-up current source is working normally, it pulls up VGATE, turning on the power MOSFET; when the pull-down current source is working normally, it pulls down VGATE, turning off the power MOSFET.

[0044] See also Figure 1 The load current sampling circuit further includes a first power supply, a second power supply, and a first reference ground. The minimum drain-source voltage circuit further includes a third switch, a fourth switch, and a first reference current source. The power supply terminal of the first current mirror is connected to one end of the third and fourth switches, and the other end of the third switch is connected to the positive terminal of the first reference current source. The first power supply is connected to the drain of the power MOSFET, the drain of the sampling MOSFET, and the positive power supply terminal of the first operational amplifier, respectively, for supplying power to the power MOSFET, the sampling MOSFET, and the first operational amplifier; the first power supply is also connected to the other end of the second switch; The second power supply is connected to the positive terminal of the drive pull-up current source, the power supply terminal of the second current mirror, and the power supply of the fourth current mirror, and is used to supply power to the drive pull-up current source, the second current mirror, and the fourth current mirror. The first reference ground is connected to the negative terminal of the second reference current source, the negative power supply terminal of the first operational amplifier, the negative terminal of the first reference current source, and the other end of the fourth switch; The voltage output by the second power supply is higher than the voltage output by the first power supply, and the voltage output by the first power supply is higher than the voltage of the first reference ground.

[0045] For example, the voltage output by the second power supply VCP can be about 10V higher than the voltage output by the first power supply VBB, and the voltage output by the first power supply VBB can be about 5V higher than the voltage of the first reference ground VBM5.

[0046] The first reference ground can serve as the negative power supply terminal in the first operational amplifier to ensure the normal operation of the first operational amplifier; it can also serve as the negative terminal of the first reference current source and the second reference current source to form a current loop; and it can also serve as an unlimited current path for the first current mirror during the start-up phase of the load current sampling circuit.

[0047] Wherein, the current output by the second reference current source is the second reference current, wherein: If the current output by the light load detection circuit is less than the second reference current, then the control signal is logic signal 1, the first switch receives logic signal 1 and closes, logic signal 1 is flipped to logic signal 0 by the inverter, the second switch receives logic signal 0 and opens, and the minimum drain-source voltage circuit is in working state. If the current output by the light load detection circuit is greater than or equal to the second reference current, then the control signal is logic signal 0, the first switch receives logic signal 0 and opens, logic signal 0 is flipped into logic signal 1 by the inverter, the second switch receives logic signal 1 and closes, and the minimum drain-source voltage circuit is in a non-operating state.

[0048] The minimum drain-source voltage circuit being in the active state corresponds to a light load scenario, while the minimum drain-source voltage circuit being in the inactive state corresponds to a non-light load scenario. The control signal is the signal output from the first output terminal of the light load determination circuit, and the inverted signal of the control signal is the signal output from the second output terminal of the light load determination circuit.

[0049] Wherein, if the voltage comparison result indicates that the source voltage of the power MOSFET is less than the preset voltage reference, the first operational amplifier outputs current; if the voltage comparison result indicates that the source voltage of the power MOSFET is greater than or equal to the preset voltage reference, the first operational amplifier does not output current. The smaller the source voltage of the power MOSFET is compared to the preset voltage reference, the larger the pull-down current output by the third current mirror to control the gate voltage of the power MOSFET becomes, thereby causing the power MOSFET to enter a saturation state. When the power MOSFET is in a saturation state, the on-resistance and source voltage of the power MOSFET increase until the source voltage of the power MOSFET is maintained near the preset voltage reference, and the minimum drain-source voltage circuit reaches a balance state.

[0050] In this configuration, when the source voltage VOUT of the power MOSFET is less than the preset voltage reference Vref, the first operational amplifier outputs current, the magnitude of which is proportional to the difference (Vref - VOUT). When the source voltage VOUT of the power MOSFET is greater than or equal to the preset voltage reference Vref, the first operational amplifier does not output current. The current output by the first operational amplifier is mirrored stage by stage through a three-stage current mirror link, ultimately resulting in a pull-down current output by the third current mirror, which acts on the gate node VGATE of the power MOSFET. The smaller VOUT is than Vref, the larger the current output by the first operational amplifier, the larger the pull-down current of the third current mirror, and the lower VGATE is pulled down; conversely, the smaller the current output by the first operational amplifier, the smaller the pull-down current, and the slower the drop in VGATE. The pull-down current and the driving pull-up current source counteract each other, jointly regulating the level of VGATE.

[0051] When VGATE is pulled low, the gate-source voltage decreases, and the difference between it and the threshold voltage decreases. When this difference is less than the minimum drain-source voltage to be maintained, the power MOSFET enters the saturation region from the linear region. Therefore, in the linear region, the drain current is affected by both the gate-source voltage and the minimum voltage to be maintained, resulting in inaccurate current replication ratio between the sampling MOSFET and the power MOSFET. In the saturation region, the drain current is determined solely by the gate-source voltage and is independent of the minimum voltage to be maintained, leading to an accurate current replication ratio. Upon entering the saturation region, the on-resistance increases, and VOUT gradually rises from its initial value, which is lower than Vref, approaching Vref, thus increasing the source voltage. As VOUT gradually approaches Vref, the output current of the first operational amplifier approaches zero, VGATE stabilizes, the gate-source voltage stabilizes, and the power MOSFET operates stably in the saturation region. The minimum drain-source voltage to be maintained is equal to VBB - VOUT = VBB - Vref. It can be seen that once VBB and Vref are determined, the minimum drain-source voltage to be maintained is also determined.

[0052] Wherein, the current output by the drive pull-up current source and the current output by the drive pull-down current source are the drive currents under normal non-light load operating conditions, wherein: When the minimum drain-source voltage circuit is in operation, the current output by the drive pull-up current source remains unchanged. The fifth switch changes from the closed state during the normal non-light load operation to the open state. The current path output by the drive pull-down current source is cut off. The current output by the first current mirror after cascading through the second and third current mirrors replaces the current output by the drive pull-down current source.

[0053] Under normal load, the power MOSFET operates in the linear region with low drain-source voltage, low on-resistance, high efficiency, and sufficient sampling accuracy—no minimum drain-source voltage circuit is needed; a fixed push-pull drive suffices. Under light load, the load current is small, the drain-source voltage is extremely low, and the power MOSFET extends deep into the linear region, resulting in distorted replication ratio of the sampling MOSFET. A minimum drain-source voltage circuit is then required to control the gate, using operational amplifier feedback to pull the gate-source voltage low, pushing the power MOSFET into the saturation region and maintaining the minimum drain-source voltage.

[0054] When the minimum drain-source voltage circuit is in the initial stage of operation, the third switch is open, the fourth switch is closed, the power supply terminal of the first current mirror is connected to the first reference ground, and the total current of the first current mirror has no upper limit, which increases the current output by the first current mirror to quickly pull down the gate voltage of the power MOSFET. When the minimum drain-source voltage circuit is in the steady-state phase of operation, the third switch is closed and the fourth switch is open. The power supply terminal of the first current mirror is connected to the first reference ground through the first reference current source. The upper limit of the total current of the first current mirror is the first reference current output by the first reference current source, which reduces the current output by the first current mirror to maintain the stability of the adjustment loop with a small current. The adjustment loop is composed of the first operational amplifier, the first current mirror, the second current mirror, the third current mirror and the power MOSFET.

[0055] In the minimum drain-source voltage circuit, VOUT is much lower than Vref at startup, requiring a rapid pull-down of VGATE to push the power MOSFET into the saturation region; otherwise, sampling will be distorted for a long time. Near the equilibrium point, excessively abrupt current regulation will cause VGATE to fluctuate violently, leading to loop oscillation. Therefore, current limiting is used to improve speed during the initial stage, while current limiting is used to improve accuracy during the steady-state stage.

[0056] In this configuration, switches 3 and 4 are mutually exclusive, with only one closed at any given time. Initially, switch 4 is closed, allowing direct connection without current limiting, while switch 3 is open, preventing the current source from flowing through. In steady-state mode, switch 3 is closed, allowing the current source to flow through, limiting the current, while switch 4 is open, preventing direct connection. This ensures that the power supply terminal of the first current mirror has only one path at any given time, avoiding current uncertainty caused by two paths conducting simultaneously.

[0057] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the implementation methods of this application, and are not intended to limit the scope of the invention.

[0058] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0059] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0060] The above are merely specific embodiments of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A light-load adaptive load current sampling circuit, characterized in that, The load current sampling circuit includes a power MOSFET, a light load detection circuit, a light load determination circuit, and a minimum drain-source voltage circuit, wherein: The first input terminal of the light load detection circuit is connected to the gate of the power MOSFET, the second input terminal of the light load detection circuit is connected to the source of the power MOSFET, the output terminal of the light load detection circuit is connected to the input terminal of the light load determination circuit, the output terminal of the light load determination circuit is connected to the enable terminal of the minimum drain-source voltage circuit, the input terminal of the minimum drain-source voltage circuit is connected to the source of the power MOSFET, and the output terminal of the minimum drain-source voltage circuit is connected to the gate of the power MOSFET. The light load detection circuit is used to sample the current output by the power MOSFET according to a preset ratio; the light load determination circuit is used to compare the current output by the light load detection circuit with a second reference current, generate a control signal, and control the operating state of the minimum drain-source voltage circuit according to the control signal; when the minimum drain-source voltage circuit is in the operating state, it is used to compare the source voltage of the power MOSFET with a preset voltage reference to obtain a voltage comparison result; and adjust the gate voltage of the power MOSFET according to the voltage comparison result to maintain the drain-source voltage of the power MOSFET at a preset minimum drain-source voltage.

2. The load current sampling circuit according to claim 1, characterized in that, The light-load detection circuit includes a sampling MOSFET, a second operational amplifier, a scaling MOSFET, a first sampling resistor, a second sampling resistor, and a fourth current mirror, wherein: The source of the sampling MOS transistor is connected to one end of the first sampling resistor and the non-inverting input of the second operational amplifier. One end of the second sampling resistor is connected to the inverting input of the second operational amplifier and the source of the scaling MOS transistor. The output of the second operational amplifier is connected to the gate of the scaling MOS transistor. The drain of the scaling MOS transistor is connected to the input of the fourth current mirror. The first input terminal of the light load detection circuit is the gate of the sampling MOS transistor, the second input terminal of the light load detection circuit is the other end of the first sampling resistor and the second sampling resistor, and the output terminal of the light load detection circuit is the output terminal of the fourth current mirror.

3. The load current sampling circuit according to claim 2, characterized in that, The light load determination circuit includes a second reference current source, a Schmitt trigger, and an inverter, wherein: The input terminal of the light load determination circuit is the positive terminal of the second reference current source and the input terminal of the Schmitt trigger. The light load determination circuit includes a first output terminal and a second output terminal. The first output terminal of the light load determination circuit is the output terminal of the Schmitt trigger and the input terminal of the inverter. The second output terminal of the light load determination circuit is the output terminal of the inverter.

4. The load current sampling circuit according to claim 3, characterized in that, The minimum drain-source voltage circuit includes a first operational amplifier, a first current mirror, a second current mirror, a third current mirror, a first switch, a second switch, a fifth switch, a pull-up current source, and a pull-down current source; wherein: The non-inverting input of the first operational amplifier is used to input a preset voltage reference. The inverting input of the first operational amplifier is connected to one end of the first switch and one end of the second switch. The other end of the first switch is connected to the source of the power MOSFET. The output of the first operational amplifier is connected to the input of the first current mirror. The output of the first current mirror is connected to the input of the second current mirror and one end of the fifth switch. The other end of the fifth switch is connected to the drive pull-down current source. The output of the second current mirror is connected to the input of the third current mirror. The input terminal of the minimum drain-source voltage circuit is the power supply terminal of the third current mirror, and the output terminal of the minimum drain-source voltage circuit is the output terminal of the third current mirror and the negative terminal of the driving pull-up current source.

5. The load current sampling circuit according to claim 4, characterized in that, The load current sampling circuit further includes a first power supply, a second power supply, and a first reference ground. The minimum drain-source voltage circuit further includes a third switch, a fourth switch, and a first reference current source. The power supply terminal of the first current mirror is connected to one end of the third and fourth switches, and the other end of the third switch is connected to the positive terminal of the first reference current source. The first power supply is connected to the drain of the power MOSFET, the drain of the sampling MOSFET, and the positive power supply terminal of the first operational amplifier, respectively, for supplying power to the power MOSFET, the sampling MOSFET, and the first operational amplifier; the first power supply is also connected to the other end of the second switch; The second power supply is connected to the positive terminal of the drive pull-up current source, the power supply terminal of the second current mirror, and the power supply of the fourth current mirror, and is used to supply power to the drive pull-up current source, the second current mirror, and the fourth current mirror. The first reference ground is connected to the negative terminal of the second reference current source, the negative power supply terminal of the first operational amplifier, the negative terminal of the first reference current source, and the other end of the fourth switch; The voltage output by the second power supply is higher than the voltage output by the first power supply, and the voltage output by the first power supply is higher than the voltage of the first reference ground.

6. The load current sampling circuit according to claim 5, characterized in that, The sampling MOSFET replicates the current output by the power MOSFET at a first scale, where the first scale is: ， The current output from the sampling MOSFET is scaled by the second operational amplifier, the scaling MOSFET, the first sampling resistor, and the second sampling resistor according to a second ratio before being fed into the input terminal of the fourth current mirror. The second ratio is: 。 7. The load current sampling circuit according to claim 6, characterized in that, The current output by the second reference current source is the second reference current, wherein: If the current output by the light load detection circuit is less than the second reference current, then the control signal is logic signal 1, the first switch receives logic signal 1 and closes, logic signal 1 is flipped to logic signal 0 by the inverter, the second switch receives logic signal 0 and opens, and the minimum drain-source voltage circuit is in working state. If the current output by the light load detection circuit is greater than or equal to the second reference current, then the control signal is logic signal 0, the first switch receives logic signal 0 and opens, logic signal 0 is flipped into logic signal 1 by the inverter, the second switch receives logic signal 1 and closes, and the minimum drain-source voltage circuit is in a non-operating state.

8. The load current sampling circuit according to claim 7, characterized in that, If the voltage comparison result indicates that the source voltage of the power MOSFET is less than the preset voltage reference, then the first operational amplifier outputs current; If the voltage comparison result indicates that the source voltage of the power MOSFET is greater than or equal to the preset voltage reference, then the first operational amplifier does not output current. The smaller the source voltage of the power MOSFET is compared to the preset voltage reference, the larger the pull-down current output by the third current mirror to control the gate voltage of the power MOSFET becomes, thereby causing the power MOSFET to enter a saturation state. When the power MOSFET is in a saturation state, the on-resistance and source voltage of the power MOSFET increase until the source voltage of the power MOSFET is maintained near the preset voltage reference, and the minimum drain-source voltage circuit reaches a balance state.

9. The load current sampling circuit according to claim 8, characterized in that, The current output by the drive pull-up current source and the current output by the drive pull-down current source are the drive currents under normal non-light load operating conditions, wherein: When the minimum drain-source voltage circuit is in operation, the current output by the drive pull-up current source remains unchanged. The fifth switch changes from the closed state during the normal non-light load operation to the open state. The current path output by the drive pull-down current source is cut off. The current output by the first current mirror after cascading through the second and third current mirrors replaces the current output by the drive pull-down current source.

10. The load current sampling circuit according to claim 9, characterized in that, When the minimum drain-source voltage circuit is in the initial stage of operation, the third switch is open, the fourth switch is closed, the power supply terminal of the first current mirror is connected to the first reference ground, and the total current of the first current mirror has no upper limit, which increases the current output by the first current mirror to quickly pull down the gate voltage of the power MOSFET. When the minimum drain-source voltage circuit is in the steady-state phase of operation, the third switch is closed and the fourth switch is open. The power supply terminal of the first current mirror is connected to the first reference ground through the first reference current source. The upper limit of the total current of the first current mirror is the first reference current output by the first reference current source, which reduces the current output by the first current mirror to maintain the stability of the adjustment loop with a small current. The adjustment loop is composed of the first operational amplifier, the first current mirror, the second current mirror, the third current mirror and the power MOSFET.

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