Multi-channel frequency time difference measurement method based on MS1050NA measurement chip

Abstract

The application discloses a multi-path frequency signal time difference measurement method based on MS1050NA measurement chips and relates to the technical field of time difference measurement, and comprises the following steps: a communication connection is established, the same reference signal is simultaneously input into each MS1050NA measurement chip, and multiple measured signals are respectively input into the measurement chips; the MCU performs the same register initialization configuration on each measurement chip through a communication interface and controls each measurement chip to start measurement work at the same time; when the measured signal is triggered, the MCU reads measurement data, establishes a STOP data cache pool, and stores and manages the measurement data of each channel of each measurement chip according to a unified channel number of the system; any two measured signal Stop channels are selected, corresponding measurement data is called from the STOP data cache pool, and the time difference between the two measured signal Stops is obtained through difference calculation. The frequency standard measurement is simpler, and the measurement precision is higher.

Description

Technical Field

[0001] This invention relates to the field of time difference measurement technology, and specifically to a method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip. Background Technology

[0002] Traditional frequency signal measurement methods are divided into two types: one is based on traditional FPGA measurement, and the other is based on traditional TDC-GP21 measurement chip.

[0003] Traditional FPGA-based measurement solutions, such as Figure 1 As shown, the hardware design circuit mainly consists of an MCU and an FPGA. The MCU is responsible for human-computer interaction and some necessary control with the FPGA. The FPGA is responsible for counting the deviation between the rising edge of the reference signal and the rising edge of the measured signal. Since the operating frequency of the FPGA is usually between 100MHz and 200MHz, the counting resolution of the FPGA is usually only 10ns to 5ns due to the influence of the operating frequency.

[0004] Solutions based on the traditional TDC-GP21 measurement chip, such as... Figure 2 As shown, the hardware design mainly consists of an MCU and a TDC_GP21. The MCU is responsible for human-computer interaction, as well as configuration and measurement data reading from the TDC_GP21. The TDC_GP21 is responsible for measuring and calculating the rising edges of the input reference signal and the measured signal. Due to the design limitations of the TDC_GP21 chip, it can only measure signals from two channels, and the reference Start signal, the measured StopP_N signal, and the measured Stop2 signal must be of the same type, resulting in a resolution of only 45ps to 90ps.

[0005] This shows that traditional FPGA-based solutions have relatively low resolution accuracy, while GP21-based solutions, although offering some improvement in resolution, still have lower convenience and scalability. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for measuring the time difference of multi-channel frequency signals based on the MS1050NA measurement chip.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] This application presents a method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip, including the following steps:

[0009] Establish a communication connection between the MCU and at least one MS1050NA measurement chip, input the same reference signal REF_CLK to each MS1050NA measurement chip simultaneously, and input multiple measured signals Stop to each MS1050NA measurement chip respectively.

[0010] The MCU performs the same register initialization configuration on each MS1050NA measurement chip through the communication interface, and controls each MS1050NA measurement chip to start measurement work at the same time.

[0011] When the measured signal Stop is triggered, the MCU reads the measurement data corresponding to each measured signal Stop in each MS1050NA measurement chip.

[0012] Establish a STOP data cache pool to store and manage the measurement data of each channel of each MS1050NA measurement chip according to the unified channel number of the system;

[0013] Select any two Stop channels of the measured signals, retrieve the corresponding measurement data from the STOP data buffer pool, and calculate the time difference between the two Stop channels of the measured signals by the difference.

[0014] Furthermore, the register initialization configuration for the MS1050NA measurement chip specifically includes:

[0015] The configuration value of the first register is set to 0x9F to enable the input pins StoP_N-Stop4, REFCLK, and REFID of the MS1050NA measurement chip.

[0016] The configuration value of the second register is set to 0x6F, which is used to internally receive and process the measured signal Stop, so that it is in normal working state, and the measured signal Stop is measured a preset number of times each time.

[0017] The configuration value of the third register is set to 0x00, which is used to configure the interrupt pin INTERUPT to be set to zero as long as one FIFO has a value, so as to operate using the standard FIFO function.

[0018] Configure the remaining registers according to the MS1050NA manual's recommended settings.

[0019] Furthermore, measurements are performed using the MS1050NA measurement chip. By counting the rising edges of the measured signal Stop and the reference signal REF_CLK, the deviation between each measured signal Stop and the reference signal REF_CLK is obtained. The measured data read includes the internal TDC measurement value tREF of the reference clock cycle, the internal TDC measurement value tSTOP of the measured signal Stop to the previous reference clock, and the number of reference clock cycles REFID when the measured signal Stop arrives.

[0020] Furthermore, the formula for calculating the time difference Δt is: Δt=(TSTOP_M-TSTOP_N)+(REFID_M-REFID_N)×REFCLK_DIVISONS, where TSTOP_M represents the internal TDC measurement value of the reference clock corresponding to the stop of the measured signal at time M, TSTOP_N represents the internal TDC measurement value of the reference clock corresponding to the stop of the measured signal at time N, REFID_M represents the number of reference clock cycles corresponding to the stop of the measured signal at time M, REFID_N represents the number of reference clock cycles corresponding to the stop of the measured signal at time N, and REFCLK_DIVISONS is the frequency division coefficient of the reference clock cycle.

[0021] Furthermore, when the trigger times of the two measured signals Stop are within the same reference clock cycle, it is not necessary to read the reference clock cycle number REFID when the measured signal Stop arrives. Instead, the internal TDC measurement value from the measured signal Stop to the previous reference clock is read to calculate the time difference, i.e., Δt=TSTOP_M-TSTOP_N, REFID_M=REFID_N.

[0022] Furthermore, when the measured time difference Δt is always less than the internal TDC measurement value tREF of the reference clock cycle, if it is not necessarily applied within the same reference clock cycle, the positive and negative time differences are distinguished for calculation, and only the measurement result TSTOP value without REFID is read.

[0023] If TSTOP_M-TSTOP_N>0, then Δt=(TSTOP_M–TSTOP_N);

[0024] If TSTOP_M - TSTOP_N < 0 and ΔT <REFCLK_DIVISONS,

[0025] Then Δt = (TSTOP_M – TSTOP_N) + REFCLK_DIVISONS, where ΔT represents the period difference between the two measured signals Stop.

[0026] Furthermore, the measurement data in the STOP data cache pool includes the following fields:

[0027] The MS1050NA measurement chip's serial number (chip_id), the stop channel serial number (chip_ch) of each MS1050NA measurement chip, the serial number (sys_channel) of all measured signals Stop, the reference clock cycle number (refid) when the measured signal Stop arrives in the MS1050NA measurement chip, and the measured value (tStop) of the measured signal Stop.

[0028] Furthermore, it also includes a frequency standard offset calculation step, specifically including:

[0029] Frequency standard measurement result processing: Select any one of the measured channels of the MS1050NA measurement chip as the calculation benchmark, subtract the measurement data of other measured channels, and obtain the phase time difference between the rising edges of any two channels;

[0030] Frequency offset calculation: Based on the frequency standard measurement results, combined with the reference signal frequency and the measured signal frequency, the frequency offset between the two channels is calculated.

[0031] The beneficial effects of this invention are:

[0032] 1) This application proposes a multi-channel time difference measurement design based on MS1050NA, which can improve the resolution to 10~20ps, simplify the design of frequency standard measurement scheme, and make it easier to expand the multi-channel measurement channels; it can provide higher measurement accuracy. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a traditional FPGA measurement scheme in the existing technology;

[0034] Figure 2 This is a schematic diagram of the traditional TDC-GP21 measurement scheme in the existing technology;

[0035] Figure 3 This is a schematic diagram of a multi-channel frequency signal time difference measurement method based on the MS1050NA measurement chip according to an embodiment of the present invention;

[0036] Figure 4 This is a flowchart illustrating the multi-channel frequency signal time difference measurement method based on the MS1050NA measurement chip according to an embodiment of the present invention.

[0037] Figure 5 This is a schematic diagram of the time difference measurement method for multi-channel frequency signal time difference measurement based on the MS1050NA measurement chip according to an embodiment of the present invention;

[0038] Figure 6 This is a schematic diagram illustrating the frequency offset calculation principle of the multi-channel frequency signal time difference measurement method based on the MS1050NA measurement chip in an embodiment of the present invention.

[0039] Figure 7 This is a schematic diagram of the frequency offset measurement calculation results according to an embodiment of the present invention;

[0040] Figure 8 This is a schematic diagram of the time deviation measurement and calculation results according to an embodiment of the present invention. Detailed Implementation

[0041] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] See Figures 3-6 This application discloses a method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip, which can improve the resolution to 10~20ps. Utilizing the characteristics of the MS1050NA measurement chip, each measured Stop signal can be independently measured against the reference signal REF_CLK, obtaining independent time difference interval data. By processing the data of each measured Stop signal through the MCU, and calculating the difference between the measurement data of any two measured Stop signals, the time difference between any two signals can be calculated, greatly improving the scalability of multiple measured signals. The method includes the following steps:

[0043] Establish a communication connection between the MCU (primarily responsible for logic unit operations, communication with the MS1050NA measurement chip, parameter configuration, and data reading) and at least one MS1050NA measurement chip (responsible for measuring the count values ​​of the rising edges of the reference signal REF_CLK and the measured signal Stop). Simultaneously input the same reference signal REF_CLK (a high-stability, high-precision 5MHz clock signal providing a reliable reference for the MS1050NA measurement chip) to each MS1050NA measurement chip, and input multiple measured signals Stop... p (a normal input signal, which can be a 1Hz, 10Hz, or 100Hz signal obtained by dividing 10MHz, 100MHz, or 200MHz, or a normal independent 1Hz, 10Hz, or 100Hz signal) is input to each MS1050NA measurement chip respectively; given the same reference signal REF_CLK, it is ensured that when the measured signal Stop inside each MS1050NA measurement chip is measured with the reference signal REF_CLK, the number of reference clock cycles REFID at the arrival of the same measured signal Stop is calculated.

[0044] The MCU performs the same register initialization configuration on each MS1050NA measurement chip through the communication interface, and controls each MS1050NA measurement chip to start measurement work at the same time.

[0045] When the measured signal Stop is triggered, the MCU reads the measurement data corresponding to each measured signal Stop in each MS1050NA measurement chip.

[0046] Establish a STOP data cache pool to store and manage the measurement data of each channel of each MS1050NA measurement chip according to the unified channel number of the system;

[0047] Select any two Stop channels of the measured signals, retrieve the corresponding measurement data from the STOP data buffer pool, and calculate the time difference between the two Stop channels of the measured signals by the difference.

[0048] For example, the register initialization configuration of the MS1050NA measurement chip specifically includes:

[0049] The configuration value of the first register is set to 0x9F to enable the input pins StoP_N-Stop4, REFCLK, and REFID of the MS1050NA measurement chip.

[0050] The configuration value of the second register is set to 0x6F, which is used to internally receive and process the measured signal Stop, so that it is in normal working state, and the measured signal Stop is measured a preset number of times each time.

[0051] The configuration value of the third register is set to 0x00, which is used to configure the interrupt pin INTERUPT to be set to zero as long as one FIFO has a value, so as to use the standard FIFO function operation.

[0052] Configure the remaining registers according to the MS1050NA manual's recommended settings.

[0053] For example, using the MS1050NA measurement chip, the deviation between each measured signal's Stop and the reference signal REF_CLK is calculated by counting the rising edges of the measured signal Stop and REF_CLK. The measured data includes the internal TDC measurement value tREF of the reference clock cycle, the internal TDC measurement value tSTOP of the measured signal Stop to the previous reference clock cycle, and the reference clock cycle number REFID when the measured signal Stop arrives. These data, tREF, tSTOP, and REFID, can be read through the communication interface between the MCU and the MS1050NA measurement chip.

[0054] For example, taking one MS1050NA chip as an example, the formula for calculating the time difference Δt is: Δt=(TSTOP_M-TSTOP_N)+(REFID_M-REFID_N)×REFCLK_DIVISONS, where TSTOP_M represents the internal TDC measurement value of the reference clock from the Stop of the measured signal to time M, TSTOP_N represents the internal TDC measurement value of the reference clock from the Stop of the measured signal to time N, REFID_M represents the number of reference clock cycles from the Stop of the measured signal to time M, REFID_N represents the number of reference clock cycles from the Stop of the measured signal to time N, and REFCLK_DIVISONS is the frequency division coefficient of the reference clock cycle (configured during MS1050NA configuration initialization).

[0055] For example, when the trigger times of the Stop signals of the two measured signals are within the same reference clock cycle (e.g.) Figure 5 (The first and second pulses), it is not necessary to read the reference clock cycle number REFID when the measured signal Stop arrives. Only the internal TDC measurement value of the measured signal Stop to the previous reference clock is read to calculate the time difference, that is, Δt=TSTOP_M-TSTOP_N, REFID_M=REFID_N.

[0056] For example, when the measured time difference Δt is always less than the internal TDC measurement value tREF of the reference clock cycle, if it is not necessarily applied within the same reference clock cycle (e.g. Figure 5 The second and third pulses in the middle are used to calculate the TSTOP value by distinguishing between positive and negative time differences, and only the measurement result without REFID is read.

[0057] If TSTOP_M-TSTOP_N>0, then Δt=(TSTOP_M–TSTOP_N);

[0058] If TSTOP_M - TSTOP_N < 0 and ΔT <REFCLK_DIVISONS ,

[0059] Then Δt = (TSTOP_M – TSTOP_N) + REFCLK_DIVISONS, where ΔT represents the period difference between the two measured signals Stop.

[0060] For example, the REFID and tSTOP data of the measured signal Stop in each MS1050NA measurement chip are saved as follows:

[0061] #define MS1050_CHIP_CNT 5 typedef struct{

[0062] UI8_T chip_id; UI8_T chip_ch;

[0063] UI16_T sys_channel; UI64 T refid; UI64_T tstop;}

[0064] MS1050 STOP CH INFO T;

[0065] static MS1050_STOP_CH_INFO_T[MS1050_CHIP_CNT].

[0066] For example, the measurement data in the STOP data cache pool includes the following fields:

[0067] The MS1050NA measurement chip's serial number (chip_id), the stop channel serial number (chip_ch) of each MS1050NA measurement chip, the serial number (sys_channel) of all measured signals Stop (when any measured signal Stop is selected, the measurement data of the corresponding measured signal Stop in the MS1050NA measurement chip can be found according to the sys_channel serial number), the reference clock cycle number (refid) when the measured signal Stop arrives in the MS1050NA measurement chip, and the measured value (tStop) of the measured signal Stop.

[0068] For example, the MCU calculates the frequency offset between arbitrary channels based on the selected arbitrary channel sys_channel, specifically including:

[0069] Frequency standard measurement result processing: Select any one of the measured channels of the MS1050NA measurement chip as the calculation benchmark, subtract the measurement data of other measured channels, and obtain the phase time difference between the rising edges of any two channels;

[0070] Frequency offset calculation: Based on the frequency standard measurement results, combined with the reference signal frequency and the measured signal frequency, the frequency offset between the two channels is calculated.

[0071] Specifically, the frequency offset is calculated through... To calculate the frequency offset between any two channels, the frequency offset is... Represented as the frequency of a signal With the frequency of another signal The difference;

[0072] Frequency standard measurement results This is represented as the rising edge of a signal within one cycle. With another signal rising edge The difference, that is, the difference during the frequency standard measurement process;

[0073] When the reference signal frequency Under stable and fixed conditions, within a certain period, the results of frequency standard measurements are obtained. The calculation can calculate the measured signal. frequency Then the frequency offset between the two signals can be calculated. .

[0074] Reference signal frequency for The tested signal The frequency of the number for: ,in, Indicates reference signal The cycle, Indicates reference signal The periods are fixed values, obtainable from hardware specifications before signal generation. The frequency standard measurement results can be used to calculate... ,in, Indicates reference signal The frequency standard measurement results Indicates reference signal Frequency standard measurement results; based on and The period can be used to calculate the reference signal. and the signal being measured frequency offset : .

[0075] For example, since each measured signal in the MS1050NA measurement chip is measured and calculated independently with the reference signal REF_CLK, it is only necessary to design hardware circuitry to connect the same reference signal REF_CLK to multiple MS1050NA measurement chips simultaneously. This allows the measured signals of multiple chips to be measured and calculated based on the same REF_CLK reference signal. Software on the MCU can then be used to calculate the frequency standard offset for any two or more channels. See also... Figure 7 With the selected StoP_N and Stop2 signals both at 10MHz, the frequency deviation of the Stop2 signal relative to the StoP_N signal can be measured. The actual measured frequency deviation between the 10MHz StoP_N and Stop2 signals is approximately between -+0.0033Hz and -0.0041Hz. (See also...) Figure 8With the selected Stop5 and StopP_N0 signals being 1PPS pulses per second, the time deviation of the StopP_N0 signal relative to the Stop5 signal can be measured. The actual measured time deviation between the 1PPS signal of the StopP_N0 and the 1PPS signal of the Stop5 is approximately between 1.856ns and 1.952ns.

[0076] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip, characterized in that, Includes the following steps: Establish a communication connection between the MCU and at least one MS1050NA measurement chip, input the same reference signal REF_CLK to each MS1050NA measurement chip simultaneously, and input multiple measured signals Stop to each MS1050NA measurement chip respectively. The MCU performs the same register initialization configuration on each MS1050NA measurement chip through the communication interface, and controls each MS1050NA measurement chip to start measurement work at the same time. When the measured signal Stop is triggered, the MCU reads the measurement data corresponding to each measured signal Stop in each MS1050NA measurement chip. Establish a STOP data cache pool to store and manage the measurement data of each channel of each MS1050NA measurement chip according to the unified channel number of the system; Select any two Stop channels of the measured signals, retrieve the corresponding measurement data from the STOP data buffer pool, and calculate the time difference between the two Stop channels of the measured signals by the difference.

2. The method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip according to claim 1, characterized in that, The specific register initialization configuration for the MS1050NA measurement chip includes: The configuration value of the first register is set to 0x9F to enable the input pins StoP_N-Stop4, REFCLK, and REFID of the MS1050NA measurement chip. The configuration value of the second register is set to 0x6F, which is used to internally receive and process the measured signal Stop, so that it is in normal working state, and the measured signal Stop is measured a preset number of times each time. The configuration value of the third register is set to 0x00, which is used to configure the interrupt pin INTERUPT to be set to zero as long as one FIFO has a value, so as to operate using the standard FIFO function. Configure the remaining registers according to the MS1050NA manual's recommended settings.

3. The method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip according to claim 1, characterized in that: Measurements are performed using the MS1050NA measurement chip. The deviation between the measured signal Stop and the reference signal REF_CLK is obtained by counting the rising edges of the measured signal Stop and REF_CLK. The measurement data read includes the internal TDC measurement value tREF of the reference clock cycle, the internal TDC measurement value tSTOP of the measured signal Stop to the previous reference clock, and the number of reference clock cycles REFID when the measured signal Stop arrives.

4. The method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip according to claim 3, characterized in that, The formula for calculating the time difference Δt is: Δt=(TSTOP_M-TSTOP_N)+(REFID_M-REFID_N)×REFCLK_DIVISONS, where TSTOP_M represents the internal TDC measurement value of the reference clock from the Stop of the measured signal to time M, TSTOP_N represents the internal TDC measurement value of the reference clock from the Stop of the measured signal to time N, REFID_M represents the number of reference clock cycles from the Stop of the measured signal to time M, REFID_N represents the number of reference clock cycles from the Stop of the measured signal to time N, and REFCLK_DIVISONS is the frequency division coefficient of the reference clock cycle.

5. The method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip according to claim 4, characterized in that: When the trigger times of the two measured signals Stop are within the same reference clock cycle, it is not necessary to read the reference clock cycle number REFID when the measured signal Stop arrives. Instead, the internal TDC measurement value from the measured signal Stop to the previous reference clock is read to calculate the time difference, i.e., Δt=TSTOP_M-TSTOP_N, REFID_M=REFID_N.

6. The method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip according to claim 4, characterized in that: When the measured time difference Δt is always less than the internal TDC measurement value tREF of the reference clock cycle, if it is not necessarily applied within the same reference clock cycle, the calculation is performed by distinguishing between positive and negative time differences, and only the measurement result TSTOP value without REFID is read. If TSTOP_M-TSTOP_N>0, then Δt=(TSTOP_M–TSTOP_N); If TSTOP_M - TSTOP_N < 0 and ΔT <REFCLK_DIVISONS, Then Δt = (TSTOP_M – TSTOP_N) + REFCLK_DIVISONS, where ΔT represents the period difference between the two measured signals Stop.

7. The method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip according to claim 1, characterized in that, The measurement data in the STOP data cache pool includes the following fields: The MS1050NA measurement chip's serial number (chip_id), the stop channel serial number (chip_ch) of each MS1050NA measurement chip, the serial number (sys_channel) of all measured signals Stop, the reference clock cycle number (refid) when the measured signal Stop arrives in the MS1050NA measurement chip, and the measured value (tStop) of the measured signal Stop.

8. The method for measuring the time difference of multiple frequency signals based on the MS1050NA measurement chip according to claim 1, characterized in that: It also includes the frequency standard offset calculation step, specifically including: Frequency standard measurement result processing: Select any one of the measured channels of the MS1050NA measurement chip as the calculation benchmark, subtract the measurement data of other measured channels, and obtain the phase time difference between the rising edges of any two channels; Frequency offset calculation: Based on the frequency standard measurement results, combined with the reference signal frequency and the measured signal frequency, the frequency offset between the two channels is calculated.

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