Memory system and operating method, memory controller and memory storage unit

Abstract

The present disclosure provides a memory system and an operating method, a memory controller and a memory storage unit, and relates to the technical field of semiconductors. The method comprises: in response to a first read command, writing first data from a first storage area to a second storage area, the first data corresponding to a first page; performing an error check and correction (ECC) operation on the first data of the second storage area; and in parallel, reading second data corresponding to a second page from a memory cell array to the first storage area while performing the ECC operation on the first data. According to the present disclosure, by setting two storage areas, the ECC operation and the data reading are performed in parallel, the waiting time is avoided, the overall operation delay is reduced, and thus the data reading speed is improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an operation method of a memory system, a memory system, a memory controller, and a memory storage cell. Background Technology

[0002] Storage devices, such as NAND flash memory, are widely used in SSDs, mobile devices, and memory cards due to their high density and low cost. Flash memory can perform read operations; the array of flash memory cells stores data, and data must first be read from the array of cells before it can be read. Error checking and correction (ECC) operations are used to correct errors in the read data to ensure its accuracy. Currently, read processes with ECC operations are time-consuming.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a memory system and operating method, a memory controller and a memory storage unit, which can improve data reading efficiency.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a method of operating a memory system is provided, comprising: writing first data from a first storage area to a second storage area in response to a first read command, the first data corresponding to a first page; performing error checking and correction (ECC) operations on the first data in the second storage area; and reading second data from a memory cell array into the first storage area in parallel while performing the ECC operation on the first data, the second data corresponding to a second page.

[0007] In some embodiments, the memory system includes a memory controller and a memory storage unit; the first storage area is located in the memory storage unit, and the second storage area is located in the memory controller; or, the first storage area and the second storage area are located in the memory storage unit.

[0008] In some embodiments, the method further includes: acquiring state information of the memory storage unit; generating a second read command when the state information of the memory storage unit is idle; writing second data from a first storage area to a second storage area in response to the second read command; performing error checking and correction (ECC) operations on the second data in the second storage area; and reading third data from the storage unit array into the first storage area in parallel while performing ECC operations on the second data, wherein the third data corresponds to a third page.

[0009] In some embodiments, the memory system includes a status register, the status register including a first status flag bit, the first status flag bit being used to characterize the status information of the memory storage cell; in response to the first read command, the parameter value of the first status flag bit in the status register is updated to a first value, wherein the first value is used to indicate that the status of the memory storage cell is Busy; after the ECC operation on the first data and the read operation on the second data are completed, the parameter value of the first status flag bit in the status register is updated to a second value, wherein the second value is used to indicate that the status of the memory storage cell is Ready; obtaining the status information of the memory storage cell includes: in response to an instruction to obtain the status information of the memory storage cell, obtaining the parameter value of the first flag bit in the status register.

[0010] In some embodiments, the method further includes: statistically analyzing the error patterns of the first data; generating a read parameter adjustment instruction based on the error patterns, the adjustment instruction including at least one of the following: applying a dynamic offset to the read voltage of the third target page, adjusting the read timing configuration of the third target page, and setting a read retry threshold for the third target page; and adjusting the read parameters according to the read parameter adjustment instruction.

[0011] In some embodiments, reading third data from the storage cell array into the first storage area includes: reading third data from the storage cell array into the first storage area according to the read parameters.

[0012] In some embodiments, when performing an ECC operation on the first data, the time for reading the second data from the storage cell array to the first storage area in parallel is 30 microseconds to 80 microseconds.

[0013] According to another aspect of this disclosure, a memory controller is also provided, characterized in that it includes: a controller memory configured to store read commands; and a controller processor coupled to the memory controller and configured to execute the read commands to perform processing, the processing including: writing first data from a first storage area to a second storage area, the first data corresponding to a first page; performing error checking and correction (ECC) operations on the first data in the second storage area; and controlling a data transfer module to read second data from a storage cell array to the first storage area, the second data corresponding to a second page, during the ECC module performing ECC operations on the first data.

[0014] In some embodiments, the second storage area is located in the controller memory.

[0015] In some embodiments, the process includes: acquiring state information of a memory storage cell; generating a second read command when the state information of the memory storage cell is in an idle state; writing second data from a first storage area to a second storage area in response to the second read command; performing error checking and correction (ECC) operations on the second data in the second storage area; and reading third data from the storage cell array into the first storage area in parallel while performing ECC operations on the second data, the third data corresponding to a third page.

[0016] In some embodiments, a status register is further included, configured to store status information of the memory storage unit; the process includes: in response to the first read command, updating the parameter value of the first status flag bit in the status register to a first value, wherein the first value is used to indicate that the status of the memory storage unit is Busy; after the ECC operation on the first data and the read operation on the second data are completed, updating the parameter value of the first status flag bit in the status register to a second value, wherein the second value is used to indicate that the status of the memory storage unit is Ready; in response to an instruction to obtain the status information of the memory storage unit, obtaining the parameter value of the first flag bit in the status register.

[0017] In some embodiments, the process includes: statistically analyzing the error patterns of the first data; generating a read parameter adjustment instruction based on the error patterns, the adjustment instruction including at least one of the following: applying a dynamic offset to the read voltage of the second target page, adjusting the read timing configuration of the second target page, and setting a read retry threshold for the second target page; and adjusting the read parameters according to the read parameter adjustment instruction.

[0018] In some embodiments, the process includes: reading third data from the storage cell array into the first storage area according to the read parameters.

[0019] In some embodiments, the process includes: receiving a page read instruction from a host; and generating a read command based on the page read instruction.

[0020] In some embodiments, the process includes: when performing an ECC operation on the first data, the read time for reading the second data from the storage cell array to the first storage area in parallel is 30 microseconds to 80 microseconds.

[0021] According to another aspect of this disclosure, a memory system is also provided, including a memory controller and memory storage cells, the memory system being configured to: write first data from a first storage area to a second storage area in response to a first read command, the first data corresponding to a first page; perform error checking and correction (ECC) operations on the first data in the second storage area; and, while performing ECC operations on the first data, read second data from a storage cell array in parallel into the first storage area, the second data corresponding to a second page.

[0022] In some embodiments, the first storage area is located in the memory storage unit, and the second storage area is located in the memory controller; or, the first storage area and the second storage area are located in the memory storage unit.

[0023] In some embodiments, the memory system is configured to: acquire state information of the memory storage cell; generate a second read command when the state information of the memory storage cell is idle; write second data from a first storage area to a second storage area in response to the second read command; perform error checking and correction (ECC) operations on the second data in the second storage area; and while performing ECC operations on the second data, read third data from the storage cell array into the first storage area in parallel, the third data corresponding to a third page.

[0024] In some embodiments, the memory system includes a status register, the status register including a first status flag bit, the first status flag bit being used to characterize the status information of the memory storage cell; the memory system is configured to: in response to a first read command, update the parameter value of the first status flag bit in the status register to a first value, wherein the first value is used to indicate that the status of the memory storage cell is Busy; after the ECC operation on the first data and the read operation on the second data are completed, update the parameter value of the first status flag bit in the status register to a second value, wherein the second value is used to indicate that the status of the memory storage cell is Ready; and in response to an instruction to obtain the status information of the memory storage cell, obtain the parameter value of the first flag bit in the status register.

[0025] In some embodiments, the memory system is configured to: count the error patterns of the first data; generate read parameter adjustment instructions based on the error patterns, the adjustment instructions including at least one of the following: applying a dynamic offset to the read voltage of the third target page, adjusting the read timing configuration of the third target page, and setting a read retry threshold for the third target page; and adjust the read parameters according to the read parameter adjustment instructions.

[0026] In some embodiments, the memory system is configured to read third data from the memory cell array into the first memory area according to the read parameters.

[0027] In some embodiments, the memory system is configured such that, when performing an ECC operation on the first data, the time for reading the second data from the memory cell array to the first memory area in parallel is 30 microseconds to 80 microseconds.

[0028] According to another aspect of this disclosure, a memory storage cell is also provided, comprising: a storage cell array, and peripheral circuitry coupled to the storage cell array; the peripheral circuitry is configured to: write first data from a first storage area to a second storage area in response to a first read command, the first data corresponding to a first page; perform error checking and correction (ECC) operations on the first data in the second storage area; and, while performing ECC operations on the first data, read second data from the storage cell array into the first storage area in parallel, the second data corresponding to a second page.

[0029] In some embodiments, the first storage area is located in the memory storage unit; or, the first storage area and the second storage area are located in the memory storage unit.

[0030] In some embodiments, the peripheral circuitry is configured to: write second data from a first storage area to a second storage area in response to a second read command; wherein the second read command is generated when the status information of the memory storage cell is in an idle state, and the status information of the memory storage cell is obtained by acquisition; perform error checking and correction (ECC) operations on the second data in the second storage area; and while performing ECC operations on the second data, read third data from the storage cell array into the first storage area in parallel, the third data corresponding to a third page.

[0031] In some embodiments, the memory storage unit includes a status register, the status register including a first status flag bit, the first status flag bit being used to characterize the status information of the memory storage unit; the peripheral circuit is configured to: in response to the first read command, update the parameter value of the first status flag bit in the status register to a first value, wherein the first value is used to indicate that the status of the memory storage unit is Busy; after the ECC operation on the first data and the read operation on the second data are completed, update the parameter value of the first status flag bit in the status register to a second value, wherein the second value is used to indicate that the status of the memory storage unit is Ready; and in response to an instruction to obtain the status information of the memory storage unit, return the parameter value of the first flag bit in the status register.

[0032] In some embodiments, the peripheral circuit is configured to: adjust the read parameters in response to the read parameter adjustment instruction; the read parameter adjustment instruction is generated based on an error mode, the error mode being obtained by statistically analyzing the first data, and the adjustment instruction includes at least one of the following: applying a dynamic offset to the read voltage of the third target page, adjusting the read timing configuration of the third target page, and setting a threshold for the number of read retries of the third target page.

[0033] In some embodiments, the peripheral circuitry is configured to read third data from the storage cell array into the first storage area according to the read parameters.

[0034] In some embodiments, the peripheral circuitry is configured such that, when performing an ECC operation on the first data, the time for reading the second data from the storage cell array to the first storage area in parallel is 30 microseconds to 80 microseconds.

[0035] According to another aspect of this disclosure, an electronic device is also provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform an operation method of the memory system described in any one of the preceding claims by executing the executable instructions.

[0036] According to another aspect of this disclosure, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the operation method of the memory system described in any of the preceding claims.

[0037] According to another aspect of this disclosure, a computer program product is also provided, comprising: a computer program or instructions, wherein the computer program or instructions, when executed by a processor, implement a method of operating a memory system that implements any of the above.

[0038] This disclosure provides a memory system and operating method, a memory controller, and memory storage cells in its embodiments. The method includes: in response to a first read command, writing first data from a first storage area to a second storage area, the first data corresponding to a first page; performing error checking and correction (ECC) operations on the first data in the second storage area; and while performing the ECC operation on the first data, simultaneously reading second data from a storage cell array into the first storage area, the second data corresponding to a second page. This disclosure, by setting up two storage areas, enables the ECC operation and data reading to be performed in parallel, avoiding wasted waiting time, reducing overall operation latency, and thus improving data reading efficiency.

[0039] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0041] Figure 1 A schematic diagram of an exemplary system having a memory storage unit is shown in an embodiment of the present disclosure;

[0042] Figure 2 A schematic diagram of an exemplary memory controller having a memory system is shown in an embodiment of this disclosure;

[0043] Figure 3 A schematic circuit diagram of a memory storage unit including peripheral circuitry is shown in an embodiment of the present disclosure.

[0044] Figure 4 A schematic diagram of a peripheral circuit according to an embodiment of this disclosure is shown;

[0045] Figure 5 This diagram illustrates an operation method flowchart of a memory system according to an embodiment of the present disclosure;

[0046] Figure 6 This diagram illustrates an interactive operation method of a memory system according to an embodiment of the present disclosure.

[0047] Figure 7 This diagram illustrates an interactive operation method of a memory system according to an embodiment of the present disclosure.

[0048] Figure 8 This diagram illustrates an interactive operation method of a memory system according to an embodiment of the present disclosure.

[0049] Figure 9 This diagram illustrates a method for verifying route verification information according to an embodiment of the present disclosure.

[0050] Figure 10 This diagram illustrates an operation method flowchart of a memory system according to an embodiment of the present disclosure;

[0051] Figure 11 This diagram illustrates a memory controller according to an embodiment of the present disclosure;

[0052] Figure 12 A schematic diagram of a memory storage unit is shown in an embodiment of this disclosure. Detailed Implementation

[0053] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0054] The features, structures, or characteristics described in this disclosure can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more specific details omitted, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0055] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0056] The flowchart shown in the accompanying drawings is merely illustrative and does not necessarily include all content and steps, nor does it require execution in the described order. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0057] In this specification, the terms “a,” “an,” “the,” “the,” and “at least one” are used to indicate the presence of at least one element / component / etc.; the terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markings and are not a limitation on the number of objects.

[0058] The specific implementation methods of the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0059] Figure 1 This diagram illustrates an exemplary system having a memory storage unit according to an embodiment of the present disclosure. Figure 1 As shown, system 100 can be a mobile phone, desktop computer, portable computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory storage unit therein. Figure 1 As shown, system 100 may include a memory system 102 having one or more memory storage units 104 and a memory controller 106, wherein the memory controller 106 may be connected to a host 108.

[0060] The memory storage cell 104 can be any memory disclosed in this disclosure, such as NAND flash memory, which includes a temporary storage area with multiple portions. It should be noted that NAND flash memory is merely one example of a memory. The memory 104 may include any suitable non-volatile memory, such as NOR (NOR Flash Memory), Mask Read-Only Memory (MROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM / E2PROM), One-Time Programmable Read-Only Memory (OTPROM), Non-Volatile Static Random-Access Memory (NVSRAM / NV-SRAM), SONOS Memory (Silicon-Oxide-Nitride-Oxide-Silicon Memory, SONOS), Nano-RAM (NRAM), etc.

[0061] According to some implementations, memory controller 106 is coupled to memory storage unit 104 and host 108 and is configured to control memory storage unit 104. Memory controller 106 can manage data stored in memory storage unit 104 and communicate with host 108. Memory controller 106 can be implemented using microprocessors, microcontroller units (MCUs), field-programmable gate arrays (FPGAs), programmable logic devices (PLDs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), state machines, gated logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0062] In some embodiments, the memory controller 106 and one or more memory storage units 104 can be integrated into various types of memory, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0063] Figure 2 A schematic diagram of an exemplary memory controller having a memory system is shown in an embodiment of this disclosure. For example... Figure 2 As shown, the memory controller 106 is coupled to the host 108 and one or more memory storage units 104, and is used to control the host 108 to send data to the memory storage unit 104 or to read data from the memory storage unit 104 and return it to the host 108. The memory controller 106 includes at least: a controller processor 210, a host interface controller 211, a controller memory 212, an ECC module 213, and a buffer memory 214.

[0064] The controller processor 210 is the core component of the memory controller, used to execute various storage-related instructions and tasks. For example, it parses read / write requests from the computer and translates them into operation commands for the storage devices; manages data caching to improve data read / write efficiency; performs data error correction and verification to ensure data integrity and accuracy; and coordinates parallel operations of multiple storage devices to improve the overall performance of the storage system. The controller processor 210 can be implemented using an embedded processor or an FPGA.

[0065] The host interface controller 211 is a key component for communication between the host and the memory controller. It connects the host 108 and the controller processor 210, undertaking data transmission tasks such as data reading and writing, as well as command reception and transmission. The host interface controller 210 supports multiple interfaces and protocols to adapt to different hardware environments and data transmission requirements, ensuring accurate and efficient data flow between the host and the memory controller, and achieving orderly data access and effective command transmission.

[0066] The controller memory 212, coupled to the controller processor 210, is a storage area for instructions and data of the memory controller, and can provide fast read and write operations and real-time control functions.

[0067] The buffer memory 214, coupled to the controller processor 210, is a component used for temporary data storage and can also be used to cache instructions and data.

[0068] The ECC module 213 is used for error detection and correction of data read from the memory storage unit. The data read from the memory storage unit can be stored in reserved space in memory storage unit 104 or in reserved space in buffer memory 214. It is understood that storing the data read from the memory storage unit in the reserved space of memory storage unit 104 facilitates centralized management of the verification data, while storing the data read from the memory storage unit in the reserved space of buffer memory 214 allows for faster response to error detection and correction needs, ensuring data accuracy and system stability.

[0069] Figure 3 This diagram illustrates a schematic circuit of a memory storage unit including peripheral circuitry, according to an embodiment of the present disclosure. The memory storage unit 300 may be... Figure 1 An example of a memory storage cell 104. Memory 300 may include a storage cell array 301 and peripheral circuitry 302 coupled to the storage cell array 301.

[0070] In some embodiments, the peripheral circuit 302 is configured to perform the operation methods provided in the embodiments of this disclosure. It is understood that the peripheral circuit 302 may be configured to perform the operation methods provided in the embodiments of this disclosure according to instructions received from the memory controller 106.

[0071] Figure 4 This is a schematic diagram of a peripheral circuit provided in an embodiment of this disclosure. (See diagram below.) Figure 4 As shown, the peripheral circuitry 302 may include a page buffer 402, a control logic unit 404, and a register 406. It is understood that in some examples, it may also include... Figure 4 Additional peripheral circuitry not shown.

[0072] In some embodiments, the page buffer 402 can be configured to read data from the memory cell array 301 according to the control signal from the control logic unit 404, connect to the ECC module 213, receive ECC operations from the ECC module 213, and store the ECC verification data in its reserved space.

[0073] In some embodiments, see Figure 4 As shown in (a), the page buffer 402 includes a first subpage buffer 402a and a second subpage buffer 402b. The second subpage buffer 402b is connected to the ECC module 213, receives the ECC operation of the ECC module 213, and writes the verified and corrected data back to the second subpage buffer 402b.

[0074] In some embodiments, see Figure 4As shown in (b), data is moved from page buffer 402 to buffer memory 214 of memory controller 106. Buffer memory 214 receives ECC operation from ECC module 213 and writes back the verified and corrected data to buffer memory 214.

[0075] Control logic unit 404 can be coupled to each part of peripheral circuitry 302 and configured to control the operation of each part. Register 406 can be coupled to control logic unit 404 and may include a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. In some embodiments, the status register may include a first status flag bit, which is used to characterize the status information of the memory storage unit. When the parameter value of the first status flag bit in the status register is a first value (e.g., BUSY = 1), it indicates that the status of the memory storage unit is Busy, indicating that the memory storage unit is performing read, write, erase, or other operations. When the parameter value of the first status flag bit in the status register is a first value (e.g., BUSY = 0), it indicates that the memory storage unit is idle and can receive new read commands.

[0076] Figure 5 A flowchart illustrating an operation method of a memory system according to an embodiment of this disclosure is shown, such as... Figure 4 As shown, the data processing method provided in this embodiment includes the following steps:

[0077] S502, in response to the first read command, writes the first data from the first storage area to the second storage area, and the first data corresponds to the first page.

[0078] In this embodiment, the first read command is an instruction signal used to initiate the action of reading data, and may include a page address, such as the page address of the first page, the page address of the second page, etc. The first data refers to the set of data selected for operation in a specific storage scenario; here, it is the data transferred from the first storage area to the second storage area. The first storage area is a temporary storage area in the memory system. The second storage area is another temporary storage area in the memory system. A page is a logical unit for storing data, and the first data corresponds to the data on the first page.

[0079] It's important to note that memory systems include blocks and pages. A block is a larger unit of storage, typically composed of multiple pages. A block is the smallest unit for erasing data; that is, data erasure is performed on a block-by-block basis. A page, on the other hand, is the basic unit for reading and writing data; data is typically read and written on a page-by-page basis. The page address contains block address information. Because pages are within blocks, the block address allows you to locate the specific block, and by combining this with the page's offset within the block, you can precisely locate a specific page, thus enabling read and write operations on that specific page.

[0080] S504 performs error checking and correction ECC operations on the first data in the second storage area.

[0081] In this embodiment, Error Checking and Correction (ECC) is a data protection mechanism. It uses specific algorithms to detect error bits generated during data transmission or storage and attempts to automatically correct these errors to ensure data accuracy and integrity.

[0082] S506, when performing an ECC operation on the first data, read the second data from the storage cell array in parallel into the first storage area, and the second data corresponds to the second page.

[0083] In this embodiment, the memory cell array is an array structure composed of a large number of memory cells used to store data. The first storage area is used to temporarily store the data to be read. The second page is a storage area unit divided within the memory cell array, and a specific second page is located and accessed through the page address carried by the read command.

[0084] Specifically, while performing an ECC operation on the first data, the system simultaneously reads the second data from the storage cell array and stores it in the first storage area, where the second data corresponds to the second page. This allows for the retrieval of potentially needed data in advance while performing data error checking and correction, improving overall system efficiency.

[0085] In some embodiments, when performing an ECC operation on the first data, the read time for reading the second data from the storage cell array to the first storage area in parallel can be reduced from 50 microseconds to 150 microseconds to 30 microseconds to 80 microseconds. It should be noted that the above read time range, such as 50 microseconds to 150 microseconds, is merely an example. In actual applications, the read time before reduction can be greater than or equal to 150 microseconds; similarly, the read time after reduction can be less than or equal to 30 microseconds.

[0086] In this embodiment, the parallel execution of data reading and verification operations reduces idle time and overall latency, thereby improving the data reading speed.

[0087] In some embodiments, the memory system may include a memory controller, with a first memory area and a second memory area located within the memory controller. Figure 6 This is an interactive schematic diagram of an operation method of a memory system provided in an embodiment of the present disclosure, combined with... Figure 6 As shown, the memory system 102 includes a memory controller 106, which includes a buffer memory 214, with a first storage area 2141 and a second storage area 2142 located in the buffer memory 214. The memory storage unit 104 has a storage unit array.

[0088] During data operations, the data on the second page is moved from the memory cell array to the second storage area of ​​the memory controller. Simultaneously, the memory controller's ECC (Error-Correcting Code) module performs ECC operations on the data on the first page cached in the second storage area. This includes data verification, checking for errors; if errors are found, data correction is performed to correct the erroneous data; finally, the corrected data is written back to ensure data accuracy and integrity.

[0089] In this embodiment, the first storage area and the second storage area are placed in the memory controller. The ECC module of the memory controller can perform ECC operations on the first page data cached in the first storage area, including data verification, error correction and write-back, so as to detect and correct data errors in a timely manner and ensure the accuracy and integrity of the data.

[0090] In some embodiments, the memory system may include a memory controller and a memory storage unit, with a first storage area and a second storage area located in the memory storage unit. Figure 7 This is an interactive schematic diagram of an operation method of a memory system provided in an embodiment of the present disclosure, combined with... Figure 7 As shown, the memory system 102 includes a memory controller 106 and a memory storage unit 104. The memory storage unit 104 includes a page buffer 402, and a first storage area 4021 and a second storage area 4022 are located in the page buffer 402. The memory storage unit 104 has a memory cell array.

[0091] In this embodiment, data movement and ECC operations are performed in parallel. While the data of the second page is moved from the storage cell array to the first storage area of ​​the page buffer, the ECC module of the memory controller performs ECC operations on the data of the first page cached in the second storage area of ​​the page buffer.

[0092] In this embodiment, data transfer and ECC operations are performed within the memory storage unit, eliminating the need for frequent large-scale data transfers between the memory controller and the memory storage unit, thus reducing transmission time. Furthermore, by placing the first and second storage areas within the memory storage unit while improving efficiency through parallel processing, data transmission latency can be reduced.

[0093] In some embodiments, the memory system may include a memory controller and a memory storage unit, with a first storage area located in the memory storage unit and a second storage area located in the memory controller. Figure 8 This is an interactive schematic diagram of an operation method of a memory system provided in an embodiment of the present disclosure, combined with... Figure 8 As shown, the memory system 102 includes a memory controller 106 and memory storage units 104. The memory controller 106 includes a buffer memory 214, and the memory storage units 104 include a page buffer 402. A first storage area 4022 is located in the page buffer 402, and a second storage area 2141 is located in the buffer memory 214. The memory storage units 104 have a memory cell array.

[0094] In this embodiment, two actions occur in parallel during operation. On one hand, the data of the second page in the memory storage unit array is moved to the first storage area of ​​the page buffer; on the other hand, the ECC module of the memory controller performs an ECC operation on the first page data cached in the second storage area of ​​the buffer memory.

[0095] In this embodiment, such parallel operation can improve data processing efficiency and ensure the accuracy and reliability of data.

[0096] In some embodiments, Figure 9 This is a flowchart illustrating another method of operating a memory system provided in this disclosure, combined with... Figure 9 As shown, the operation method of the memory system also includes the following steps:

[0097] S902, obtain the status information of the memory storage unit.

[0098] In some embodiments, the memory system includes a status register, which includes a first status flag bit used to characterize the status information of a memory storage cell; in response to a first read command, the parameter value of the first status flag bit in the status register is updated to a first value, wherein the first value is used to indicate that the status of the memory storage cell is Busy; after the ECC operation on the first data and the read operation on the second data are completed, the parameter value of the first status flag bit in the status register is updated to a second value, wherein the second value is used to indicate that the status of the memory storage cell is Ready; in response to an instruction to obtain the status information of the memory storage cell, the parameter value of the first flag bit in the status register is obtained.

[0099] In this embodiment, the user (such as a host system, such as a CPU or main control chip) sends a GET_FEATURE command to the memory storage unit through the memory controller to query the status of the memory storage unit. The memory controller forwards this command to the memory storage unit and waits for its response. GET_FEATURE returns a BUSY status. If BUSY = 1, it indicates that the memory storage unit is performing read, write, or erase operations. If BUSY = 0, it indicates that the memory storage unit is idle and can receive new read commands.

[0100] S904: When the status information of the memory storage cell is idle, a second read command is generated.

[0101] In this embodiment, the memory controller will continue to send read commands to the memory storage unit only when BUSY = 0. The memory storage unit then performs the actual physical read operation (such as reading data from a page of the NAND Flash). In this embodiment, after the data of the current page is moved, the page address of the read command is updated to point to the new target address for the next operation, which can ensure the continuity and efficiency of the data processing flow.

[0102] S906, in response to the second read command, writes the second data from the first storage area to the second storage area.

[0103] S908 performs error checking and correction (ECC) operations on the second data in the second storage area.

[0104] S910, when performing ECC operation on the second data, reads the third data from the storage cell array in parallel into the first storage area, and the third data corresponds to the third page.

[0105] In some embodiments, this disclosure supports the function of continuously reading multiple pages of data or reading specific pages on demand (non-continuously) to flexibly adapt to different working modes.

[0106] Example 1

[0107] Page addresses N, N+1, and N+2 are read sequentially, and parallel operations are achieved using the first and second memory areas.

[0108] Initial State: Both the first and second storage areas are in an idle state (status = IDLE); pages N, N+1, and N+2 in the storage cell array are arranged in physical order. Reading Page N to the First Storage Area: The memory controller sends a read instruction Read(N) to transfer the data of page N from the second storage area to the first storage area. The status of the first storage area is updated to BUSY, and an ECC operation is initiated. Parallel Operation Trigger: During the ECC operation of page N, a read instruction Read(N+1) for page N+1 is automatically initiated, and the data is stored in the second storage area. A GET FEATURE instruction is sent to update the status bit BUSY in the status register. BUSY = 0 indicates that both storage areas are ready, and BUSY = 1 indicates that either storage area is BUSY. When both the ECC operation and the parallel read operation are completed (BUSY = 0), a read command is sent to read page N+1 into the second storage area. Simultaneously, page N+2 is read from the first storage area. This process is repeated until all consecutive pages are read. This embodiment operates in parallel on two storage areas while continuously loading data from multiple pages through a continuous read mechanism. This allows ECC operations to overlap with data transmission, improving read efficiency. Furthermore, the two buffers are always in an alternating busy state, avoiding resource idleness. This approach can be applied to scenarios involving large file reading.

[0109] Example 2

[0110] Reading non-contiguous pages N, M, and K (e.g., N = 0x1000, M = 0x5000, K = 0x2000) requires dynamic management of the cache and address mapping, and parallel operation is achieved using the first and second storage areas.

[0111] Initial state: Both the first and second storage areas are IDLE, with no prefetch rules. Page N is read into the first storage area. The user explicitly sends Read(N), the data is stored in the first storage area, and ECC is initiated. The first storage area is marked as BUSY. Random page M read decision: If the second storage area is IDLE, the user sends Read(M), page M is read into the second storage area in parallel, and the second storage area is marked as BUSY. When the ECC of page N is completed (the first storage area returns to IDLE), page M is transferred from the second storage area to the first storage area, ECC is initiated, the second storage area is marked as IDLE, the user sends Read(K), and this process repeats until all non-contiguous pages are read. This embodiment utilizes the state transitions of the two storage areas to achieve parallel reading of non-contiguous pages, improving efficiency and applicable to scenarios with distributed data storage.

[0112] In some embodiments, to further improve read quality, Figure 10 This is a flowchart illustrating another method of operating a memory system provided in this disclosure, combined with... Figure 10 As shown, the method also includes:

[0113] S110, Error pattern for the first data point.

[0114] In this embodiment, the ECC module of the memory controller can statistically analyze the error patterns of the first data. Error patterns can include the physical location distribution of error bits within a page, as well as the maximum length and distribution density of consecutive error bits.

[0115] S112, generate read parameter adjustment instructions according to the error mode. The adjustment instructions include at least one of the following: apply a dynamic offset to the read voltage of the third target page, adjust the read timing configuration of the third target page, and set the read retry threshold of the third target page.

[0116] In this embodiment, since the ECC operation of the first page and the reading of the second page are executed in parallel, the reading parameters of the third page after the second page are adjusted to improve the reading quality of the subsequent third page, thereby reducing the error rate and ensuring the accuracy of data reading. Reading voltage affects data reading accuracy; dynamic offset can change the voltage value in real time according to the error mode, making the reading more precise. Reading timing refers to the timing and rhythm of data reading; adjusting it can adapt to changes in storage unit characteristics and reduce read errors caused by timing mismatches. Setting a threshold for the number of read retry attempts is to avoid wasting resources with unlimited retries. When a read fails, the system retryes; this threshold specifies the maximum number of retries, and a reasonable setting can balance the read success rate and efficiency.

[0117] S114, adjust the read parameters according to the read parameter adjustment instruction.

[0118] In this embodiment, if error bits accumulate at the page edge, voltage compensation is applied to the adjacent word lines of the third target page; if the length of consecutive error bits exceeds a threshold, the number of read retries for the third target page is increased to a preset upper limit.

[0119] In some embodiments, reading third data from the storage cell array into the first storage area includes: reading third data from the storage cell array into the first storage area according to read parameters.

[0120] In this embodiment, by embedding error mode analysis and dynamic parameter adjustment into the parallel process of ECC operation and data transmission, a closed-loop control of "correcting errors and optimizing simultaneously" is achieved, which can improve data reading quality and thus increase data reading rate.

[0121] Figure 11This is a schematic diagram of a memory controller provided in an embodiment of the present disclosure, combined with... Figure 11 As shown, the memory controller includes:

[0122] Controller memory 111 is configured to store read commands; and

[0123] The controller processor 112 is coupled to the memory controller and configured to execute read commands to perform processing, the processing including: writing first data from a first storage area to a second storage area, the first data corresponding to a first page; performing error checking and correction ECC operations on the first data in the second storage area; and controlling the data transfer module to read second data from the storage cell array to the first storage area, the second data corresponding to a second page, while the ECC module performs ECC operations on the first data.

[0124] In some embodiments, the second storage area is located in the controller memory.

[0125] In some embodiments, the controller processor 112 is configured to: acquire state information of a memory storage cell; generate a second read command when the state information of the memory storage cell is idle; write second data from a first storage area to a second storage area in response to the second read command; perform error checking and correction (ECC) operations on the second data in the second storage area; and while performing ECC operations on the second data, read third data from the storage cell array into the first storage area in parallel, wherein the third data corresponds to a third page.

[0126] In some embodiments, a status register is also included, configured to store status information of the memory storage unit;

[0127] The controller processor 112 is configured to: update the parameter value of the first status flag bit in the status register to a first value in response to a first read command, wherein the first value is used to indicate that the status of the memory storage unit is Busy; update the parameter value of the first status flag bit in the status register to a second value after the ECC operation on the first data and the read operation on the second data are completed, wherein the second value is used to indicate that the status of the memory storage unit is Ready; and retrieve the parameter value of the first flag bit in the status register in response to a command to retrieve the status information of the memory storage unit.

[0128] In some embodiments, the controller processor 112 is configured to: count error patterns of the first data; generate read parameter adjustment instructions based on the error patterns, the adjustment instructions including at least one of the following: applying a dynamic offset to the read voltage of the second target page, adjusting the read timing configuration of the second target page, and setting a read retry threshold for the second target page; and adjust the read parameters according to the read parameter adjustment instructions.

[0129] In some embodiments, the controller processor 112 is configured to: read third data from the storage cell array into the first storage area according to read parameters.

[0130] In some embodiments, the controller processor 112 is configured to: receive a page read instruction from the host; and generate a read command based on the page read instruction.

[0131] In some embodiments, the controller processor 112 is configured to: reduce the read time from the storage cell array to the first storage area from 50 microseconds to 150 microseconds to 30 microseconds to 80 microseconds when performing an ECC operation on the first data.

[0132] Figure 12 This is a schematic diagram of a memory storage unit provided in an embodiment of the present disclosure, combined with... Figure 12 As shown, the memory storage unit includes: a storage cell array 121, and peripheral circuitry 123 coupled to the storage cell array; the peripheral circuitry is configured to: in response to a first read command, write first data from a first storage area to a second storage area, the first data corresponding to a first page; perform error checking and correction (ECC) operations on the first data in the second storage area; and while performing ECC operations on the first data, read second data from the storage cell array into the first storage area in parallel, the second data corresponding to a second page.

[0133] In some embodiments, the first storage area is located in the memory storage unit, or the first storage area and the second storage area are located in the memory storage unit.

[0134] In some embodiments, the peripheral circuitry is configured to: write second data from the first storage area to the second storage area in response to a second read command; wherein the second read command is generated when the status information of the memory storage cell is in an idle state, and the status information of the memory storage cell is obtained by acquisition; perform error checking and correction (ECC) operations on the second data in the second storage area; and while performing ECC operations on the second data, read third data from the storage cell array into the first storage area in parallel, wherein the third data corresponds to a third page.

[0135] In some embodiments, the memory storage unit includes a status register, which includes a first status flag bit used to characterize the status information of the memory storage unit; the peripheral circuitry is configured to: in response to a first read command, update the parameter value of the first status flag bit in the status register to a first value, wherein the first value is used to indicate that the status of the memory storage unit is Busy; after the ECC operation on the first data and the read operation on the second data are completed, update the parameter value of the first status flag bit in the status register to a second value, wherein the second value is used to indicate that the status of the memory storage unit is Ready; and in response to an instruction to obtain the status information of the memory storage unit, return the parameter value of the first flag bit in the status register.

[0136] In some embodiments, the peripheral circuitry is configured to: adjust read parameters in response to a read parameter adjustment instruction; the read parameter adjustment instruction is generated based on an error mode, the error mode being obtained by statistical analysis of first data, and the adjustment instruction includes at least one of the following: applying a dynamic offset to the read voltage of the third target page, adjusting the read timing configuration of the third target page, and setting a threshold for the number of read retries of the third target page.

[0137] In some embodiments, the peripheral circuitry is configured to read third data from the memory cell array into the first memory area according to read parameters.

[0138] In some embodiments, the peripheral circuitry is configured such that, when performing an ECC operation on the first data, the read time from the second data to the first storage area in parallel is reduced from 50 microseconds to 150 microseconds to 30 microseconds to 80 microseconds.

[0139] It should be noted that the examples and application scenarios implemented by the modules in the above device embodiments and the corresponding steps in the method embodiments are the same, but are not limited to the content disclosed in the above method embodiments. It should also be noted that the above modules, as part of the device, can be executed in a computer system such as a set of computer-executable instructions.

[0140] Those skilled in the art will understand that various aspects of this disclosure can be implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which can be collectively referred to herein as a "circuit", "module" or "system".

[0141] Based on the same inventive concept, this disclosure also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements any of the above-described data processing methods. Since the principle by which this computer-readable storage medium embodiment solves the problem is similar to that of the above-described method embodiments, the implementation of this computer-readable storage medium embodiment can refer to the implementation of the above-described method embodiments, and repeated details will not be elaborated further.

[0142] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0143] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.

[0144] Optionally, the program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0145] In practical implementation, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0146] Based on the same inventive concept, this disclosure also provides a computer program product, including a computer program or instructions, which, when executed by a processor, implements any one of the data processing methods described in the above method embodiments. Since the principle by which this computer program product embodiment solves the problem is similar to that of the above method embodiments, the implementation of this computer program product embodiment can refer to the implementation of the above method embodiments, and repeated details will not be elaborated further.

[0147] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0148] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0149] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0150] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for operating a memory system, characterized in that, include: In response to the first read command, the first data is written from the first storage area to the second storage area, and the first data corresponds to the first page; Perform error checking and correction ECC operations on the first data in the second storage area; When performing an ECC operation on the first data, second data is read from the storage cell array into the first storage area in parallel, and the second data corresponds to the second page.

2. The method of operating the memory system according to claim 1, characterized in that, The memory system includes a memory controller and memory storage units; The first storage area is located in the memory storage unit, and the second storage area is located in the memory controller; or, The first storage area and the second storage area are located in the memory storage unit.

3. The method of operating the memory system according to claim 2, characterized in that, The method further includes: Obtain the status information of the memory storage unit; When the status information of the memory storage unit is in an idle state, a second read command is generated; In response to the second read command, the second data is written from the first storage area to the second storage area; Perform error checking and correction ECC operations on the second data in the second storage area; When performing an ECC operation on the second data, third data is read from the storage cell array into the first storage area in parallel, and the third data corresponds to the third page.

4. The method of operating the memory system according to claim 3, characterized in that, The memory system includes a status register, which includes a first status flag bit, which is used to characterize the status information of the memory storage unit. In response to the first read command, the parameter value of the first status flag bit in the status register is updated to a first value, wherein the first value is used to indicate that the status of the memory storage unit is Busy. After the ECC operation on the first data and the read operation on the second data are completed, the parameter value of the first status flag bit in the status register is updated to the second value, wherein the second value is used to indicate that the status of the memory storage unit is Ready. The step of obtaining the status information of the memory storage unit includes: In response to an instruction to obtain the status information of the memory storage unit, the parameter value of the first flag bit in the status register is obtained.

5. The method of operating the memory system according to claim 3, characterized in that, The method further includes: Analyze the error patterns in the first data; Based on the error mode, a read parameter adjustment instruction is generated, the adjustment instruction including at least one of the following: applying a dynamic offset to the read voltage of the third target page, adjusting the read timing configuration of the third target page, and setting a read retry threshold for the third target page; Adjust the reading parameters according to the reading parameter adjustment command.

6. The method of operating the memory system according to claim 5, characterized in that, The step of reading third data from the storage cell array into the first storage area includes: According to the read parameters, third data is read from the storage cell array into the first storage area.

7. The method of operating the memory system according to claim 1, characterized in that, When performing an ECC operation on the first data, the time for reading the second data from the storage cell array to the first storage area in parallel is 30 microseconds to 80 microseconds.

8. A memory controller, characterized in that, include: The controller memory is configured to store read commands; as well as A controller processor, coupled to the memory controller and configured to execute the read command to perform processing, the processing including: First data is written from the first storage area to the second storage area, and the first data corresponds to the first page; Perform error checking and correction ECC operations on the first data in the second storage area; During the ECC operation performed on the first data by the ECC module, the data transmission module is controlled to read the second data from the storage unit array into the first storage area, and the second data corresponds to the second page.

9. The memory controller according to claim 8, characterized in that, The second storage area is located in the controller memory.

10. The memory controller according to claim 9, characterized in that, The process includes: Obtain the status information of the memory storage unit; When the status information of the memory storage unit is in an idle state, a second read command is generated; In response to the second read command, the second data is written from the first storage area to the second storage area; Perform error checking and correction ECC operations on the second data in the second storage area; When performing an ECC operation on the second data, third data is read from the storage cell array into the first storage area in parallel, and the third data corresponds to the third page.

11. The memory controller according to claim 10, characterized in that, It also includes a status register, configured to store status information of the memory storage unit; The process includes: In response to the first read command, the parameter value of the first status flag bit in the status register is updated to a first value, wherein the first value is used to indicate that the status of the memory storage unit is Busy. After the ECC operation on the first data and the read operation on the second data are completed, the parameter value of the first status flag bit in the status register is updated to the second value, wherein the second value is used to indicate that the status of the memory storage unit is Ready. In response to an instruction to obtain the status information of the memory storage unit, the parameter value of the first flag bit in the status register is obtained.

12. The memory controller according to claim 10, characterized in that, The process includes: Analyze the error patterns in the first data; Based on the error mode, a read parameter adjustment instruction is generated, the adjustment instruction including at least one of the following: applying a dynamic offset to the read voltage of the second target page, adjusting the read timing configuration of the second target page, and setting a read retry threshold for the second target page; Adjust the reading parameters according to the reading parameter adjustment command.

13. The memory controller according to claim 13, characterized in that, The process includes: According to the read parameters, third data is read from the storage cell array into the first storage area.

14. The memory controller according to claim 8, characterized in that, The process includes: Receive page read instructions from the host; A read command is generated based on the page read instruction.

15. The memory controller according to claim 8, characterized in that, The process includes: When performing an ECC operation on the first data, the time for reading the second data from the storage cell array to the first storage area in parallel is 30 microseconds to 80 microseconds.

16. A memory system, comprising a memory controller and memory storage units, characterized in that, The memory system is configured as follows: In response to the first read command, the first data is written from the first storage area to the second storage area, and the first data corresponds to the first page; Perform error checking and correction ECC operations on the first data in the second storage area; When performing an ECC operation on the first data, second data is read from the storage cell array into the first storage area in parallel, and the second data corresponds to the second page.

17. The memory system according to claim 16, characterized in that, The first storage area is located in the memory storage unit, and the second storage area is located in the memory controller; or, The first storage area and the second storage area are located in the memory storage unit.

18. The memory system according to claim 17, characterized in that, The memory system is configured as follows: Obtain the status information of the memory storage unit; When the status information of the memory storage unit is in an idle state, a second read command is generated; In response to the second read command, the second data is written from the first storage area to the second storage area; Perform error checking and correction ECC operations on the second data in the second storage area; When performing an ECC operation on the second data, third data is read from the storage cell array into the first storage area in parallel, and the third data corresponds to the third page.

19. The memory system according to claim 18, characterized in that, The memory system includes a status register, which includes a first status flag bit, which is used to characterize the status information of the memory storage unit. The memory system is configured as follows: In response to the first read command, the parameter value of the first status flag bit in the status register is updated to a first value, wherein the first value is used to indicate that the status of the memory storage unit is Busy. After the ECC operation on the first data and the read operation on the second data are completed, the parameter value of the first status flag bit in the status register is updated to the second value, wherein the second value is used to indicate that the status of the memory storage unit is Ready. In response to an instruction to obtain the status information of the memory storage unit, the parameter value of the first flag bit in the status register is obtained.

20. The memory system according to claim 18, characterized in that, The memory system is configured as follows: Analyze the error patterns in the first data; Based on the error mode, a read parameter adjustment instruction is generated, the adjustment instruction including at least one of the following: applying a dynamic offset to the read voltage of the third target page, adjusting the read timing configuration of the third target page, and setting a read retry threshold for the third target page; Adjust the reading parameters according to the reading parameter adjustment command.

21. The memory system according to claim 20, characterized in that, The memory system is configured as follows: According to the read parameters, third data is read from the storage cell array into the first storage area.

22. The memory system according to claim 16, characterized in that, The memory system is configured such that, when performing an ECC operation on the first data, the time for reading the second data from the memory cell array to the first memory area in parallel is 30 microseconds to 80 microseconds.

23. A memory storage unit, characterized in that, include: Storage cell array, and Peripheral circuitry coupled to the memory cell array; The peripheral circuit is configured as follows: In response to the first read command, the first data is written from the first storage area to the second storage area, and the first data corresponds to the first page; Perform error checking and correction ECC operations on the first data in the second storage area; When performing an ECC operation on the first data, second data is read from the storage cell array into the first storage area in parallel, and the second data corresponds to the second page.

24. The memory storage unit according to claim 23, characterized in that, The first storage area is located in the memory storage unit; or, The first storage area and the second storage area are located in the memory storage unit.

25. The memory storage unit according to claim 24, characterized in that, The peripheral circuit is configured as follows: In response to the second read command, second data is written from the first storage area to the second storage area; wherein, the second read command is generated when the status information of the memory storage unit is in an idle state, and the status information of the memory storage unit is obtained by acquisition; Perform error checking and correction ECC operations on the second data in the second storage area; When performing an ECC operation on the second data, third data is read from the storage cell array into the first storage area in parallel, and the third data corresponds to the third page.

26. The memory storage unit according to claim 25, characterized in that, The memory storage unit includes a status register, and the status register includes a first status flag bit, which is used to characterize the status information of the memory storage unit. The peripheral circuit is configured as follows: In response to the first read command, the parameter value of the first status flag bit in the status register is updated to a first value, wherein the first value is used to indicate that the status of the memory storage unit is Busy. After the ECC operation on the first data and the read operation on the second data are completed, the parameter value of the first status flag bit in the status register is updated to the second value, wherein the second value is used to indicate that the status of the memory storage unit is Ready. In response to an instruction to obtain the status information of the memory storage unit, the parameter value of the first flag bit in the status register is returned.

27. The memory storage unit according to claim 25, characterized in that, The peripheral circuit is configured as follows: In response to the read parameter adjustment instruction, the read parameters are adjusted; the read parameter adjustment instruction is generated based on the error mode, the error mode is obtained by statistical analysis of the first data, and the adjustment instruction includes at least one of the following: applying a dynamic offset to the read voltage of the third target page, adjusting the read timing configuration of the third target page, and setting a threshold for the number of read retries of the third target page.

28. The memory storage unit according to claim 27, characterized in that, The peripheral circuit is configured as follows: According to the read parameters, third data is read from the storage cell array into the first storage area.

29. The memory storage unit according to claim 23, characterized in that, The peripheral circuit is configured as follows: When performing an ECC operation on the first data, the time for reading the second data from the storage cell array to the first storage area in parallel is 30 microseconds to 80 microseconds.

Images