Register debug system

Abstract

The application provides a register debugging system, comprising: a plurality of IP modules, each of the IP modules comprising an interface access unit and at least one register connected with the interface access unit; the interface access units in the plurality of IP modules are connected in series to form a serial debugging link, the serial debugging link being used for serial transmission of debugging signals of the registers; a debugging clock source being used for driving the serial debugging link; the serial debugging link being independent of a system bus, and the debugging clock source being independent of a system bus clock. The system provided by the application realizes independent debugging access paths for the registers of the IP modules in the chip, solves the problem that in the related art, a debugging mode depends on the system bus and the registers cannot be read and written when the bus is hung, and greatly improves the reliability and fault coverage of the register debugging.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a register debugging system. Background Technology

[0002] Currently, debugging of the chip's internal registers is typically based on JTAG (Joint Test Action Group).

[0003] However, JTAG-based register access relies on the normal routing of the chip's system bus. If the system bus fails or other deep hangs occur, JTAG-based register debugging immediately becomes ineffective. Furthermore, JTAG-based register debugging cannot cover all internal registers of the chip, making it difficult to guarantee the reliability and comprehensiveness of register debugging. Summary of the Invention

[0004] This invention provides a register debugging system to address the shortcomings of poor stability and insufficient coverage in related technologies for register debugging.

[0005] This invention provides a register debugging system, comprising: Multiple IP modules, each IP module including an interface access unit and at least one register connected to the interface access unit; the interface access units in the multiple IP modules are connected in series to form a serial debugging link, which is used to serially transmit debugging signals of the register; A debug clock source is used to drive the serial debug link; The serial debug link is independent of the system bus, and the debug clock source is independent of the system bus clock.

[0006] According to a register debugging system provided by the present invention, the debugging signal includes: The valid bit field is used to indicate whether the debug signal is valid; The read / write control field is used to indicate whether the debug signal corresponds to a read or write operation; The address field is used to indicate the offset address of the register to be debugged within the register debugging system; The data field is used to carry the register value corresponding to the read operation or the write operation; The master device identifier field is used to identify the master device that initiated this debugging process.

[0007] According to a register debugging system provided by the present invention, the interface access unit is used for: When a debug signal corresponding to a write operation is received through the serial debug link, the data field of the debug signal is written into the register pointed to by the address field in the IP module, a feedback debug signal is generated based on the value written into the register, and the feedback debug signal is returned to the debug master device through the serial debug link. Upon receiving a debug signal corresponding to a read operation via the serial debug link, the register value is read from the register pointed to by the address field in the IP module, a feedback debug signal is generated based on the register value, and the feedback debug signal is returned to the debug master device via the serial debug link.

[0008] According to a register debugging system provided by the present invention, the IP module further includes a system bus interface, which is used to connect to the system bus, and the system bus interface is independent of the interface access unit.

[0009] According to the register debugging system provided by the present invention, a bridging module is further included, the bridging module being connected to the serial debugging link and multiple debugging master devices; The bridging module is used to serially forward multiple concurrent debugging signals to the serial debugging link based on the debugging priority order of the multiple debugging master devices when multiple debugging master devices send concurrent debugging signals.

[0010] According to a register debugging system provided by the present invention, the bridging module is further configured to receive the debugging signal returned by the interface access unit based on the serial debugging link, and forward the debugging signal to the corresponding debugging master device.

[0011] According to the register debugging system provided by the present invention, it further includes a cross-die conversion module, which is connected to the serial debugging link within the die and the die interconnect link between dies respectively; The cross-die conversion module is used to convert the debug signal output from the serial debug link into a cross-die signal and input it to the die interconnect link, and to convert the cross-die signal output from the die interconnect link into a debug signal and input it to the serial debug link.

[0012] According to a register debugging system provided by the present invention, the cross-die conversion module is further used for: While converting the debug signal into a die-crossing signal, a die-crossing clock signal and a chip select signal are generated. When the cross-die clock signal and chip select signal are detected, the cross-die signal output by the die interconnect link is acquired.

[0013] According to a register debugging system provided by the present invention, the cross-die signal is a serial peripheral interface protocol signal.

[0014] According to the present invention, a register debugging system is applied to a chip.

[0015] The register debugging system provided by this invention connects the interface access units of multiple IP modules end to end to form a serial debugging link independent of the system bus, and uses a debugging clock source independent of the system bus clock to drive the serially transmitted debugging signal in the serial debugging link. This realizes an independent debugging access path for the registers of each IP module in the chip, solves the problem in related technologies that the debugging method depends on the system bus and cannot complete register reading and writing when the bus is suspended, and greatly improves the reliability and fault coverage of register debugging. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of JTAG serial testing in related technologies.

[0018] Figure 2 This is one of the structural schematic diagrams of the register debugging system provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the debugging signal transmission path provided by the present invention.

[0020] Figure 4 This is a schematic diagram of the IP module provided by the present invention.

[0021] Figure 5 This is a schematic diagram of the bridging module provided by the present invention.

[0022] Figure 6 This is a schematic diagram of the cross-die conversion module provided by the present invention.

[0023] Figure 7 This is the second schematic diagram of the register debugging system provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] With the development of integrated circuit technology, how to reliably and efficiently read and write the registers inside the chip in the processes of pre-silicon verification, post-silicon debugging, board-level testing and fault analysis is one of the key issues to ensure chip research and development and maintenance.

[0026] In related technologies, the common debugging method for chip internal registers is the JTAG (Joint Test Action Group) debugging method. Figure 1 This is a schematic diagram of JTAG serial testing in related technologies, such as... Figure 1 As shown, in a System-on-Chip (SOC) employing JTAG technology, JTAG controls the internal Test Access Port (TAP) state machine via the Test Clock (TCK) signal and the Test Mode Select (TMS) signal. Specifically, debug instructions are first serially shifted into the chip via Test Data Input (TDI), and then data is serially shifted in or out via TDI / Test Data Output (TDO), thereby completing read and write operations on the chip's internal registers or memory. For example, in... Figure 1 In JTAG, serial data can be transmitted sequentially through IP (Intellectual Property) 1, IP2, and IP3 via TDI, and the read result is returned by TDO. In addition, TCK and TMS signals are broadcast to each IP to drive the operation of the TAP state machine.

[0027] However, JTAG debugging relies on the normal routing and forwarding of the chip's internal system bus to access memory and various IP registers. If the chip experiences a deep hang, such as a system bus failure, it becomes impossible to perform any register read / write operations via the system bus. This means that at the crucial moment when the chip most needs to locate the root cause of the fault through register states, JTAG debugging loses its intended function, severely limiting the reliability of the chip's debugging capabilities.

[0028] Furthermore, in JTAG debugging, the TDR (Test Data Register) structure typically only covers the chip's boundary scan unit and some major debugging interfaces, without connecting all the registers of the chip's internal IP modules to the scan chain. This results in limited debugging coverage and makes it impossible to achieve unified access and monitoring of all registers within the chip.

[0029] To address this issue, the present invention provides a register debugging system, which aims to solve the problems of current JTAG-based debugging methods being heavily dependent on the system bus, unable to complete register read / write access when the system bus fails, and having insufficient debugging coverage to cover all registers within the chip.

[0030] Figure 2 This is one of the structural schematic diagrams of the register debugging system provided by the present invention, such as... Figure 2 As shown, the system includes: Multiple IP modules 100, each IP module including an interface access unit 110 and at least one register 120 connected to the interface access unit 110; the interface access units 110 in the multiple IP modules 100 are connected in series to form a serial debugging link, which is used to serially transmit debugging signals of register 120. Debug clock source 200 is used to drive the serial debug link; The serial debugging link is independent of the system bus, and the debugging clock source 200 is independent of the system bus clock.

[0031] Specifically, IP module 100 refers to a processing unit with independent IP, such as IP inside a chip. Each IP module 100 includes an interface access unit 110 and at least one register 120.

[0032] Register 120, as the basic storage unit inside IP module 100 for storing configuration parameters, operating status, or intermediate data, is the object that needs to be debugged in this embodiment of the invention. In some embodiments, the number of registers 120 contained in a single IP module 100 may be as many as hundreds or even thousands.

[0033] The interface access unit 110 is a hardware logic unit in the IP module 100 responsible for providing register access capabilities to the outside world. The interface access unit 110 is connected to each register 120 within the IP module 100. The interface access unit 110 can receive debugging signals sent from the outside and perform corresponding read or write operations on the registers 120 within the IP module 100 based on the information contained in the debugging signals. As the interface between the IP module 100 and the external debugging link, the interface access unit 110 realizes the mapping and conversion between debugging signals and register read / write operations.

[0034] In this embodiment of the invention, the interface access units 110 in multiple IP modules 100 are connected in series to form a serial debugging chain, which can be referred to as an RBC (Register Debug Chain). In other words, for each interface access unit 110 in each IP module 100 that needs to be debugged, they can be connected sequentially in a daisy chain. That is, the output of the interface access unit 110 of the first IP module 100 is connected to the input of the interface access unit 110 of the second IP module 100, the output of the interface access unit 110 of the second IP module 100 is connected to the input of the interface access unit 110 of the third IP module 100, and so on, until the interface access unit 110 of the last IP module 100, thereby forming a serial debugging chain that runs through multiple IP modules 100. In the aforementioned serial debugging link, there is only one set of data input interfaces and one set of data output interfaces, corresponding to the input terminal of the interface access unit 110 of the first IP module 100 and the output terminal of the interface access unit 110 of the last IP module 100. Therefore, the serial shifting in and out of debugging signals can be achieved based on the data input and data output interfaces of the serial debugging link, without the need to provide a separate debugging interface for each IP module 100.

[0035] The debug clock source 200 is used to drive the aforementioned serial debug link to perform serial data transmission. The debug clock source 200 is the source of the clock signal clk for serial data transmission. The clock signal generated by the debug clock source 200 acts on the serial debug link, driving each interface access unit 110 on the serial debug link to complete the reception, processing and forwarding of debug signals in sequence according to the clock, thereby realizing the serial transmission of debug signals on the serial debug link.

[0036] Debug signals are data frames transmitted on the serial debug link, used to instruct read or write operations to be performed on the register 120 within the IP module 100 that needs to be debugged, and carrying the address and data information of the register 120. Debug signals are generated by the entity initiating the debug, i.e., the debug master device, and are serially transmitted via the serial debug link to the interface access unit 110 of the IP module 100 that needs to be debugged. The interface access unit 110 then performs the actual read and write operations on the register 120 that needs to be debugged. The debug master device can be, for example, an external debug tool, a CPU (Central Processing Unit), or a JTAG.

[0037] In this embodiment of the invention, the serial debugging link formed by connecting the interface access units 110 in multiple IP modules 100 end to end is independent of the system bus. The system bus here can be an AXI (Advanced eXtensible Interface) bus, an AHB (Advanced High-performance Bus) bus, etc.

[0038] In other words, the transmission path of the debug signal does not route through the system bus, and the read and write operations of the interface access unit 110 on the registers 120 within the IP module 100 do not depend on the initiation and response of system bus transactions. The serial debug link and the system bus are two parallel and independent paths that do not interfere with each other. Therefore, even in the event of an extreme failure such as system bus paralysis or deep hang, the serial debug link can still function normally, and the debug master device can still perform normal read and write access to the registers 120 within all IP modules 100 through the serial debug link, thereby ensuring the reliability of register debugging.

[0039] Furthermore, the debug clock source 200 is independent of the system bus clock; the two are undependent and isolated from each other. Here, the system bus clock refers to the clock used to drive the operation of each module on the system bus. This means that even if the system bus clock malfunctions or stops working, the debug clock source 200 can still independently generate a clock signal to continuously drive data transmission on the serial debug link, thereby further ensuring the availability and reliability of the register debug system under extreme failure scenarios.

[0040] Furthermore, since the serial debugging link does not initiate any system bus transactions, the debugging operation on the registers will not interfere with the normal operation of the chip's internal functional logic. Therefore, the register debugging system of this application is also suitable for real-time monitoring of the internal registers during actual chip operation, and will not affect other working behaviors of the chip, thus possessing the characteristics of non-intrusive operation.

[0041] It should be noted that during the actual chip design phase, automated tools can be used to replace or add registers in each IP module to support serial debugging links, and automatically complete the chain connection between interface access units. The whole process is almost transparent to the designer, has low implementation cost, and facilitates the rapid transformation of existing IP modules into IP modules that support the register debugging system provided in the embodiments of this invention.

[0042] In the register debugging system provided in this embodiment of the invention, the interface access units in multiple IP modules are connected in series to form a serial debugging link independent of the system bus, and a debugging clock source independent of the system bus clock is used to drive the serially transmitted debugging signal in the serial debugging link. This realizes an independent debugging access path for the registers of each IP module in the chip, solves the problem in related technologies that the debugging method depends on the system bus and cannot complete register reading and writing when the bus is hung, and greatly improves the reliability and fault coverage capability of register debugging.

[0043] Based on the above embodiments, the debugging signal includes: The valid bit field is used to indicate whether the debug signal is valid; The read / write control field is used to indicate whether the debug signal corresponds to a read or write operation; The address field is used to indicate the offset address of the register to be debugged within the register debugging system; The data field is used to carry the register value corresponding to the read operation or the write operation; The master device identifier field is used to identify the master device that initiated this debugging process.

[0044] Specifically, the debug signal, through a combination of the valid bit field, the read / write control field, the addr field, the data field, and the client_id field, fully describes all the control and data information required for a register access operation. The debug master device can initiate register read / write requests to the IP module under test on the serial debug link based on this data format. Correspondingly, the interface access unit of the IP module under test can complete the corresponding register access operation and return the result based on the content of each field in the debug signal.

[0045] For example, the table below shows an example of the name, bit width, and field description of each field in the debug signal:

[0046] The valid bit field occupies 1 bit in the debug signal and is used to indicate whether the debug signal is valid. When the valid bit field is valid, for example, when the valid bit field value is 1, it indicates that the debug signal currently transmitted on the serial debug link is a valid debug command, and the interface access unit should parse and process it; when the valid bit field is invalid, for example, when the valid bit field value is 0, it indicates that the current debug signal is invalid, and the interface access unit does not respond and directly ignores the debug signal.

[0047] The read / write control field occupies 1 bit in the debug signal and is used to indicate the operation type corresponding to the debug signal. For example, when the read / write control field is 1, it indicates that the current debug operation is a read operation, and the interface access unit should read the currently stored register value from the register to be debugged and feed it back to the debug master device; when the read / write control field is 0, it indicates that the current debug operation is a write operation, and the interface access unit should write the data carried in the data field to the target register and feed back the value written to the target register to the debug master device.

[0048] The address field `addr` occupies multiple bits in the debug signal, for example, 32 bits. The address field `addr` indicates the offset address of the register to be debugged within the register debugging system. When the register debugging system is applied to a chip, the address field `addr` can indicate the offset address of the register to be debugged within the chip. After receiving the debug signal, the interface access unit can accurately locate the register to be debugged in the internal register space of the IP module based on the offset address indicated by the address field, and perform corresponding read or write operations. In some embodiments, using a 32-bit address field can support indexing and addressing a large number of registers within each IP module, meeting the needs of the continuously increasing number of registers within IP modules in current and future chip designs.

[0049] The data field occupies multiple bits in the debug signal, for example, up to 32 bits. The data field carries the register value corresponding to the current read or write operation. For example, when the debug signal corresponds to a write operation, the data field carries the value that the debug master device expects to write to the register to be debugged. The interface access unit writes this value to the register pointed to by the address field. After writing the value to the register, the interface access unit fills the data field with the written value, generating a feedback debug signal, and returns this feedback debug signal to the debug master device via the serial debug link. When the debug signal corresponds to a read operation, the data field in the debug signal sent by the debug master device can be any value. After reading the current value of the register to be debugged, the interface access unit fills the register value into the data field, generating a feedback debug signal, and returns this feedback debug signal to the debug master device via the serial debug link. The debug master device can obtain the current value of the register to be debugged by parsing the data field.

[0050] The client_id field, representing the master device identifier, occupies one or more bits in the debug signal, for example, two bits. The client_id field identifies the debug master device that initiated the debug operation. For example, in a chip system, there may be multiple debug masters, and all of them may simultaneously have the ability to initiate debug requests. By carrying the client_id field in the debug signal, the serial debug link and its upstream and downstream modules can distinguish and identify debug signals issued by different debug masters based on this field. After the interface access unit completes the register operation, it accurately routes the feedback debug signal containing the register value back to the debug master device that initiated the debug operation, avoiding response confusion between different debug masters. Taking a two-bit client_id field as an example, it can support the unique identifier of up to four debug masters. In practical applications, the bit width of the client_id field can be adjusted accordingly based on the number of debug masters in the system.

[0051] The aforementioned fields can be transmitted bit-by-bit sequentially on the serial debug link, thereby achieving serial transmission of debug signals on the serial debug link. Taking the command transmission direction (CMD) of debug signals on the serial debug link as an example, the valid bit field, read / write control field, address field, data field, and master device identifier field are sent serially in sequence. Simultaneously, the debug signal generated by the interface access unit after completing the register operation is also serially returned to the debug master device along the feedback transmission direction (RSP) according to the above field format. The debug master device can obtain the result of the write or read operation of the target register by parsing the data field in the feedback debug signal.

[0052] In this embodiment of the invention, a standardized signal format is defined for the debug signal, including a valid bit field, a read / write control field, an address field, a data field, and a master device identifier field. This enables the debug signal to carry all the information required for register access operations, allowing the interface access unit to independently complete the precise read / write location and operation of any register within the IP module without the aid of the system bus. At the same time, the master device identifier field supports accurate response routing in scenarios with multiple debug master devices, further enhancing the completeness and practicality of the register debug system.

[0053] Based on any of the above embodiments, the interface access unit is used for: When a debug signal corresponding to a write operation is received through the serial debug link, the data field of the debug signal is written into the register pointed to by the address field in the IP module, a feedback debug signal is generated based on the value written into the register, and the feedback debug signal is returned to the debug master device through the serial debug link. Upon receiving a debug signal corresponding to a read operation via the serial debug link, the register value is read from the register pointed to by the address field in the IP module, a feedback debug signal is generated based on the register value, and the feedback debug signal is returned to the debug master device via the serial debug link.

[0054] Specifically, the interface access unit receives debugging signals through a serial debugging link and performs corresponding write or read operations on the registers to be debugged within the IP module based on the information carried in each field of the debugging signal.

[0055] When a debug signal is received via the serial debug link, the interface access unit first parses the received debug signal. Only if the valid bit field in the debug signal indicates that the debug signal is valid will the remaining fields be processed. Subsequently, the interface access unit detects the read / write control field. If it determines that the read / write control field indicates that the operation is a write operation, a write operation is performed on the register. If it determines that the read / write control field indicates that the operation is a read operation, a read operation is performed on the register.

[0056] The process of performing a write operation on a register includes: after confirming that it is a write operation, the interface access unit further parses the address field and locates the register to be debugged in the internal register space of the IP module based on the offset address carried by the address field; finally, the interface access unit writes the value carried by the data field in the debug signal into the above register.

[0057] After writing the value to the register, the interface access unit generates a feedback debug signal based on the value written to the register. Here, the feedback debug signal has the same data format as the debug signal received by the interface access unit, that is, it also includes a valid bit field, a read / write control field, an address field, a data field, and a master device identifier field. Specifically, the data field of the feedback debug signal is filled with the value written to the register, and the master device identifier field retains the content of the master device identifier field in the debug signal to identify the initiator of this write operation, thereby ensuring that the feedback debug signal can be accurately routed to the corresponding debug master device.

[0058] After generating the feedback debug signal, the interface access unit returns the feedback debug signal to the debug master device that initiated the write operation through the serial debug link, thereby completing a complete register write operation.

[0059] The process of performing a read operation on a register includes: after confirming that it is a read operation, the interface access unit parses the address field in the debug signal, locates the register to be debugged in the IP module according to the offset address carried by the address field, and reads the currently stored register value from the register.

[0060] After obtaining the register value, the interface access unit generates a feedback debug signal based on that register value. Here, the feedback debug signal has the same data format as the debug signal received by the interface access unit, that is, it also includes a valid bit field, a read / write control field, an address field, a data field, and a master device identifier field. Specifically, the data field of the feedback debug signal is filled with the register value read from the target register, and the master device identifier field retains the content of the master device identifier field in the debug signal to identify the initiator of this read operation, thereby ensuring that the feedback debug signal can be accurately routed to the corresponding debug master device.

[0061] After generating the feedback debug signal, the interface access unit returns the feedback debug signal to the debug master device that initiated this read operation through the serial debug link. The debug master device can obtain the register value in the register to be debugged by parsing the data field in the feedback debug signal, thereby completing a complete register read operation.

[0062] It should be noted that when multiple IP modules in a chip are connected in series via interface access units to form a serial debug link, as the debug signal propagates along the serial debug link, each interface access unit on the link parses the received debug signal and determines whether the register pointed to by the address field in the debug signal is located within its own IP module. If the register to be debugged is located within the IP module, the interface access unit executes the write or read operation procedure described above; if the register to be debugged is not located within the IP module, the interface access unit directly transmits the debug signal downstream of the serial debug link without performing any register operations, thus ensuring that the debug signal can be accurately transmitted to the designated IP module along the serial debug link.

[0063] For example, Figure 3 This is a schematic diagram of the debugging signal transmission path provided by the present invention, as shown below. Figure 3 As shown, on a serial debug link, debug signals can be transmitted sequentially in the command transmission direction (CMD) and the feedback transmission direction (RSP). Figure 3 The signals are labeled "write" and "read" to represent debug signals for corresponding write and read operations. The debug signals undergo address remapping (addr remap) via the interface access unit to enable access to registers within the IP module. For example, debugging can be performed on register REG1 in IP module IP1, register REG2 in IP module IP2, and register REG3 in IP module IP3.

[0064] In this embodiment of the invention, the interface access unit implements read and write control of any register in the IP module by the interface access unit in two scenarios: write operation and read operation. This provides a complete register access mechanism for chip debugging, verification and fault location.

[0065] Based on any of the above embodiments, the IP module further includes a system bus interface, which is used to connect to the system bus, and the system bus interface is independent of the interface access unit.

[0066] Specifically, in the register debugging system, each IP module also includes a system bus interface, thereby enabling the connection between the IP module and the system bus. Furthermore, within the IP module, the system bus interface and the interface access unit are independent of each other, thus forming two independent access paths within the IP module for the registers in that IP module.

[0067] For example, Figure 4 This is a schematic diagram of the IP module provided by the present invention, as shown below. Figure 4As shown, there are two access paths inside the IP module 100: a register access path based on the serial debug link and a register access path based on the system bus.

[0068] The register access path based on the serial debug link is driven by a debug clock source to transmit debug signals along the serial debug link, and finally the interface access unit performs read and write operations on the registers to be debugged within the IP module. This path is completely independent of the system bus and can work independently in extreme cases where the system bus fails or hangs.

[0069] The system bus-based register access path allows a register read / write request to be initiated to the system bus interface via the system bus. Upon receiving the request, the system bus interface performs the corresponding read / write operation on the register to be accessed within the IP module and returns the result via the system bus. This path represents the standard procedure for configuring and accessing IP module registers during normal chip operation.

[0070] It should be noted that the two access paths mentioned above are physically independent and logically non-interfering. That is, the serial debug link access path and the system bus access path are two parallel access paths, each capable of independently initiating read and write accesses to registers within the IP module without interfering with the other. The interface access unit and the system bus interface can each handle access requests from the serial debug link and the system bus, respectively, ensuring that the access results from both paths are correctly applied to their respective pointed-to registers.

[0071] For example in Figure 4 In this configuration, the register access path based on the serial debug link can be accessed through the interface access unit 110 inside the IP module 100, and this interface access unit 110 is controlled by the debug clock signal rbc_clock and the debug reset signal rbc_reset. The register access path based on the system bus can be accessed through the system bus interface inside the IP module 100, and this system bus interface is controlled by the bus clock signal Func_clock and the bus reset signal Func_reset. Furthermore, an arbitration & routing module RR is provided within the IP module 100, which is connected to both the interface access unit and the system bus interface, thereby coordinating concurrent accesses of the two access paths through built-in arbitration logic. Additionally, the arbitration & routing module RR is connected to the register access layer MMIO (Memory-Mapped I / O) interface to implement register access operations within the IP module.

[0072] In this embodiment of the invention, the interface access unit and the system bus interface are connected to the serial debugging link and the system bus, respectively, realizing a dual-path access architecture for the registers in the IP module, which further improves the flexibility and practicality of the register debugging system.

[0073] Based on any of the above embodiments, the register debugging system further includes a bridging module, which is connected to the serial debugging link and multiple debugging master devices; The bridging module is used to serially forward multiple concurrent debugging signals to the serial debugging link based on the debugging priority order of the multiple debugging master devices when multiple debugging master devices send concurrent debugging signals.

[0074] Specifically, in situations where there are multiple master debugging devices capable of initiating debugging operations, if no control is exercised when multiple master debugging devices simultaneously initiate debugging signals, the concurrent debugging signals will conflict at the entry point of the serial debugging link, leading to mutual interference or even loss of debugging signals.

[0075] To address this, embodiments of the present invention include a bridging module in the register debugging system. Specifically, the bridging module is connected to both the serial debugging link and multiple debugging master devices, and is located between the multiple debugging master devices and the serial debugging link, serving as a hub for scheduling and forwarding.

[0076] When multiple debugging master devices send debugging signals concurrently, that is, when multiple debugging master devices send debugging signals to the bridging module at the same time or close to the same time, the bridging module arbitrates the multiple concurrent debugging signals based on the pre-configured debugging priority order, and forwards each debugging signal serially to the serial debugging link in sequence according to the arbitration result.

[0077] Here, the debug priority order is a predefined priority arrangement for multiple debug master devices, used to determine which debug signal should be processed and forwarded first when multiple debug signals occur concurrently.

[0078] In some implementations, the debugging priority order can adopt a fixed priority arbitration strategy, whereby each debugging master device is pre-assigned a fixed priority number. Debugging signals initiated by a debugging master device with a higher priority number have priority in the competition for the right to use the serial debugging link, and their corresponding debugging signals are preferentially forwarded to the serial debugging link. The specific allocation of fixed priorities can be defined according to actual application requirements, and this embodiment of the invention does not impose specific limitations on this.

[0079] After the bridging module completes priority arbitration, the debugging signal corresponding to the highest priority debugging master device in the current round will be forwarded by the bridging module to the serial debugging link, and then transmitted along the serial debugging link under the drive of the debugging clock source. Subsequently, the bridging module forwards the next debugging signal to be forwarded, thereby serializing multiple concurrent debugging signals and forwarding them to the serial debugging link in sequence, ensuring the orderliness of the debugging signals.

[0080] In this embodiment of the invention, the bridging module arbitrates the concurrent debugging signals from multiple debugging master devices based on the debugging priority order, and forwards the arbitration results sequentially to the serial debugging link. This effectively solves the access conflict problem when multiple debugging master devices initiate debugging requests at the same time. While supporting concurrent debugging by multiple debugging master devices, it ensures the orderliness and reliability of debugging signal transmission on the serial debugging link.

[0081] Based on any of the above embodiments, the bridging module is further configured to receive the debugging signal returned by the interface access unit based on the serial debugging link, and forward the debugging signal to the corresponding debugging master device.

[0082] Specifically, when the debugging master device sends a debugging signal to the serial debugging link through the bridging module, and the interface access unit completes the read and write operations of the corresponding registers, the interface access unit will package the operation results into a debugging signal and return it to the bridging module via the serial debugging link.

[0083] Accordingly, the bridging module can receive the returned debugging signal based on the serial debugging link, parse the returned debugging signal, extract the master device identifier field that identifies the master device that initiated this debugging, and then accurately forward the returned debugging signal to the corresponding master device according to the predefined mapping relationship.

[0084] For example, the bridging module can maintain a predefined mapping table that records the correspondence between the identifiers of each debugging master device and their corresponding response interfaces. Upon receiving a returned debugging signal, the bridging module parses the master device identifier field, queries the mapping table, determines the corresponding debugging master device, and outputs the returned debugging signal to the response interface of that master device, thus completing the routing of the debugging signal feedback.

[0085] For example, Figure 5 This is a schematic diagram of the bridging module provided by the present invention, as shown below. Figure 5As shown, the bridging module is connected to three debug masters: CPU0, CPU1, and JTAG. CPU0, CPU1, and JTAG send debug signals Rbc_cmd1, Rbc_cmd2, and Rbc_cmd3 to the bridging module, respectively. The bridging module can perform arbitration routing for the concurrent debug signals Rbc_cmd1, Rbc_cmd2, and Rbc_cmd3, thus forwarding them serially to the serial debug link based on the debug priority order of the three debug masters (CPU0, CPU1, and JTAG). Figure 5 The Rbc_cmd signal in the system.

[0086] In addition, the bridging module can also receive the debug signal Rbc_rsp returned by the serial debug link, parse the master device identifier field in the debug signal Rbc_rsp, select the debug master device corresponding to the value of the master device identifier field through the built-in multiplexer MUX, and then output the debug signal Rbc_rsp to the response interface of the corresponding debug master device.

[0087] In this embodiment of the invention, the bridging module also implements the function of receiving and routing the returned debugging signals, thereby realizing full-link management of debugging requests and responses in scenarios with multiple concurrent debugging master devices, and further ensuring the reliability of the register debugging system in scenarios with multiple debugging master devices.

[0088] Based on any of the above embodiments, the register debugging system further includes a cross-die conversion module, which is connected to the serial debugging link within the die and the die interconnect link between dies, respectively. The cross-die conversion module is used to convert the debug signal output from the serial debug link into a cross-die signal and input it to the die interconnect link, and to convert the cross-die signal output from the die interconnect link into a debug signal and input it to the serial debug link.

[0089] Specifically, a die refers to a single integrated circuit chip that is independently cut from a semiconductor wafer. In chip design, multiple dies are often integrated into the same chip package using packaging interconnect technology to form a multi-die system.

[0090] To address the register debugging needs of multi-die systems, and in order to enable unified debugging access to registers in functional modules across different dies, this embodiment of the invention includes a cross-die conversion module in the register debugging system.

[0091] Here, the cross-die conversion module is a hardware bridging module. It is installed on each die in the multi-die system and connected to the serial debug link within the die and the die interconnect link between dies. This enables the connection between the serial debug link within the die and the die interconnect link between dies, thereby realizing the transmission of debug signals across dies.

[0092] Serving as a bridge between the internal serial debug link of a die and the inter-die interconnect link, the cross-die conversion module enables bidirectional conversion between debug signals and cross-die signals. Cross-die signals refer to signal formats that, after adaptation processing, can be transmitted over die interconnect links.

[0093] Furthermore, the cross-die conversion module supports two independent data conversion paths: a sending path and a receiving path. In the transmission path, the cross-die conversion module converts the debug signal output from the serial debug link within its local die into a cross-die signal, and inputs this cross-die signal to the die interconnect link for transmission to the remote die. Specifically, after receiving the debug signal from the serial debug link within its local die, the cross-die conversion module latches the information in each field of the debug signal, repackages and frames the information according to the cross-die signal format required by the die interconnect link, generates a compliant cross-die signal, and then outputs the cross-die signal serially to the die interconnect link, thereby completing the cross-die transmission of the debug signal from the local die to the remote die.

[0094] In the receiving path, the cross-die conversion module converts the cross-die signal output from the die interconnect link into a debug signal and inputs this debug signal into the serial debug link within the die. Specifically, the cross-die conversion module continuously monitors the status of the die interconnect link. When a valid cross-die signal is detected on the die interconnect link, it begins to formally receive a complete frame of cross-die signal data and stores it in the receive buffer. Subsequently, it parses the required field information for the debug signal from the receive buffer according to the frame format of the cross-die signal, completes the format restoration of the cross-die signal to the debug signal, and injects the restored debug signal into the serial debug link of the local die, thereby completing the cross-die transmission of the debug signal from the remote die to the local die.

[0095] Based on the combination of the aforementioned transmission and reception paths, the cross-die conversion module enables the propagation of debug signals across dies in a multi-die system. Furthermore, the signal conversion performed by the cross-die conversion module is still conducted within the serial debug link architecture, independent of the system bus. The characteristic of the debug clock source being independent of the system bus clock is also maintained in multi-die scenarios.

[0096] In this embodiment of the invention, by setting a cross-die conversion module in the register debugging system, bidirectional protocol conversion between debugging signals and cross-die signals is realized, thereby extending the serial debugging link capability within a single die to a multi-die system. This supports unified debugging access to the registers of all functional modules across single-die or multi-die architectures, expanding the debugging coverage and application scenarios of the register debugging system.

[0097] Based on any of the above embodiments, the cross-die conversion module is further configured to: While converting the debug signal into a die-crossing signal, a die-crossing clock signal and a chip select signal are generated. When the cross-die clock signal and chip select signal are detected, the cross-die signal output by the die interconnect link is acquired.

[0098] Specifically, the cross-die clock signal is a clock signal actively generated by the cross-die conversion module during the execution of the transmission path. It drives the serial transmission of cross-die signals on the die interconnect link, ensuring that the transmitting and receiving ends complete bit-by-bit sampling and alignment of the cross-die signals under the same clock reference. The chip select signal is a frame synchronization control signal actively generated by the cross-die conversion module during the execution of the transmission path. It indicates whether there is a valid cross-die signal currently being transmitted on the die interconnect link. The receiving end can determine whether to start receiving a complete frame of cross-die signal by monitoring the valid status of the chip select signal, thereby realizing frame-level handshake and synchronization between the transmitting and receiving ends.

[0099] In the transmission path, before the cross-die conversion module begins outputting the cross-die signal to the die interconnect link, it outputs a chip select signal to notify the remote die that it is about to begin receiving a cross-die signal. Simultaneously, the cross-die conversion module continuously generates a cross-die clock signal to drive the bit-by-bit serial output of the cross-die signal, ensuring that each bit of the cross-die signal is stably output to the die interconnect link under the drive of the cross-die clock signal. The cross-die clock signal and chip select signal, along with the cross-die signal data, are transmitted to the remote die via the die interconnect link, serving as the control basis for signal acquisition and frame synchronization at the receiving end.

[0100] In the receiving path, the cross-die conversion module continuously monitors the status of the cross-die clock signal and chip select signal on the die interconnect link. When the cross-die conversion module detects that the chip select signal is valid, it determines that the remote transmitter has started outputting cross-die signals to the die interconnect link. Driven by the cross-die clock signal, the cross-die conversion module then samples and receives the cross-die signal bit by bit from the die interconnect link, storing it sequentially in the receive shift buffer until the chip select signal returns to an invalid state. This is considered a complete frame of cross-die signal reception. Afterward, the cross-die conversion module parses the field information from the receive shift buffer according to the frame format of the cross-die signal, completing the restoration of the cross-die signal to a debug signal, and injects the restored debug signal into the serial debug link of the local die.

[0101] In this embodiment of the invention, the cross-die conversion module synchronously generates a cross-die clock signal and a chip select signal in the transmission path, and triggers the acquisition and reception of cross-die signals in the reception path based on the state of the cross-die clock signal and the chip select signal. This achieves clock synchronization and frame-level handshake between the transmitting and receiving ends during the cross-die signal transmission process, effectively ensuring the timing accuracy and data integrity of the cross-die signal transmission on the die interconnect link, and further improving the cross-die debugging reliability of the register debugging system under a multi-die system.

[0102] Based on any of the above embodiments, the cross-die signal is a serial peripheral interface protocol signal.

[0103] Specifically, the cross-die signal is a Serial Peripheral Interface (SPI) protocol signal.

[0104] For example, Figure 6 This is a schematic diagram of the cross-die conversion module provided by the present invention, as shown below. Figure 6 As shown, the cross-die conversion module is responsible for performing bidirectional conversion between the SPI protocol signals on the serial debug link within the die and the die interconnect link, specifically including the following two data paths: One path is the transmission path, used to convert debug signals into SPI protocol signals. Figure 6 The diagram shows how the debug signal RBC_CMD is converted into the SPI protocol signal SPI_Data via RBC2SPI, and then the SPI protocol signal SPI_Data is input to the die interconnect link; the other path is the receiving path, used to convert the SPI protocol signal into a debug signal. Figure 6 The diagram shows how the SPI protocol signal SPI_Data is converted into the debug signal RBC_CMD and input into the serial debug link via SPI2RBC.

[0105] In this embodiment of the invention, signal transmission between dies is achieved based on SPI protocol signals. Leveraging the advantages of the SPI protocol interface, such as its simplicity, clear timing specifications, and low hardware implementation cost, a standardized and low-overhead cross-die signal transmission scheme is provided for multi-die systems.

[0106] Based on any of the above embodiments, the register debugging system is applied to the chip.

[0107] Here, "chip" refers to an integrated circuit chip that integrates multiple IP modules and their internal registers. For example, a chip can be a GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Network Processing Unit), DPU (Deep Learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit), etc., and other types of artificial intelligence chips; or, for example, a SoC chip or other types of digital integrated circuit chips, which are not specifically limited in this embodiment of the invention.

[0108] Based on any of the above embodiments Figure 7 This is the second schematic diagram of the register debugging system provided by the present invention. Figure 7 A register debugging system for a chip integrating two dies is shown. Figure 7 In the chip, Die0 and Die1 are two bare dies. Die0 is connected to three debug master devices: JTAG, CPU0, and CPU1. The three debug master devices convert their respective debug signals to a debug clock domain independent of the system bus clock domain through JTAG2RBC or CPU2RBC, and then input them into the bridge module built into Die0.

[0109] The bridging module can serially forward multiple concurrent debug signals to the serial debug link based on the debug priority order of the three debug masters: JTAG, CPU0, and CPU1. This allows the debug signal Rbc_cmd to be transmitted within the serial debug link. Essentially, the serial debug link in Die0 connects the interface access units in IP modules IP0 to IPn and is connected to the cross-die conversion module RBC2SPI in Die0. The serial debug link in Die1 connects the interface access units in IP modules IP0 to IPn, using the cross-die conversion module SPI2RBC in Die1 as input and RBC2SPI as output. Therefore, debug signals can be exchanged between Die0 and Die1 via the die interconnect link between the cross-die conversion modules.

[0110] Furthermore, in Die1, multiplexers mux0 and mux1 and output selectors sel0 and sel1 can be set in the serial debug link, which allows Die1 to not only exchange debug signals with Die0, but also potentially transmit debug signals to other dies.

[0111] In addition, in Die0, the SPI2RBC cross-die conversion module is connected to the bridge module, so that the debug signal returned by Die1 can also be returned to the corresponding debug master device through the bridge module.

[0112] In this embodiment of the invention, only a few additional interfaces are needed to support register access and debugging of various IP modules within the chip. Furthermore, the register debugging system provided in this embodiment supports both single-die and multi-die modes, enabling efficient read / write access to up to tens of thousands of registers in both modes.

[0113] Furthermore, the register debugging system provided in this embodiment of the invention has a completely independent debugging channel, which does not rely on the chip's internal memory or system bus. Even in the extreme case of bus hang, normal access to the registers of all IP modules can still be performed.

[0114] Furthermore, building an independent serial debugging link only requires automatically replacing or adding registers in each IP module to support the serial debugging link using tools, and completing the chain connection. The entire process is almost transparent to the designer and has low implementation cost.

[0115] Since register debugging does not initiate any system bus transactions and does not interfere with the normal functional logic of the chip, the register debugging system can also monitor the internal registers of the chip in real time during actual chip operation.

[0116] Because the serial debugging link structure is simple and easy to copy and expand, it can check the register status of each IP module one by one at high speed and with high reliability when the chip is powered on for the first time after tape-out or when a deep fault occurs, thus enabling simple and efficient chip fault diagnosis.

[0117] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0118] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of software products. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A register debugging system, characterized in that, include: Multiple IP modules, each IP module including an interface access unit and at least one register connected to the interface access unit; The interface access units in the multiple IP modules are connected in series to form a serial debugging link, which is used to serially transmit the debugging signals of the registers. A debug clock source is used to drive the serial debug link; The serial debug link is independent of the system bus, and the debug clock source is independent of the system bus clock.

2. The register debugging system according to claim 1, characterized in that, The debugging signals include: The valid bit field is used to indicate whether the debug signal is valid; The read / write control field is used to indicate whether the debug signal corresponds to a read or write operation; The address field is used to indicate the offset address of the register to be debugged within the register debugging system; The data field is used to carry the register value corresponding to the read operation or the write operation; The master device identifier field is used to identify the master device that initiated this debugging process.

3. The register debugging system according to claim 2, characterized in that, The interface access unit is used for: When a debug signal corresponding to a write operation is received through the serial debug link, the data field of the debug signal is written into the register pointed to by the address field in the IP module, a feedback debug signal is generated based on the value written into the register, and the feedback debug signal is returned to the debug master device through the serial debug link. Upon receiving a debug signal corresponding to a read operation via the serial debug link, the register value is read from the register pointed to by the address field in the IP module, a feedback debug signal is generated based on the register value, and the feedback debug signal is returned to the debug master device via the serial debug link.

4. The register debugging system according to claim 1, characterized in that, The IP module also includes a system bus interface, which is used to connect to the system bus. The system bus interface is independent of the interface access unit.

5. The register debugging system according to claim 1, characterized in that, It also includes a bridging module, which is connected to the serial debugging link and multiple debugging master devices; The bridging module is used to serially forward multiple concurrent debugging signals to the serial debugging link based on the debugging priority order of the multiple debugging master devices when multiple debugging master devices send concurrent debugging signals.

6. The register debugging system according to claim 5, characterized in that, The bridging module is also used to receive the debugging signal returned by the interface access unit based on the serial debugging link, and forward the debugging signal to the corresponding debugging master device.

7. The register debugging system according to claim 1, characterized in that, It also includes a cross-die conversion module, which is connected to the serial debug link within the die and the die interconnect link between dies, respectively; The cross-die conversion module is used to convert the debug signal output from the serial debug link into a cross-die signal and input it to the die interconnect link, and to convert the cross-die signal output from the die interconnect link into a debug signal and input it to the serial debug link.

8. The register debugging system according to claim 7, characterized in that, The cross-die conversion module is also used for: While converting the debug signal into a die-crossing signal, a die-crossing clock signal and a chip select signal are generated. When the cross-die clock signal and chip select signal are detected, the cross-die signal output by the die interconnect link is acquired.

9. The register debugging system according to claim 7, characterized in that, The cross-die signal is a serial peripheral interface protocol signal.

10. The register debugging system according to any one of claims 1 to 9, characterized in that, The register debugging system is applied to the chip.

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