Signal receiving device and chip
By designing a signal receiving device in the display system of mobile devices, using the cache module and detection module in the physical layer interface to align the synchronization heads of each MIPI signal, the data analysis error problem caused by misalignment of data signals and clock signals is solved, and more stable and reliable data transmission is achieved.
Patent Information
- Application Number
- CN202323567908.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2033-12-26
AI Technical Summary
In the display system of mobile devices, the receiving port of the MIPI signal may cause the data signal to be misaligned with the clock signal due to problems such as impedance matching and external disturbance, which may cause data analysis errors.
A signal receiving device is designed, including a physical layer interface and a resolution unit. By building a cache module and a detection module in the physical layer interface, the synchronization head alignment of each data signal is realized to avoid data misalignment.
It effectively avoids data parsing errors caused by data misalignment, improves the stability and reliability of data transmission, and reduces power consumption.
Smart Images
Figure CN222619114U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of display, and particularly designs a signal receiving device and a chip. Background Art
[0002] With the rapid development of information technology and mobile portable devices, people have higher and higher requirements for mobile devices. On the premise of meeting high-performance display effects, the power consumption of mobile devices should be reduced as much as possible. At present, the mainstream video interface in the mobile field uses the Mobile Industry Processor Interface (MIPI), which defines the interface specifications for high-speed data transmission and low-power transmission.
[0003] The display system of a mobile device (such as a mobile phone, tablet computer, etc.) usually includes a processor and a display module. The processor controls the display module to display images. The processor and the display module usually communicate using the MIPI protocol, that is, the processor is provided with a sending port for sending MIPI signals, and the display module is provided with a receiving port for receiving MIPI signals. The sending port and the receiving port transmit clock signals through a clock channel, and transmit data signals through multiple data channels.
[0004] However, the separate transmission of multiple data signals through multiple data channels may cause the data signal and clock signal of one or several data channels to be misaligned due to impedance matching, external disturbance and other issues, that is, the data signal of the one or several data channels are not synchronized with other data signals, thereby causing errors in data parsing at the receiving port of the MIPI signal. Utility Model Content
[0005] In view of the above problems, the purpose of the present application is to provide a signal receiving device and chip to realize the alignment of synchronization headers in various data signals in the physical layer interface, so as to avoid data parsing errors caused by data signal asynchrony due to external interference.
[0006] According to one aspect of the present application, a signal receiving device is provided, wherein the signal receiving device is used to receive and process at least two data signals, the data signals including valid data carrying information to be transmitted and a synchronization header for marking the starting position of the valid data, the signal receiving device including: a physical layer interface, used to receive the data signal transmitted in serial and convert the data signal into the data signal transmitted in parallel, a cache module built into the physical layer interface is used to store the data signal transmitted in parallel and provide an interface output signal transmitted in parallel, so that the synchronization headers of each data signal in the interface output signal are aligned with each other; and a parsing unit, connected to the physical layer interface, receiving and parsing the interface output signal.
[0007] Optionally, the physical layer interface also has a built-in detection module, which is communicatively connected to the cache module, and is used to detect the cache module and provide an error signal based on the transmission protocol of the data signal when the detection result indicates that the synchronization header of at least one data signal has not been written into the storage area corresponding to the data signal within a preset time period.
[0008] Optionally, the signal receiving device further comprises a statistical unit, which is communicatively connected to the detection module built into the physical layer interface, and the statistical unit provides a reset signal according to the error signal to reset the physical layer interface.
[0009] Optionally, the physical layer interface also includes: a conversion module, which is used to receive the data signal transmitted serially and convert it into the data signal transmitted in parallel; and a search module, which is communicatively connected to the conversion module and searches for the synchronization header in each of the data signals. The cache module is communicatively connected to the search module and includes the storage area corresponding to each of the data signals. For each of the data signals, the cache module is configured to write the synchronization header and the valid data of the data signal in sequence in the corresponding storage area since the search module finds the synchronization header, and provide the interface output signal when the synchronization header is written in each of the storage areas.
[0010] Optionally, the cache module includes a first-in-first-out memory to provide the storage area.
[0011] Optionally, the detection module starts timing from when the synchronization header is written into the storage area corresponding to at least one of the data signals to determine whether the preset time duration has elapsed.
[0012] Optionally, the transmission protocol of the data signal includes a mobile industry processor interface protocol.
[0013] Optionally, the method by which the search module searches for the synchronization head includes searching by means of a sliding window.
[0014] According to another aspect of the present application, a chip is provided, comprising a signal receiving device as described in any one of the above items.
[0015] According to the signal receiving device and chip provided by the present application, the synchronization headers of various data signals are aligned at the physical layer interface, thereby avoiding data parsing errors caused by data misalignment.
[0016] Furthermore, a cache module is set after the search module. For each data signal, the synchronization header and valid data of the data signal are cached in sequence from the time the synchronization header is detected, and the stored data in each cache area is synchronously output after the synchronization header is written to the cache area corresponding to each data signal. This can effectively reduce the number of data channel delays, improve timing performance and reduce power consumption.
[0017] Furthermore, a cache module is set in the physical layer interface to increase an additional time window, so that based on the built-in error reporting mechanism of the data signal transmission protocol, it is possible to detect whether the data signal is transmitted incorrectly in the physical layer interface according to the protocol provisions, thereby improving the practicality of the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0019] Figure 1 A schematic diagram showing the transmission of a data signal;
[0020] Figure 2 A schematic structural block diagram showing a signal receiving device according to an embodiment of the present application;
[0021] Figure 3 A schematic flow chart showing a signal receiving method according to an embodiment of the present application;
[0022] Figure 4 A schematic diagram showing the search for the synchronization head is shown;
[0023] Figure 5 A storage schematic diagram of the cache module is shown. DETAILED DESCRIPTION
[0024] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.
[0025] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.
[0026] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.
[0027] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.
[0028] In order to facilitate those skilled in the art to better understand the present application, the application scenarios involved in the present application are briefly introduced below.
[0029] The display system of a mobile device (such as a mobile phone, a tablet computer, etc.) usually includes a processor and a display module. The processor and the display module usually communicate using the MIPI protocol. Specifically, a clock line and multiple data lines are usually connected between the processor and the display module. The clock line provides a clock channel to transmit a clock signal, and the data line provides a data channel to transmit a data signal. The processor sends a control signal to the display module through the clock channel and the data channel to control the display module to display an image.
[0030] Figure 1 The transmission diagram of the data signal is shown, still taking the example of the processor sending a control signal to the display module, and the processor and the display module are connected with one clock channel and four data channels. Figure 1 As shown, each data channel is used to transmit a data signal. Specifically, each data signal includes virtual data, a synchronization header, and valid data. Among them, the valid data carries the information to be transmitted (for example, a control signal for controlling the display module); the virtual data does not carry the information to be transmitted, but is only used to occupy a place to fully utilize the bandwidth to improve the data transmission efficiency; the synchronization header is located between the virtual data and the valid data, and is used to mark the starting position of the valid data so that the signal receiving device can correctly parse the data.
[0031] During data transmission, each data signal is synchronized according to the clock signal. The synchronization headers of each data signal should be aligned (that is, transmitted at the same time). After receiving the data signal, the signal receiving device needs to find the synchronization header of each data signal and parse the valid data based on this position. However, due to impedance matching, external disturbances and other issues, the data signal and clock signal transmitted by some data channels may be misaligned. Figure 1 In the example, during the transmission process of the data signal Data4, noise is generated due to external disturbance, so that the data signal has additional virtual data, thereby causing the synchronization header of the data signal to be misaligned with other data signals.
[0032] After receiving the data signal, the display module searches for the synchronization header in each data signal Data1 to Data4 to analyze the valid data of each channel. Figure 1 As shown, data signals Data1~Data3 can complete the search for the synchronization header at time T1, while data signal Data 4 can complete the search for the synchronization header at time T2. Therefore, when parsing data, the synchronization header and valid data of data signal Data 4 are not aligned with the synchronization header and valid data of data signals Data 1~Data 3, which will cause parsing errors.
[0033] In view of the above problems, the present application provides a signal receiving device and chip, which realizes the alignment of synchronization headers in various data signals in the physical layer interface, so as to avoid data parsing errors caused by data signal asynchrony due to external interference.
[0034] Figure 2 Schematic structural block diagram of a signal receiving device of an embodiment of the present application is shown. In the embodiment provided in the present application, for example, the data signal is transmitted according to the MIPI transmission protocol. Figure 2 As shown, the signal receiving device 1 includes a physical layer interface 100 and a parsing unit 200 and a statistical unit 300 respectively connected to the physical layer interface 100 .
[0035] The physical layer interface 100 is used to receive a serially transmitted data signal and convert it into a parallelly transmitted data signal. In addition, the physical layer interface 100 is also used to provide an interface output signal for parallel transmission, wherein the synchronization headers of the data signals in the interface output signal are aligned with each other.
[0036] Furthermore, the physical layer interface 100 includes a conversion module 110 , a search module 120 , a cache module 130 and a detection module 140 .
[0037] The conversion module 110 is used to receive a serially transmitted clock signal and at least two data signals, and convert them into a parallelly transmitted clock signal and data signal. Figure 1 In the embodiment, the conversion module 110 receives the clock signal CLK and four data signals Data1-Data4, which are transmitted in serial and synchronized according to the clock signal. The conversion module 110 converts the received serially transmitted clock signal CLK and data signals Data1-Data4 into parallel transmitted clock signals and data signals.
[0038] The search module 120 is connected to the conversion module 110 and is used to search for synchronization headers in each data signal. In some embodiments, the search module 120 searches for synchronization headers by sliding windows (described in detail below).
[0039] The cache module 130 is connected to the search module 120, and the cache module 130 includes a storage area corresponding to each data channel (i.e., each data signal). For each data signal, the cache module 130 is configured to sequentially write the synchronization header and valid data of the data signal in the corresponding storage area since the search module 120 finds the synchronization header, and to synchronously read out the stored data in each storage area in sequence when the corresponding synchronization header is written in each storage area to provide an interface output signal. In some embodiments, a first-in first-out (FIFO) memory is selected to provide a storage area corresponding to each data channel, so as to output the stored data in sequence according to the order in which the data is written to the storage area. In addition, since the cache module 130 is arranged after the search module 120, the synchronization header is first searched and then the synchronization header and valid data found are stored, which can effectively reduce the number of data channel delays, improve timing performance and reduce power consumption.
[0040] The detection module 140 is connected to the cache module 130, and detects whether the data signal is transmitted incorrectly in the physical layer interface 100 based on the built-in error reporting mechanism of the MIPI protocol and the time window provided by the cache module 130. Specifically, in the embodiment of the present application, the detection module 140 detects each storage area in the cache module 130, and when the detection result indicates that there is a storage area corresponding to at least one data signal within a preset time period without writing the synchronization header of the data signal, it determines that the data transmission is wrong, and provides an error signal based on the built-in error reporting mechanism of the MIPI transmission protocol.
[0041] The parsing unit 200 is connected to the physical layer interface 100. Specifically, the parsing unit 200 is connected to the cache module 130 in the physical layer interface 100. The valid data is parsed based on the interface output signal output by the cache module 130 that has been aligned with the synchronization header of each data signal, so as to convert it into information that can be used by the signal receiving end. In some embodiments, for example, corresponding to the data signal received by the display module, the parsing unit 200 parses the valid data in these data signals so that the display module can correctly display the image or video sent by the processor. In some other embodiments, the parsing unit 200 may also parse the received data signal into text or instructions to be executed.
[0042] The statistical unit 300 is connected to the physical layer interface 100. Specifically, the statistical unit 300 is connected to the detection module 140 in the physical layer interface 100, receives an error signal, and based on the built-in error mechanism of the MIPI protocol, outputs a reset signal to the physical layer interface 100 when an error signal (i.e., data transmission error) is received to reset the physical layer interface 100.
[0043] Figure 3 A schematic flow chart showing a signal receiving method according to an embodiment of the present application; Figure 4 A flowchart of searching for a synchronization header is shown; Figure 5 The storage diagram of the cache module is shown below. Figures 2 to 5 The signal receiving device provided in this application is further explained.
[0044] See also Figure 3 The workflow of the signal receiving device provided in this application specifically includes the following steps:
[0045] Step S10, receiving at least two data signals;
[0046] In this step, a signal receiving device (eg Figure 2 The signal receiving device 100 provided in the first embodiment of the present application receives at least two data signals.
[0047] Take the example of the processor sending a control signal to the display module. The control signal is transmitted based on the MIPI transmission protocol. The processor and the display module use a clock channel and at least two data channels. Each data channel independently transmits a data signal, and each data signal is synchronized by a clock signal transmitted by the clock channel. The clock signal and each data signal are transmitted in the form of serial data.
[0048] Step S20, performing serial-to-parallel conversion on each data signal;
[0049] In this step, for example, the physical layer interface (specifically, the conversion module 110) in the signal receiving device converts the serially transmitted clock signal and at least two data signals into the parallelly transmitted clock signal and at least two data signals.
[0050] Step S30, searching for a synchronization header in each data signal transmitted in parallel;
[0051] In this step, for example, the physical layer interface (eg, the search module 120) in the signal receiving device searches for the synchronization header in each data signal.
[0052] In some embodiments, the synchronization header is searched in each data signal by means of a sliding window.
[0053] See also Figure 4 , taking eight bits of binary numbers transmitted in each clock cycle as an example, and using the binary number "10111000" as the synchronization header. The length of the sliding window I is the same as the length of the synchronization header. The sliding window I slides one bit at a time, and the synchronization header is found by comparing whether the data in the sliding window is the same as the predefined synchronization header. However, the present application is not limited to this, and for example, a more complex algorithm can also be used for matching.
[0054] Furthermore, since the data transmission process may be interfered by noise, in order to improve the accuracy of synchronization header search, in some embodiments, such as Figure 4 As shown, the data within the sliding window may correspond to a data signal transmitted over at least two consecutive clock cycles (eg, cycles T3 and T4).
[0055] Step S40, for each data signal, storing the synchronization header and valid data of the data signal from the time the synchronization header is found;
[0056] For each valid data, when a synchronization header is found in the valid data, a storage area corresponding to the data signal in the physical layer interface (eg, the buffer module 130) in the signal receiving device is opened. The storage area is provided by, for example, a FIFO.
[0057] See also Figure 5For example, take the transmission of four data signals as an example. L1 to L4 represent the storage areas corresponding to Data1 to Data4 respectively. Figure 5 In the example, the storage capacity of each storage area corresponds to the valid data transmitted in three clock cycles. For each data signal, when the synchronization header is found, data is written to its corresponding storage area. At time T5, the synchronization header is found in the data signals Data1~Data3 transmitted by the data channels L1~L3, so the storage area corresponding to the data channels L1~L3 is opened and the synchronization header is written. At time T6, the synchronization header is found in the data signal Data4 transmitted by the data channel L4, so the storage area corresponding to the data channel L4 is opened and the synchronization header is written, and the storage area corresponding to the data channels L1~L3 continues to write valid data.
[0058] Step S50, determining whether the synchronization header is written into each storage area;
[0059] In this step, the storage area corresponding to each data signal is detected. If the synchronization header is written into the storage area corresponding to each data signal, the data transmission is determined to be correct, and steps S60 and S70 are continued. If the synchronization header is not written into the storage area corresponding to at least one data channel, step S80 is continued.
[0060] Step S60, providing an interface output signal;
[0061] In this step, when the synchronization headers are written into the storage areas corresponding to the data signals, the data transmission is determined to be correct, and the storage contents of each storage area (ie, the synchronization headers and valid data of each data signal) are read out synchronously in sequence as the interface output signal.
[0062] Step S70, valid data analysis;
[0063] In this step, the parsing unit in the signal receiving device parses the interface output signal to convert it into information that can be used by the signal receiving end. In some embodiments, for example, the interface output signal is parsed corresponding to the data signal received by the display module, so that the display module can correctly display the image or video sent by the processor. Since the synchronization heads of the data signals in the interface output signal are aligned with each other, data parsing errors caused by data signal asynchrony due to external interference are avoided, thereby improving the stability and reliability of data transmission.
[0064] Step S80, determining whether a preset time has elapsed;
[0065] If there is at least one storage area corresponding to the data signal that has not written the synchronization header, it is determined whether the preset time has elapsed. In some embodiments, the timing is started from the start of searching for the synchronization header to determine whether the preset time has elapsed. In a preferred embodiment, the timing is started from the time when at least one valid data is found to the synchronization header to determine whether the preset time has elapsed. If the preset time has elapsed, it is determined that the signal transmission is wrong, and step S90 is executed; if the preset time has not elapsed, step S50 and subsequent steps are repeated.
[0066] Step S90, device reset;
[0067] If after a preset period of time, there is still at least one storage area corresponding to a data signal that has not been written with a synchronization header, the current data transmission error is determined based on the built-in error reporting mechanism of the MIPI protocol, and the signal receiving device is reset.
[0068] According to the signal receiving device provided by the present application, the synchronization headers of the data signals of each channel are aligned at the physical layer interface, thereby avoiding data parsing errors caused by data misalignment.
[0069] Furthermore, a cache module is set after the search module. For each data signal, the synchronization header and valid data of the data signal are cached in sequence from the time the synchronization header is detected, and the stored data in each cache area is synchronously output after the synchronization header is written to the cache area corresponding to each data signal. This can effectively reduce the number of data channel delays, improve timing performance and reduce power consumption.
[0070] Furthermore, a cache module is set in the physical layer interface to increase an additional time window, so that based on the built-in error reporting mechanism of the data signal transmission protocol, it is possible to detect whether the data signal is transmitted incorrectly in the physical layer interface according to the protocol provisions, thereby improving the practicality of the system.
[0071] In addition, the present application also provides a chip, including the above-mentioned signal receiving device, and thus also has any of the above-mentioned beneficial effects, which will not be repeated here.
[0072] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the present invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and describes these embodiments in detail in order to better explain the principles and practical applications of the present invention, so that technicians in the relevant technical field can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.
Claims
1. A signal receiving device, the signal receiving device is used to receive and process at least two data signals, the data signals include valid data carrying information to be transmitted and a synchronization header for marking the starting position of the valid data, The signal receiving device comprises: A physical layer interface, used to receive the data signal transmitted in series and convert the data signal into the data signal transmitted in parallel, wherein the physical layer interface searches for the synchronization header in each channel of the data signal and provides an interface output signal; as well as A parsing unit connected to the physical layer interface, receiving and parsing the interface output signal, Characterized in that the physical layer interface comprises: a cache module, used for storing the data signals transmitted in parallel and providing the interface output signal after the synchronization headers are written into the storage areas corresponding to the data signals of each channel, wherein the synchronization headers of the data signals of each channel in the interface output signal are aligned with each other; and A detection module is communicatively connected to the cache module, and is used to detect the cache module and provide an error signal based on the transmission protocol of the data signal when the detection result indicates that the synchronization header of at least one data signal is not written into the storage area corresponding to the data signal within a preset time period.
2. The signal receiving device according to claim 1, characterized in that: The signal receiving device further comprises a statistical unit which is communicatively connected with the detection module built into the physical layer interface, and the statistical unit provides a reset signal according to the error signal to reset the physical layer interface.
3. The signal receiving device according to claim 1, characterized in that: The physical layer interface also includes: a conversion module, configured to receive the data signal transmitted in series and convert it into the data signal transmitted in parallel, The cache module includes the storage area corresponding to each of the data signals. For each of the data signals, the cache module stores the synchronization header and the valid data of the data signal in the corresponding storage area.
4. The signal receiving device according to claim 3, characterized in that: The cache module includes a first-in first-out memory to provide the storage area.
5. The signal receiving device according to claim 3, characterized in that: The detection module starts timing from when the synchronization header is written into the storage area corresponding to at least one of the data signals to determine whether the preset time period has elapsed.
6. The signal receiving device according to claim 1, characterized in that: The transmission protocol of the data signal includes a mobile industry processor interface protocol.
7. A chip, characterized in that: The invention comprises a signal receiving device as claimed in any one of claims 1 to 6.