Data transmission chip and electronic equipment

Abstract

The invention discloses a data transmission chip and electronic equipment, and belongs to the technical field of electronics. Wherein the low-speed interface of the data transmission chip is used for receiving multiple paths of first signals, and the high-speed serial interface of the data transmission chip is used for serially transmitting the multiple paths of first signals to another data transmission chip in a data frame manner. As the plurality of paths of signals can be serially transmitted between the data transmission chips in a data frame manner, the number of signal lines required to be arranged between the data transmission chips can be effectively reduced, and the structure of the electronic equipment is further simplified. And the data transmission rate of the high-speed serial interface is relatively high, so that the transmission efficiency of the multiple paths of first signals can be effectively ensured.

Description

[0001] This application is a divisional application. The application number of the original application is 202111665986.0, and the original application date is December 31, 2021. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a data transmission chip and an electronic device. Background Art

[0003] As the performance of electronic devices improves, the number of chips in the electronic devices is also increasing. For example, an electronic device generally includes multiple complex programmable logic devices (CPLDs), and different CPLDs generally communicate with each other through multiple interfaces.

[0004] Since each interface in a CPLD needs to be connected to a corresponding interface in another CPLD through multiple signal lines, communication between CPLDs through multiple interfaces will result in a large number of signal lines between CPLDs and a more complex structure of the electronic device. Summary of the invention

[0005] The present application provides a data transmission chip and an electronic device, which can solve the technical problem that a large number of signal lines between chips in an electronic device leads to a more complex structure of the electronic device.

[0006] In a first aspect, a data transmission chip is provided, which includes a high-speed serial interface and a low-speed interface; the low-speed interface is used to receive multiple first signals; the high-speed serial interface is used to serially transmit the multiple first signals to another data transmission chip in the form of data frames; wherein the data transmission rate of the high-speed serial interface is higher than the data transmission rate of the low-speed interface.

[0007] Since the high-speed serial interface in the data transmission chip can transmit multiple first signals in serial form to another data transmission chip in the form of data frames, the number of signal lines required to be set between the data transmission chips can be effectively reduced, thereby saving the pin resources of the data transmission chip and simplifying the structure of the electronic device. Since the data transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multiple signals can be effectively ensured.

[0008] It is understandable that the data transmission chip may include one or more low-speed interfaces, each of which may have multiple pins. The multiple first signals may be signals received by multiple different low-speed interfaces, or may be signals received by different pins of the same low-speed interface.

[0009] In a possible implementation, the high-speed serial interface is used to generate a data frame based on data obtained by sampling multiple first signals. Since the high-speed serial interface can carry data of multiple first signals in one data frame, the transmission efficiency and flexibility of the signal are effectively improved.

[0010] In another possible implementation, the high-speed serial interface is used to perform parallel sampling of multiple first signals based on the frequency of a clock signal of a data transmission chip.

[0011] For example, the high-speed serial interface can perform parallel sampling of multiple first signals at a first sampling frequency, and the first sampling frequency can be less than or equal to the frequency of the clock signal of the data transmission chip, and can be K1 times the transmission frequency of the data frame, where K1 is an integer greater than 1. By setting the first sampling frequency higher, it can be ensured that the first signal is less distorted, thereby enabling another data transmission chip to accurately recover the first signal.

[0012] In another possible implementation, the data sampled by the high-speed serial interface may include multiple first sampling sequences arranged in sequence according to sampling time, and each first sampling sequence includes a multi-bit sampling value obtained by parallel sampling of multiple first signals.

[0013] Based on this, the high-speed serial interface can synchronously send the data frame in the process of generating the data frame based on the sampled data, without waiting for each field of the data frame to be encapsulated before sending, thereby effectively improving the data transmission efficiency.

[0014] In another possible implementation, the high-speed serial interface is further used to receive multiple second signals sent serially in the form of data frames by another data transmission chip, and transmit the multiple second signals to the low-speed interface.

[0015] The high-speed serial interface in the data transmission chip provided in the present application has both the function of sending data and the function of receiving data, that is, the high-speed serial interface can realize bidirectional transmission of data.

[0016] Optionally, the data transmission chip may include multiple low-speed interfaces. As a possible example, the data frame received by the high-speed serial interface also carries an identifier of each second signal, and the high-speed serial interface can distinguish each second signal based on the identifier and transmit each second signal to the corresponding low-speed interface. The identifier of the second signal can also be called a tag.

[0017] As another possible example, another data transmission chip can encapsulate the multiple second signals in a data frame in a pre-agreed fixed order. After the high-speed serial interface receives the data frame, it can identify the multiple second signals according to the fixed order and send the multiple second signals to the corresponding low-speed interface respectively.

[0018] In another possible implementation, the high-speed serial interface is further used to sample data frames sent by another data transmission chip based on the frequency of a clock signal of the data transmission chip, and to recover multiple second signals based on the sampled data.

[0019] For example, the high-speed serial interface can perform parallel sampling of multiple second signals according to a second sampling frequency, and the second sampling frequency can be less than or equal to the frequency of the clock signal of the data transmission chip, or can be twice the frequency of the clock signal of the data transmission chip. In addition, the second sampling frequency can be K2 times the frequency of the clock signal of another data transmission chip, where K2 is an integer greater than 1. Since the second sampling frequency is an integer multiple of the frequency of the clock signal of another data transmission chip, it can be ensured that the high-speed serial interface can accurately sample the data carried in the data frame.

[0020] In another possible implementation, the data obtained by sampling a data frame sent by another data transmission chip includes: a plurality of second sampling sequences arranged in sequence according to the chronological order of sampling time, each second sampling sequence including a multi-bit sampling value; the high-speed serial interface is also used to sequentially obtain a sampling value from each second sampling sequence, and restore a second signal based on the multi-bit sampling values ​​obtained in sequence.

[0021] For example, for the j-th second signal among multiple second signals, the high-speed serial interface is used to obtain the j-th sampling value from each second sampling sequence in sequence according to the arrangement order of the multiple second sampling sequences, and restore the j-th second signal based on the multi-bit sampling values ​​obtained in sequence, where j is a positive integer and j is not greater than the total number of multiple second signals.

[0022] In another possible implementation, the data transmission chip and another data transmission chip may be located on the same printed circuit board (PCB); or, the data transmission chip and another data transmission chip may be located on different PCBs. That is, in the solution provided by the present application, the high-speed serial interface in the data transmission chip may realize data communication within the board, and may also realize data communication between boards.

[0023] In another possible implementation, the data frame may include: a frame header, multiple data fields, and a gap field located after each data field; wherein the frame header includes a continuous N-bit first value and an M-bit second value, the multiple data fields are used to carry data obtained by sampling multiple first signals, and the length of each data field is W bits, the gap field includes an M-bit second value, N is a positive integer greater than W, and M is a positive integer less than W.

[0024] Based on the frame structure of the above data frame, it can be ensured that another data transmission chip can accurately sample the data in the data field to restore multiple first signals, thereby ensuring the reliability of signal transmission.

[0025] The difference between N and W can be greater than or equal to 2, and the value of M can be 1. By making the difference between N and W greater than or equal to 2, it can be ensured that another data transmission chip can distinguish the frame header and data field in the data frame, avoiding the data field from being mistakenly sampled as the frame header. By setting M to 1, the proportion of effective payload (i.e., the length of the data field) in the data frame can be increased, thereby effectively improving the data transmission efficiency.

[0026] Optionally, the first value in the data frame may be 1, and the second value may be 0.

[0027] In another possible implementation, the data frame may further include: a check field located after the multiple data fields, and a gap field located after the check field; the check field is used to carry the check bit, and the length of the check field is equal to the length of the data field.

[0028] The check bit carried by the check field is obtained by calculating the data carried by multiple data fields using a check algorithm by the high-speed serial interface. After another data transmission chip obtains the data carried in multiple data fields and obtains the check bit carried by the check field, it can use the check bit to verify the obtained data to ensure the accuracy of the received data.

[0029] In a second aspect, a data transmission method is provided, which is applied to the data transmission chip provided in the first aspect, and the method includes: receiving multiple first signals through a low-speed interface; serially transmitting the multiple first signals in the form of data frames to another data transmission chip through a high-speed serial interface; wherein the data transmission rate of the high-speed serial interface is higher than the data transmission rate of the low-speed interface.

[0030] In a possible implementation manner, the method may further include: sampling the multiple channels of first signals, and generating a data frame based on the sampled data.

[0031] In another possible implementation, the process of sampling the multiple channels of first signals may include: sampling the multiple channels of first signals in parallel based on the frequency of the clock signal of the data transmission chip.

[0032] In another possible implementation, the sampled data includes a plurality of first sampling sequences arranged in sequence according to sampling time, and each first sampling sequence includes a multi-bit sampling value obtained by performing one parallel sampling on a plurality of first signals.

[0033] In another possible implementation, the method may further include: receiving, through the high-speed serial interface, a plurality of second signals serially sent by another data transmission chip in the form of data frames, and transmitting the plurality of second signals to the low-speed interface.

[0034] In another possible implementation, the method may further include: sampling a data frame sent by another data transmission chip based on the frequency of the clock signal of the data transmission chip, and recovering the multiple second signals based on the sampled data.

[0035] In another possible implementation, the data obtained by sampling the data frame sent by the other data transmission chip includes: a plurality of second sampling sequences arranged in sequence according to the chronological order of sampling time, each second sampling sequence including a multi-bit sampling value; recovering the multiple second signals based on the sampled data includes: obtaining a sampling value from each second sampling sequence in turn, and recovering one second signal based on the multi-bit sampling values ​​obtained in sequence.

[0036] In a third aspect, a data transmission chip is provided, which includes: a programmable logic circuit and / or program instructions, and the controller is used to implement the functions of the data transmission chip provided in the first aspect.

[0037] In a fourth aspect, a data transmission chip is provided, which includes at least one module, and the at least one module can be used to implement the functions of the data transmission chip provided in the first aspect.

[0038] In a fifth aspect, a computer-readable storage medium is provided, in which instructions are stored, and the instructions are executed by a processing circuit to implement the data transmission method provided in the second aspect.

[0039] In a sixth aspect, a computer program product comprising instructions is provided. When the computer program product is run on a processing circuit, the processing circuit executes the data transmission method provided in the second aspect.

[0040] In a seventh aspect, an electronic device is provided, which includes a data transmission chip, and the data transmission chip is used to implement the functions of the data transmission chip provided in the first aspect above.

[0041] In a possible implementation, the electronic device may include a plurality of data transmission chips, and high-speed serial interfaces of two data transmission chips may be connected via an electrical signal transmission medium.

[0042] In summary, the present application provides a data transmission chip and an electronic device. In the solution provided by the present application, the low-speed interface of the data transmission chip is used to receive multiple first signals, and the high-speed serial interface of the data transmission chip is used to transmit the multiple first signals in serial form to another data transmission chip in the form of data frames. Since multiple signals can be transmitted serially between data transmission chips in the form of data frames, the number of signal lines required to be set between data transmission chips can be effectively reduced, thereby simplifying the structure of the electronic device. And since the data transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multiple first signals can be effectively ensured.

[0043] Based on the implementations provided in the above aspects, the present application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application;

[0045] Figure 2 is a schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0046] Figure 3 This is a schematic diagram of a data structure of a data frame provided in an embodiment of the present application;

[0047] Figure 4 It is a schematic diagram of a partial structure of a data frame provided in an embodiment of the present application;

[0048] Figure 5 It is a schematic diagram of sampling a signal to generate a data frame provided by an embodiment of the present application;

[0049] Figure 6 It is a schematic diagram of a data transmission chip sending a data frame provided in an embodiment of the present application;

[0050] Figure 7 It is a schematic diagram of a data transmission chip receiving a data frame provided by an embodiment of the present application;

[0051] Figure 8 is a structural schematic diagram of another electronic device provided in an embodiment of the present application;

[0052] Fig. 9 It is a schematic diagram of a CPU sending a control instruction to a low-speed device through a data transmission chip provided in an embodiment of the present application;

[0053] Fig.10 It is a schematic diagram of a low-speed device sending an execution result to a CPU through a data transmission chip provided by an embodiment of the present application;

[0054] Fig.11 is a structural schematic diagram of another electronic device provided in an embodiment of the present application;

[0055] Fig.12 It is a schematic diagram of a master control device sending a control instruction to a low-speed device through a data transmission chip provided by an embodiment of the present application;

[0056] Fig.13 It is a schematic diagram of a low-speed device sending an execution result to a main control device through a data transmission chip provided by an embodiment of the present application;

[0057] Fig.14 It is a structural schematic diagram of a data transmission chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to solve the above technical problems, the embodiment of the present application provides a data transmission chip, which, after receiving multiple signals through a low-speed interface, can transmit the multiple signals in serial form to another data transmission chip through a high-speed serial interface in the form of data frames. Thus, while ensuring a high data transmission rate, the number of signal lines between data transmission chips can be effectively reduced.

[0059] The data transmission chip and electronic device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0060] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may be a computing device such as a server, an edge device, a personal computer (PC), or a mobile terminal such as a smart phone, or a switching device such as a switch or a router. Figure 1 As shown, the electronic device includes two data transmission chips 01a and 01b, each of which has a high-speed serial port (Hisport) and a low-speed interface.

[0061] The high-speed serial interface 011a of the data transmission chip 01a and the high-speed serial interface 011b of the data transmission chip 01b can be connected via the electrical signal transmission medium 03, and can transmit multiple signals of the low-speed interface in serial form in the form of data frames via the electrical signal transmission medium 03. That is, the high-speed serial interface in the data transmission chip can carry multiple signals of the low-speed interface in the form of data frames.

[0062] by Figure 1 For example, the high-speed serial interface 011a of the data transmission chip 01a is used to encapsulate the multiple first signals received by the low-speed interface 012a into data frames, and transmit the data frames in series to the high-speed serial interface 011b of the data transmission chip 01b. The high-speed serial interface 011b is used to decapsulate (also called decoding) the received data frames to restore the multiple first signals, and transmit the multiple first signals to the low-speed interface 012b.

[0063] It is understandable that both the high-speed serial interface 011a and the high-speed serial interface 011b may include a connection port (such as a pin) for connecting to the electrical signal transmission medium 03, and a logic circuit for processing data. For example, the high-speed serial interface 011a may include a logic circuit for encapsulating multiple first signals into a data frame, and the high-speed serial interface 011b may include a logic circuit for decapsulating the data frame.

[0064] In the embodiment of the present application, the data transmission rate of the high-speed serial interface in each data transmission chip is higher than the data transmission rate of the low-speed interface. For example, the data transmission rate of the high-speed serial interface can be 10 times the data transmission rate of the low-speed interface, or even higher. The data transmission rate can refer to the number of bits of data transmitted per unit time, and the unit time can be 1 second. Accordingly, the unit of the data transmission rate can be bits per second (bps).

[0065] It is understood that the low-speed interface described in the embodiments of the present application is relative to the high-speed serial interface. The low-speed interface in each data transmission chip may include one or more of the following interfaces: parallel input output (IO) interface, serial peripheral interface (SPI), internal integrated circuit (IIC or I 2 C) interface, universal asynchronous receiver / transmitter (UART) interface and local bus (LBUS) interface, etc.

[0066] In the embodiment of the present application, each data transmission chip may include one or more low-speed interfaces, each low-speed interface may be connected to a low-speed device, and each low-speed interface has multiple pins. The multiple first signals received by the data transmission chip 01a may be signals from different low-speed devices received by different low-speed interfaces 012a, or may be different types of signals from a low-speed device received by different pins of a low-speed interface 012a.

[0067] For example, assuming that the data transmission chip 01a includes multiple IIC interfaces, each of which is connected to a sensor (such as a temperature sensor or a humidity sensor), the multiple first signals may be signals from different sensors received by the multiple IIC interfaces.

[0068] Optionally, the number of data transmission chips included in the electronic device provided in the embodiment of the present application may be greater than 2. Each data transmission chip may have multiple high-speed serial interfaces, and may be connected to multiple other data transmission chips through the multiple high-speed serial interfaces. Wherein, each high-speed serial interface in any data transmission chip is connected to one or more low-speed interfaces, and different high-speed serial interfaces may be connected to different low-speed interfaces respectively.

[0069] In the embodiment of the present application, the data transmission chip can be an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a processor. The PLD can be a complex programmable logic device (CPLD), a field programmable gate array (FPGA) or a generic array logic (GAL). The processor can be a central processing unit (CPU), a network processing unit (NPU) or a data processing unit (DPU).

[0070] Since in the solution provided in the embodiment of the present application, the data transmission chips can transmit multiple signals in serial in the form of data frames through a high-speed serial interface, the number of signal lines required to be set between the data transmission chips can be effectively reduced. Furthermore, the number of pins occupied by the signal lines between the chips can be effectively reduced, saving the pin resources of the data transmission chip. Since the transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multiple signals can be effectively ensured.

[0071] It is understandable that each data transmission chip in the electronic device provided in the embodiment of the present application may have both the function of sending data and the function of receiving data. The following takes the data transmission chip 01a in the electronic device as a chip on the data sending side and the data transmission chip 01b as a chip on the data receiving side as an example to introduce the functions of the data transmission chip in the electronic device.

[0072] refer to Figure 1 The low-speed interface 012a in the data transmission chip 01a is used to receive multiple first signals. The high-speed serial interface 011a is used to serially send the multiple first signals to the data transmission chip 01b in the form of data frames. That is, the data transmission chip 01a can carry the data of the multiple first signals in the data frames and send the data frames serially to the data transmission chip 01b.

[0073] Correspondingly, the high-speed serial interface 011b of the data transmission chip 01b is used to serially receive multiple first signals sent by the data transmission chip 01a in the form of data frames, and transmit the multiple first signals to the low-speed interface 012b.

[0074] It is understandable that the high-speed serial interface 011b can transmit the multiple first signals obtained from the data frame to different low-speed interfaces 012b respectively, or can also transmit them to multiple different pins of a low-speed interface 012a.

[0075] Optionally, at least one low-speed interface 012b in the data transmission chip 01b may correspond to at least one low-speed interface 012a in the data transmission chip 01a, and each low-speed interface 012b and the corresponding low-speed interface 012a may be of the same type. Accordingly, the data transmission chip 01b can transmit at least one first signal of each low-speed interface 012a in the received data frame to a corresponding low-speed interface 012b.

[0076] For example, Figure 2As shown, assuming that at least one low-speed interface 012a in the data transmission chip 01a includes: an IIC interface, a UART interface and an SPI, then at least one low-speed interface 012b in the data transmission chip 01b may also include an IIC interface, a UART interface and an SPI. In addition, the data transmission chip 01b is capable of transmitting at least one first signal from the IIC interface of the data transmission chip 01a in the data frame to the IIC interface in the data transmission chip 01b, and is capable of transmitting at least one first signal from the UART interface of the data transmission chip 01a in the data frame to the UART interface in the data transmission chip 01b, and is also capable of transmitting at least one first signal from the SPI of the data transmission chip 01a in the data frame to the SPI in the data transmission chip 01b.

[0077] In the embodiment of the present application, the high-speed serial interface 011a of the data transmission chip 01a is used to: sample the multiple first signals received by the low-speed interface 012a based on the frequency of the clock signal of the data transmission chip 01a, and generate a data frame based on the sampled data. For example, the high-speed serial interface 011a can sample the multiple first signals received by the low-speed interface 012a according to the first sampling frequency f1, and the first sampling frequency f1 can be equal to the frequency of the clock signal of the data transmission chip 01a, or can be 1 / n of the frequency of the clock signal of the data transmission chip 01a, where n is an integer greater than 1.

[0078] After the high-speed serial interface 011b of the data transmission chip 01b serially receives the data frame sent by the data transmission chip 01a, it can sample the data frame based on the frequency of the clock signal of the data transmission chip 01b to recover the multiple first signals. For example, the high-speed serial interface 011b can sample the received data frame according to the second sampling frequency f2, and the second sampling frequency f2 can be equal to the frequency of the clock signal of the data transmission chip 01b, or can be twice the frequency of the clock signal of the data transmission chip 01b, or can be 1 / m of the frequency of the clock signal of the data transmission chip 01b, where m is an integer greater than 1. Moreover, based on the sampling theorem, it can be known that the second sampling frequency f2 used by the high-speed serial interface 011b when sampling the data frame must be greater than the data transmission rate of the data frame.

[0079] Figure 3 Schematic diagram of a data structure of a data frame provided in an embodiment of the present application. Figure 3 As shown, the data frame sent by the high-speed serial interface 011a of the data transmission chip 01a may include: a frame header, multiple data fields, and a gap field after each data field. Figure 3 It can also be seen that the data transmission chip 01a can send multiple data frames serially through the high-speed serial interface 011a.

[0080] refer to Figure 4 , the frame header may include a continuous N-bit first value and an M-bit second value; the multiple data fields are used to carry data obtained by sampling multiple first signals, and the length of each data field is W bits; the gap field includes the M-bit second value. Wherein, N is a positive integer greater than W, and M is a positive integer less than W.

[0081] In the embodiment of the present application, the first number and the second value may both be binary numbers. The data carried by the multiple data fields obtained by sampling the multiple first signals are also binary numbers. Since the frame header includes an N-bit first value and an M-bit second value, and N is an integer greater than W, it can be ensured that the content of any data field will not be repeated with the frame header, and further ensure that the high-speed serial interface 011b of the data transmission chip 01b can accurately distinguish the frame header and the data field in the data frame after receiving the data frame.

[0082] For example, Figure 4 As shown, the first value may be 1, and the second value may be 0. Accordingly, the frame header may include N consecutive bits of 1 and M bits of 0.

[0083] Optionally, in order to ensure the accuracy of the high-speed serial interface 011b in distinguishing the frame header and the data field, and to prevent the high-speed serial interface 011b from mistakenly sampling the data field as the frame header, the difference between N and W may be greater than or equal to 2. Furthermore, in order to improve the data transmission efficiency of the data frame, the length M of the gap field may be set to be less than a preset value, which is less than W. The preset value may be set according to business requirements, or data transmission delay or other parameters that affect performance. For example, refer to Figure 4 , the M can be set to 1. Correspondingly, if the length of each data field W=8, and the difference between N and W is 2, the frame header can include 10 consecutive bits of 1 and 1 bit of 0, that is, the length of the frame header is 11 bits.

[0084] Based on the setting mode of the frame header, data field and gap field of the data frame in the embodiment of the present application, on the one hand, the high-speed serial interface 011b of the data transmission chip 01b can accurately sample the data in the data field to recover the multi-channel first signal, thereby ensuring the reliability of signal transmission. On the other hand, compared with other serial interfaces that use a logical low level as the start bit of data transmission, the frame format of the data frame in the embodiment of the present application can make the data transmission chip 01b not need to sample the data in the data field through a state machine, thereby simplifying the circuit structure of the data transmission chip 01b and reducing the requirements for the sampling frequency of the data transmission chip 01b. Since the requirements for the sampling frequency of the data transmission chip 01b are relatively low, the high-speed serial interface 011a of the data transmission chip 01a can send data frames at a higher data transmission rate, thereby effectively improving the rate of data transmission. Since each data frame can carry multiple data fields, the amount of data that can be transmitted by a single data frame is effectively increased, thereby improving the transmission efficiency of the data.

[0085] Optionally, continue to refer to Figure 3 The data frame may further include: a check field after the plurality of data fields, and a gap field after the check field, wherein the check field is used to carry a check bit, and the length of the check field is equal to the length of the data field.

[0086] In the embodiment of the present application, the check bit carried by the check field is obtained by the high-speed serial interface 011a of the data transmission chip 01a using a check algorithm to calculate the data carried by multiple data fields. After the high-speed serial interface 011b of the data transmission chip 01b obtains the data carried in the multiple data fields and obtains the check bit carried by the check field, the obtained data can be checked using the check bit to ensure the accuracy of the received data.

[0087] The check algorithm used by the high-speed serial interface 011a when calculating the check bit may include a cyclic redundancy check (CRC) algorithm, an XOR algorithm, or a cumulative sum algorithm.

[0088] Assuming that the number of data fields included in each data frame sent by the high-speed serial interface 011a is T, the first value is 1, and the second value is 0, the key parameters of the data frame can be expressed as follows:

[0089] Frame header pattern frame_header_bitmap (i.e., frame header structure): {N′b1, M′b0}; wherein, N′b1 represents N bits of 1, and M′b0 represents M bits of 0.

[0090] Frame length frame_length: frame_length=(W+M)×(T+2)+(NW);

[0091] The effective payload payload_length satisfies: payload_length = (W × T);

[0092] Data transmission efficiency frame_efficiency (i.e. the proportion of effective payload in the data frame): frame_efficiency = payload_length / frame_length.

[0093] It is understandable that the data transmission rate when the high-speed serial interface 011a sends a data frame, the number of data fields included in the data frame, and the length of each data field (also referred to as the bit width of the data field) can be flexibly set according to the requirements of the application scenario. For example, the requirements for data transmission bandwidth and delay can be set according to the transmission data requirements of different application scenarios. The transmission data requirements include at least one of the transmission factors such as transmission rate, transmission delay, and the number of data transmitted each time.

[0094] Optionally, in order to improve the data transmission efficiency, the high-speed serial interface 011a can perform parallel sampling of the multiple first signals based on the frequency of the clock signal of the data transmission chip 01a, and generate a data frame based on the data obtained by the parallel sampling. For example, the high-speed serial interface 011a can perform parallel sampling of the multiple first signals according to the first sampling frequency f1, and the first sampling frequency f1 can be K1 times the transmission frequency of the data frame, where K1 is an integer greater than 1.

[0095] The sampling frequency refers to the number of samples per unit time, and the unit time may be 1 second. The transmission frequency of the data frame refers to the number of data frames transmitted by the high-speed serial interface 011a per unit time. It is understood that the high-speed serial interface 011a samples one first signal once to obtain a 1-bit sampling value, and the high-speed serial interface 011a performs parallel sampling on X first signals once to obtain an X-bit sampling value, where X is an integer greater than 1.

[0096] Since the first sampling frequency f1 is K1 times the transmission frequency of the data frame, the high-speed serial interface 011a can perform K1 parallel sampling on multiple first signals during the transmission period of a data frame. If the effective payload of a data frame is W×T, then a data frame can carry multi-bit sampling values ​​obtained by performing K1 parallel sampling on X=(W×T) / K1 first signals.

[0097] For example, Figure 5As shown, it is assumed that the data frame includes 20 data fields from D0 to D19, the length of each data field and the length of the check field C0 are 8 bits, the length of the gap field is 1 bit, and the length of the frame header is 11 bits. Then the frame length frame_length of the data frame is 200 bits, and the effective payload is 160 bits. If the data transmission rate of the high-speed serial interface 11a is 25 megabits per second (Mbps), it can be determined that the transmission frequency f0 of the data frame is: f0 = 25Mbps / 200bit = 125 kilohertz (KHz).

[0098] refer to Figure 5 , if K1=2, the first sampling frequency f1 can be 250KHz, and each data frame can carry a multi-bit sampling value obtained by performing two parallel samplings on X=80 first signals. That is, in each data frame, for each of the 80 first signals, the high-speed serial interface 011a can perform two samplings on the first signal to obtain a 2-bit sampling value.

[0099] If K1=4, the first sampling frequency f1 can be 500KHz, and each data frame can carry a multi-bit sampling value obtained by performing 4 parallel sampling on X=40 first signals. That is, in each data frame, for each of the 40 first signals, the high-speed serial interface 011a can perform 4 sampling on the first signal to obtain a 4-bit sampling value.

[0100] If K1=8, the first sampling frequency f1 can be 1MHz, and each data frame can carry a multi-bit sampling value obtained by performing 8 parallel samplings on X=20 first signals. That is, in each data frame, for each of the 20 first signals, the high-speed serial interface 011a can perform 8 samplings on the first signal to obtain an 8-bit sampling value.

[0101] Figure 5 The figure also shows the original waveform of a first signal of a certain path, and the sampling waveform obtained after the first signal of the path is sampled 4 times (ie, K1=4) and 8 times (ie, K1=8). Figure 5 It can be seen from the waveform shown that the higher the first sampling frequency f1 is, the closer the sampled signal waveform is to the original waveform of the signal.

[0102] The method provided in the embodiment of the present application adopts the first sampling frequency f1 to perform parallel sampling on multiple first signals. On the one hand, the data of multiple first signals can be transmitted simultaneously in one data frame, thereby effectively improving the transmission efficiency and transmission flexibility of the signal. On the other hand, since the first sampling frequency f1 is K1 times the transmission frequency of the data frame, each first signal can be sampled at a higher sampling frequency, thereby ensuring less signal distortion, so that the high-speed serial interface 011b in the data transmission chip 01b can accurately restore the first signal.

[0103] Optionally, in the data frame sent by the high-speed serial interface 011a, the data carried by the multiple data fields may include: K1 first sampling sequences arranged in sequence according to the sampling time, each first sampling sequence including a multi-bit sampling value obtained by parallel sampling the multiple first signals.

[0104] Based on this, the high-speed serial interface 011a can synchronously sample the multiple first signals in parallel and synchronously send data frames during the process of receiving the multiple first signals by the low-speed interface 012a. That is, the high-speed serial interface 011a can synchronously send the data frame during the process of generating the data frame based on the sampled data, without waiting for each field of the data frame to be encapsulated before sending. Thus, the data transmission efficiency is effectively improved.

[0105] For example, assume that the data frame includes 20 data fields from D0 to D19, and the length of each data field is 8 bits. If K1=4, the 20 data fields can carry 4 first sampling sequences, and each first sampling sequence can include a 40-bit sampling value obtained by parallel sampling of 40 first signals. If K1=8, the 20 data fields can carry 8 first sampling sequences, and each first sampling sequence can include a 20-bit sampling value obtained by parallel sampling of 20 first signals.

[0106] It can be understood that, in each first sampling sequence, the multiple sampling values ​​obtained by sampling each first signal can be arranged in a pre-agreed fixed order. For example, the j-th sampling value in each first sampling sequence is a sampling value obtained by sampling the j-th first signal, where j is a positive integer not greater than X. Thus, after the high-speed serial interface 011b in the data transmission chip 01b obtains multiple sampling values ​​from the data frame, it can accurately restore each first signal based on the fixed order.

[0107] The following describes a process of recovering multiple first signals from a data frame after the high-speed serial interface 011b in the data transmission chip 01b receives the data frame.

[0108] In the embodiment of the present application, after receiving the data frame, the high-speed serial interface 011b can sample the data frame based on the frequency of the clock signal of the data transmission chip 01b, and restore the multiple first signals based on the sampled data. For example, the high-speed serial interface 011b can sample the received data frame according to the second sampling frequency f2, and the second sampling frequency f2 is K2 times the frequency of the clock signal CLK1 of the data transmission chip 01a, and K2 is an integer greater than 1, for example, K2 can be equal to 4. Since the second sampling frequency f2 is K2 times the frequency of the clock signal CLK1 of the data transmission chip 01a, it can be ensured that the data transmission chip 01b can accurately sample the data carried in each data field of the data frame.

[0109] It can be understood that when the high-speed serial interface 011a serially transmits data frames based on the clock signal CLK1 of the data transmission chip 01a, the data transmission rate of the high-speed serial interface 011a can be twice the frequency of the clock signal CLK1, or can be less than or equal to the frequency of the clock signal CLK1.

[0110] For example, Figure 6 As shown, assuming that the high-speed serial interface 011a sends 1 bit of data at each falling edge of the clock signal CLK1, the data transmission rate of the high-speed serial interface 011a can be equal to the frequency of the clock signal CLK1. Alternatively, if the high-speed serial interface 011a sends 1 bit of data at each falling edge and each rising edge of the clock signal CLK1, the data transmission rate of the high-speed serial interface 011a can be equal to twice the frequency of the clock signal CLK1. Alternatively, if the high-speed serial interface 011a sends 1 bit of data at every K0 falling edges (or every K0 rising edges) of the clock signal CLK1, the data transmission rate of the high-speed serial interface 011a can be equal to 1 / K0 times the frequency of the clock signal CLK1. Wherein, K0 is an integer greater than 1.

[0111] like Figure 7 As shown, assuming that after the high-speed serial interface 011b of the data transmission chip 01b receives the data frame, the data frame is sampled according to the frequency of the clock signal CLK2 of the data transmission chip 01b, that is, the second sampling frequency f2 is equal to the frequency of the clock signal CLK2, then the frequency of the clock signal CLK2 can be K2 times the frequency of the clock signal CLK1. Figure 6 and Figure 7 It can be seen that the frequency of the clock signal CLK2 is 4 times the frequency of the clock signal CLK1, that is, K2=4.

[0112] It can be understood that the high-speed serial interface 011b can sample the data frame once at each transition edge (e.g., rising edge or falling edge) of the clock signal CLK2 of the data transmission chip 01b. For a scenario where the frequency of the clock signal CLK2 (i.e., the second sampling frequency f2) is K2 times the frequency of the clock signal CLK1, the high-speed serial interface 011b can obtain the sampled value sampled at the kth transition edge among the K2 transition edges in every K2 transition edges of the clock signal CLK2, and use the sampled value sampled at the kth transition edge as data for recovering the first signal. Wherein, k is a positive integer not greater than K2.

[0113] In addition, the high-speed serial interface 011b can also adjust the value of k based on the phase deviation of the sampled frame header. For example, when the high-speed serial interface 011b detects that the phase deviation of the frame header exceeds one clock cycle of the clock signal CLK2, it can adjust the value of k to ensure the accuracy of the sampled data.

[0114] Optionally, the high-speed serial interface 011b may also determine that the sampling of a data field has been completed after sampling the sampling value of the gap field G0 each time. Further, the high-speed serial interface 011b may recover the first signal based on the data in the sampled data field.

[0115] Example, reference Figure 7 , assuming K2=4, k=2, the high-speed serial interface 011b can obtain the sampling value sampled by the second edge of every four edges of the clock signal CLK2, and store the obtained sampling value in a register (such as a shift register). That is, the second sampling pulse of every four sampling pulses is a valid sampling pulse.

[0116] Furthermore, the high-speed serial interface 011b can generate a valid pulse after sampling the sampling value of the gap field G0, and based on the valid pulse, take out the sampling value stored in the register as data carried in a data field to recover the signal.

[0117] Based on the above description, it can be known that the high-speed serial interface 011a can transmit data frames based on the frequency of the local clock signal of the data transmission chip 01a, and the high-speed serial interface 011b can sample the received data frames based on the frequency of the local clock signal of the data transmission chip 01b. That is, the solution provided in the embodiment of the present application adopts an asynchronous clock for data communication. Accordingly, the high-speed serial interface can also be called a high-speed asynchronous serial interface.

[0118] Compared with using synchronous clock for data communication, since there is no need for the high-speed serial interface 011a to transmit the clock signal to the high-speed serial interface 011b separately, there is no need to set a clock signal line for transmitting the clock signal between the data transmission chips. Therefore, the number of signal lines required to be set between the data transmission chips can be effectively reduced, saving the pin resources of the data transmission chip.

[0119] It can be understood that if the second sampling frequency f2 when the high-speed serial interface 011b samples the data frame is K2 times the frequency of the clock signal CLK1 of the data transmission chip 01a, the frequency deviation tolerance frequency_bias between the clock signal CLK1 of the data transmission chip 01a and the clock signal CLK2 of the data transmission chip 01b can satisfy: frequency_bias = 1 / (K2×frame_length). The frequency deviation tolerance refers to the maximum frequency deviation allowed by the frequencies of the local clock signals of the two data transmission chips.

[0120] For a scenario where the high-speed serial interface 011a generates a data frame after sampling multiple first signals in parallel, the data obtained by the high-speed serial interface 011b after sampling the data frame may include: K1 first sampling sequences arranged in sequence according to the sampling time, each first sampling sequence includes a multi-bit sampling value. Accordingly, the process of the high-speed serial interface 011b restoring the multiple first signals based on the sampled data may include:

[0121] For the j-th first signal among the multiple first signals, the j-th sampling value is obtained from each first sampling sequence in sequence according to the arrangement order of the K1 first sampling sequences, and the j-th first signal is restored based on the K1 sampling values ​​obtained in sequence. If each first sampling sequence is obtained after the high-speed serial interface 011a performs parallel sampling on the X-channel first signals, then j is a positive integer not greater than X.

[0122] Optionally, for a scenario where the data transmission chip 01b includes multiple low-speed interfaces 012b, in a possible example, the data field in the data frame received by the high-speed serial interface 011b may also carry an identifier of each first signal, and the high-speed serial interface 011b may further distinguish each first signal based on the identifier and transmit each first signal to the corresponding low-speed interface 012b.

[0123] In another possible example, the high-speed serial interface 011a can encapsulate the multiple first signals in a data frame according to a pre-agreed fixed order. After the high-speed serial interface 011b samples the data in the data frame, it can restore and identify the multiple first signals according to the fixed order, and then send the multiple first signals to the corresponding low-speed interface 012b respectively.

[0124] As an optional implementation, Figure 8 As shown, the two data transmission chips 01a and 01b can be located on the same PCB in the electronic device. For example, the PCB can be the mainboard of the electronic device. Accordingly, the electrical signal transmission medium 03 between the two data transmission chips 01a and 01b can be a metal trace on the PCB. Among them, the PCB can also be called a single board. For example, in the scenario where the electronic device is a server, the PCB can be a server single board.

[0125] In this implementation, the electronic device may further include a main control device located on the mainboard, which may be a central processing unit (CPU) or a microcontroller unit (MCU). Figure 8 Take the CPU as an example for illustration. The master control device can be connected to the low-speed interface 012b of the data transmission chip 01b through a parallel bus. After the high-speed serial interface 011a of the data transmission chip 01a transmits the data frame to the data transmission chip 01b, the high-speed serial interface 011b of the data transmission chip 01b can sample the data in the data frame and store it in its internal register 013b. Afterwards, the low-speed interface 012b can transmit the data in the internal register 013b to the master control device.

[0126] from Figure 8 It can be seen that the data transmission chip 01b may include two groups of internal registers 013b, and each group of internal registers 013b may include one or more registers. One group of internal registers 013b can store data inside the data transmission chip 01b, and the other group of internal registers 013b can be used to store data sent by the data transmission chip 01a. Since the main control device can access the two groups of internal registers 013b through a parallel bus, it can not only obtain the data in the data transmission chip 01b, but also obtain the data in the data transmission chip 01a. As a result, the main control device no longer needs to be connected to the data transmission chip 01a through a parallel bus, thereby effectively reducing the number of signal lines on the PCB.

[0127] Alternatively, if Figure 8 As shown, the high-speed serial interface 011a of the data transmission chip 01a can also be connected to the internal register 013a therein. Accordingly, in addition to serially transmitting the multiple first signals received by the low-speed interface 012a to the data transmission chip 01b, the high-speed serial interface 011a can also serially transmit the data in the internal register 013a to the data transmission chip 01b.

[0128] As another optional implementation, Figure 2As shown, the two data transmission chips 01a and 01b may be located on different PCBs in the electronic device. Figure 2 As shown, the data transmission chip 01a is located on the single board 1 of the electronic device, and the data transmission chip 01b is located on the single board 2 of the electronic device. The electrical signal transmission medium 03 between the two data transmission chips 01a and 01b can be an electrical signal transmission line, such as a cable. Alternatively, the electrical signal transmission medium 03 can be a backplane (also called a backplane connector), and the PCBs where the two data transmission chips 01a and 01b are located are both inserted into the backplane and can communicate through the backplane.

[0129] In this implementation, the electronic device may further include at least one low-speed device and a main control device for controlling the at least one low-speed device, and the main control device may be a CPU or an MCU. Figure 2 As shown, the main control device (such as CPU) can be located on the same PCB as the data transmission chip 01a, and connected to at least one low-speed interface of the data transmission chip 01a. The at least one low-speed device can be located on the same PCB as the data transmission chip 01b, and connected to at least one low-speed interface of the data transmission chip 01a.

[0130] Among them, the low-speed devices connected to the IIC interface may include sensors (such as temperature sensors or humidity sensors) and electrically erasable programmable read only memory (EEPROM), etc. The low-speed devices connected to the UART interface may include MCU, etc. The low-speed devices connected to the SPI interface may include flash memory (FLASH), etc.

[0131] Based on the above connection mode, the main control device can control multiple low-speed devices on different PCBs through the high-speed serial interface in the data transmission chip, thereby effectively reducing the number of signal lines between different PCBs in the electronic device and simplifying the structure of the electronic device.

[0132] Fig. 9 is a flow chart of a data transmission method provided in an embodiment of the present application, Fig. 9 The CPU transmits multiple first signals to multiple low-speed devices through data transmission chips 01a and 01b as an example for explanation. Fig. 9 As shown, the method includes:

[0133] Step S11: The CPU writes multiple first signals into a data queue.

[0134] The multiple first signals may be control commands for controlling the multiple low-speed devices.

[0135] Step S12: The low-speed interface of the data transmission chip 01a reads the multiple first signals.

[0136] Step S13: The high-speed serial interface 011a of the data transmission chip 01a generates a data frame based on the multiple first signals, and sends the data frame in series to the data transmission chip 01b. That is, the high-speed serial interface 011a can encapsulate the multiple first signals in the data field of the data frame.

[0137] Step S14: After receiving the data frame, the high-speed serial interface 011b of the data transmission chip 01b decodes the data frame to recover the multiple first signals.

[0138] Step S15: The high-speed serial interface 011b of the data transmission chip 01b dispatches the multiple first signals to different low-speed interfaces so that each low-speed interface transmits the first signals to the corresponding low-speed device. For example, the high-speed serial interface 011b can dispatch the first signals to the controllers of different low-speed interfaces, and each low-speed interface controller can then transmit the first signals to the corresponding low-speed device through the low-speed interface.

[0139] The above descriptions are all based on the data transmission chip 01a as the chip on the data transmission side, and the data transmission chip 01b as the chip on the data receiving side. It can be understood that the data transmission chip 01b can also be used as a chip on the data transmission side to transmit data frames serially to the data transmission chip 01a, that is, the high-speed serial interface 011a in the data transmission chip 01a can also have the functions of the high-speed serial interface 011b described above, and the high-speed serial interface 011b can also have the functions of the high-speed serial interface 011a described above.

[0140] For example, the high-speed serial interface 011a is also used to receive multiple second signals sent serially by the data transmission chip 01b in the form of data frames, and transmit the multiple second signals to the low-speed interface 012a.

[0141] Optionally, the high-speed serial interface 011a can sample the data frame sent by the data transmission chip 01b based on the frequency of the clock signal of the data transmission chip 01a, and restore the multiple second signals based on the sampled data.

[0142] The data obtained by the high-speed serial interface 011a sampling the data frame sent by the data transmission chip 01a may include: a plurality of second sampling sequences arranged in sequence according to the sampling time, each second sampling sequence including a multi-bit sampling value. Accordingly, the high-speed serial interface 011a is also used to sequentially obtain a sampling value from each second sampling sequence, and restore a second signal based on the multi-bit sampling values ​​obtained in sequence.

[0143] The process of the high-speed serial interface 011a sampling the received data frame to recover the multiple second signals can refer to the related description of the high-speed serial interface 011b recovering the multiple first signals in the above embodiment, which will not be repeated here.

[0144] Fig.10 is a flowchart of another data transmission method provided in an embodiment of the present application, Fig.10 Take the example of multiple low-speed devices transmitting multiple second signals to the CPU through data transmission chips 01a and 01b. Fig.10 As shown, the method may include:

[0145] Step S21: The high-speed serial interface 011b of the data transmission chip 01b polls each low-speed interface 012b to obtain multiple second signals.

[0146] In the embodiment of the present application, each second signal may be a signal sent by a low-speed device to a low-speed interface 012b to which it is connected. Fig. 9 In the embodiment shown, the first signal is a control instruction. After receiving the control instruction, each low-speed device can respond to the control instruction, perform a corresponding operation, and return the execution result of the operation to the corresponding low-speed interface 012b in the data transmission chip 01b. That is, each second signal can be an execution result fed back by a low-speed device.

[0147] Step S22, the high-speed serial interface 011b of the data transmission chip 01b generates a data frame based on the acquired multiple second signals, and sends the data frame serially to the data transmission chip 01a. That is, the data transmission chip 01b can encapsulate the multiple second signals in the data field of the data frame, and send the data frame generated after encapsulation to the data transmission chip 01a.

[0148] Step S23: After receiving the data frame, the high-speed serial interface 011a of the data transmission chip 01a decodes the data frame to recover multiple second signals.

[0149] Step S24: The high-speed serial interface 011a of the data transmission chip 01a writes the multiple second signals into a data queue.

[0150] Step S25 : The CPU reads the data queue through the low-speed interface 012 a of the data transmission chip 01 a to obtain the multiple second signals.

[0151] As a possible example, Figure 2 As shown, the type of the low-speed interface used in the data transmission chip 01a to connect to the master device can be the same as the type of the low-speed interface used in the data transmission chip 01b to connect to the low-speed device. Figure 2The low-speed interfaces used to connect to the main control device in the data transmission chip 01a include: IIC interface, UART interface and SPI interface. Correspondingly, the low-speed interfaces used to connect to the low-speed device in the data transmission chip 01b also include: IIC interface, UART interface and SPI interface.

[0152] As another possible example, Fig.11 As shown, the type of low-speed interface used in the data transmission chip 01a to connect to the master device may be different from the type of low-speed interface used in the data transmission chip 01b to connect to the low-speed device. Fig.11 The low-speed interface in the data transmission chip 01a connected to the main control device may be an LBUS interface, and the low-speed interface in the data transmission chip 01b connected to the low-speed device may include: an IIC interface, a UART interface, and an SPI interface.

[0153] Optionally, Figure 2 In the example shown, the data transmission chip 01a may further include an LBUS interface, and the IIC interface, UART interface and SPI interface in the data transmission chip 01a may be connected to the CPU via the LBUS interface.

[0154] The following description will be made by taking the example that the master control device communicates with low-speed devices connected to multiple IIC interfaces of the data transmission chip 01b through the LBUS interface of the data transmission chip 01a.

[0155] like Fig.12 As shown, the data transmission chip 01a in the single board 1 also includes an LBUS interface controller, which can write the control command sent by the master device to the LBUS interface into the LBUS transmission queue. The LBUS transmission queue can be a first-in first-out (FIFO) queue, for example, the width (width) of the transmission queue can be 64 bits, and the depth (depth) can be 512. Afterwards, the high-speed serial interface scheduler in the data transmission chip 01a can read data from the LBUS transmission queue and write the read data (i.e., the control command) into the transmission buffer of the high-speed serial interface 011a. The width of the transmission buffer can be equal to the length of each data field in the data frame, for example, it can be 8 bits; the depth of the transmission buffer can be equal to the number of data fields included in the data frame, for example, it can be 20.

[0156] The high-speed serial interface 011a can generate a data frame based on the data stored in its transmission buffer, and send the data frame serially to the data transmission chip 01b in the single board 2. Fig.12, the data frame may include T data fields from D0 to DT, and a check field C0 located after the T data fields. Assuming that the length W of each data field is 8 bits and the length M of the gap field is 1 bit, the length of the frame header of the data frame may be 11 bits, and include 10 consecutive bits of 1 and 1 bit of 0. The frame header can be represented as FFE in hexadecimal.

[0157] Continue to refer Fig.12 After receiving the data frame, the high-speed serial interface 011b of the data transmission chip 01b in the single board 2 can decode the data frame and store the decoded data (i.e., the control command carried in the multiple data fields) into the receiving buffer of the high-speed serial interface 011b. The high-speed serial interface scheduler in the data transmission chip 01b can read the control command from the receiving buffer, parse the control command, and write it into the corresponding low-speed device through the IIC interface. The IIC controller in the low-speed device can then write the received control command into the command queue.

[0158] Fig.13 FIG. 1 is a flow chart showing that the data transmission chip 01b in the single board 2 sends data to the data transmission chip 01a in the single board 1. Fig.13 As shown, after the low-speed device in the single board 2 performs an operation based on the received control command, the IIC controller can write the execution result of the operation into the result queue of the low-speed device. The high-speed serial interface scheduler in the data transmission chip 01b can read the execution result from the result queue of the low-speed device through the IIC interface, and write the execution result into the transmission buffer of the high-speed serial interface 011b. After that, the high-speed serial interface 011b can generate a data frame based on the data stored in its transmission buffer, and send the data frame serially to the data transmission chip 01a in the single board 1.

[0159] After receiving the data frame, the high-speed serial interface 011a of the data transmission chip 01a in the single board 1 can decode the data frame and store the data obtained after decoding (i.e., the execution results carried in the multiple data fields) in the receiving buffer of the high-speed serial interface 011a. The high-speed serial interface scheduler in the data transmission chip 01a can read the execution result from the receiving buffer and send the execution result to the main control device through the LBUS interface.

[0160] It is understandable that if the high-speed serial interfaces of the data transmission chips are connected by signal lines (such as metal traces or cables), then for the scenario where the data transmission chip 01a sends data unidirectionally to the data transmission chip 01b, only one signal line can be set between the high-speed serial interfaces of the two data transmission chips. Figure 1 As shown, two signal lines can be set between the high-speed serial interfaces of the two data transmission chips, one of which is used for the data transmission chip 01a to send a data frame to the data transmission chip 01b, and the other signal line is used for the data transmission chip 01b to send a data frame to the data transmission chip 01a. Optionally, the signal line between the high-speed serial interfaces can also be called a high-speed serial bus, or a Hisport bus.

[0161] Fig.14 is a schematic diagram of the structure of a data transmission chip provided in an embodiment of the present application, such as Fig.14 As shown, the data transmission chip includes at least one high-speed serial interface 011 and at least one low-speed interface 012. For example, Fig.14 A high-speed serial interface 011 and a plurality of low-speed interfaces 012 are shown.

[0162] The high-speed serial interface 011 may include a connection port 0111, and the connection port 0111 is used to connect to the electrical signal transmission medium 03. For example, if the electrical signal transmission medium 03 is a metal trace, the connection port 0111 may be a pin; if the electrical signal transmission medium 03 is a cable, the connection port 0111 may be a cable interface.

[0163] Continue to refer Fig.14 , the high-speed serial interface 011 may also include:

[0164] The first sampling module 0112 is used to sample multiple channels of first signals.

[0165] The frame assembly module 0113 is used to generate a data frame based on the sampled data.

[0166] The first sampling module 0112 may perform parallel sampling on the multiple first signals based on the frequency of the clock signal of the data transmission chip 01a.

[0167] Optionally, the data sampled by the first sampling module 0112 may include a plurality of first sampling sequences arranged in sequence according to the sampling time, and each first sampling sequence includes a multi-bit sampling value obtained by performing a parallel sampling on the multiple first signals.

[0168] Optionally, the connection port 0111 is also used for transmitting data frames sent serially by the data chip 01b; Fig.14 As shown, the high-speed serial interface 011 may also include:

[0169] The second sampling module 0114 is used to sample the data frames received by the connection port 0111 to obtain multiple second signals.

[0170] The scheduling module 0115 is used to transmit the multiple second signals to the low-speed interface 012. The scheduling module 0115 may be the high-speed serial interface scheduler described in the above embodiment.

[0171] Optionally, the second sampling module 0114 is used to sample the data frame based on the frequency of the clock signal of the data transmission chip 01a, and restore the multiple second signals based on the sampled data.

[0172] Optionally, the data sampled by the second sampling module 0114 may include a plurality of second sampling sequences arranged in sequence according to the sampling time, and each first sampling sequence includes a plurality of sampling values. The second sampling module 0114 may be used to:

[0173] A sampling value of one bit is sequentially acquired from each second sampling sequence, and a second signal is restored based on the multi-bit sampling values ​​acquired in sequence.

[0174] It can be understood that each module in the data transmission chip described above can be a circuit module, for example, can be implemented by a programmable logic circuit.

[0175] In summary, the embodiment of the present application provides a data transmission chip, the low-speed interface of the data transmission chip is used to receive multiple first signals, and the high-speed serial interface of the data transmission chip is used to serially transmit the multiple first signals to another data transmission chip in the form of data frames. Since multiple signals can be serially transmitted between data transmission chips in the form of data frames, the number of signal lines required to be set between data transmission chips can be effectively reduced, thereby simplifying the structure of the electronic device. And since the data transmission rate of the high-speed serial interface is relatively high, the transmission efficiency of the multiple first signals can be effectively ensured.

[0176] An embodiment of the present application further provides a data transmission chip, which includes a programmable logic circuit and is used to implement the functions of the data transmission chip described in the above embodiment.

[0177] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0178] In the present application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, multiple data fields means two or more data fields.

[0179] The above is only an optional implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A data transmission chip, characterized in that: The data transmission chip includes a high-speed asynchronous serial interface and at least one low-speed interface; The high-speed asynchronous serial interface is used to receive a first signal, which carries at least one low-speed signal, and transmit the at least one low-speed signal to at least one corresponding low-speed interface, wherein the data transmission rate of the high-speed serial interface is higher than the data transmission rate of the at least one low-speed interface.

2. The data transmission chip according to claim 1, characterized in that: The first signal carries the at least one low-speed signal in the form of a data frame.

3. The data transmission chip according to claim 1 or 2, characterized in that: The receiving a first signal comprises: The first signal is sampled based on the frequency of the clock signal of the data transmission chip, and the at least one low-speed signal is restored based on the sampled data.

4. The data transmission chip according to claim 3, characterized in that: The sampling of the first signal based on the frequency of the clock signal of the data transmission chip includes: A plurality of first sampling sequences arranged in sequence according to the chronological order of sampling time, each of the second sampling sequences comprising a plurality of sampling values; The high-speed serial interface is further used to sequentially obtain a single-bit sampling value from each of the first sampling sequences, and restore the at least one low-speed signal based on the multiple-bit sampling values ​​obtained in sequence.

5. The data transmission chip according to claim 2, characterized in that: The data frame includes: a frame header, a plurality of data fields, and a gap field located after each of the data fields; In which, the frame header includes a continuous N-bit first value and an M-bit second value, the multiple data fields are used to carry data obtained by sampling the multiple first signals, and the length of each of the data fields is W bits, the gap field includes the M-bit second value, the N is a positive integer greater than the W, and the M is a positive integer less than the W.

6. The data transmission chip according to claim 5, characterized in that: The difference between the N and the W is greater than or equal to 2, and the M is 1.

7. The data transmission chip according to claim 5 or 6, characterized in that: The first value is 1, and the second value is 0.

8. The data transmission chip according to any one of claims 5 to 7, characterized in that: The data frame further includes: a check field located after the plurality of data fields, and a gap field located after the check field; The check field is used to carry a check bit, and the length of the check field is equal to the length of the data field.

9. An electronic device, characterized in that: The electronic device comprises a data transmission chip, and the data transmission chip is used to implement the function of the data transmission chip as claimed in any one of claims 1 to 8.

Images