A circuit timing state analysis method based on CJTAG waveform

Abstract

The present application relates to circuit timing analysis technology, disclose a kind of circuit timing state analysis method based on CJTAG waveform.The method generates exit waveform and activation waveform in initialization stage, clock output signal of specified pulse number is generated by first timer in working stage, and clock output signal is synchronously provided to second timer, first serial peripheral interface and target chip;Second timer forms three clock phase control according to the same clock, so that first serial peripheral interface outputs TMS and nTDI in the first two clock slots, so that the second serial peripheral interface samples TDO in the third clock slot;Then align data according to clock number, three clock period group sequence number and transceiver bit sequence, form circuit timing state sequence, for debugging end to read the timing state of target chip, so as to realize CJTAG waveform state analysis under the condition of reducing special hardware dependence.

Description

Technical Field

[0001] This invention relates to the field of circuit timing analysis technology, and in particular to a method for analyzing circuit timing states based on CJTAG waveforms. Background Technology

[0002] The field of circuit timing analysis technology involves processing chip debug interface waveforms, clock phases, single-wire interface transmission directions, and return data sampling states, especially the alignment of TMS, nTDI, and TDO states under CJTAG working waveforms. Traditional circuit timing state analysis methods based on CJTAG waveforms involve generating CJTAG timing data using a dedicated JTAG controller IP core, programmable logic, or general-purpose GPIO simulation, and then having the processor or debug control logic read the target chip's return signals to obtain the debug interface state.

[0003] Existing solutions rely on dedicated controller IP cores or programmable logic to generate CJTAG waveforms. Hardware costs and verification cycles are constrained by dedicated circuits. Different frequencies or protocol variants require re-adaptation. Using general-purpose GPIO to simulate timing bit-level control relies on processor interrupts, increasing processor load. The lack of fixed phase division between the TMS and nTDI transmission phases and the TDO return phase makes it difficult to stably align sampled data with TCKC timing. This results in limited real-time performance and consistency of the target chip state parsing results, and the development process is constrained by dedicated hardware. Summary of the Invention

[0004] To address the technical problems of existing CJTAG waveform generation and state analysis relying on dedicated hardware, lacking fixed phase division between the transmission and return phases, and difficulty in aligning sampled data stably with TCKC timing, this invention provides a circuit timing state analysis method based on CJTAG waveforms, comprising the following steps: After power-on, configuring the input / output ports on the target chip's connection side to a general input / output mode, generating CJTAG exit waveform and CJTAG activation waveform through the general input / output mode, causing the target chip to enter OSCAN working mode; configuring a first timer to a specified pulse output mode, generating a clock output signal from the first timer, and synchronously providing the clock output signal to a second timer, a first serial peripheral interface, and the target chip; configuring the second timer to a phase-split pulse width modulation mode driven by the clock output signal, so that the second timer operates in groups of three clocks. A first phase-splitting control signal and a second phase-splitting sampling signal with opposite phase to the first phase-splitting control signal are generated. The first phase-splitting control signal is used to control the gating switch to switch the single-wire debug interface between the first serial peripheral interface and the second serial peripheral interface, and the second phase-splitting sampling signal is used to provide a sampling clock to the second serial peripheral interface. The TMS data and nTDI data are combined into transmit buffer data and then output by the first serial peripheral interface. In the first two clock slots of each group of three clocks, the gating switch is used to connect the first serial peripheral interface to the single-wire debug interface. In the third clock slot, the gating switch is used to connect the single-wire debug interface to the second serial peripheral interface and sample the TDO data. The phase is aligned according to the clock sequence number, the three-clock cycle group sequence number, the bit order of the transmit buffer data, and the bit order of the TDO data, and the circuit timing state sequence of the target chip is output.

[0005] Furthermore, the clock output signal is connected to the external clock input of the second timer, the clock input of the first serial peripheral interface, and the TCK input of the target chip; the gating switch includes a first gating terminal, a second gating terminal, a common terminal, and a control terminal. The control terminal receives the first phase split control signal. The first gating terminal is connected to the data output of the first serial peripheral interface, the second gating terminal is connected to the data input of the second serial peripheral interface, and the common terminal is connected to the TMSC terminal of the target chip. As a progressive scheme, the first phase split control signal maintains a first valid state in the first two clock slots of each group of three clocks to conduct the first gating terminal and the common terminal, switches to a second valid state in the third clock slot to conduct the second gating terminal and the common terminal, and ensures that the first gating terminal and the second gating terminal are not simultaneously connected to the common terminal in any clock slot.

[0006] Furthermore, generating the CJTAG exit waveform includes controlling the TMS toggling a specified number of times while the TCK remains high, the specified number being determined by the interface design requirements of the target chip; generating the CJTAG activation waveform includes, after completing the CJTAG exit waveform, controlling the TCK and TMS to change according to the activation timing of the target chip, causing the target chip to enter the OSCAN operating mode. As a progressive scheme, the CJTAG activation waveform includes the sequentially formed Escape phase, OAC phase, EC phase, CP phase, and OSCAN entry phase. When the OSCAN entry phase is completed, the first timer is started to output the clock output signal, and the clock output signal is used as the TCKC clock beat of the subsequent OSCAN operating waveform.

[0007] Furthermore, for the OSCAN1 working waveform, each group of three clocks is used as a timing analysis unit. The first two clock slots of the timing analysis unit correspond to the probe drive interval and parse the TMS data and the nTDI data. The third clock slot of the timing analysis unit corresponds to the target return interval and parses the TDO data. Based on the timing analysis unit, the system clock state, system input state, system mode state, and system output state under the TCKC clock tick are formed. As an optional solution, for OSCAN working waveforms other than OSCAN1, the processor reassembles the transmit buffer data according to the bit slot order of the OSCAN working waveform and adjusts the frequency division enable mode of the second timer so that the reassembled transmit buffer data corresponds to the probe drive interval in the timing analysis unit, and the sampling clock of the second serial peripheral interface corresponds to the target return interval.

[0008] Furthermore, the transmit buffer data establishes a transmit record according to the three-clock cycle group sequence number. The transmit record includes the TMS bit value, the nTDI bit value, and the corresponding transmit clock slot identifier. The second serial peripheral interface generates a receive record according to the sampling clock. The receive record includes the TDO bit value and the corresponding sampling clock slot identifier. The circuit timing state sequence is generated based on the transmit record and the receive record. As an additional limitation, when the number of transmit records does not match the specified number of pulses, the transmit buffer data is supplemented before starting the next set of clock output signals. When the receive record is missing the sampling clock slot identifier, the corresponding three-clock cycle group sequence number is marked as an invalid parsing unit, and the clock sequence number continuity of adjacent valid parsing units is preserved when outputting the circuit timing state sequence. As a preferred embodiment, both the first serial peripheral interface and the second serial peripheral interface are configured as slave devices. The first serial peripheral interface continuously receives and transmits the clock under the action of the clock output signal, while the second serial peripheral interface intermittently receives the sampling clock only under the action of the second phase sampling signal. The direction switching of the single-wire debugging interface does not use the chip select control signal and does not generate a phase control signal through an inverter.

[0009] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, a unified clock is provided by a first timer and a three-clock phase control is formed by a second timer. The transmission intervals of TMS and nTDI and the return interval of TDO are fixed to different phase windows. The gating switch automatically switches the direction of the single-line interface according to the phase signal. The first serial peripheral interface and the second serial peripheral interface are responsible for transmission and sampling respectively. The processor only needs to preset and supplement the cached data, reducing the dependence on dedicated controllers and programmable logic, avoiding the sampling uncertainty introduced by interrupt-driven bit-level flips, and enabling the CJTAG working waveform to be aligned according to the period group and bit order to form a traceable circuit timing state sequence, satisfying the state analysis closed loop. Attached Figure Description

[0010] Figure 1 This is the main flowchart of the circuit timing state analysis based on CJTAG waveform of the present invention, which shows the overall processing chain of the target chip entering OSCAN working mode, unified clock output, three-clock phase control, single-line debugging interface switching, transmission and sampling, and phase alignment output. Figure 2 This is a flowchart illustrating the connection between the CJTAG exit waveform and CJTAG activation waveform stages in the present invention, showing the sequential relationship between TCK and TMS control, CJTAG exit waveform, Escape stage, OAC stage, EC stage, CP stage, OSCAN entry stage, and the start of the first timer in general input / output mode. Figure 3This is a signal flow diagram for the three-clock phase split control and single-wire debugging interface switching of the present invention, showing the clock output signal entering the second timer, the first serial peripheral interface and the target chip, as well as the relationship between the first phase split control signal and the second phase split sampling signal on the gating switch and the second serial peripheral interface; Figure 4 The present invention provides a data flow diagram for phase alignment between transmit buffer data and TDO data, illustrating the data relationships between TMS data, nTDI data, transmit buffer data, transmit record, receive record, TDO data, clock sequence number, three-clock cycle group sequence number, and circuit timing state sequence. Figure 5 This is a partial flowchart of the bit slot resynthesis and sampling matching of the working waveform other than OSCAN1 in this invention. It shows the local processing relationship between the bit slot order, transmission buffer data resynthesis, second timer frequency division enable adjustment, target return interval sampling, and status sequence output under different OSCAN working waveforms. Detailed Implementation

[0011] The following embodiments illustrate the implementability of the technical solutions described in this invention in CJTAG waveform generation, single-wire debug interface direction switching, return data sampling, and circuit timing state analysis. In these embodiments, the "target chip" is the chip object that receives the CJTAG working waveform and returns TDO data; the "clock output signal" is the clock generated by the first timer and synchronously provided to the second timer, the first serial peripheral interface, and the target chip; the "three-clock cycle group" is a timing analysis unit divided according to three consecutive clock cycles; the "transmit buffer data" is data synthesized from TMS data and nTDI data according to the slot order of the OSCAN working waveform and output by the first serial peripheral interface; the "TDO data" is data provided by the target chip through the single-wire debug interface during the return interval and sampled by the second serial peripheral interface; and the "circuit timing state sequence" is the state result formed after aligning the clock sequence number, the three-clock cycle group sequence number, the transmit buffer data bit order, and the TDO data bit order.

[0012] Example 1 Please see Figures 1 to 4 This embodiment provides a method for analyzing circuit timing states based on CJTAG waveforms. In this embodiment, after the target chip is powered on, it first receives the CJTAG exit waveform and the CJTAG activation waveform through a general input / output mode, causing the target chip to enter the OSCAN working mode. Subsequently, a unified clock is provided by a first timer, and a three-clock phase control is formed under the drive of the second timer, so that the transmission interval of the first serial peripheral interface and the sampling interval of the second serial peripheral interface are fixed within different phase windows. Finally, the bit order of the transmit buffer data and TDO data is aligned according to the three clock cycle groups to obtain the circuit timing state sequence of the target chip.

[0013] S1. Configure the input / output ports on the target chip's connection side to a general-purpose input / output mode, and generate CJTAG exit and activation waveforms using this mode. The input condition for this step is that the target chip has completed power-on and has an initial interface state capable of receiving TCK and TMS changes. The target chips are the TCK-related and TMS-related ports connected to the target chip. After configuration, the ports can have their level states directly changed by the control side executing this method, used to generate the preparatory waveforms required before the target chip enters OSCAN operating mode, even before the timer is started.

[0014] S111, when generating the CJTAG exit waveform, the TMS is controlled to toggle a specified number of times while the TCK remains high. This specified number of toggles is not extended to a fixed value in this embodiment, but is determined by the interface design requirements of the target chip. The input source for this sub-step is the interface design requirements of the target chip, the processing rule is to change the TMS level a specified number of times while the TCK remains high, the intermediate state is that the target chip receives the exit trigger sequence, and the output state is that the target chip completes the CJTAG exit-related identification.

[0015] In step S112, when generating the CJTAG activation waveform, after completing the CJTAG exit waveform, the TCK and TMS are controlled to change according to the target chip's activation timing sequence. This activation waveform sequentially forms the Escape stage, OAC stage, EC stage, CP stage, and OSCAN entry stage. Each stage is connected sequentially according to the activation timing required by the target chip, with the interface state formed in the previous stage serving as the input condition for the next stage. After the OSCAN entry stage is completed, the target chip enters the OSCAN operating mode and uses the subsequent clock output signal from the first timer as the TCKC clock beat of the OSCAN operating waveform.

[0016] S2: Configure the first timer to a specified pulse output mode. The first timer generates a clock output signal and synchronously provides the clock output signal to the second timer, the first serial peripheral interface, and the target chip. This step is triggered when the OSCAN entry phase in S1 is completed. The input source is the specified pulse output configuration of the first timer, and the output is a continuous clock output signal. The clock output signal is connected to the external clock input of the second timer, allowing the second timer to use this clock as the basis for phase counting. The clock output signal is also connected to the clock input of the first serial peripheral interface, enabling the first serial peripheral interface to output transmit buffer data at the same clock cycle. Furthermore, the clock output signal is connected to the TCK input of the target chip, ensuring that the TCKC clock cycle of the target chip is consistent with the transmit and sampling control.

[0017] S3 configures the second timer to a phase-split pulse width modulation mode driven by the clock output signal, causing the second timer to generate a first phase-split control signal and a second phase-split sampling signal in groups of three clock cycles. The input to this step is the clock output signal provided in S2. The processing rule is to divide the continuous clock into three clock cycle groups and form a fixed phase window within each group of three clock cycles. The first phase-split control signal is used to control the conduction direction of the gating switch, and the second phase-split sampling signal is opposite in phase to the first phase-split control signal and is used to provide a sampling clock to the second serial peripheral interface. Thus, the transmit control and return sampling no longer depend on the processor's bit-by-bit toggling, but are determined by the timing phase relationship under the same clock source.

[0018] In S311, during the first two clock slots of each group of three clocks, the first phase split control signal remains in a first active state, causing the gating switch to activate the first serial peripheral interface to the single-wire debug interface. In this state, the data output terminal of the first serial peripheral interface forms a transmission path with the TMSC terminal of the target chip, and the TMS bit value and nTDI bit value in the transmission buffer data sequentially enter the single-wire debug interface. The first two clock slots serve as the probe drive interval, corresponding to the transmission phase in the OSCAN1 working waveform.

[0019] In S312, in the third clock slot of each group of three clocks, the first phase-splitting control signal switches to the second active state, causing the gating switch to connect the single-wire debug interface to the second serial peripheral interface. Simultaneously, the second phase-splitting sampling signal provides a sampling clock to the second serial peripheral interface. In this state, the target chip outputs TDO data through the TMSC terminal, and the second serial peripheral interface reads the TDO bit value under the influence of the sampling clock. The first and second active states do not overlap in any clock slot, ensuring that the first and second serial peripheral interfaces are not simultaneously connected to the single-wire debug interface.

[0020] S4 uses the first phase-splitting control signal to control the gating switch to switch the single-wire debug interface between the first and second serial peripheral interfaces, and uses the second phase-splitting sampling signal to provide a sampling clock to the second serial peripheral interface. The gating switch includes a first gating terminal, a second gating terminal, a common terminal, and a control terminal. The control terminal receives the first phase-splitting control signal, the first gating terminal is connected to the data output terminal of the first serial peripheral interface, the second gating terminal is connected to the data input terminal of the second serial peripheral interface, and the common terminal is connected to the TMSC terminal of the target chip. Both the first and second serial peripheral interfaces are configured as slave devices. The first serial peripheral interface continuously receives the transmit clock under the action of the clock output signal, while the second serial peripheral interface intermittently receives the sampling clock only under the action of the second phase-splitting sampling signal. The direction switching of the single-wire debug interface does not use a chip select control signal, nor does it generate a phase control signal through an inverter. Instead, the second timer directly generates two phase-splitting signals with opposite phases to separate the transmit window and the sampling window.

[0021] S5, after combining the TMS data and nTDI data into transmit buffer data, is output by the first serial peripheral interface. Transmission is completed in the first two clock slots and sampling in the third clock slot within each three-clock cycle. The input data for this step includes the TMS data and nTDI data to be transmitted. The processing rule is to combine them into transmit buffer data according to the slot order of the OSCAN1 working waveform. The transmit buffer data is shifted out by the first serial peripheral interface according to the clock output signal. In the first two clock slots of the three-clock cycle group, it enters the single-wire debug interface through a gating switch. In the third clock slot, the gating switch opens the return path from the target chip to the second serial peripheral interface, and the second serial peripheral interface samples the TDO data under the action of the second phase sampling signal.

[0022] In step S511, for the OSCAN1 operating waveform, each group of three clocks is used as a timing analysis unit. The first two clock slots of the timing analysis unit correspond to the probe drive interval, carrying the corresponding bits of TMS data and nTDI data in the transmit buffer data, respectively; the third clock slot corresponds to the target return interval, carrying the TDO data returned by the target chip. The intermediate state formed by this sub-step has two transmit bit slots and one return bit slot for each three-clock-cycle group, and the subsequent step S6 performs phase alignment accordingly.

[0023] S512 establishes a transmission record according to the three-clock cycle group sequence number. The transmission record includes the TMS bit value, the nTDI bit value, and the corresponding transmission clock slot identifier. The transmission clock slot identifier is used to record whether the bit value is located in the first or second clock slot of the current three-clock cycle group, so that the transmission buffer data bit sequence can correspond to the transmission interval under the TCKC clock tick. The second serial peripheral interface establishes a reception record according to the sampling clock. The reception record includes the TDO bit value and the corresponding sampling clock slot identifier. The sampling clock slot identifier is used to record that the TDO bit value comes from the third clock slot of the current three-clock cycle group.

[0024] S513: When the number of transmitted records does not match the specified number of pulses, supplement the transmitted buffer data before starting the next set of clock output signals. This exception handling identifies the consistency between the number of transmitted records and the specified number of pulses; when they do not match, it indicates that the current transmitted buffer data is insufficient to cover the transmission interval corresponding to the subsequent specified pulse output. The supplemented transmitted buffer data continues to be output by the first serial peripheral interface under the action of the subsequent clock output signal. This processing does not change the sequence number of the three-clock-cycle group that has already been sampled; it only ensures that the subsequent transmitted bit slots have a traceable data source.

[0025] S514: When the received record lacks a sampling clock slot identifier, the corresponding three-clock-cycle group number is marked as an invalid parsing unit. This anomaly handling identifies whether the second serial peripheral interface forms a traceable sampling clock slot identifier for the third clock slot; if missing, the TDO data in that three-clock-cycle group cannot stably correspond to the target return interval. When outputting the timing state sequence of the circuit, the clock sequence number continuity of adjacent valid parsing units is preserved, enabling subsequent state reads to identify the timing relationship between valid parsing units and preventing units lacking sampling identifiers from being mistakenly identified as valid target return results.

[0026] S6 performs phase alignment based on the clock sequence number, the three-clock cycle group sequence number, the bit order of the transmit buffer data, and the bit order of the TDO data, outputting the circuit timing state sequence of the target chip. The inputs to this step are the transmit and receive records generated in S5. The processing rules are as follows: using the three-clock cycle group sequence number as the parsing unit index; using the clock sequence number to determine the position of each slot in the TCKC clock cycle; using the transmit buffer data bit order to determine the source of the TMS bit value and nTDI bit value; and using the TDO data bit order to determine the sampling position of the target return data. After alignment, a timing parsing unit can correspondingly generate the system clock state, system input state, system mode state, and system output state under the TCKC clock cycle. This output result can be traced and verified through the clock sequence number, transmit clock slot identifier, and sampling clock slot identifier in the record, thereby confirming that no phase aliasing has occurred between the transmit and return intervals.

[0027] Through the above process, the first timer provides a unified clock, the second timer forms a three-clock phase control under the same source clock, the gating switch completes the single-wire debugging interface direction switching according to the first phase control signal, and the second serial peripheral interface reads the TDO data of the target return interval according to the second phase sampling signal. Since both the transmit and receive records have three-clock cycle group numbers and clock slot identifiers, the output circuit timing state sequence can maintain the traceability relationship between the transmit bit, return bit, and TCKC clock beat, thereby reducing the dependence on dedicated controllers and programmable logic, and reducing the sampling uncertainty caused by bit-by-bit analog general input / output.

[0028] Example 2 Please see Figure 1 , Figures 3 to 5This embodiment provides a circuit timing state analysis method based on CJTAG waveforms. The difference between this embodiment and Embodiment 1 is that when the target chip enters an OSCAN working waveform other than OSCAN1, the transmit buffer data is no longer directly synthesized according to the fixed first two clock slots of OSCAN1. Instead, the transmit buffer data is resynthesized according to the slot order of the corresponding OSCAN working waveform, and the frequency division enable mode of the second timer is adjusted so that the resynthesized transmit buffer data still corresponds to the probe drive interval in the timing analysis unit, and the sampling clock of the second serial peripheral interface still corresponds to the target return interval. The direct technical effect of this difference is that the phase traceability relationship between the transmit and return slots is maintained even under waveform slot orders other than OSCAN1.

[0029] S1: After the target chip is powered on, it first generates a CJTAG exit waveform and a CJTAG activation waveform using the general input / output mode. The CJTAG exit waveform is formed by controlling the TMS to toggle a specified number of times while the TCK is held high; the CJTAG activation waveform sequentially passes through the Escape stage, OAC stage, EC stage, CP stage, and OSCAN entry stage. Similar to Example 1, the output state of this step is that the target chip has entered the OSCAN working mode, the only difference being that the bit slot order of the subsequent OSCAN working waveform is different from OSCAN1.

[0030] In step S2, the first timer is still configured to the specified pulse output mode, and the clock output signal is synchronously provided to the second timer, the first serial peripheral interface, and the target chip. This step ensures that the second timer phase splitting, the first serial peripheral interface transmission, and the target chip TCK input still share the same clock source. Since the bit slot order of different OSCAN working waveforms may change the relative arrangement of the transmit and return bits, the clock output signal output by S2 does not change its own source, but serves as a common clock reference for subsequent re-division of the probe drive interval and the target return interval.

[0031] S3, the second timer is still driven by the clock output signal and generates the first phase split control signal and the second phase split sampling signal, but the frequency division enable mode is adjusted according to the slot order of the current OSCAN working waveform. The input to this process is the slot order of the current OSCAN working waveform and the clock output signal. The processing rule is to make the first phase split control signal cover the probe drive interval corresponding to the resynthesized transmit buffer data, and to make the second phase split sampling signal fall into the target return interval of the target chip's TDO data. The adjusted intermediate state is: the transmit conduction window of the gating switch corresponds to the transmit buffer data bit order, and the sampling clock of the second serial peripheral interface corresponds to the TDO return bit order.

[0032] S4, the gating switch still switches the single-wire debug interface between the first and second serial peripheral interfaces based on the first phase split control signal. The first gating terminal is connected to the data output terminal of the first serial peripheral interface, the second gating terminal is connected to the data input terminal of the second serial peripheral interface, and the common terminal is connected to the TMSC terminal of the target chip. When the first phase split control signal is in the transmit on state, the transmit buffer data enters the single-wire debug interface through the first serial peripheral interface; when the first phase split control signal is in the return on state, the TDO data of the target chip enters the second serial peripheral interface through the single-wire debug interface. The second phase split sampling signal only provides a sampling clock to the second serial peripheral interface during the sampling window corresponding to the return on state.

[0033] S5. Reassemble the transmit buffer data according to the slot order of the OSCAN working waveform other than OSCAN1, and output the reassembled transmit buffer data through the first serial peripheral interface. The inputs to this step include TMS data, nTDI data, and the slot order of the current OSCAN working waveform; the processing rule is to place the TMS bit value and nTDI bit value into the transmit buffer data position corresponding to the current probe drive interval. Unlike Embodiment 1, this step does not directly use the correspondence between the first two clock slots of OSCAN1 as the unique transmit slot relationship, but determines the output position of each bit in the transmit buffer data based on the slot order of the current OSCAN working waveform.

[0034] S511, establish the transmission record corresponding to the current OSCAN working waveform. The transmission record still includes the TMS bit value, nTDI bit value, and transmission clock slot identifier, but the transmission clock slot identifier is determined by the bit slot order of the current OSCAN working waveform. After the record is formed, the first serial peripheral interface outputs the resynthesized transmission buffer data under the action of the clock output signal, and the first phase split control signal causes the gating switch to conduct the first serial peripheral interface to the single-wire debugging interface in the corresponding probe drive interval.

[0035] S512, establish the receive record corresponding to the current OSCAN working waveform. The receive record still includes the TDO bit value and the sampling clock slot identifier, but the sampling clock slot identifier is generated by the second phase sampling signal within the target return interval. This record is used to indicate that the TDO bit value does not come from the transmit conduction window, but from the return sampling window after the frequency division enable mode is adjusted. Therefore, the TDO data under the current OSCAN working waveform can be associated with the resynthesized transmit buffer data in the same three-clock-cycle group.

[0036] S513: If the resynthesized transmit buffer data is insufficient to match the specified number of pulses, the transmit buffer data is supplemented before starting the next set of clock output signals. This process verifies whether the number of transmit records under the current OSCAN working waveform covers the transmit slots required for the specified pulse output. If the number of transmit records does not cover the required transmit slots for the specified pulse output, the transmit buffer data is supplemented first, and then the next set of clock output signals is started to avoid a gap in the correspondence between the transmit slots and the specified pulse output. If the received record lacks a sampling clock slot identifier, the corresponding parsing unit is marked as an invalid parsing unit, and the clock sequence number continuity between adjacent valid parsing units is maintained in the output circuit timing state sequence. This process verifies whether the received record under the current OSCAN working waveform carries the identifier information corresponding to the sampling clock slot. If the received record lacks a sampling clock slot identifier, the received record is not parsed as a valid TDO bit value, and the valid parsing result only comes from the received record with a sampling clock slot identifier. This exception handling is used to prevent TDO bit values ​​lacking sampling source identifiers from entering the valid parsing result.

[0037] S6 performs phase alignment based on the clock sequence number, the three-clock cycle group sequence number, the resynthesized transmit buffer data bit sequence, and the TDO data bit sequence, outputting the circuit timing state sequence of the target chip. The input to this step is the transmit and receive records under the current OSCAN operating waveform. The processing rule is to first locate the transmit and return bits under the same working cycle according to the three-clock cycle group sequence number, then confirm the probe drive interval and target return interval according to the transmit clock slot identifier and the sampling clock slot identifier, and finally merge the TMS bit value, nTDI bit value, and TDO bit value into the target chip's state result under the TCKC clock cycle. This output result can be verified by the number of transmit records, the sampling clock slot identifier, and the continuity of the clock sequence numbers of adjacent valid parsing units.

[0038] Through the aforementioned differential processing, when the OSCAN working waveform other than OSCAN1 changes its slot order, it is not necessary to change the way the first timer provides a unified clock, nor is it necessary to add a dedicated controller. Only by resynthesizing the transmit buffer data within the range supported by the original disclosure and adjusting the frequency division enable mode of the second timer, the transmit and return intervals can be re-corresponded to the slot boundaries of the current working waveform. Therefore, the TDO data returned by the target chip under different OSCAN working waveforms can form a traceable circuit timing state sequence with the TMS data, nTDI data, and TCKC clock ticks.

[0039] The specific processes, signal relationships, data recording, clock slot division, interface connection methods, exception marking methods, and status output methods described in the above embodiments are used to illustrate the feasible implementation methods of the technical solutions recorded in this invention, and do not limit this invention to the specific embodiments listed. Without departing from the technical solutions recorded in this invention, any equivalent substitutions, equivalent modifications, equivalent combinations, order adjustments, equivalent transformations of field names, equivalent inheritance of execution subjects, or equivalent changes in carrier forms that can be conceived by those skilled in the art should fall within the protection scope of this invention; however, such changes should not be extended to unclaimed topics, nor should they alter the substantial correspondence between technical objects through name changes.

Claims

1. A circuit timing state analysis method based on CJTAG waveforms, characterized in that, include: After power-on, the input / output ports on the target chip connection side are configured to general input / output mode. CJTAG exit waveform and CJTAG activation waveform are generated through the general input / output mode, so that the target chip enters OSCAN working mode. Configure the first timer to a specified pulse output mode, generate a clock output signal from the first timer, and synchronously provide the clock output signal to the second timer, the first serial peripheral interface, and the target chip. Configure the second timer to a phase-split pulse width modulation mode driven by the clock output signal, so that the second timer generates a first phase-split control signal and a second phase-split sampling signal with the opposite phase to the first phase-split control signal in a group of three clock cycles; The first phase control signal is used to control the gating switch to switch the single-wire debugging interface between the first serial peripheral interface and the second serial peripheral interface, and the second phase sampling signal is used to provide a sampling clock to the second serial peripheral interface. After combining TMS data and nTDI data into transmit buffer data, it is output by the first serial peripheral interface. In the first two clock slots of each group of three clocks, the gating switch is turned on to connect the first serial peripheral interface to the single-wire debug interface. In the third clock slot, the gating switch is turned on to connect the single-wire debug interface to the second serial peripheral interface and TDO data is sampled. Phase alignment is performed based on the clock sequence number, the three-clock cycle group sequence number, the bit order of the transmitted buffer data, and the bit order of the TDO data, and the circuit timing state sequence of the target chip is output.

2. The circuit timing state analysis method based on CJTAG waveforms according to claim 1, characterized in that, The clock output signal is connected to the external clock input terminal of the second timer, the clock input terminal of the first serial peripheral interface, and the TCK input terminal of the target chip; The gating switch includes a first gating terminal, a second gating terminal, a common terminal, and a control terminal. The control terminal receives the first phase split control signal. The first gating terminal is connected to the data output terminal of the first serial peripheral interface. The second gating terminal is connected to the data input terminal of the second serial peripheral interface. The common terminal is connected to the TMSC terminal of the target chip.

3. The circuit timing state analysis method based on CJTAG waveforms according to claim 2, characterized in that, The first phase split control signal maintains a first active state in the first two clock slots of each group of three clocks to connect the first strobe terminal and the common terminal, switches to a second active state in the third clock slot to connect the second strobe terminal and the common terminal, and ensures that the first strobe terminal and the second strobe terminal are not simultaneously connected to the common terminal in any clock slot.

4. The circuit timing state analysis method based on CJTAG waveforms according to claim 1, characterized in that, Generating the CJTAG exit waveform includes controlling the TMS to toggle a specified number of times while the TCK remains high, the specified number of times being determined by the interface design requirements of the target chip; Generating the CJTAG activation waveform includes, after completing the CJTAG exit waveform, controlling the changes of TCK and TMS according to the activation timing of the target chip, so that the target chip enters the OSCAN working mode.

5. The circuit timing state analysis method based on CJTAG waveforms according to claim 4, characterized in that, The CJTAG activation waveform includes the Escape phase, OAC phase, EC phase, CP phase and OSCAN entry phase formed in sequence. When the OSCAN entry phase is completed, the first timer is started to output the clock output signal, and the clock output signal is used as the TCKC clock beat of the subsequent OSCAN working waveform.

6. The circuit timing state analysis method based on CJTAG waveforms according to claim 1, characterized in that, For the OSCAN1 working waveform, each group of three clocks is used as a timing analysis unit. The first two clock slots of the timing analysis unit correspond to the probe drive interval and analyze the TMS data and the nTDI data. The third clock slot of the timing analysis unit corresponds to the target return interval and analyzes the TDO data. Based on the timing analysis unit, the system clock state, system input state, system mode state and system output state under the TCKC clock tick are formed.

7. The circuit timing state analysis method based on CJTAG waveforms according to claim 6, characterized in that, For OSCAN working waveforms other than OSCAN1, the processor reassembles the transmit buffer data according to the bit slot order of the OSCAN working waveform, and adjusts the frequency division enable mode of the second timer so that the reassembled transmit buffer data corresponds to the probe drive interval in the timing parsing unit, and so that the sampling clock of the second serial peripheral interface corresponds to the target return interval.

8. The circuit timing state analysis method based on CJTAG waveforms according to claim 1, characterized in that, The transmit buffer data establishes a transmit record according to the three clock cycle group sequence number. The transmit record includes the TMS bit value, the nTDI bit value and the corresponding transmit clock slot identifier. The second serial peripheral interface generates a receive record according to the sampling clock. The receive record includes the TDO bit value and the corresponding sampling clock slot identifier. The circuit timing state sequence is generated based on the transmit record and the receive record.

9. The circuit timing state analysis method based on CJTAG waveforms according to claim 8, characterized in that, When the number of transmitted records does not match the specified number of pulses, the transmitted buffer data is supplemented before starting the next set of clock output signals; When the received record is missing the sampling clock slot identifier, the corresponding three-clock cycle group number is marked as an invalid parsing unit, and the continuous relationship of the clock numbers of adjacent valid parsing units is preserved when outputting the circuit timing state sequence.

10. The circuit timing state analysis method based on CJTAG waveforms according to claim 1, characterized in that, Both the first serial peripheral interface and the second serial peripheral interface are configured as slave devices. The first serial peripheral interface continuously receives and transmits the clock under the action of the clock output signal, while the second serial peripheral interface intermittently receives the sampling clock only under the action of the second phase sampling signal. The direction switching of the single-wire debugging interface does not use the chip select control signal and does not generate a phase control signal through an inverter.

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