A control circuit and chip of a stepper motor

Abstract

The application discloses a control circuit and a chip of a stepping motor, and relates to the technical field of motor driving control, which comprises a mute stepping adjustment unit, a sampling unit and a driving unit. At the zero-crossing point in the preset PWM period, the sampling unit is controlled to collect the actual current value of the motor winding, and the current error is obtained by subtracting the actual current value from the theoretical current value. The driving signal is generated according to the current error, and finally the driving unit controls the time proportion of the current in the motor winding in the conduction stage and the decay stage in the PWM period according to the driving signal. Since the control mode of real-time detection of winding instantaneous current is no longer relied on, the time proportion distribution of the current in the conduction stage and the decay stage in the PWM period is determined by periodically sampling the actual current value, and the sampling time is limited in the zero-crossing point window, the transient noise of the switching tube switching is avoided, the influence of the current burr on the stepping motor is effectively reduced, and the mute and stable driving of the motor is realized.

Description

Technical Field

[0001] This invention relates to the field of motor drive control technology, and in particular to a control circuit and chip for a stepper motor. Background Technology

[0002] Stepper motors, as control actuators that convert digital pulse signals into angular displacement, are widely used in precision instruments, industrial automation, and smart homes. Traditional stepper motor current control schemes typically generate drive signals by real-time detection of the winding's instantaneous current and comparison with theoretical current values, thereby controlling the increase and decrease of the current in the windings.

[0003] However, during the switching of the transistor in the drive circuit, high-frequency transient current spikes are easily generated. Since the existing control scheme detects the instantaneous winding current in real time, when sampling during the spike-intensive phase, these transient spikes can easily cause the current comparator to malfunction and frequently jump, resulting in distortion of the drive signal. This causes oscillations in the motor winding current waveform, which in turn leads to significant mechanical vibration and noise during motor operation. Summary of the Invention

[0004] The purpose of this invention is to provide a control circuit and chip for a stepper motor, which solves the problem that existing stepper motor control schemes, which detect the instantaneous current of the winding in real time, are susceptible to the influence of current spikes, resulting in significant mechanical vibration and noise during motor operation.

[0005] To solve the above-mentioned technical problems, the present invention provides a control circuit for a stepper motor, comprising: Silent step adjustment unit, sampling unit, drive unit; The first input terminal of the silent step adjustment unit is connected to the output terminal of the sampling unit and is used to receive the actual current value; the second input terminal of the silent step adjustment unit is used to input the theoretical current value; the first output terminal of the silent step adjustment unit is connected to the control terminal of the sampling unit and is used to output a sampling enable signal to the sampling unit at the zero-crossing point within a preset PWM cycle; the second output terminal of the silent step adjustment unit is connected to the input terminal of the drive unit and is used to transmit the drive signal generated based on the difference between the theoretical current value and the actual current value to the drive unit. The input terminal of the sampling unit is connected to the first terminal of the driving unit, and is used to collect the actual current value when the sampling enable signal is received; The second end of the drive unit is connected to a power supply, and the output end of the drive unit is connected to the motor winding. It is used to control the proportion of time that the current in the motor winding is in the conduction phase and the decay phase within the PWM cycle according to the drive signal.

[0006] Optional, also includes: Transimpedance gain circuit; The control terminal of the transimpedance gain circuit is connected to the third output terminal of the mute step adjustment unit, and is used to receive the transimpedance gain enable signal transmitted by the mute step adjustment unit; the output terminal of the transimpedance gain circuit is connected to the third input terminal of the mute step adjustment unit, and is used to sample the actual voltage-current conversion efficiency of the circuit to obtain the transimpedance gain when the transimpedance gain enable signal is received.

[0007] Optionally, the silent step adjustment unit includes: PI control module, control module, comparison module, and drive control module; The first input terminal of the PI adjustment module serves as the first input terminal of the silent step adjustment unit, used to receive the actual current value; the second input terminal of the PI adjustment module serves as the second input terminal of the silent step adjustment unit, used to receive the theoretical current value; the third input terminal of the PI adjustment module serves as the third input terminal of the silent step adjustment unit, used to receive the transimpedance gain; the output terminal of the PI adjustment module is connected to the first input terminal of the comparison module, used to output the PI control quantity to the comparison module; the PI adjustment module is used to calculate the difference between the actual current value and the theoretical current value, correct it according to the transimpedance gain to obtain the accurate current error, and perform proportional-integral operation on the accurate current error to obtain the PI control quantity; the electrical poles of the motor are canceled by configuring the zero points of the proportional gain and integral gain control loop in the proportional-integral operation; The input terminal of the control module is used to receive the mute step enable signal. The sampling enable signal output terminal of the control module serves as the first output terminal of the mute step adjustment unit, and is used to output the sampling enable signal to the sampling unit at the zero-crossing time within a preset PWM cycle. The PWM signal output terminal of the control module is connected to the second input terminal of the comparator module and is used to output the PWM count signal. The transimpedance gain enable signal output terminal of the control module serves as the third output terminal of the mute step adjustment unit and is used to output the transimpedance gain enable signal after the actual current value is acquired. The first and second output terminals of the comparison module are respectively connected to the first and second input terminals of the drive control module, and are used to compare the magnitude of the PI control quantity with the magnitude of the PWM counting signal, and output the first and second control signals according to the comparison result. The output terminal of the drive control module serves as the second output terminal of the silent step adjustment unit, and is used to convert the first control signal and the second control signal into the drive signal and output it to the drive unit.

[0008] Optional, also includes: Theoretical current calculation unit; The first and second input terminals of the theoretical current calculation unit are respectively connected to the step signal generation terminal and the direction signal generation terminal. The output terminal of the theoretical current calculation unit is connected to the second input terminal of the silent step adjustment unit, and is used to obtain the theoretical current value according to the step signal and the direction signal and output it to the silent step adjustment unit.

[0009] Optionally, the transimpedance gain circuit includes: Voltage comparator, resistor network, and transimpedance gain sampling counter; The first input terminal of the transimpedance gain sampling counter is connected to the output terminal of the voltage comparator, and the second input terminal of the transimpedance gain sampling counter serves as the control terminal of the transimpedance gain circuit; the output terminal of the transimpedance gain sampling counter is connected to the first terminal of the resistor network and serves as the output terminal of the transimpedance gain circuit. The second end of the resistor network is connected to the first input terminal of the voltage comparator; The second input terminal of the voltage comparator is connected to a reference voltage source.

[0010] Optionally, the PI adjustment module includes: The module includes a current error calculation module, a calculation module, a frequency division module, and a superposition module. The first and second input terminals of the current error calculation module are respectively used as the first and second input terminals of the PI adjustment module, and the output terminal of the current error calculation module is connected to the first input terminal of the calculation module. The second input terminal of the arithmetic module serves as the third input terminal of the PI adjustment module. The first and second output terminals of the arithmetic module are respectively connected to the first and second input terminals of the frequency divider module, and are used to output the proportional term and integral term to the frequency divider module. The first and second output terminals of the frequency division module are respectively connected to the first and second input terminals of the superposition module, and are used to perform frequency division processing on the integral term and the proportional term according to the preset frequency division coefficient and then output them to the superposition module. The output terminal of the superposition module serves as the output terminal of the PI adjustment module, and is used to superimpose the integral term and the proportional term after frequency division processing as the PI control quantity.

[0011] Optionally, the driving unit includes: Level conversion unit, full-bridge circuit; The input terminal of the level conversion unit serves as the input terminal of the driving unit, and the first, second, third, and fourth output terminals of the level conversion unit are respectively connected to the control terminals of the four switching transistors in the full-bridge circuit. The output terminal of the full-bridge circuit serves as the output terminal of the driving unit; the first terminal of the full-bridge circuit serves as the first terminal of the driving unit; and the second terminal of the full-bridge circuit serves as the second terminal of the driving unit.

[0012] Optionally, the control module includes: State machine, PWM counter, zero-crossing current sampling time counter, transimpedance gain sampling time counter; The input terminal of the state machine serves as the input terminal of the control module. The sampling trigger output terminal of the state machine is connected to the enable terminal of the zero-crossing current sampling time counter. The transimpedance gain sampling trigger output terminal of the state machine is connected to the enable terminal of the transimpedance gain sampling time counter. The PWM signal trigger output terminal of the state machine is connected to the enable terminal of the PWM counter. The output terminal of the zero-crossing current sampling time counter serves as the sampling enable signal output terminal of the control module, used to perform timed counting after the state machine is triggered, and continuously output the sampling enable signal during the counting period; The output of the transimpedance gain sampling time counter serves as the transimpedance gain enable signal output of the control module. It is used to perform transimpedance gain sampling time counting after the state machine is triggered, and to continuously output the transimpedance gain enable signal during the counting period. The clock input terminal of the PWM counter is connected to the system clock signal, and the output terminal of the PWM counter serves as the PWM signal output terminal of the control module, used for periodic cyclic counting and real-time output of the PWM counting signal.

[0013] Optionally, the sampling unit includes: Analog-to-digital converter and sampling resistor; The analog input terminal of the analog-to-digital converter is connected to the first terminal of the sampling resistor and the first terminal of the full-bridge circuit; the control terminal of the analog-to-digital converter serves as the control terminal of the sampling unit; the digital output terminal of the analog-to-digital converter serves as the output terminal of the sampling unit. The second terminal of the sampling resistor is grounded.

[0014] To address the aforementioned problems, the present invention also provides a stepper motor control chip, including the stepper motor control circuit described above.

[0015] This invention provides a control circuit for a stepper motor, including a silent stepping adjustment unit, a sampling unit, and a driving unit. At the zero-crossing point within a preset PWM cycle, the silent stepping adjustment unit transmits a sampling enable signal to the sampling unit via its first output terminal. This enables the sampling unit to collect the actual current value of the motor windings and return it from the first input terminal. The silent stepping adjustment unit calculates the current error by subtracting the theoretical current value received from the second input terminal from the actual current value. Based on this current error, a driving signal is generated. Finally, the driving unit controls the time ratio of the current in the motor windings during the conduction and decay phases within the PWM cycle based on this driving signal. This mechanism no longer relies on real-time detection of the instantaneous winding current. Instead, it uses periodic sampling of the actual current value to determine the time ratio of the current in the motor windings during the conduction and decay phases within the PWM cycle. Furthermore, limiting the sampling time to the zero-crossing window avoids transient noise from switching transistors, effectively reducing the impact of current spikes on the stepper motor control. This reduces mechanical vibration and high-frequency noise during motor operation, achieving silent and smooth motor drive.

[0016] Furthermore, the control chip for the stepper motor provided by this invention has the same effect as above. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a stepper motor control circuit provided by the present invention; Figure 2 This is a schematic diagram of the silent step adjustment unit provided by the present invention; Figure 3 A schematic diagram of angle counting provided for this invention; Figure 4 A schematic diagram of a transimpedance gain circuit provided by the present invention; Figure 5 A schematic diagram of the PI control module provided by the present invention; Figure 6 This is a schematic diagram of the control module provided by the present invention. Detailed Implementation

[0019] The core of this invention is to provide a control circuit and chip for a stepper motor.

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Stepper motors, as control actuators that convert digital pulse signals into angular displacement, are widely used in precision instruments, industrial automation, and smart homes. Traditional stepper motor current control schemes typically generate drive signals by real-time detection of the winding's instantaneous current and comparison with the theoretical current value CUR_TARGE, in order to control the increase and decrease of the current in the winding.

[0022] However, during the switching of the transistor in the drive circuit, high-frequency transient current spikes are easily generated. Since the existing control scheme detects the instantaneous winding current in real time, when sampling during the spike-intensive phase, these transient spikes can easily cause the current comparator to malfunction and frequently jump, resulting in distortion of the drive signal. This causes oscillations in the motor winding current waveform, which in turn leads to significant mechanical vibration and noise during motor operation.

[0023] To address the aforementioned technical problems, this invention provides a control circuit for a stepper motor.

[0024] For details, please see Figure 1 , Figure 1 This is a schematic diagram of a stepper motor control circuit provided by the present invention.

[0025] like Figure 1 As shown, the control circuit includes: Silent step adjustment unit, sampling unit, drive unit; The first input terminal of the silent step adjustment unit is connected to the output terminal of the sampling unit to receive the actual current value CUR_ACTUAL; the second input terminal of the silent step adjustment unit is used to input the theoretical current value CUR_TARGE; the first output terminal of the silent step adjustment unit is connected to the control terminal of the sampling unit to output a sampling enable signal to the sampling unit at the zero-crossing point within a preset PWM cycle; the second output terminal of the silent step adjustment unit is connected to the input terminal of the drive unit to transmit the drive signal generated based on the difference between the theoretical current value CUR_TARGE and the actual current value CUR_ACTUAL to the drive unit. The input terminal of the sampling unit is connected to the first terminal of the driving unit and is used to acquire the actual current value CUR_ACTUAL when a sampling enable signal is received; The second end of the drive unit is connected to the power supply, and the output end of the drive unit is connected to the motor winding. It is used to control the proportion of time that the current in the motor winding is in the conduction stage and the decay stage within the PWM cycle according to the drive signal.

[0026] Specifically, the silent stepping adjustment unit is the core calculation and scheduling part of the control circuit. It outputs a sampling enable signal to the sampling unit at the zero-crossing point within the preset PWM cycle. The sampling time is set at the zero-crossing point because the transients caused by switching near the zero-crossing point have stabilized. At this point, the actual current value CUR_ACTUAL obtained by sampling is more accurate, effectively avoiding periods of dense transient current spikes. In practical applications, the zero-crossing point is the moment when both power transistors in the full-bridge circuit of the drive unit are simultaneously turned on. After acquiring the actual current value CUR_ACTUAL, the silent stepping adjustment unit transmits a drive signal generated based on the difference between the theoretical current value CUR_TARGE and the actual current value CUR_ACTUAL to the drive unit. This signal controls whether the current in the motor windings is in the conduction or decay phase. Specifically, it controls the on and off states of each switch in the full-bridge circuit, thereby achieving the switching of the operating mode. As an example, the silent stepper adjustment unit includes a PI adjustment module, a control module, a comparison module, and a drive control module. The control module is responsible for generating timing signals, locking the sampling time at the zero-crossing point, and outputting a PWM counting signal in real time. The PI adjustment module is used to perform proportional-integral calculation on the difference between the theoretical current value CUR_TARGE and the actual current value CUR_ACTUAL to obtain the PI control quantity CUR_PI. The comparison module compares the PI control quantity CUR_PI with the PWM counting signal and outputs a first control signal S1 and a second control signal S2. The drive control module converts these two control signals into drive signals and sends them to the drive unit.

[0027] Specifically, the drive unit is the power execution section of the control circuit. Based on the drive signal from the silent stepper adjustment unit, it controls the proportion of time the motor winding current is in the conduction and decay phases within the PWM cycle. During the conduction phase, the current value in the motor winding increases; during the decay phase, the current value decreases. By controlling the proportion of time the motor winding current is in the conduction and decay phases within the PWM cycle, the actual current value CUR_ACTUAL can follow the theoretical current value CUR_TARGE. As an example, the drive unit consists of a level conversion unit and a full-bridge circuit. The full-bridge circuit contains four switching transistors. The input terminal of the level conversion unit serves as the input terminal of the drive unit to receive the drive signal. Its first, second, third, and fourth output terminals are respectively connected to the control terminals of the four switching transistors in the full-bridge circuit. These terminals convert the low-voltage drive signal from the preceding stage into gate control levels suitable for each switching transistor, thereby driving the corresponding switching transistors to turn on and off according to a preset timing sequence to adjust the magnitude of the winding current. By having an independent drive unit handle the on / off switching of the bridge arm switches, the silent stepping adjustment unit can output only drive signals representing the duty cycle or bridge arm status, without having to directly process the power switches. It should be noted that the time ratio of the winding current's on-phase and decay phases determined by the drive signal takes effect before the next update, forming a cycle-refreshed digital closed loop.

[0028] Specifically, the sampling unit is responsible for obtaining the actual feedback of the motor winding current from the drive unit. Its input is connected to the first terminal of the drive unit, i.e., the current sampling output terminal, and it performs sampling when it receives the sampling enable signal from the silent stepping adjustment unit. As an example, the sampling unit consists of an analog-to-digital converter and a sampling resistor. The sampling resistor is connected in series in the low-side path of the full-bridge circuit to convert the current flowing through the motor winding into a voltage signal. The analog input terminal of the analog-to-digital converter is connected to the first terminal of the sampling resistor. Its control terminal serves as the control terminal of the sampling unit to receive the sampling enable signal, and its digital output terminal serves as the output terminal of the sampling unit to convert the voltage signal across the sampling resistor into a digital form of the actual current value CUR_ACTUAL and output it during the valid period of the sampling enable signal.

[0029] During operation, the control circuit runs in a cycle according to each PWM cycle: First, the silent stepping adjustment unit sends a sampling enable signal to the sampling unit at the moment when the winding current crosses zero; the sampling unit collects the actual current value CUR_ACTUAL based on this signal and sends it back to the silent stepping adjustment unit; the silent stepping adjustment unit calculates the difference between the received actual current value CUR_ACTUAL and the theoretical current value CUR_TARGE to obtain the current error, and generates a corresponding drive signal based on this error and transmits it to the input terminal of the drive unit; the drive unit adjusts the state of its bridge arm in the next PWM cycle according to the drive signal, thereby adjusting the magnitude and direction of the winding current.

[0030] As can be seen, this invention no longer relies on the control mode of real-time detection of the instantaneous winding current. Instead, it uses periodic sampling of the actual current value CUR_ACTUAL to determine the time ratio of the conduction phase and decay phase of the winding current within the PWM cycle. Furthermore, the sampling timing is limited to the zero-crossing window, avoiding the transient noise of the switching transistor. This effectively reduces the impact of current spikes on the stepper motor control, thereby reducing mechanical vibration and high-frequency noise during motor operation and achieving quiet and smooth motor drive.

[0031] Based on the above embodiments: As an optional embodiment, it also includes: Transimpedance gain circuit; The control terminal of the transimpedance gain circuit is connected to the third output terminal of the mute step adjustment unit to receive the transimpedance gain KV_DAC enable signal transmitted by the mute step adjustment unit; the output terminal of the transimpedance gain circuit is connected to the third input terminal of the mute step adjustment unit to sample the actual voltage-current conversion rate of the circuit when the transimpedance gain KV_DAC enable signal is received to obtain the transimpedance gain KV_DAC.

[0032] Specifically, during the actual construction and operation of the circuit, parasitic effects of the components, such as parasitic resistance on the wires, can cause the physical conversion rate of current to voltage within the chip to deviate from the ideal design value. If uncalibrated sampled values ​​are used directly for control, it will lead to input error distortion in the control loop, thereby reducing the accuracy of current regulation. Therefore, a transimpedance gain circuit is further incorporated into the circuit to dynamically and in real-time correct the actual voltage-to-current conversion rate. When the mute step adjustment unit outputs a transimpedance gain KV_DAC enable signal to the transimpedance gain circuit according to a preset control timing sequence, the transimpedance gain circuit is triggered and initiates the sampling calibration process. The transimpedance gain circuit physically samples and compares the current actual voltage-to-current conversion rate within the circuit to obtain the transimpedance gain KV_DAC, which reflects the true conversion characteristics, and feeds it back to the mute step adjustment unit. After acquiring the transimpedance gain KV_DAC, the silent step adjustment unit performs a correction calculation on the original difference between the theoretical current value CUR_TARGE and the actual current value CUR_ACTUAL to obtain the accurate calibrated true current error, and sends this precisely quantified current error into the subsequent control loop for closed-loop adjustment.

[0033] As can be seen, this embodiment effectively improves the accuracy of current control by setting up a transimpedance gain circuit to dynamically acquire real-time voltage-current conversion rate in order to correct the deviation between the actual current value CUR_ACTUAL and the theoretical current value CUR_TARGE.

[0034] Please see Figure 2 , Figure 2 This is a schematic diagram of the silent step adjustment unit provided by the present invention.

[0035] As an optional embodiment, such as Figure 2 As shown, the silent step adjustment unit includes: PI control module, control module, comparison module, and drive control module; The first input terminal of the PI control module serves as the first input terminal of the silent stepping control unit, used to receive the actual current value CUR_ACTUAL; the second input terminal of the PI control module serves as the second input terminal of the silent stepping control unit, used to receive the theoretical current value CUR_TARGE; the third input terminal of the PI control module serves as the third input terminal of the silent stepping control unit, used to receive the transimpedance gain KV_DAC; the output terminal of the PI control module is connected to the first input terminal of the comparator module, used to output the PI control quantity CUR_PI to the comparator module; the PI control module is used to calculate the difference between the actual current value CUR_ACTUAL and the theoretical current value CUR_TARGE, correct it according to the transimpedance gain KV_DAC to obtain the accurate current error, and perform proportional-integral operation on the accurate current error to obtain the PI control quantity CUR_PI; the electrical poles of the motor are canceled by configuring the zero point of the control loop of the proportional gain KP and integral gain KI in the proportional-integral operation.

[0036] The input terminal of the control module is used to receive the mute step enable signal. The sampling enable signal output terminal of the control module serves as the first output terminal of the mute step adjustment unit, which is used to output the sampling enable signal to the sampling unit at the zero-crossing point within the preset PWM cycle. The PWM signal output terminal of the control module is connected to the second input terminal of the comparator module and is used to output the PWM count signal. The transimpedance gain KV_DAC enable signal output terminal of the control module serves as the third output terminal of the mute step adjustment unit, which is used to output the transimpedance gain KV_DAC enable signal after acquiring the actual current value CUR_ACTUAL. The first and second output terminals of the comparison module are respectively connected to the first and second input terminals of the drive control module, and are used to compare the magnitude of the PI control quantity CUR_PI with the PWM counting signal, and output the first control signal S1 and the second control signal S2 according to the comparison result. The output terminal of the drive control module serves as the second output terminal of the silent step adjustment unit, used to convert the first control signal S1 and the second control signal S2 into drive signals and output them to the drive unit.

[0037] Specifically, the PI control module calculates the difference between the actual current value CUR_ACTUAL and the theoretical current value CUR_TARGE, and corrects it based on the transimpedance gain KV_DAC to obtain a precise current error. This precise current error is then subjected to proportional and integral calculations to generate the PI control quantity CUR_PI. In this module, by configuring the proportional gain KP and integral gain KI in the proportional-integral operation to cancel the electrical poles of the motor at the zero point of the control loop, the influence of the electrical poles caused by the inherent resistance and inductance of the motor is eliminated, significantly improving the dynamic response performance and stability of the loop.

[0038] Specifically, to eliminate electrical poles caused by motor resistance and inductance by controlling the zero point of the control loop, the proportional gain KP and integral gain KI parameters can be adjusted to adapt to the motor, thereby achieving the most effective control loop. The specific calculation process for the proportional gain KP and integral gain KI is as follows: Electrical cutoff frequency of the motor FP for: ; Where R is the motor resistance and L is the motor inductance. This cutoff frequency determines the system's response rate to changes in the motor's electrical circuit.

[0039] Silent stepping PWM switching frequency FZ for: ; Where KI is the integral gain, KP is the proportional gain, and FPWM is the PWM generator frequency.

[0040] To adapt to the motor, the KP setting formula is: ; Where FC is the unity-gain bandwidth of the PI control loop, L is the motor inductance, VM is the power supply voltage, and n is a parameter related to the chip package. FC is generally set in the low to mid-frequency range, such as around 200Hz. The low to mid-frequency range is the optimal setting for a trade-off between response speed and system stability. Although this setting sacrifices some response speed, it greatly improves noise immunity. At the same time, the phase lag caused by digital delay is small at this frequency, ensuring that the system has sufficient phase margin and reducing dependence on parameters. Even with a parameter error of about 15%, the system can still operate stably, improving system stability. However, if FC is set too high, although the response speed is fast, it may not only cause glitches in the current ripple, leading to motor overheating and high-frequency noise, but may also cause system instability because the phase lag exceeds the phase safety margin.

[0041] Because zeros are needed to cancel out poles, according to FP=FZ: ; Solving for: ; The resulting proportional gain KP and integral gain KI offset the electrical pole effects caused by the inherent resistance and inductance of the motor, thereby improving the dynamic response performance and stability of the loop.

[0042] Specifically, the comparison module is configured to implement PWM modulation. It receives the PI control quantity CUR_PI and the PWM count signal PWM_CNT, compares the magnitudes of the PI control quantity CUR_PI and the PWM count signal PWM_CNT, and outputs a first control signal S1 and a second control signal S2 via its first output terminal and second output terminal respectively according to the comparison result. The comparison rule is: if CUR_PI is a positive number, when 0<=PWM_CNT<CUR_PI, the control signal S1 of half-bridge 1 is 1, otherwise S1 is 0. When -2 n +PWM_CNT MAX +CUR_PI < PWM_CNT < PWM_CNT MAX , the control signal S2 of half-bridge 2 is 1, otherwise S2 is 0, where n is the number of bits of PWM_CNT. If CUR_PI is a negative number, when PWM_CNT<CUR_PI or PWM_CNT>=0, the control signal S1 of half-bridge 1 is 1, otherwise S1 is 0. When 2 n -PWM_CNT MAX +CUR_PI < PWM_CNT < PWM_CNT MAX , the control signal S2 of half-bridge 2 is 1, otherwise S2 is 0, where n is the number of bits of PWM_CNT, and PWM_CNT MAX is the maximum value of the PWM count signal.

[0043] In addition, the comparison module also receives a sampling enable signal, and controls the first control signal S1 and the second control signal S2 to remain at a high level during the period when the sampling enable signal is active.

[0044] Specifically, the drive control module converts the comparison result into drive signals that can be executed by the power stage. It receives a first control signal S1 and a second control signal S2, converts these two control signals into drive signals, and outputs them to the drive unit, thereby controlling the time ratio of the winding current's conduction and decay phases in the next PWM cycle. The drive signals include four signals: the upper MOSFET control signal HA1_H for half-bridge 1, the lower MOSFET control signal HA1_L for half-bridge 1, the upper MOSFET control signal HA2_H for half-bridge 2, and the lower MOSFET control signal HA2_L for half-bridge 2. The specific conversion rules are: the upper MOSFET control signal HA1_H for half-bridge 1 = S1, and the lower MOSFET control signal HA1_L for half-bridge 1 = !S1 (S1 inverted). The upper MOSFET control signal HA2_H for half-bridge 2 = S2, and the lower MOSFET control signal HA2_L for half-bridge 2 = !S2 (S2 inverted). If HA1_H=1, HA1_L=0, HA2_H=0, and HA2_L=1, the current in the motor windings is in the forward conduction stage, causing the motor winding current to increase in the positive direction. If HA1_H=0, HA1_L=1, HA2_H=1, and HA2_L=0, the current in the motor windings is in the reverse conduction stage, causing the motor winding current to increase in the reverse direction. If HA1_H=1, HA1_L=0, HA2_H=1, and HA2_L=0, the current in the motor windings is in the forward decay stage, causing the motor winding current to decrease in the positive direction. If HA1_H=0, HA1_L=1, HA2_H=0, and HA2_L=1, the current in the motor windings is in the reverse decay stage, causing the motor winding current to decrease in the reverse direction.

[0045] Specifically, the control module, as the core of timing control and signal generation within the silent stepper motor adjustment unit, receives silent stepper enable signals from external sources or a host computer at its input terminals, and initiates the operation control of the stepper motor. Please refer to Table 1, which is the state control timing diagram of the control module.

[0046] Table 1

[0047] As shown in Table 1, the control module uses an internal state machine to uniformly schedule the working timing. Within one PWM cycle: upon receiving the mute step enable signal, the state machine transitions from state 0 to state 1, and the PWM counter begins periodic counting; at the zero-crossing point, i.e., when both half-bridge 1 control signal S1 and half-bridge 2 control signal S2 in the full-bridge circuit are high, the state machine enters state 2, where the zero-crossing current sampling time counter generates and maintains the sampling enable signal to acquire the actual current value CUR_ACTUAL. While acquiring the actual current value CUR_ACTUAL, the half-bridge 1 control signal S1 and half-bridge 2 control signal S2 remain high; after the actual current value CUR_ACTUAL acquisition is completed, the state machine enters state 3, where the transimpedance gain sampling time counter... The transimpedance gain KV_DAC enable signal is generated and maintained. The transimpedance gain circuit samples and calibrates the actual current-to-voltage conversion rate of the circuit to obtain the transimpedance gain KV_DAC. After obtaining the transimpedance gain KV_DAC, the state machine sequentially enters states 4, 5, and 6 to complete the three-stage operation of the PI adjustment module and obtain the PI control quantity CUR_PI. The comparison module compares the PI control quantity CUR_PI with the magnitude of the PWM counting signal, and outputs the first control signal S1 and the second control signal S2 through its first and second output terminals respectively according to the comparison result. Then, the drive control module converts them into drive signals for output. The state machine enters state 7 and remains there until the PWM counter reaches its maximum value. Then, the control module automatically resets and jumps back to state 1, realizing closed-loop synchronization of periodic refresh.

[0048] As can be seen, this embodiment uses a PI adjustment module to correct errors with the transimpedance gain KV_DAC and perform proportional-integral calculations, thereby ensuring fast current response while also providing sufficient phase margin and noise immunity. At the same time, the control module uniformly schedules zero-crossing sampling and transimpedance gain KV_DAC enabling, and the comparison module compares the PI control quantity CUR_PI with the PWM counting signal and generates a drive signal through the drive control module, thus achieving precise and stable silent step control.

[0049] Optional, also includes: Theoretical current calculation unit; The first and second input terminals of the theoretical current calculation unit are connected to the step signal generation terminal and the direction signal generation terminal, respectively. The output terminal of the theoretical current calculation unit is connected to the second input terminal of the silent step adjustment unit, which is used to obtain the theoretical current value CUR_TARGE based on the step signal and the direction signal and output it to the silent step adjustment unit.

[0050] Please see Figure 3 , Figure 3 A schematic diagram of angle counting provided by the present invention.

[0051] Specifically, the theoretical current calculation unit determines the current phase based on the step signal and direction signal, and then obtains and outputs the corresponding theoretical current value CUR_TARGE. The step signal is an externally input PWM signal. During operation, the theoretical current calculation unit generates the theoretical current value CUR_TARGE based on the externally input PWM step signal and direction signal. Figure 3 As shown, the direction signal determines the direction of increase or decrease of the angle count value ANGLE_CNT: when the direction signal is 0, the angle count value ANGLE_CNT increases by one microstep resolution n at the rising edge of each PWM step signal; when the direction signal is 1, the angle count value ANGLE_CNT decreases by one microstep resolution n at the rising edge of each PWM step signal. Here, the microstep resolution n represents the number of microsteps subdivided in each step, and its value is generally set by a register; the angle count value ANGLE_CNT typically ranges from 0 to 1023, corresponding to a motor angle of 0° to 360° (for example, 1023 represents a motor angle of 360°). After obtaining the angle count value ANGLE_CNT, the theoretical current calculation unit looks up the microstep sine table using a lookup table method to obtain the corresponding theoretical current curve. Thus, the theoretical current calculation unit can obtain the theoretical voltage representing the theoretical current in real time based on the externally input pulse width modulation signal and direction signal, and output it to the silent step adjustment unit as the target reference for subsequent proportional-integral adjustment.

[0052] As can be seen, this embodiment can automatically generate a target value representing the theoretical current by using the theoretical current calculation unit based on the externally input stepping signal and direction signal, and by using angle counting and microstep sine table lookup, thus achieving precise control of the stepper motor.

[0053] For details, please see Figure 4 , Figure 4 This is a schematic diagram of a transimpedance gain circuit provided by the present invention.

[0054] As an optional embodiment, the transimpedance gain circuit includes: Voltage comparator, resistor network, and transimpedance gain sampling counter; The first input terminal of the transimpedance gain sampling counter is connected to the output terminal of the voltage comparator, and the second input terminal of the transimpedance gain sampling counter serves as the control terminal of the transimpedance gain circuit; the output terminal of the transimpedance gain sampling counter is connected to the first terminal of the resistor network and serves as the output terminal of the transimpedance gain circuit. The second end of the resistor network is connected to the first input of the voltage comparator; The second input of the voltage comparator is connected to a reference voltage source.

[0055] Specifically, since the sampling unit converts analog voltage signals into digital signals through its internal resistor network, and this resistor network is affected by device tolerances and parasitic effects, its actual voltage-to-current conversion rate may deviate from the ideal value. Directly using the ideal conversion rate in calculations will lead to inaccurate current errors. To address this, a transimpedance gain circuit is set up, and the resistor network in the transimpedance gain circuit uses the same set or the same parameters as the resistor network in the sampling unit. Since the conversion rate deviation of the same resistor network is consistent and correlated, by acquiring the actual conversion rate of its own resistor network through the transimpedance gain circuit, the actual voltage-to-current conversion rate of the sampling unit can be obtained equivalently. This can then be used to correct the current error and calibrate the gain deviation of the sampling link.

[0056] During operation, when the transimpedance gain KV_DAC enable signal is valid, the transimpedance gain sampling counter uses the intermediate value as the initial zero reference. For example, when the transimpedance gain KV_DAC is 9-bit data, it starts outputting with 256 as the initial zero reference value. This digital quantity is converted into a voltage signal VKV after being divided by a resistor network and applied to the first input terminal of the voltage comparator. It is compared with the reference voltage VREF of the reference voltage source connected to the second input terminal of the voltage comparator. If the comparator output KV_COMP is low, it means that the voltage at the first input terminal of the comparator is lower than the reference voltage. At this time, the transimpedance gain sampling counter continuously increases the output digital quantity, causing the voltage obtained by the resistor network to gradually increase until the comparator output flips to a high level and the counter stops changing. Conversely, if the comparator output is high, it means that the voltage at the first input terminal of the comparator is higher than the reference voltage. The transimpedance gain sampling counter continuously decreases the output digital quantity, causing the divided voltage to gradually decrease until the comparator output flips to a low level and the counter stops changing. Finally, the final transimpedance gain KV_DAC corresponding to the reference voltage is obtained. This transimpedance gain KV_DAC is output to the mute step adjustment unit through the output terminal of the transimpedance gain circuit. It is used to correct the difference between the actual current value CUR_ACTUAL and the theoretical current value CUR_TARGE. The correction formula is as follows: ; in, ΔE To accurately measure current error, CUR_TARGE The theoretical current value is CUR_TARGE. CUR_ACTUAL The actual current value is CUR_ACTUAL. KV_DAC KV_DAC is the transimpedance gain.

[0057] As can be seen, this embodiment uses a voltage comparator, a resistor network, and a transimpedance gain sampling counter to form a hardware closed loop. When the transimpedance gain KV_DAC is enabled, it autonomously completes the sampling and calibration of the actual current-voltage conversion rate. The structure is simple and easy to integrate.

[0058] Please see Figure 5 , Figure 5 This is a schematic diagram of the PI adjustment module provided by the present invention.

[0059] As an optional embodiment, such as Figure 5 As shown, the PI control module includes: The module includes a current error calculation module, a calculation module, a frequency division module, and a superposition module. The first and second input terminals of the current error calculation module are respectively used as the first and second input terminals of the PI adjustment module, and the output terminal of the current error calculation module is connected to the first input terminal of the arithmetic module. The second input terminal of the arithmetic module serves as the third input terminal of the PI adjustment module. The first and second output terminals of the arithmetic module are respectively connected to the first and second input terminals of the frequency divider module, and are used to output the proportional term and integral term to the frequency divider module. The first and second output terminals of the frequency division module are respectively connected to the first and second input terminals of the superposition module, and are used to perform frequency division processing on the integral term and the proportional term according to the preset frequency division coefficient and then output them to the superposition module. The output of the superposition module serves as the output of the PI control module, used to superimpose the integral and proportional terms after frequency division processing as the PI control quantity CUR_PI.

[0060] Specifically, the current error calculation module receives the actual current value CUR_ACTUAL and the theoretical current value CUR_TARGE at its two input terminals, respectively, to calculate the difference between them, CUR_ERR, and then sends the obtained difference CUR_ERR to the next stage. As an example, the current error calculation module can be implemented by a digital subtractor. The subtractor's IN1 terminal receives the theoretical current value CUR_TARGE, its IN2 terminal receives the actual current value CUR_ACTUAL, its IN3 terminal receives the operating clock CLK to control the calculation cycle, and its IN4 terminal receives the reset signal RST to clear the module state and initialize the difference calculation upon initial power-up or when needed.

[0061] Specifically, the first input terminal of the arithmetic module receives the aforementioned difference, and its second input terminal receives the transimpedance gain KV_DAC. This transimpedance gain KV_DAC is used to correct the difference to obtain the accurate current error, and a proportional-integral operation is performed on the accurate current error. The proportional term and integral term are output through its first and second output terminals, respectively. As an example, the arithmetic module can consist of a multiplier / divider and a first adder. The IN2 terminal of the multiplier / divider receives the difference value CUR_ERR; the IN3 terminal receives the transimpedance gain KV_DAC, which is corrected to obtain the accurate current error ΔE and then input to the IN1 terminal; the IN4 terminal receives the state machine state 4 enable STATE_4, which controls the multiplier / divider to perform proportional term calculations; the IN5 terminal receives the preset proportional gain KP, which is multiplied by the accurate current error ΔE to obtain the proportional term CUR_P; the IN6 terminal receives the state machine state 5 enable STATE_5, which controls the multiplier / divider to perform integral term calculations; the IN7 terminal receives the preset integral gain KI, which is multiplied by the accurate current error ΔE to obtain the integral increment CUR_KI. The IN1 terminal of the first adder receives the integration result of the previous cycle as the accumulated historical integration value, enabling the integration term to have memory capability; the IN2 terminal of the first adder receives the integration increment CUR_KI, which is added to the integration result of the previous cycle to obtain the new integration term CUR_I; the IN3 terminal of the first adder receives the operating clock CLK; and the IN4 terminal of the first adder receives the reset signal RST, which is used to clear the initial integration value.

[0062] Specifically, the frequency divider module provides accurate proportional gain (KP) and integral gain (KI) values. The theoretical KP and KI values ​​calculated using the aforementioned formulas typically contain decimal parts. However, the KP and KI registers within the PI control module, used to store the gains, are integer registers and cannot be directly written with fractions. Directly truncating the integer values ​​would introduce significant errors, thus affecting the control performance. Therefore, the KP and KI registers are used to store integer values, while registers KP_DIV and KI_DIV store the division coefficients of the proportional gain and integral gain, respectively, to output accurate proportional gain (KP) and integral gain (KI) values.

[0063] As an example, the frequency divider module includes a first frequency divider circuit and a second frequency divider circuit, which can divide the proportional term CUR_P and the integral term CUR_I respectively. For example, the proportional term CUR_P is divided to obtain CUR_P_S, and the division coefficient is determined by the register KP_DIV. Please refer to Table 2, which is the frequency division calculation table provided by this invention.

[0064] Table 2

[0065] For example, if KP=2.09, set register KP_DIV=011 and set KP register=67, then 67÷32≈2.09; if KI=0.0252, set register KI_DIV=111 and set KI register=13, then 13÷512≈0.0252.

[0066] Specifically, the superposition module adds the proportional term and integral term after frequency division, and its output is used as the output of the PI control module to output the final PI control quantity CUR_PI. As an example, the superposition module is implemented by a second adder. The IN1 terminal of the second adder is input to the proportional term CUR_P_S after frequency division; the IN2 terminal of the second adder is input to the integral term CUR_I_S after frequency division; the IN3 terminal of the second adder is connected to state machine state 6, enabling STATE_6, which is used to start superposition after both the proportional and integral terms have been calculated; the IN4 terminal of the second adder is input to the working clock CLK; and the IN5 terminal of the second adder is input to the reset signal RST.

[0067] As an optional embodiment, the driving unit includes: Level conversion unit, full-bridge circuit; The input terminal of the level conversion unit serves as the input terminal of the driver unit, and the first, second, third, and fourth output terminals of the level conversion unit are respectively connected to the control terminals of the four switching transistors in the full-bridge circuit. The output terminal of the full-bridge circuit serves as the output terminal of the driving unit; the first terminal of the full-bridge circuit serves as the first terminal of the driving unit; and the second terminal of the full-bridge circuit serves as the second terminal of the driving unit.

[0068] Specifically, the level conversion unit receives the drive signal, which consists of four logic control signals: the control signal HA1_H for the upper half-bridge 1 transistor, the control signal HA1_L for the lower half-bridge 1 transistor, the control signal HA2_H for the upper half-bridge 2 transistor, and the control signal HA2_L for the lower half-bridge 2 transistor. Different level combinations of these four signals correspond to four winding current states: forward conduction, reverse conduction, forward decay, and reverse decay. These states are used to determine the time proportion of the motor winding current in the conduction and decay phases within the next PWM cycle. After the drive signal is sent to the level conversion unit of the drive unit, it is converted into four actual gate drive signals: the first high-side output HOUT1, the second high-side output HOUT2, the first low-side output LOUT1, and the second low-side output LOUT2. The four output terminals are respectively connected to the control terminals of the four switching transistors in the full-bridge circuit.

[0069] Specifically, the full-bridge circuit includes a full-bridge power stage circuit composed of the upper half-bridge transistor 1, the lower half-bridge transistor 1, the upper half-bridge transistor 2, and the lower half-bridge transistor 2. It receives the gate drive signal output by the level conversion unit and then controls the conduction and turn-off of the four switching transistors.

[0070] As can be seen, this embodiment achieves matching drive between low-voltage control logic and high-voltage power stage through level conversion unit, ensuring rapid turn-on and turn-off of the switching transistors in the full-bridge circuit.

[0071] Please see Figure 6 , Figure 6 This is a schematic diagram of the control module provided by the present invention.

[0072] As an optional embodiment, such as Figure 6 As shown, the control module includes: State machine, PWM counter, zero-crossing current sampling time counter, transimpedance gain sampling time counter; The input terminal of the state machine serves as the input terminal of the control module. The sampling trigger output terminal of the state machine is connected to the enable terminal of the zero-crossing current sampling time counter. The transimpedance gain KV_DAC sampling trigger output terminal of the state machine is connected to the enable terminal of the transimpedance gain sampling time counter. The PWM signal trigger output terminal of the state machine is connected to the enable terminal of the PWM counter. The output of the zero-crossing current sampling time counter is used as the sampling enable signal output of the control module. It is used to perform timed counting after the state machine is triggered and to continuously output the sampling enable signal during the counting period. The output of the transimpedance gain sampling time counter is used as the transimpedance gain KV_DAC enable signal output of the control module. It is used to perform transimpedance gain KV_DAC sampling timing count after the state machine is triggered, and continuously output the transimpedance gain KV_DAC enable signal during the counting period. The clock input of the PWM counter is connected to the system clock signal, and the output of the PWM counter serves as the PWM signal output of the control module, used for periodic counting and real-time output of the PWM count signal.

[0073] Specifically, the state machine is the scheduling core of the control module. The IN1 terminal of the state machine receives the feedback signal PWM_CNT_OVER from the PWM counter, indicating that the PWM count has reached its maximum value for the current cycle, thus triggering a transition from state 7 to state 1. The IN2 terminal of the state machine receives the mute step enable signal SILENT_EN, serving as the start signal for the entire regulation unit. The IN3 terminal of the state machine receives the first control signal S1, and the IN4 terminal receives the second control signal S2, receiving feedback on the current bridge arm state from the drive unit, used for the first control signal S1... When both control signals S1 and S2 are high, the actual current value CUR_ACTUAL is sampled; the working clock CLK is input to the IN5 terminal of the state machine; the reset signal RST is input to the IN6 terminal of the state machine, which is used to clear the state machine to return to the initial state upon initial power-up or when needed; KV_EN is input to the IN7 terminal of the state machine, which is fed back by the KV sampling time counter to indicate whether the transimpedance gain KV_DAC sampling is complete; CUR_EN is input to the IN8 terminal of the state machine, which is fed back by the zero-crossing current sampling time counter to indicate whether the zero-crossing current sampling is complete. The state machine outputs STATE_1 at OUT1 to trigger the PWM counter to start its cyclic counting; that is, OUT1 acts as the PWM signal trigger output. When both the first control signal S1 and the second control signal S2 are high, the state machine outputs STATE_2 at OUT2, acting as the sampling trigger output to trigger the zero-crossing current sampling time counter. After the zero-crossing current sampling time counter finishes counting, the state machine outputs STATE_3 at OUT3, acting as the transimpedance gain KV_DAC sampling trigger output to trigger the transimpedance gain sampling time counter. After the transimpedance gain sampling time counter finishes counting, the state machine outputs STATE_4 at OUT4 to trigger the proportional term calculation of the PI control module, STATE_5 at OUT5 to trigger the integral term calculation of the PI control module, and STATE_6 at OUT6 to trigger the superposition operation of the PI control module. These three outputs enable the three-stage operation of the PI control module. After the PI control module finishes its operation, it waits for the PWM count to reach its maximum value before starting the next cycle.

[0074] Specifically, the IN1 pin of the PWM counter receives STATE_1, the start signal from the state machine; the IN2 pin receives PWM_FREQ, used to configure the PWM period length; the IN3 pin receives the operating clock CLK; and the IN4 pin receives the reset signal RST, used to clear and initialize the PWM counter. The OUT1 pin of the PWM counter outputs PWM_CNT_OVER, which is fed back to the IN1 pin of the state machine as a flag indicating that the PWM period has reached its maximum value. The OUT2 pin outputs PWM_CNT, which serves as the PWM count signal and is sent in real-time to the comparator module for comparison with the PI control quantity CUR_PI.

[0075] Specifically, the IN1 pin of the zero-crossing current sampling time counter receives STATE_2, a trigger signal from the state machine, used to start the counter at the zero-crossing point; the IN2 pin receives SAMP_TIME, used to configure the duration of zero-crossing current sampling; the IN3 pin receives the operating clock CLK; and the IN4 pin receives the reset signal RST, used to clear the initial timing value. The OUT pin of the zero-crossing current sampling time counter outputs CUR_EN, which remains high during the timing count, serving as a sampling enable signal sent to the sampling unit and simultaneously fed back to the IN8 pin of the state machine. The zero-crossing sampling time is set to a certain period because there is a phase shift between the actual current and the theoretical current, and the zero-crossing current is very small, so sufficient time is needed to sample the zero-crossing current to ensure that the sampled zero-crossing current is stable and reliable.

[0076] Specifically, the IN1 terminal of the transimpedance gain sampling time counter receives the trigger signal STATE_3 from the state machine, which is used to start the counter after the zero-crossing current sampling is completed; the IN2 terminal of the transimpedance gain sampling time counter receives the operating clock CLK; and the IN3 terminal of the transimpedance gain sampling time counter receives the reset signal RST. The OUT terminal of the transimpedance gain sampling time counter outputs KV_EN, which remains high during the timing count and is sent to the transimpedance gain circuit as the transimpedance gain KV_DAC enable signal, while also being fed back to the IN7 terminal of the state machine.

[0077] As can be seen, the unified scheduling of the state machine in this embodiment provides a reliable timing basis for the low noise and stable operation of the entire control loop.

[0078] As an optional embodiment, the sampling unit includes: Analog-to-digital converter and sampling resistor; The analog input terminal of the analog-to-digital converter is connected to the first terminal of the sampling resistor and the first terminal of the full-bridge circuit; the control terminal of the analog-to-digital converter serves as the control terminal of the sampling unit; the digital output terminal of the analog-to-digital converter serves as the output terminal of the sampling unit. The second terminal of the sampling resistor is grounded.

[0079] To address the aforementioned problems, the present invention also provides a stepper motor control chip, including the stepper motor control circuit described above.

[0080] Specifically, a sampling resistor is connected in series in the return path of the winding current. All the winding current flows through the sampling resistor and generates a sampling voltage VSENSE proportional to the current. The analog input terminal of the analog-to-digital converter is connected to the first end of the sampling resistor to acquire the sampling voltage VSENSE. Its control terminal serves as the control terminal of the sampling unit, receiving the sampling enable signal output by the control module. The analog-to-digital conversion is initiated only once within the zero-crossing sampling time window, thereby avoiding the current spikes and vibrations generated during the switching of the transistor. The converted digital quantity is sent to the silent step adjustment unit as the output of the sampling unit via the digital output terminal. The difference between this output and the theoretical current value CUR_TARGE is used to participate in subsequent proportional-integral calculations, achieving high-precision closed-loop regulation of the winding current.

[0081] As can be seen, this implementation achieves the sampling of the actual current value CUR_ACTUAL through an analog-to-digital converter and a sampling resistor, which has a simple structure and stable sampling.

[0082] For an introduction to the stepper motor control chip provided by this invention, please refer to the embodiments of the stepper motor control circuit; this invention will not be described in detail here.

[0083] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A control circuit for a stepper motor, characterized in that, include: Silent step adjustment unit, sampling unit, drive unit; The first input terminal of the silent step adjustment unit is connected to the output terminal of the sampling unit and is used to receive the actual current value; the second input terminal of the silent step adjustment unit is used to input the theoretical current value; the first output terminal of the silent step adjustment unit is connected to the control terminal of the sampling unit and is used to output a sampling enable signal to the sampling unit at the zero-crossing point within a preset PWM cycle; the second output terminal of the silent step adjustment unit is connected to the input terminal of the drive unit and is used to transmit the drive signal generated based on the difference between the theoretical current value and the actual current value to the drive unit. The input terminal of the sampling unit is connected to the first terminal of the driving unit, and is used to collect the actual current value when the sampling enable signal is received; The second end of the drive unit is connected to a power supply, and the output end of the drive unit is connected to the motor winding. It is used to control the proportion of time that the current in the motor winding is in the conduction phase and the decay phase within the PWM cycle according to the drive signal.

2. The control circuit for the stepper motor as described in claim 1, characterized in that, Also includes: Transimpedance gain circuit; The control terminal of the transimpedance gain circuit is connected to the third output terminal of the mute step adjustment unit, and is used to receive the transimpedance gain enable signal transmitted by the mute step adjustment unit; the output terminal of the transimpedance gain circuit is connected to the third input terminal of the mute step adjustment unit, and is used to sample the actual voltage-current conversion efficiency of the circuit to obtain the transimpedance gain when the transimpedance gain enable signal is received.

3. The control circuit for the stepper motor as described in claim 2, characterized in that, The silent step adjustment unit includes: PI control module, control module, comparison module, and drive control module; The first input terminal of the PI adjustment module serves as the first input terminal of the silent step adjustment unit, used to receive the actual current value; the second input terminal of the PI adjustment module serves as the second input terminal of the silent step adjustment unit, used to receive the theoretical current value; the third input terminal of the PI adjustment module serves as the third input terminal of the silent step adjustment unit, used to receive the transimpedance gain; the output terminal of the PI adjustment module is connected to the first input terminal of the comparison module, used to output the PI control quantity to the comparison module; the PI adjustment module is used to calculate the difference between the actual current value and the theoretical current value, correct it according to the transimpedance gain to obtain the accurate current error, and perform proportional-integral operation on the accurate current error to obtain the PI control quantity; wherein, the electrical poles of the motor are canceled by configuring the zero point of the proportional gain and integral gain control loop in the proportional-integral operation; The input terminal of the control module is used to receive the mute step enable signal. The sampling enable signal output terminal of the control module serves as the first output terminal of the mute step adjustment unit, and is used to output the sampling enable signal to the sampling unit at the zero-crossing time within a preset PWM cycle. The PWM signal output terminal of the control module is connected to the second input terminal of the comparator module and is used to output the PWM count signal. The transimpedance gain enable signal output terminal of the control module serves as the third output terminal of the mute step adjustment unit and is used to output the transimpedance gain enable signal after the actual current value is acquired. The first and second output terminals of the comparison module are respectively connected to the first and second input terminals of the drive control module, and are used to compare the magnitude of the PI control quantity with the magnitude of the PWM counting signal, and output the first and second control signals according to the comparison result. The output terminal of the drive control module serves as the second output terminal of the silent step adjustment unit, and is used to convert the first control signal and the second control signal into the drive signal and output it to the drive unit.

4. The control circuit for the stepper motor as described in claim 1, characterized in that, Also includes: Theoretical current calculation unit; The first and second input terminals of the theoretical current calculation unit are respectively connected to the step signal generation terminal and the direction signal generation terminal. The output terminal of the theoretical current calculation unit is connected to the second input terminal of the silent step adjustment unit, and is used to obtain the theoretical current value according to the step signal and the direction signal and output it to the silent step adjustment unit.

5. The control circuit for the stepper motor as described in claim 2, characterized in that, The transimpedance gain circuit includes: Voltage comparator, resistor network, and transimpedance gain sampling counter; The first input terminal of the transimpedance gain sampling counter is connected to the output terminal of the voltage comparator, and the second input terminal of the transimpedance gain sampling counter serves as the control terminal of the transimpedance gain circuit; the output terminal of the transimpedance gain sampling counter is connected to the first terminal of the resistor network and serves as the output terminal of the transimpedance gain circuit. The second end of the resistor network is connected to the first input terminal of the voltage comparator; The second input terminal of the voltage comparator is connected to a reference voltage source.

6. The control circuit for the stepper motor as described in claim 3, characterized in that, The PI adjustment module includes: The module includes a current error calculation module, a calculation module, a frequency division module, and a superposition module. The first and second input terminals of the current error calculation module are respectively used as the first and second input terminals of the PI adjustment module, and the output terminal of the current error calculation module is connected to the first input terminal of the calculation module. The second input terminal of the arithmetic module serves as the third input terminal of the PI adjustment module. The first and second output terminals of the arithmetic module are respectively connected to the first and second input terminals of the frequency divider module, and are used to output the proportional term and integral term to the frequency divider module. The first and second output terminals of the frequency division module are respectively connected to the first and second input terminals of the superposition module, and are used to perform frequency division processing on the integral term and the proportional term according to the preset frequency division coefficient and then output them to the superposition module. The output of the superposition module serves as the output of the PI adjustment module, and is used to superimpose the integral term and the proportional term after frequency division processing as the PI control quantity.

7. The control circuit for the stepper motor as described in claim 1, characterized in that, The driving unit includes: Level conversion unit, full-bridge circuit; The input terminal of the level conversion unit serves as the input terminal of the driving unit, and the first, second, third, and fourth output terminals of the level conversion unit are respectively connected to the control terminals of the four switching transistors in the full-bridge circuit. The output terminal of the full-bridge circuit serves as the output terminal of the driving unit; the first terminal of the full-bridge circuit serves as the first terminal of the driving unit; and the second terminal of the full-bridge circuit serves as the second terminal of the driving unit.

8. The control circuit for the stepper motor as described in claim 3, characterized in that, The control module includes: State machine, PWM counter, zero-crossing current sampling time counter, transimpedance gain sampling time counter; The input terminal of the state machine serves as the input terminal of the control module. The sampling trigger output terminal of the state machine is connected to the enable terminal of the zero-crossing current sampling time counter. The transimpedance gain sampling trigger output terminal of the state machine is connected to the enable terminal of the transimpedance gain sampling time counter. The PWM signal trigger output terminal of the state machine is connected to the enable terminal of the PWM counter. The output terminal of the zero-crossing current sampling time counter serves as the sampling enable signal output terminal of the control module, used to perform timed counting after the state machine is triggered, and continuously output the sampling enable signal during the counting period; The output of the transimpedance gain sampling time counter serves as the transimpedance gain enable signal output of the control module. It is used to perform transimpedance gain sampling time counting after the state machine is triggered, and to continuously output the transimpedance gain enable signal during the counting period. The clock input terminal of the PWM counter is connected to the system clock signal, and the output terminal of the PWM counter serves as the PWM signal output terminal of the control module, used for periodic cyclic counting and real-time output of the PWM counting signal.

9. The control circuit for the stepper motor as described in claim 7, characterized in that, The sampling unit includes: Analog-to-digital converter and sampling resistor; The analog input terminal of the analog-to-digital converter is connected to the first terminal of the sampling resistor and the first terminal of the full-bridge circuit; the control terminal of the analog-to-digital converter serves as the control terminal of the sampling unit; the digital output terminal of the analog-to-digital converter serves as the output terminal of the sampling unit. The second terminal of the sampling resistor is grounded.

10. A control chip for a stepper motor, characterized in that, Includes the control circuit for the stepper motor as described in any one of claims 1 to 9.

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