Multi-phase clock signal generation circuit
Patent Information
- Application Number
- CN202610991293.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-05
- Publication Date
- 2026-11-03
AI Technical Summary
When traditional clock generation circuits generate multi-phase clock signals through delay circuits, the edge jitter is large and the spectrum contains glitches, which cannot meet the requirements.
Multiple differential latches are cascaded to form a latching loop. By asynchronously enabling adjacent differential latches, a differential output signal with a phase difference of π/n is output, resulting in a stable signal with low jitter.
It achieves more stable signals, less jitter, lower hardware costs, lower drive clock frequency, and higher operational stability.
Smart Images
Figure CN123034810A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and in particular to a multi-phase clock signal generation circuit. Background Technology
[0002] Many communication or signal processing systems require multi-phase clock signal generation circuits to produce multiple clock signals with equal phase differences. Examples include serial-to-parallel / parallel-to-serial conversion circuits in high-speed interconnects, fractional clock synthesis modules in phase-locked loops, and high-precision test and measurement circuits. Traditional clock generation circuits often use a combination of delay circuits and phase detectors to output multi-phase clock signals. The delay circuit outputs multiple clock signals with equal phase differences, while the phase detector identifies the phase differences between these signals, generating control signals to dynamically adjust the delay circuit and ensure the accuracy of the phase differences.
[0003] However, since this method generates multi-phase clock signals through delay circuits, the greater the delay, the greater the jitter on the edge of the clock signal, which in turn results in a large number of glitches in the spectrum of the output clock signal, failing to meet the requirements. Summary of the Invention
[0004] The purpose of this application is to provide a multi-phase clock signal generation circuit, which latches the differential input signal by asynchronously enabling adjacent differential latches in the latching loop according to the differential clock signal, thereby obtaining a differential output signal with a phase difference of π / n between the outputs of adjacent differential latches, resulting in a stable signal with low jitter.
[0005] To address the aforementioned technical problems, embodiments of this application provide a multi-phase clock generation circuit, comprising: a latching loop consisting of multiple cascaded differential latches, with the output of the last differential latch connected to the input of the first differential latch; for each differential latch's differential output signal and differential input signal, wherein, except for the last differential latch, the positive differential output signal of each differential latch serves as the positive differential input signal of the next differential latch, and the negative differential output signal serves as the negative differential input signal of the next differential latch. The input signal is as follows: the positive differential output signal of the last differential latch serves as the negative differential input signal of the first differential latch, and the negative differential output signal serves as the positive differential input signal of the first latch. Adjacent differential latches in the latch loop are asynchronously enabled according to the differential clock signal to obtain differential output signals with a phase difference of π / n. Here, n is an even number representing the number of differential latches, and the frequency of the differential clock signal is n times the frequency of the differential output signal of each differential latch.
[0006] The multi-phase clock generation circuit provided in this application includes a latch loop composed of multiple cascaded differential latches. The positive differential output signal of the last differential latch serves as the negative differential input signal and the negative differential output signal of the first differential latch serve as the positive differential input signal of the first latch. Conversely, the positive differential output signal of each differential latch (excluding the last one) serves as the positive differential input signal and the negative differential output signal serves as the negative differential input signal of the next differential latch. That is, the middle part of the latch loop is connected in the same direction, and the last and first latches are connected in opposite directions. Then, the differential clock signal received at the control terminal of the differential latch enables adjacent differential latches asynchronously. Thus, adjacent differential latches can output differential output signals with a phase difference of π / n. In other words, by setting the number of differential latches, their connection relationship, and the frequency relationship between the differential clock signal and the differential output signal in the latch loop, multiple clock signals with arbitrary phase differences can be obtained. Compared to using delay circuits to generate multi-phase clock signals, the method in this application exhibits less signal jitter and greater stability. Compared to using D flip-flops to generate multi-phase clock signals, the method in this application has lower hardware costs, requires a lower drive clock frequency, and offers higher operational stability. Attached Figure Description
[0007] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0008] Figure 1 This is a schematic diagram of the structure of the multi-phase clock generation circuit provided in the embodiments of this application. Figure 1 ; Figure 2 This is a signal timing diagram including a differential clock signal and each differential output signal provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of the multi-phase clock generation circuit provided in the embodiments of this application. Figure 2 ; Figure 4 This is a schematic diagram of the structure of the multi-phase clock generation circuit provided in the embodiments of this application. Figure 3 ; Figure 5 This is a schematic diagram of phase integration in the multi-phase clock generation circuit provided in the embodiments of this application. Detailed Implementation
[0009] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable readers to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.
[0010] Embodiments of this application relate to a multi-phase clock signal generation circuit, such as... Figure 1 As shown, it specifically includes a latching loop consisting of multiple differential latches 101 cascaded together, with the output of the last differential latch connected to the input of the first differential latch.
[0011] Specifically, the differential latch includes two input terminals ( , ), two output terminals ( , ) and two control terminals ( , The differential latch has two input terminals for differential input signals, two output terminals for differential output signals, and two control terminals for a differential clock signal to enable or disable it. When enabled, the differential latch latches the differential input signals; its output remains constant and does not change with the input. When disabled, the differential latch directly outputs the input signals; its output matches the input and changes with the input. Furthermore, differential signals refer to two signals with the same amplitude but opposite phase.
[0012] For each differential latch, the differential output signal and differential input signal are configured such that, except for the last differential latch, the positive differential output signal of each differential latch is used as the positive differential input signal of the next differential latch, and the negative differential output signal is used as the negative differential input signal of the next differential latch. The positive differential output signal of the last differential latch is used as the negative differential input signal of the first differential latch, and the negative differential output signal is used as the positive differential input signal of the first latch.
[0013] That is, the output and input of the differential latches in the middle part of the latch loop are connected in the same direction, and the last differential latch is connected in reverse to the first differential latch.
[0014] In the latching loop, adjacent differential latches are asynchronously enabled based on a differential clock signal to obtain differential output signals with a phase difference of π / n between adjacent differential latch outputs; where n is an even number representing the number of differential latches, and the frequency of the differential clock signal is n times the frequency of the differential output signal of each differential latch. Preferably, n is greater than 2.
[0015] Specifically, when the odd-numbered bits of the differential latch are enabled, the even-numbered bits are disabled; conversely, when the odd-numbered bits are disabled, the even-numbered bits are enabled. The differential clock signal used to enable or disable the differential latches is predetermined. It should be noted that since the latch loop has no input, at the initial moment, one or more initial input signals (equivalent to one or more initial output signals) need to be provided to the latch loop to define its initial input state (equivalent to defining its initial output state).
[0016] by Figure 1 Taking the latching loop shown as an example, six differential latches are cascaded to form a latching loop. The Q terminals of the six differential latches output output signals with phases of 0 degrees, 30 degrees, 60 degrees, 90 degrees, 120 degrees, and 150 degrees, respectively. The terminals output phase signals of 180 degrees, 210 degrees, 240 degrees, 270 degrees, 300 degrees, and 330 degrees respectively. In other words, the differential latch divides the signal with a phase between 0 and 2π into differential signals with phases between 0 and π and between π and 2π for processing. Then, by setting the frequency of each differential output signal to 1 / 6 of the differential clock signal frequency, which is equivalent to dividing the differential clock signal by six, adjacent differential latches can obtain differential output signals with a phase difference of π / 6 = 30°. Figure 2 The diagram shows the timing of the differential clock signal and each differential output signal. It can be seen that adjacent differential latches are enabled at different levels of the differential clock signal, and the frequency of each differential output signal is 1 / 6 of the differential clock signal frequency. Similarly, if eight differential latches are cascaded in a similar manner, and the frequency of each differential output signal is 1 / 8 of the differential clock frequency, then adjacent differential latches can obtain differential output signals with a phase difference of π / 8 = 22.5°.
[0017] It should be noted that this application does not limit the model, structure, or latching method (active low latching or active high latching) of the differential latches, as long as they are cascaded in the above manner and the frequency relationship between the output signal and the clock signal is set.
[0018] In one embodiment, the differential latches in the latch loop that are in odd-numbered bits are enabled by a low level at the positive terminal of the differential clock signal to latch the differential input signal; the differential latches in the latch loop that are in even-numbered bits are enabled by a high level at the positive terminal of the differential clock signal to latch the differential input signal; or, the differential latches in the latch loop that are in odd-numbered bits are enabled by a high level at the positive terminal of the differential clock signal to latch the differential input signal; the differential latches in the latch loop that are in even-numbered bits are enabled by a low level at the positive terminal of the differential clock signal to latch the differential input signal.
[0019] The multi-phase clock signal generation circuit provided in this application includes a latch loop composed of multiple cascaded differential latches. The middle part of the latch loop is connected in the same direction, and the last latch is connected in opposite directions to the first latch. By setting the number of differential latches, their connection relationship, and the frequency relationship between the differential clock signal and the differential output signal in the latch loop, multiple clock signals with arbitrary phase differences can be obtained. Compared to generating multi-phase clock signals using delay circuits, the method of this application has less signal jitter and is more stable. Compared to generating multi-phase clock signals using twelve D flip-flops, the method of this application has lower hardware costs, requires a lower drive clock frequency, and has higher operational stability.
[0020] Another embodiment of this application relates to a multi-phase clock signal generation circuit. This embodiment is an improvement on the aforementioned embodiment, wherein an output preset value module, a control module, and an amplifier module are added to the circuit.
[0021] In one embodiment, such as Figure 3 As shown, the circuit also includes: multiple output preset value modules 102 corresponding to multiple differential latches; the two output terminals of each output preset value module 102 are connected to the differential output terminals of the corresponding differential latches 101, and are used to set the initial output state of each differential latch 101.
[0022] Specifically, the two output terminals of the preset value output module 102 are used to output level signals to set the initial output state of the differential output terminal of each differential latch 101. Since the output of each differential latch 101 is connected to the input of the next differential latch, it is also equivalent to setting the initial input state of each differential latch 101. It should be noted that the output preset value module 102 only outputs a level signal once at the initial moment of each time the circuit is turned on. After the level signal is given to the latch loop, the output preset value module 102 is immediately turned off.
[0023] Furthermore, each output preset value module 102 outputs a high-level signal at its positive output terminal and a low-level signal at its negative output terminal; or, each output preset value module 102 outputs a low-level signal at its positive output terminal and a high-level signal at its negative output terminal; the level signals output by the positive output terminals of multiple output preset value modules 102 are arranged in the cascaded order of the differential latches 101 to form a level flip.
[0024] Specifically, the level signals output by the positive and negative output terminals of each output preset value module 102 are not limited by the positive or negative sign of the output terminal, as long as the level signals output by the positive output terminal are arranged in the cascaded order of the latches to form a level flip. Of course, once the level signal output by the positive output terminal forms a level flip, the level signal output by the negative output terminal will also necessarily form a level flip.
[0025] For example: the positive output terminal of the first output preset value module 102 outputs a high-level signal (1) and the negative output terminal outputs a low-level signal (0); the positive output terminal of the second output preset value module 102 outputs a high-level signal (1) and the negative output terminal outputs a low-level signal (0); the positive output terminal of the third output preset value module 102 outputs a high-level signal (1) and the negative output terminal outputs a low-level signal (0); the positive output terminal of the fourth output preset value module 102 outputs a high-level signal (1) and the negative output terminal outputs a low-level signal (0); the positive output terminal of the fifth output preset value module 102 outputs a low-level signal (0) and the negative output terminal outputs a high-level signal (1); and the positive output terminal of the sixth output preset value module 102 outputs a low-level signal (0) and the negative output terminal outputs a high-level signal (1). Arranging the level signals output from the positive output terminal in the cascaded sequence of the differential latches results in (1,1,1,1,0,0), thus constituting one level flip.
[0026] Furthermore, among the level signals output by the positive output terminals of the multiple output preset value modules 102, the number of high-level signals is the same as the number of low-level signals, so that the duty cycle of the differential output signal output by each differential latch is 50%.
[0027] Specifically, in this embodiment, the duty cycle of the differential output signal can be controlled by the number of high-level signals and the number of low-level signals.
[0028] In one embodiment, such as Figure 4 As shown, the circuit also includes a control module 103; the output terminal of the control module 103 is connected to the control terminals of multiple differential latches 101 respectively, and is used to control the opening or closing of each differential latch through output level signals. In addition, the output preset value module 102 and the control module 103 are turned on synchronously.
[0029] Specifically, the control module 103 controls the opening or closing of each differential latch 101 by outputting a level signal to the control terminal of the differential latch 101, which is equivalent to controlling the initial working state (enabled or disabled) of each differential latch 101. After the control module 103 sends the level signal to the latch loop, it immediately shuts down. Since the output preset value module 102 controls the initial state of the differential latch 101, the control module 103 and the output preset value module 102 are turned on synchronously. They can be controlled by the same start signal or by different start signals.
[0030] In one embodiment, such as Figure 4 As shown, the circuit also includes: an amplifier module 104; the input terminal of the amplifier module 104 is connected to the initial differential clock signal, and the output terminal is connected to the control terminals of multiple differential latches 101 respectively, for amplifying the initial differential clock signal, obtaining the differential clock signal, and outputting the differential clock signal to the control terminals of multiple differential latches 101.
[0031] In this embodiment, amplifier module 104 amplifies the differential clock signal before outputting it to the latch loop. Amplifier module 104 and control module 103 are asynchronously activated by the same start signal. That is, when control module 103 is activated, amplifier module 104 is deactivated, and when control module 103 is deactivated, amplifier module 104 is activated. In other words, at any given time, the control terminal of differential latch 101 is controlled only by the signal output from amplifier module 104 or control module 103.
[0032] In one embodiment, such as Figure 5 As shown, the circuit also includes a phase integration module 105; the phase integration module 105 is used to integrate the differential output signals with a phase difference of 90° to obtain multiple sets of quadrature signals. Specifically, the phase integration module can be an AND / OR logic gate or other logic gate device, to... Figure 1 Taking the twelve differential output signals as an example, the phase integration module 105 can combine the twelve differential output signals in pairs, with each combination having a 90-degree phase difference, to generate three sets of quadrature phase clocks. Each set has a clock of 0 / 90 / 180 / 270 degrees, namely Ip / Qp / Im / Qm, and each clock has a 25% duty cycle.
[0033] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.
Claims
1. A multi-phase clock signal generation circuit, characterized in that, include: A latching loop consisting of multiple cascaded differential latches, with the output of the last differential latch connected to the input of the first differential latch; For each differential latch, the differential output signal and differential input signal are defined as follows: the positive differential output signal of each differential latch except the last differential latch is used as the positive differential input signal of the next differential latch, and the negative differential output signal is used as the negative differential input signal of the next differential latch. The positive differential output signal of the last differential latch is used as the negative differential input signal of the first differential latch, and the negative differential output signal is used as the positive differential input signal of the first latch. The adjacent differential latches in the latching loop are asynchronously enabled according to the differential clock signal to obtain a differential output signal with a phase difference of π / n between the outputs of the adjacent differential latches. Where n is an even number, representing the number of differential latches, and the frequency of the differential clock signal is n times the frequency of the differential output signal of each differential latch.
2. The multi-phase clock signal generation circuit according to claim 1, characterized in that, The differential latches in the latching loop that are in odd-numbered positions are enabled by a low level at the positive terminal of the differential clock signal to latch the differential input signal; the differential latches in the latching loop that are in even-numbered positions are enabled by a high level at the positive terminal of the differential clock signal to latch the differential input signal. or, The differential latches in the latching loop that are in odd-numbered positions are enabled at a high level at the positive terminal of the differential clock signal to latch the differential input signal; the differential latches in the latching loop that are in even-numbered positions are enabled at a low level at the positive terminal of the differential clock signal to latch the differential input signal.
3. The multi-phase clock signal generation circuit according to claim 1, characterized in that, The circuit further includes: multiple output preset value modules corresponding one-to-one with multiple differential latches; The two output terminals of each output preset value module are connected to the differential output terminal of the corresponding differential latch, which is used to set the initial output state of the differential output terminal of each differential latch.
4. The multi-phase clock signal generation circuit according to claim 3, characterized in that, Each of the output preset value modules outputs a high-level signal at its positive output terminal and a low-level signal at its negative output terminal; or, each of the output preset value modules outputs a low-level signal at its positive output terminal and a high-level signal at its negative output terminal. The level signals output from the positive output terminals of the multiple output preset value modules are arranged in the cascaded order of the latches to form a level flip.
5. The multi-phase clock signal generation circuit according to claim 4, characterized in that, In the level signals output from the positive output terminals of the plurality of output preset value modules, the number of high-level signals and the number of low-level signals are the same, so that the duty cycle of the differential output signal output by each differential latch is 50%.
6. The multi-phase clock signal generation circuit according to claim 3, characterized in that, The circuit also includes: a control module; The output of the control module is connected to the control terminals of multiple differential latches, respectively, and is used to control the opening or closing of each differential latch by outputting a level signal.
7. The multi-phase clock signal generation circuit according to claim 6, characterized in that, The output preset value module and the control module are activated simultaneously.
8. The multi-phase clock signal generation circuit according to claim 6, characterized in that, The circuit also includes: an amplifier module; The amplifier module receives an initial differential clock signal at its input and is connected to the control terminals of the plurality of differential latches at its output. It amplifies the initial differential clock signal to obtain a differential clock signal and outputs the differential clock signal to the control terminals of the plurality of differential latches.
9. The multi-phase clock signal generation circuit according to claim 8, characterized in that, The amplifier module and the control module are asynchronously activated by the same start signal.
10. The multi-phase clock signal generation circuit according to any one of claims 1-9, the circuit further comprising: Phase integration module; The phase integration module is used to integrate differential output signals with a phase difference of 90° to obtain multiple sets of orthogonal signals.