Control circuit for light emitting diodes and light emitting device

Abstract

The embodiment of the application provides a light emitting diode control circuit and a light emitting device, which belong to the field of analog integrated circuit and optoelectronic communication technology. The circuit comprises a reference voltage branch, a first resistor, a first voltage follower, a first digital bias current source, a first constant current source and a current mirror driving circuit module. The first electrical node, the first resistor and the non-inverting input terminal of the first voltage follower are connected in series. The tail current bias pin of the first voltage follower is connected to the first digital bias current source. The first constant current source is connected to the second end of the first resistor. The two current extraction ends of the differential switch sub-branch are respectively connected to the two ends of the first resistor. The current bias end of the differential switch sub-branch is connected to the first end of the second digital bias current source. The two driving input terminals of the current mirror driving circuit module are respectively connected to the output terminals of the reference voltage branch and the first voltage follower, so as to reduce the high-frequency signal integrity problem and improve the electromagnetic compatibility.

Description

Technical Field

[0001] This application relates to the fields of analog integrated circuits and optoelectronic communication technology, and in particular to a control circuit for a light-emitting diode and a light-emitting device. Background Technology

[0002] In modern visible light communication (VLC) and optical wireless digital transmission systems, light-emitting diodes (LEDs) serve as the core optical signal transmitters, converting electrical signals into information-carrying optical signals through pulse width modulation (PWM) or high-frequency digital pulses. To adapt to different communication distances and channel attenuation, the LED control circuitry in the optical transmitter must possess flexible multi-level dimming capabilities. However, existing LED control circuits are prone to high-frequency signal integrity issues and have poor electromagnetic compatibility. Summary of the Invention

[0003] The main objective of this application is to provide a control circuit for a light-emitting diode and a light-emitting device that can reduce high-frequency signal integrity issues and improve electromagnetic compatibility for multi-level dimming emitters.

[0004] To achieve the above objectives, a first aspect of this application provides a control circuit for a light-emitting diode, the method comprising: A voltage modulation circuit module includes a reference voltage branch and a differential voltage modulation branch. The input terminals of both the reference voltage branch and the differential voltage modulation branch are electrically connected to the same first electrical node. The differential voltage modulation branch includes a differential voltage modulation main sub-branch and a differential switch sub-branch. The differential voltage modulation main sub-branch includes a first resistor, a first voltage follower, a first digital bias current source, and a first constant current source. The first and second terminals of the first resistor are respectively connected to the first electrical node and the non-inverting input terminal of the first voltage follower. The inverting input terminal of the first voltage follower and the... The output terminal is connected, the tail current bias pin of the first voltage follower is connected to the first digital bias current source; the first terminal of the first constant current source is connected between the second terminal of the first resistor and the non-inverting input terminal of the first voltage follower, the second terminal of the first constant current source is grounded, the two current extraction terminals of the differential switch sub-branch are respectively connected to the first terminal and the second terminal of the first resistor; the control terminal of the differential switch sub-branch is used to receive pulse width modulation (PWM) signals, and the current bias terminal of the differential switch sub-branch is connected to the first terminal of the second digital bias current source to adjust the reference current output by the reference voltage branch to a preset level; A current mirror drive circuit module, wherein the two drive input terminals of the current mirror drive circuit module are respectively connected to the first output terminal of the reference voltage branch and the second output terminal of the first voltage follower. When the PWM signal is high, the voltage difference between the output of the first voltage follower and the first electrical node is equal to the product of the first resistor and the total control current, where the total control current is the sum of the currents provided by the second digital bias current source and the first constant current source.

[0005] To achieve the above objectives, a second aspect of the present application provides a light emitting device, including a control circuit for a light-emitting diode as described in any one of the first aspects.

[0006] The control circuit and light emitting device for the light-emitting diode proposed in this application can automatically adjust multiple levels of the reference voltage branch by combining a second digital bias current source with a differential switch sub-branch. Simultaneously, by setting a first constant current source between the second terminal of the first resistor and the first voltage follower, and when the PWM signal is high, the voltage difference between the output voltage of the first voltage follower and the first electrical node is equal to the product of the first resistor and the total control current. The total control current is the sum of the currents of the second digital bias current source and the first constant current source. This allows the current in the differential voltage modulation main sub-branch to be determined by the magnitudes of the currents from the first constant current source and the second digital bias current source. Since the first constant current source can continuously draw current, even when the PWM signal is low, current always flows through the first resistor. Combined with the current mirror drive circuit module, the driving current of the output LED is always non-zero, and the LED is always in a micro-conduction ready state, reducing the generation of high-frequency signal integrity problems. Furthermore, by dynamically adjusting the tail current of the first follower through the first digital bias current source, the charging and discharging speed of the node capacitors inside the first follower can be adjusted. At this time, the square wave edge of the reference voltage output from the second output terminal is a controlled trapezoidal harmonic, thus smoothing the rising and falling edges of the tens of milliamps of LED main driving current. Simultaneously, in conjunction with the current mirror drive circuit module, the waveform of the main driving current supplied to the LED can strictly follow the waveform slope of the reference voltage, improving electromagnetic compatibility. Therefore, compared with related technologies, the embodiments of this application can reduce high-frequency signal integrity problems while improving electromagnetic compatibility for multi-level dimming transmitters. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the module structure of the control circuit for the light-emitting diode provided in this application; Figure 2 A schematic diagram of the voltage modulation circuit module in one embodiment of the control circuit for the light-emitting diode provided in this application; Figure 3 A schematic diagram of the circuit principle of the current mirror drive circuit module in one embodiment of the control circuit for the light-emitting diode provided in this application; Figure 4 A schematic diagram of the circuit principle of the first operational amplifier AMP01 in one embodiment of the control circuit for the light-emitting diode provided in this application; Figure 5 A schematic diagram of the circuit principle of the second operational amplifier AMP02 in one embodiment of the control circuit for the light-emitting diode provided in this application; Figure 6 A simulation curve of DC scanning of 16 adjustable drive current levels in one embodiment of the control circuit for the light-emitting diode provided in this application; Figure 7 A simulation waveform of transient drive current at the 20mA level for an embodiment of the control circuit for the light-emitting diode provided in this application; Figure 8 A schematic diagram illustrating the transient edge characteristics of the output current slew rate of the first voltage follower as a function of the digital control level, under a fixed 20mA output, according to an embodiment of the control circuit for the light-emitting diode provided in this application. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0009] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0010] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0011] In modern visible light communication (VLC) and optical wireless digital transmission systems, light-emitting diodes (LEDs) serve as the core optical signal transmitters, converting electrical signals into information-carrying optical signals through pulse width modulation (PWM) or high-frequency digital pulses. To adapt to varying communication distances and channel attenuation, the control circuitry of the LEDs in the optical transmitter must possess flexible multi-level dimming capabilities. However, in practical applications, the pursuit of extremely high communication baud rates generates extremely steep current / voltage transitions during the switching on and off of the LEDs controlled by the PWM signal. These current / voltage jumps contain a wealth of high-frequency harmonic energy, which can easily generate severe electromagnetic interference (EMI) through spatial radiation or conduction via the power supply ground line. Simultaneously, traditional drive control circuits completely cut off the LED drive current when the PWM signal is low. When the next data pulse arrives, the drive loop needs to completely recharge the large parasitic capacitance of the large-size power transistor. This deep charging and discharging process causes severe turn-on delay in the optical pulses, leading to inter-symbol interference (ISI) and directly locking the highest baud rate of optical communication, making it difficult to meet high-frequency signal integrity requirements. Therefore, existing LED control circuits are prone to high-frequency signal integrity problems and have poor electromagnetic compatibility. This paper proposes a control circuit for a light-emitting diode and a light-emitting device that can reduce high-frequency signal integrity problems while improving electromagnetic compatibility for multi-level dimming emitters.

[0012] Understandably, referring to Figures 1 to 3 As shown, a control circuit for a light-emitting diode according to an embodiment of this application includes: The voltage modulation circuit module includes a reference voltage branch and a differential voltage modulation branch. The input terminals of both the reference voltage branch and the differential voltage modulation branch are electrically connected to the same first electrical node. The differential voltage modulation branch includes a differential voltage modulation main sub-branch and a differential switch sub-branch. The differential voltage modulation main sub-branch includes a first resistor, a first voltage follower, a first digital bias current source, and a first constant current source. The first and second terminals of the first resistor are respectively connected to the first electrical node and the non-inverting input terminal of the first voltage follower. The inverting input terminal of the first voltage follower and the first voltage follower... The output terminal is connected, the tail current bias pin of the first voltage follower is connected to the first digital bias current source; the first terminal of the first constant current source is connected between the second terminal of the first resistor and the non-inverting input terminal of the first voltage follower, the second terminal of the first constant current source is grounded, the two current extraction terminals of the differential switch sub-branch are respectively connected to the first terminal and the second terminal of the first resistor; the control terminal of the differential switch sub-branch is used to receive pulse width modulation (PWM) signals, and the current bias terminal of the differential switch sub-branch is connected to the first terminal of the second digital bias current source to adjust the reference current output by the reference voltage branch to a preset level; The current mirror drive circuit module has two drive input terminals connected to the first output terminal of the reference voltage branch and the second output terminal of the first voltage follower, respectively. When the PWM signal is high, the voltage difference between the output voltage of the first voltage follower and the first electrical node is equal to the product of the first resistor and the total control current. The total control current is the sum of the currents provided by the second digital bias current source and the first constant current source.

[0013] By combining the second digital bias current source with the differential switch sub-branch, the automatic adjustment of multiple levels of the reference voltage branch can be achieved. Simultaneously, by setting a first constant current source between the second terminal of the first resistor and the first voltage follower, and when the PWM signal is high, the voltage difference between the output voltage of the first voltage follower and the first electrical node is equal to the product of the first resistor and the total control current. The total control current is the sum of the currents from the second digital bias current source and the first constant current source. This allows the current in the differential voltage modulation main sub-branch to be determined by the magnitudes of the currents from the first constant current source and the second digital bias current source. Since the first constant current source can continuously draw current, even when the PWM signal is low, current always flows through the first resistor. Combined with the current mirror drive circuit module, the driving current of the output LED is always non-zero, and the LED is always in a micro-conduction ready state, reducing high-frequency signal integrity issues. Furthermore, by dynamically adjusting the tail current of the first follower through the first digital bias current source, the charging and discharging speed of the node capacitors inside the first follower can be adjusted. At this time, the square wave edge of the reference voltage output from the second output terminal is a controlled trapezoidal harmonic, thereby smoothing the rising and falling edges of the tens of milliamps of LED main driving current. Simultaneously, in conjunction with the current mirror drive circuit module, the waveform of the main driving current supplied to the LED can strictly follow the waveform slope of the reference voltage, improving electromagnetic compatibility. Therefore, the embodiments of this application can reduce high-frequency signal integrity problems while improving electromagnetic compatibility for multi-level dimming transmitters.

[0014] The first electrical node is used to generate a fixed base voltage. This application does not limit how the voltage of this electrical node is generated. For example, in some embodiments, it can be generated by a second constant current source and a second voltage follower. For instance,... Figure 2 As shown, the second constant current source is IBP1, and the second voltage follower is Follower02. The first terminal of IBP1 is connected in series with resistor R2 and the external power supply VDD; the second terminal of IBP1 is grounded; the non-inverting input of Follower02 is connected between R2 and the first terminal of IBP1; the inverting input of Follower02 is connected to the output of Follower02; and the first electrical node is connected to the output of Follower02. In some embodiments, such as... Figure 2 As shown, the first electrical node is VERF, which is the far-end node obtained by extending the output terminal of Follower02 outward through PCB traces. In other embodiments, other methods may be used to generate a fixed voltage, which will not be described in detail in this application.

[0015] Both the first and second digital bias current sources represent current sources whose bias current magnitude can be controlled via programming methods such as digital registers. In some embodiments, multiple bias current branches can be pre-configured using NMOS transistors, and different bias current branches can be switched on using digital registers to achieve dynamic control of the bias current magnitude. In other embodiments, different bias current magnitudes can also be provided using other methods, which will not be elaborated upon in this application.

[0016] This application does not limit the adjustable range of the reference current in its embodiments. In practical applications, it can be achieved by the number of conducting branch combinations set in the differential switch sub-branch and the combination of bias current ranges supported by the second digital bias current source. For example, in some embodiments, 16 levels of reference current control can be achieved.

[0017] In some embodiments, the current mirror drive circuit module includes a second operational amplifier with an active push-pull output architecture, thereby enabling the current mirror drive circuit module to have an extremely wide closed-loop bandwidth and microsecond-level response capability.

[0018] Understandably, the differential switch sub-branch includes a first inverter and a second inverter, a fifteenth P-type power transistor, a sixteenth P-type power transistor, a tenth N-type power transistor, an eleventh N-type power transistor, and a third resistor. The source of the tenth N-type power transistor, the drain of the fifteenth P-type power transistor, the drain of the sixteenth P-type power transistor, and the source of the eleventh N-type power transistor are all connected to the first terminal of the second digital bias current source. The gate of the tenth N-type power transistor and the gate of the sixteenth P-type power transistor are connected. The drain of the tenth N-type power transistor and the source of the fifteenth P-type power transistor are connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the first... Between the first terminal of a resistor and the first electrical node; the source of the sixteenth P-type power transistor and the drain of the eleventh N-type power transistor are connected between the second terminal of the first resistor and the first terminal of the first constant current source; the gate of the eleventh N-type power transistor is connected between the output terminal of the second inverter and the gate of the fifteenth P-type power transistor; the gate of the fifteenth P-type power transistor is connected to the output terminal of the second inverter; the input terminal of the second inverter is connected to the output terminal of the first inverter; the output terminal of the first inverter is also connected between the gate of the tenth N-type power transistor and the gate of the sixteenth P-type power transistor; the input terminal of the first inverter is used to receive PWM signals.

[0019] The first and second inverters connected in series can be used to shape the PWM signal.

[0020] For example, refer to Figure 2As shown, assuming the first inverter is INV1, the second inverter is INV2, the fifteenth P-type power transistor is PM1, the sixteenth P-type power transistor is PM2, the tenth N-type power transistor is NM5, the eleventh N-type power transistor is NM6, the third resistor is R3, the first resistor is R4, the first voltage follower is Follower01, the first constant current source is IBP3, the first digital bias current source is IBN3, the second digital bias current source is IBP2, and the first electrical node is VERF, then... Figure 2 As shown, the first and second terminals of R4 are connected to VERF and the non-inverting input of Follower01, respectively. The inverting input and output of Follower01 are connected. The tail current bias pin of Follower01 is connected to IBN3. The first terminal of IBP3 is connected between the second terminal of R4 and the non-inverting input of Follower01. The second terminal of IBP3 is grounded. The source of NM5, the drain of PM1, the drain of PM2, and the source of NM6 are all connected to the first terminal of IBP2. The second terminal of IBP2 is grounded. The gate of NM5 and the gate of PM2 are connected. The drain of NM5 and the source of PM1 are connected to the first terminal of R3. The second terminal of R3 is connected to R... The first terminal of R4 is connected to VERF; the source of PM2 and the drain of NM6 are connected between the second terminal of R4 and the first terminal of IBP3; the gate of NM6 is connected between the output terminal of INV2 and the gate of PM1; the gate of PM1 is connected to the output terminal of INV2; the input terminal of INV2 is connected to the output terminal of INV1; the output terminal of INV1 is also connected between the gate of NM5 and the gate of PM2; the input terminal of INV1 is used to receive PWM signals. At this time, different bias voltages are provided to PM1, NM5, PM2 and NM6 through IBP2, so that the current through R4 and R1 can reach different levels by different combinations of the conduction states of PM1, NM5, PM2 and NM6.

[0021] Understandably, referring to Figure 3 As shown, the current mirror drive circuit module includes a first operational amplifier, a reference power transistor, a common-gate protection power transistor, and a main power transistor. The non-inverting and inverting inputs of the first operational amplifier are connected to the first and second outputs, respectively. The output of the first operational amplifier is connected to the gate of the reference power transistor, the source of the reference power transistor is grounded, the drain of the reference power transistor is connected to the source of the common-gate protection power transistor, the drain of the common-gate protection power transistor is connected between the first output and the non-inverting input of the first operational amplifier, and the gate of the common-gate protection power transistor is connected to an external bias voltage. The gate of the main power transistor is connected to the gate of the reference power transistor, the source of the main power transistor is grounded, and the drain of the main power transistor is used to electrically connect to the first terminal of the light-emitting diode (LED). The main power transistor is used to mirror and replicate the reference current of the first output according to the device aspect ratio.

[0022] For example, assuming the first operational amplifier is AMP01, the reference power transistor is NM2, the common-gate protection power transistor is NM1, and the main power transistor is NM4, then as follows: Figure 3 As shown, the non-inverting input and inverting input of AMP01 are connected to the first output and the second output, respectively. The output of AMP01 is connected to the gate of NM2. The source of NM2 is grounded. The drain of NM2 is connected to the source of NM1. The drain of NM1 is connected between the first output and the non-inverting input of AMP01. The gate of NM1 is connected to an external bias voltage. The gate of NM4 is connected to the gate of NM2. The source of NM4 is grounded. The drain of NM4 is used to electrically connect to the first terminal of the LED.

[0023] Understandably, referring to Figure 3 As shown, the current mirror drive circuit module also includes a second operational amplifier and a cascaded power transistor; the drain of the cascaded power transistor is used to connect to the first terminal of the LED; the source of the cascaded power transistor and the drain of the main power transistor are connected; the gate of the cascaded power transistor and the output terminal of the second operational amplifier are connected; the non-inverting input terminal of the second operational amplifier is connected between the source of the common-gate protection power transistor and the drain of the reference power transistor; and the inverting input terminal of the second operational amplifier is connected between the source of the cascaded power transistor and the drain of the main power transistor.

[0024] For example, assuming the first operational amplifier is AMP01, the reference power transistor is NM2, the common-gate protection power transistor is NM1, the main power transistor is NM4, the second operational amplifier is AMP02, and the cascaded power transistor is NM3, then as follows Figure 3 As shown, the non-inverting input and inverting input of AMP01 are connected to the first output and the second output, respectively. The output of AMP01 is connected to the gate of NM2. The source of NM2 is grounded. The drain of NM2 is connected to the source of NM1. The drain of NM1 is connected between the first output and the non-inverting input of AMP01. The gate of NM1 is connected to an external bias voltage. The gate of NM4 is connected to the gate of NM2. The source of NM4 is grounded. The drain of NM4 is connected to the source of NM3. The drain of NM3 is used to connect to the first terminal of the LED. The gate of NM3 is connected to the output of AMP02. The non-inverting input of AMP02 is connected between the source of NM1 and the drain of NM2. The inverting input of AMP02 is connected between the source of NM3 and the drain of NM4.

[0025] Understandably, referring to Figure 4As shown, the first operational amplifier includes a first N-type power transistor, a second N-type power transistor, a first P-type power transistor, a second P-type power transistor, a feedforward push-pull cascode sub-circuit, a first bias control sub-circuit, a transistor, and a third N-type power transistor. The gate of the first N-type power transistor is connected to the second output terminal, and the gate of the second N-type power transistor is connected to the first output terminal. The sources of both the first and second N-type power transistors are connected to the first control terminal of the first bias control sub-circuit. The drain of the first N-type power transistor is connected to the drain of the first P-type power transistor, and the gate of the first P-type power transistor is connected to the drain of the first P-type power transistor. The gates of the first and second P-type power transistors are connected, and the drains of the first and second P-type power transistors are connected to the feedforward push-pull cascode push-pull sub-circuit. The upper bridge arm of the push-pull cascode sub-circuit is connected to the collector of the transistor. The upper control terminal of the feedforward push-pull cascode sub-circuit is connected between the drain of the second P-type power transistor and the drain of the second N-type power transistor. The lower control terminal of the feedforward push-pull cascode sub-circuit is connected to the second control terminal of the first bias control sub-circuit. The feedforward control terminal of the feedforward push-pull cascode sub-circuit is connected to the third control terminal of the first bias control sub-circuit. The base of the transistor is connected to the pull-up node of the feedforward push-pull cascode sub-circuit. The emitter of the transistor is connected to the gate of the reference power transistor and the drain of the third N-type power transistor. The gate of the third N-type power transistor is connected to the fourth control terminal of the first bias control sub-circuit. The source of the third N-type power transistor is grounded.

[0026] For example, assuming the first N-type power transistor is NM11, the second N-type power transistor is NM12, the first P-type power transistor is PM3, the second P-type power transistor is PM4, the transistor is Q1, and the third N-type power transistor is NM15, then refer to... Figure 4As shown, the gate of NM11 is connected to the second output terminal (i.e., the output terminal of the first voltage follower Follower01), and the gate of NM12 is connected to the first output terminal (i.e., the second terminal of the first resistor R4); the sources of NM11 and NM12 are both connected to the first control terminal of the first bias control sub-circuit; the drain of NM11 is connected to the drain of PM3, and the gate of PM3 is connected to the drain of PM3; the gate of PM3 is connected to the gate of PM4, and the drains of PM3 and PM4, as well as the upper bridge arm connection terminal of the feedforward push-pull cascode sub-circuit, are all connected to the collector of Q1; the feedforward... The upper control terminal of the push-pull cascode sub-circuit is connected between the drain of PM4 and the drain of NM12. The lower control terminal of the feedforward push-pull cascode sub-circuit is connected to the second control terminal of the first bias control sub-circuit. The feedforward control terminal of the feedforward push-pull cascode sub-circuit is connected to the third control terminal of the first bias control sub-circuit. The base of Q1 is connected to the pull-up node of the feedforward push-pull cascode sub-circuit. The emitter of Q1 is connected to the gate of the reference power transistor and the drain of NM15. The gate of NM15 is connected to the fourth control terminal of the first bias control sub-circuit. The source of NM15 is grounded. The reference... Figure 4 As shown, according to Kirchhoff's current law, at the source node of NM13, the current always satisfies the following relationship: = - Since INM14 has a constant bias current, as the IN_P input voltage increases, the gate voltages of PM5 and PM6 decrease, and their turn-on degree increases simultaneously. PM6 quickly provides a large pull-up current. The current flows from the source of PM6 to the drain, and the corresponding current flowing through PM5 is ( The current also increases sharply, flowing from the source to the drain of PM5. At this time, as... Figure 4 As shown, the current The flow originates from the drain of the NM13 to the source. The current flows from the drain to the source of the NM14.

[0027] This application does not limit the structure of the first bias control sub-circuit. In some embodiments, a current mirror circuit can be set to provide different bias currents. In some embodiments, the first bias control sub-circuit includes a twelfth-type N-type power transistor, a thirteenth-type N-type power transistor, a fourteenth-type N-type power transistor, and a fifteenth-type N-type power transistor. For example, assuming the twelfth-type N-type power transistor is NM7, the thirteenth-type N-type power transistor is NM8, the fourteenth-type N-type power transistor is NM9, and the fifteenth-type N-type power transistor is NM10, then... Figure 4As shown, the sources of NM7 and NM10 are grounded, the drains of NM10 and NM7 are connected to the sources of NM9 and NM7 respectively, the gate of NM6 is connected to the gate of NM10, the drain of NM6 is connected to the gate of NM6, the drain of NM7 is connected to the gate of NM7, the gate of NM7 is connected to the gate of NM9, the gate of NM9 is connected as the first control terminal to the sources of NM11 and NM12, the drain of NM7 is also connected to the power supply IBN1; the gate of NM7 is also connected as the second control terminal to the lower control terminal, the gate of NM8 is also connected as the third control terminal to the feedforward control terminal, and the gate of NM8 is also connected as the fourth control terminal to NM15.

[0028] Understandably, referring to Figure 4 As shown, the feedforward push-pull common-source cascode stage sub-circuit includes a third P-type power transistor, a fourth P-type power transistor, a common-gate amplifier power transistor, and a fourth N-type power transistor. The gates of the third and fourth P-type power transistors serve as the upper control terminals and are connected between the second P-type and second N-type power transistors. The sources of the fourth and third P-type power transistors serve as the upper bridge arm connection terminals and are connected to the collectors of the transistors. The gate of the common-gate amplifier power transistor serves as the lower control terminal and the second control terminal of the first bias control sub-circuit. The common-gate power transistor's drain is connected to the drain of the fourth P-type power transistor, the common-gate power transistor's source is connected to the drain of the fourth N-type power transistor, the fourth N-type power transistor's source is grounded, and the fourth N-type power transistor's gate is connected as a feedforward control terminal to the third control terminal of the first bias control sub-circuit. The drain of the third P-type power transistor is connected between the common-gate power transistor's source and the fourth N-type power transistor's drain, and the pull-up node is located between the fourth P-type power transistor's drain and the common-gate power transistor's drain.

[0029] For example, assuming the twelfth N-type power transistor is NM7, the thirteenth N-type power transistor is NM8, the fourteenth N-type power transistor is NM9, the fifteenth N-type power transistor is NM10, the first N-type power transistor is NM11, the second N-type power transistor is NM12, the first P-type power transistor is PM3, the second P-type power transistor is PM4, the transistor is Q1, the third N-type power transistor is NM15, the third P-type power transistor is PM5, the fourth P-type power transistor is PM6, the common-gate amplifier power transistor is NM13, and the fourth N-type power transistor is NM14, then refer to... Figure 4As shown, the gates of PM5 and PM6 are connected between PM4 and NM12 as the upper control terminals; the sources of PM6 and PM5 are connected to the collector of Q1 as the upper bridge arm connection terminals; the gate of NM13 is connected to the gate of NM7 as the lower control terminal; the drain of NM13 is connected to the drain of PM6; the source of NM13 is connected to the drain of NM14; the source of NM14 is grounded; and the gate of NM14 is connected to the gate of NM8 as the feedforward control terminal; the drain of PM5 is connected between the source of NM13 and the drain of NM14; and the pull-up node is located between the drain of PM6 and the drain of NM13.

[0030] Understandably, referring to Figure 4 As shown, the feedforward push-pull common source cascode sub-circuit also includes a second resistor and a first capacitor connected in series. The first end of the second resistor, away from the first capacitor, is connected between the gate of the fourth P-type power transistor and the drain of the second P-type power transistor. The first end of the first capacitor, away from the second resistor, is connected between the drain of the fourth P-type power transistor and the pull-up node.

[0031] For example, assuming the second resistor is R5 and the first capacitor is C3, then as follows Figure 4 As shown, R5 and C3 are connected in series. The second end of C3 is connected to the drain of PM6, and the second end of R5 is connected between the drain of PM6 and the drain of PM4.

[0032] Understandably, referring to Figure 5As shown, the second operational amplifier includes a fifth P-type power transistor, a sixth P-type power transistor, a seventh P-type power transistor, an eighth P-type power transistor, a ninth P-type power transistor, a tenth P-type power transistor, an eleventh P-type power transistor, a twelfth P-type power transistor, a thirteenth P-type power transistor, a fourteenth P-type power transistor, a fifth N-type power transistor, a sixth N-type power transistor, a seventh N-type power transistor, an eighth N-type power transistor, and a ninth N-type power transistor. The gate of the fifth P-type power transistor serves as the inverting input terminal of the second operational amplifier, connected between the source of the cascaded power transistors and the drain of the main power transistor. The gate of the sixth P-type power transistor serves as the inverting input terminal of the second operational amplifier. The non-inverting input of the amplifier is connected between the source of the common-gate protected power transistor and the drain of the reference power transistor; the drain of the fifth P-type power transistor is connected between the source of the fifth N-type power transistor and the drain of the sixth N-type power transistor; the drain of the sixth P-type power transistor is connected between the source of the seventh N-type power transistor and the drain of the eighth N-type power transistor; the sources of the fifth and sixth P-type power transistors are both connected to the drain of the seventh P-type power transistor; the gate of the seventh P-type power transistor is connected to the gate of the eighth P-type power transistor; the gate of the eighth P-type power transistor is connected to the drain of the eighth P-type power transistor; the source of the eighth P-type power transistor and... The drain connection of the ninth P-type power transistor; the drain and gate connection of the ninth P-type power transistor; the gate connection of the ninth P-type power transistor and the gate connection of the tenth P-type power transistor; the drain connection of the tenth P-type power transistor and the source connection of the seventh P-type power transistor; the drain and gate connection of the eleventh P-type power transistor and the drain connection of the fifth N-type power transistor; the gate connection of the eleventh P-type power transistor and the gate connection of the twelfth P-type power transistor; the drain connection of the twelfth P-type power transistor and the drain connection of the seventh N-type power transistor and the gate connection of the thirteenth P-type power transistor; the thirteenth P-type power transistor and the twelfth P-type power transistor... The sources of the 11th P-type power transistor, the 10th P-type power transistor, and the 9th P-type power transistor are interconnected. The drain of the 13th P-type power transistor serves as the output terminal of the second operational amplifier and is connected to the gate of the cascaded power transistor and the drain of the 9th N-type power transistor. The gate of the 9th N-type power transistor is connected between the source of the 7th N-type power transistor and the drain of the 8th N-type power transistor. The drain of the 14th P-type power transistor is connected to the source of the 7th N-type power transistor. The source of the 14th P-type power transistor is connected between the drain of the 12th P-type power transistor and the drain of the 7th N-type power transistor. The gate of the 14th P-type power transistor is used to connect the bias voltage.

[0033] In some embodiments, the second amplifier further includes a second bias control sub-circuit. The first control terminal of the second bias control sub-circuit is connected to the gate of the fifth N-type power transistor and the gate of the seventh N-type power transistor. The second control terminal of the second bias control sub-circuit is connected to the gate of the sixth N-type power transistor and the gate of the eighth N-type power transistor. In some embodiments, the second bias control sub-circuit includes a sixteenth N-type power transistor, a seventeenth N-type power transistor, an eighteenth N-type power transistor, and a nineteenth N-type power transistor. Assuming the sixteenth N-type power transistor is NM16, the seventeenth N-type power transistor is NM17, the eighteenth N-type power transistor is NM18, and the nineteenth N-type power transistor is NM19, then refer to... Figure 5 As shown, the gate of NM16 is connected to the gates of NM20 and NM22 as the first control terminal, and the gate of NM16 is also connected to the gate of NM18. The gate of NM17 is connected to the gates of NM21 and NM23 as the second control terminal, and the gate of NM17 is also connected to the gate of NM19. The drain of NM17 is connected to the source of NM16, the drain of NM19 is connected to the source of NM18, the gate of NM17 is connected to the drain of NM17, the gate of NM16 is also connected to the drain of NM16, and the drain of NM16 is also connected to the bias power supply IBN2.

[0034] For example, suppose the fifth P-type power transistor is PM11, the sixth P-type power transistor is PM12, the seventh P-type power transistor is PM10, the eighth P-type power transistor is PM8, the ninth P-type power transistor is PM7, the tenth P-type power transistor is PM9, the eleventh P-type power transistor is PM13, the twelfth P-type power transistor is PM14, the thirteenth P-type power transistor is PM16, the fourteenth P-type power transistor is PM15, the fifth N-type power transistor is NM20, the sixth N-type power transistor is NM21, the seventh N-type power transistor is NM22, the eighth N-type power transistor is NM23, and the ninth N-type power transistor is NM24; then... Figure 5 and Figure 4As shown, the gate of PM11 serves as the inverting input of the second operational amplifier, connected between the source of NM3 and the drain of NM4; the gate of PM12 serves as the non-inverting input of the second operational amplifier, connected between the source of NM1 and the drain of NM2; the drain of PM11 is connected between the source of NM20 and the drain of NM21, and the drain of PM12 is connected between the source of NM22 and the drain of NM23; the sources of PM11 and PM12 are both connected to the drain of PM10; the gate of PM10 is connected to the gate of PM8; the gate of PM8 is connected to the drain of PM8; the source of PM8 is connected to the drain of PM7; the drain of PM7 is connected to the gate of PM7; and the gate of PM7 is connected to the gate of PM9. The drain of PM9 is connected to the source of PM10, the drain of PM11 is connected to the gate of PM11 and the drain of NM20, the gate of PM13 is also connected to the gate of PM14, the drain of PM14 is connected to the drain of NM22 and the gate of PM16, and the sources of PM16, PM13, PM14, PM9 and PM7 are interconnected. The drain of PM16 serves as the output of the second operational amplifier and is connected to the gate of NM3 and the drain of NM24. The gate of NM24 is connected between the source of NM22 and the drain of NM23. The drain of PM15 is connected to the source of NM22, and the source of PM15 is connected between the drain of PM14 and the drain of NM22. The gate of PM15 is used to connect the bias voltage. When the gate voltage IN_P of PM12 increases, the conduction of PM12 weakens. Correspondingly, the gate voltage of PM16 decreases, which strengthens the conduction of PM16. Current flows from the source to the drain of PM16. Correspondingly, due to the weakening of the conduction of PM12, the gate voltage of NM24 decreases, which weakens the conduction of NM24. Current flows from the drain to the source of NM24.

[0035] Understandably, referring to Figure 5 As shown, the gate of the fourteenth P-type power transistor is connected between the gate of the eighth P-type power transistor and the gate of the seventh P-type power transistor.

[0036] For example, see below. Figure 2 As for Figure 5 The control circuit and principle of the light-emitting diode in the embodiments of this application are described in detail, such as... Figure 2 As shown, the second constant current source IBP1 and resistor R2 generate a fixed base voltage. This voltage is regulated and isolated by the second voltage follower Follower02 before being output, forming a global core reference point (i.e., the first electrical node VERF) on the extension line of the output terminal of Follower02. Simultaneously, two electrical paths are formed within the voltage modulation circuit module: one corresponding to the reference voltage branch and the other to the differential voltage modulation branch. The reference voltage branch outputs a reference current (i.e.,... Figure 2The current at Vin1 shown), the output control current of the differential voltage modulation branch (i.e. Figure 2 The current at Vin2 shown in the diagram.

[0037] like Figure 2 As shown, the external PWM signal is shaped sequentially by the first inverter INV1 and the second inverter INV2, and then drives the differential switching network composed of PM1 / NM5 and PM2 / NM6 to select a path, thereby dynamically controlling the current extraction path of the second digital bias current source IBP2. When the PWM is in the conduction period (i.e., alternately outputting high-level and low-level signals), the differential switching network performs corresponding switching actions based on the PWM signal, causing a specific current to flow through the first resistor R4 (and parallel capacitor C2) on the main circuit. At this time, an adjustable voltage drop is generated on R4 based on VREF, thus forming reference currents of different levels. Since the differential switching network composed of PM1 / NM5 and PM2 / NM6 can support more than 16 switching state combinations, 16 different levels of bias current can be provided to the second digital bias current source through external digital training period control, achieving 16-level current control from 2.5mA to 40mA. At this time, the reference... Figure 3 As shown, the reference current is finally amplified by a predetermined ratio through a current mirror (such as NM2, NM1) and converted into the actual output LED driving current on NM4.

[0038] At the same time, such as Figure 2 As shown, a first constant current source IBP3 is introduced into the second terminal of the first resistor R4. IBP3 continuously draws a small current downwards, ensuring that even when the PWM is low (the main drive current should be off), a fixed small voltage drop is maintained across resistor R4. At this time, when the PWM is high, the voltage Vin2 at the second output terminal satisfies the following relationship: ; in, Let R4 be the resistance value of the first resistor. The bias current provided at the second digital bias current source IBP2. The current drawn by the first constant current source, This is the total control current.

[0039] At this point, according to the above formula, due to the continuous existence of IBP3, even if the PWM duty cycle is 0, a very small effective voltage difference will still be maintained between Vin1 (statically close to VREF) and Vin2. This voltage difference will be converted into a fixed, tiny idle current for the LED in the subsequent current mirror drive circuit module, ensuring that the LED is always in a micro-conduction ready state, completely eliminating the parasitic capacitance charging and discharging delay caused by deep shutdown, and achieving a microsecond-level delay-free response to high-frequency optical communication pulses.

[0040] The slew rate formula for the first voltage follower, Follower01, is as follows: .

[0041] in, This represents the slew rate of Follower01. This refers to the capacitance value of the internal node capacitor of Follower01. The bias current supplied at the first digital bias current source; therefore, it can be adjusted... The current value is used to limit the voltage, so that the square wave edge of the reference voltage Vin2 becomes a controlled trapezoidal slope, thereby smoothing the rising and falling edges of the tens of milliamps of LED main drive current. The above embodiments of this application reduce the high-frequency harmonic energy brought by di / dt from the reference source, which can further improve the electromagnetic compatibility of low EMI without increasing the power consumption of high-power nodes.

[0042] like Figure 3 As shown, in the current mirror drive circuit module, the non-inverting input (+) of the first operational amplifier AMP01 is connected to the current sensing terminal Vin1, and the inverting input (-) of AMP01 is connected to the reference voltage Vin2. The output of AMP01 drives the gate of the reference transistor NM2. When NM2 is turned on, the pulled current flows sequentially through the Vin1 port, the common-gate protection power transistor NM1 (whose gate is connected to the bias VB), and then to ground. At this time, according to the "virtual short" principle of deep negative feedback of the operational amplifier, AMP01 will continuously adjust the pull-down current of NM2, forcing the potential of its non-inverting terminal (Vin1) to be pulled down to be equal to the potential of its inverting terminal (Vin2). Since the Vin1 port is directly connected to the fourth resistor R1, the actual voltage drop across R1 is precisely locked to VREF - Vin2. The resulting precise reference current is: ; in, This refers to the current at Vin1 (i.e., the first output terminal). This is the voltage at the second output terminal. Let R1 be the resistance value of the fourth resistor. At this time, as... Figure 2 As shown, since the reference transistor NM2 and the main power transistor NM4 are connected to form a current mirror, NM4 mirrors and replicates the above reference current according to the device width-to-length ratio N. That is, the main driving current of the LED satisfies the following formula: ; Therefore, based on and The aspect ratio N of the device can be determined.

[0043] Reference Figure 3 As shown, due to the addition of a second operational amplifier AMP02 and a cascaded power transistor NM3 in the current mirror drive circuit module, the drain potential of NM2 can be monitored through the non-inverting input (+) of AMP02, and the drain potential of the main power transistor NM4 can be monitored through the inverting input (-) of AMP02. When the drain voltage of NM4 attempts to change due to external power supply or load fluctuations, AMP02 reverse-adjusts the gate of NM3 to form a deep negative feedback, clamping the drain voltage of NM4 to be equal to the drain voltage of NM2 (i.e., forcing VDS,NM4 = VDS,NM2). Therefore, the negative feedback loop composed of AMP02 and NM3 increases the output impedance Rout_total of the entire constant current source, which is as follows: ; in, This represents the open-loop gain of the op-amp. Indicates the transconductance of NM3, This indicates the output resistance of NM3. This represents the output resistance of NM4. Therefore, as shown in the above formula, this negative feedback loop mechanism will reduce the output impedance. The open-loop gain of the operational amplifier was increased, ensuring the extreme stability of the optical communication pulse amplitude.

[0044] Among them, such as Figure 4 As shown, since the first operational amplifier AMP01 uses an amplifier with a low-impedance buffer stage on the NMOS input pair, it can provide a peak current for rapid charging when facing the huge gate parasitic capacitance of the large-size reference transistors NM2 and NM4, ensuring that the entire reference current loop has an extremely excellent large-signal transient setup capability during PWM dimming.

[0045] like Figure 4 As shown, AMP01 consists of a front-end composed of NMOS differential pairs NM11 and NM12 and PMOS current mirror loads PM3 and PM4. The DC gain formed by this differential pair and the current mirror loads... Satisfy the following formula: ; in, This represents the transconductance of the differential pair NM11 and NM12; This indicates the output resistance of NM12; This indicates the output resistance of PM4.

[0046] At the same time, such as Figure 4 As shown, since the first capacitor C3 and the second resistor R5 are connected across the gate of the third P-type power transistor PM5 and the drain of the fourth P-type power transistor PM6, a Miller compensation network can be formed to ensure the loop phase margin.

[0047] Meanwhile, since the drain of PM6 is connected to the output drive node (the base of Q1), it acts as an active pull-up transistor; the drain of NM13 is also connected to this node, acting as an active pull-down transistor. Furthermore, the gate of PM5 shares the pre-amplifier drive signal with PM6; and the drain of PM5 is connected across the source of the common-gate amplifier NM13; therefore, based on Kirchhoff's current law, the current at the source node of NM13 always satisfies the following relationship: ; in, The current flowing through NM13, The current flowing from PM5 to NM14. The current flows to NM14, and since NM14 is controlled by an internal bias network, it acts as a constant current sink. It is a constant bias current.

[0048] At this point, when pull-up drive is required: the gate voltages of PM5 and PM6 decrease, and their turn-on levels increase simultaneously. PM6 rapidly provides a large pull-up current (IPM6 surges), while the current flowing through PM5 (IPM5) also increases sharply. This is based on... As can be seen, since INM14 is constant, the pull-down current (INM13) flowing into NM13 will be rapidly reduced to a minimum or even shut off. At the output node, the current pushed in from above (PM6) increases, while the current pulled out from below (NM13) decreases. This synergistic effect of "pushing in and pulling out" causes the net charging current to the output node OUT to increase dramatically. Therefore, in this embodiment, PM5, PM6, NM13, and NM14 together constitute a feedforward push-pull cascode sub-circuit operating in Class A mode. This feedforward push-pull cascode sub-circuit can cleverly increase the equivalent transconductance to the sum of the transconductances of the two transistors without increasing the static current of the main branch, greatly enhancing the circuit's transient charging and discharging capability for the load. Combined with the low-impedance output buffer stage composed of emitter follower Q1 and static load NM15, AMP01 can provide a peak current for rapid charging when facing the huge gate parasitic capacitance of the large-size reference transistors NM2 and NM4, ensuring that the entire reference current loop has an extremely excellent large-signal transient setup capability during PWM dimming.

[0049] Simultaneously refer to Figure 5As shown, the preamplifier stage of the second operational amplifier AMP02 employs a folded cascode architecture based on PMOS input pairs to ensure compatibility with the low input common-mode range. Specifically, as... Figure 5 As shown, the differential input is converted into current by the PMOS pair PM11 and PM12, and then "folded down" and injected into the folded node (i.e., the drain of NM21 / NM23 and the source of NM20 / NM22) formed by NM21 and NM23 (current sources) and NM20 and NM22 (common gate transistors). The NM18 / NM19 branch on the left provides precise mirror bias for the common gate transistor and current source at the bottom (the gate of NM18 is connected to the gate of NM20 / NM22, and the gate of NM19 is connected to the gate of NM21 / NM23). At this time, the small-signal gain of this folded common-source common-gate stage is... for: ; in, .

[0050] in, Indicates the transconductance of PM11 and PM12; This indicates the output resistance of the folded cascode stage. Indicates the transconductance of NM22. This indicates the output resistance of the NM22; This indicates the output resistance of PM12; This represents the output resistance of NM23. Meanwhile, by introducing PM15 across the drain and source of the common gate transistor NM22, the gate bias voltage of PM15 is directly provided by the gate of the top bias transistor PM10. This establishes a constant DC voltage difference between the main signal node (i.e., the drain of NM22) driving the pull-up transistor PM16 and the secondary signal node (i.e., the source of NM22 / drain of NM23) driving the pull-down transistor NM24. This ensures that PM16 and NM24 (with the gate of NM24 connected to the source of NM22) in the output stage can simultaneously be in a slightly on standby state, forming a Class-AB active push-pull output. This allows APM02 to have a high gain-bandwidth product (GBW) and high slew rate (SR), enabling it to generate powerful dynamic pull-up / sink current and rapidly charge and discharge the parasitic gate capacitance of the main power drive transistor (NM3). This results in the main drive current mirror having an extremely wide closed-loop bandwidth and microsecond-level response capability. When high-level compensation is required (the drain voltage of the main power transistor drops instantaneously): the folding node voltage drops collectively, PM16 is strongly turned on, providing a large pull-up source current, while NM24 is quickly turned off. When low-level compensation is required (the drain voltage of the main power transistor rises instantaneously): the node voltage rises, and through the coupling shift of PM15, NM24 is strongly turned on, providing a large pull-down sink current, while PM16 is turned off. Therefore, the AMP02 in this embodiment can provide peak current in transient response that is not limited by static power consumption. Combined with the extremely high open-loop gain derived above, this clamping loop achieves microsecond-level delay-free precise clamping, completely suppressing the interference of external digital PWM dimming and power supply fluctuations on the current mirror accuracy.

[0051] At this time, refer to Figure 6 As shown, Figure 6 The diagram illustrates a DC sweep waveform showing the LED drive current increasing progressively with each digital register control word (0 to 15). The curve exhibits a remarkably linear upward trend, successfully covering a wide dynamic range of nearly 40 mA. According to the difference vernier data in the figure, when the horizontal axis span Δx = 2.0, the corresponding current change Δy stabilizes at approximately 4.82 mA, meaning the single-step current (slope) of adjacent digital codes remains consistently around 2.41 mA. Therefore, this embodiment achieves extremely high resolution and linearity in the indirect control link of "weak differential voltage modulation → closed-loop conversion → current mirroring".

[0052] At the same time, refer to Figure 7 As shown, Figure 7 The transient drive waveform is shown under PWM modulation, set to a target level of 20 mA. For example... Figure 7As shown, during the pulse turn-off period (low level), the drive current did not drop to 0 mA, but remained stably at a valley current of approximately 0.8 mA (803.164 μA). Therefore, the pre-bias mechanism introduced by IBP3 in this embodiment successfully establishes a fixed, small idle current, enabling the drive link to remain slightly conductive even in the "off" state. This eliminates the dead time caused by deep charging and discharging of parasitic capacitance, supporting extremely high baud rates for optical communication transmission. Furthermore, during PWM conduction, the peak current is precisely and smoothly locked at the set target level of 20 mA, with the pulse top exhibiting an extremely flat "flat-top" characteristic, without any obvious ripple or drift over time. Therefore, the adjustable cascode feedback loop composed of the auxiliary operational amplifier AMP02 and the high-voltage cascaded transistor in this embodiment has a strong constant voltage clamping effect. This architecture increases the output impedance of the drive stage by the operational amplifier's open-loop gain multiple, completely suppressing the channel length modulation effect of the main power transistor, ensuring absolute consistency of the optical communication signal amplitude, and effectively reducing the bit error rate.

[0053] At the same time, refer to Figure 8 As shown, Figure 8 The transient edge characteristics of the output current slew rate of the first voltage follower as a function of the digital control range are demonstrated under a fixed 20mA output. Figure 8 The M-point cursor extracted the quantized slew rate values ​​(unit: kA / s, equivalent to mA / μs) at four different bias levels, as shown below. Figure 8 As shown, the quantized slew rate values ​​corresponding to the four different bias levels exhibit a controlled, stepped distribution. Therefore, in this embodiment, the transient jump slope (di / dt) of the high-power output current can be quantitatively adjusted simply by switching the IBN3 control word within the low-voltage buffer. This embodiment allows the system to actively soften edges to reduce high-frequency harmonic radiation (EMI) under harsh EMC testing environments, and restore steep edges when pursuing the ultimate baud rate, thereby achieving an intelligent dynamic compromise between optical communication speed and electromagnetic compatibility.

[0054] It is understood that a light emitting device provided according to an embodiment of this application includes a control circuit for a light-emitting diode as described above.

[0055] This application does not limit the specific type of optical emitting device. In some embodiments, the optical emitting device may be such as an optical communication lamp, vehicle headlight, traffic light, industrial explosion-proof optical communication equipment, IoT optical wireless node, wearable device, etc. This application will not elaborate on these specific types of devices.

[0056] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A control circuit for a light-emitting diode, characterized in that, include: A voltage modulation circuit module includes a reference voltage branch and a differential voltage modulation branch. The input terminals of both the reference voltage branch and the differential voltage modulation branch are electrically connected to the same first electrical node. The differential voltage modulation branch includes a differential voltage modulation main sub-branch and a differential switch sub-branch. The differential voltage modulation main sub-branch includes a first resistor, a first voltage follower, a first digital bias current source, and a first constant current source. The first and second terminals of the first resistor are respectively connected to the first electrical node and the non-inverting input terminal of the first voltage follower. The inverting input terminal of the first voltage follower and the... The output terminal is connected, the tail current bias pin of the first voltage follower is connected to the first digital bias current source; the first terminal of the first constant current source is connected between the second terminal of the first resistor and the non-inverting input terminal of the first voltage follower, the second terminal of the first constant current source is grounded, the two current extraction terminals of the differential switch sub-branch are respectively connected to the first terminal and the second terminal of the first resistor; the control terminal of the differential switch sub-branch is used to receive pulse width modulation (PWM) signals, and the current bias terminal of the differential switch sub-branch is connected to the first terminal of the second digital bias current source to adjust the reference current output by the reference voltage branch to a preset level; A current mirror drive circuit module, wherein the two drive input terminals of the current mirror drive circuit module are respectively connected to the first output terminal of the reference voltage branch and the second output terminal of the first voltage follower. When the PWM signal is high, the voltage difference between the output of the first voltage follower and the first electrical node is equal to the product of the first resistor and the total control current, where the total control current is the sum of the currents provided by the second digital bias current source and the first constant current source.

2. The control circuit for the light-emitting diode according to claim 1, characterized in that, The current mirror driving circuit module includes a first operational amplifier, a reference power transistor, a common-gate protection power transistor, and a main power transistor. The non-inverting input and inverting input of the first operational amplifier are connected to the first output and the second output, respectively. The output of the first operational amplifier is connected to the gate of the reference power transistor. The source of the reference power transistor is grounded. The drain of the reference power transistor is connected to the source of the common-gate protection power transistor. The drain of the common-gate protection power transistor is connected between the first output and the non-inverting input of the first operational amplifier. The gate of the common-gate protection power transistor is connected to an external bias voltage. The gate of the main power transistor is connected to the gate of the reference power transistor. The source of the main power transistor is grounded. The drain of the main power transistor is used to electrically connect to the first terminal of the light-emitting diode (LED). The main power transistor is used to mirror the reference current of the first output according to the device aspect ratio.

3. The control circuit for the light-emitting diode according to claim 2, characterized in that, The current mirror drive circuit module further includes a second operational amplifier and a cascaded power transistor; the drain of the cascaded power transistor is used to connect to the first terminal of the LED; the source of the cascaded power transistor is connected to the drain of the main power transistor, the gate of the cascaded power transistor is connected to the output terminal of the second operational amplifier, the non-inverting input terminal of the second operational amplifier is connected between the source of the common-gate protection power transistor and the drain of the reference power transistor, and the inverting input terminal of the second operational amplifier is connected between the source of the cascaded power transistor and the drain of the main power transistor.

4. The control circuit for the light-emitting diode according to claim 2, characterized in that, The first operational amplifier includes a first N-type power transistor, a second N-type power transistor, a first P-type power transistor, a second P-type power transistor, a feedforward push-pull cascode sub-circuit, a first bias control sub-circuit, a transistor, and a third N-type power transistor. The gate of the first N-type power transistor is connected to the second output terminal, and the gate of the second N-type power transistor is connected to the first output terminal. The sources of both the first N-type and second N-type power transistors are connected to the first control terminal of the first bias control sub-circuit. The drain of the first N-type power transistor is connected to the drain of the first P-type power transistor, and the gate of the first P-type power transistor is connected to the drain of the first P-type power transistor. The gate of the first P-type power transistor is connected to the gate of the second P-type power transistor, and the drains of the first P-type and second P-type power transistors are connected. The upper bridge arm of the feedforward push-pull cascode sub-circuit is connected to the collector of the transistor; the upper control terminal of the feedforward push-pull cascode sub-circuit is connected between the second P-type power transistor and the second N-type power transistor; the lower control terminal of the feedforward push-pull cascode sub-circuit is connected to the second control terminal of the first bias control sub-circuit; the feedforward control terminal of the feedforward push-pull cascode sub-circuit is connected to the third control terminal of the first bias control sub-circuit; the base of the transistor is connected to the pull-up node of the feedforward push-pull cascode sub-circuit; the emitter of the transistor is connected to the gate of the reference power transistor and the drain of the third N-type power transistor; the gate of the third N-type power transistor is connected to the fourth control terminal of the first bias control sub-circuit; and the source of the third N-type power transistor is grounded.

5. The control circuit for the light-emitting diode according to claim 4, characterized in that, The feedforward push-pull common-source common-gate sub-circuit includes a third P-type power transistor, a fourth P-type power transistor, a common-gate amplifier power transistor, and a fourth N-type power transistor. The gates of the third and fourth P-type power transistors serve as upper control terminals and are connected between the drains of the second P-type and second N-type power transistors. The sources of the fourth and third P-type power transistors serve as upper bridge arm connections and are connected to the collectors of the transistors. The gate of the common-gate amplifier power transistor serves as the lower control terminal and is connected to the second control terminal of the first bias control sub-circuit. The drain of the common-gate power amplifier is connected to the drain of the fourth P-type power transistor, the source of the common-gate power amplifier is connected to the drain of the fourth N-type power transistor, the source of the fourth N-type power transistor is grounded, and the gate of the fourth N-type power transistor is connected as a feedforward control terminal to the third control terminal of the first bias control sub-circuit. The drain of the third P-type power transistor is connected between the source of the common-gate power amplifier and the drain of the fourth N-type power transistor, and the pull-up node is located between the drain of the fourth P-type power transistor and the drain of the common-gate power amplifier.

6. The control circuit for a light-emitting diode according to claim 5, characterized in that, The feedforward push-pull common source cascode sub-circuit further includes a second resistor and a first capacitor connected in series. The first end of the second resistor, away from the first capacitor, is connected between the gate of the fourth P-type power transistor and the drain of the second P-type power transistor. The first end of the first capacitor, away from the second resistor, is connected between the drain of the fourth P-type power transistor and the pull-up node.

7. The control circuit for a light-emitting diode according to claim 3, characterized in that, The second operational amplifier includes a fifth P-type power transistor, a sixth P-type power transistor, a seventh P-type power transistor, an eighth P-type power transistor, a ninth P-type power transistor, a tenth P-type power transistor, an eleventh P-type power transistor, a twelfth P-type power transistor, a thirteenth P-type power transistor, a fourteenth P-type power transistor, a fifth N-type power transistor, a sixth N-type power transistor, a seventh N-type power transistor, an eighth N-type power transistor, and a ninth N-type power transistor; the gate of the fifth P-type power transistor serves as the inverting input terminal of the second operational amplifier and is connected between the source of the cascaded power transistors and the drain of the main power transistor; the gate of the sixth P-type power transistor serves as the non-inverting input terminal of the second operational amplifier and is connected to the common... The source of the gate-protected power transistor is connected to the drain of the reference power transistor; the drain of the fifth P-type power transistor is connected between the source of the fifth N-type power transistor and the drain of the sixth N-type power transistor; the drain of the sixth P-type power transistor is connected between the source of the seventh N-type power transistor and the drain of the eighth N-type power transistor; the sources of the fifth P-type power transistor and the sixth P-type power transistor are both connected to the drain of the seventh P-type power transistor; the gate of the seventh P-type power transistor is connected to the gate of the eighth P-type power transistor; the gate of the eighth P-type power transistor is connected to the drain of the eighth P-type power transistor; the source of the eighth P-type power transistor is connected to the drain of the ninth P-type power transistor. The drain and gate of the ninth P-type power transistor are connected, the gate of the ninth P-type power transistor is connected to the gate of the tenth P-type power transistor, the drain of the tenth P-type power transistor is connected to the source of the seventh P-type power transistor, the drain and gate of the eleventh P-type power transistor are connected to the drain of the fifth N-type power transistor, the gate of the eleventh P-type power transistor is also connected to the gate of the twelfth P-type power transistor, the drain of the twelfth P-type power transistor is connected to the drain of the seventh N-type power transistor and the gate of the thirteenth P-type power transistor, and the thirteenth P-type power transistor, the twelfth P-type power transistor, and the eleventh P-type power transistor are connected. The sources of the P-type power transistor, the tenth P-type power transistor, and the ninth P-type power transistor are interconnected; the drain of the thirteenth P-type power transistor serves as the output terminal of the second operational amplifier and is connected to the gate of the cascaded power transistor and the drain of the ninth N-type power transistor; the gate of the ninth N-type power transistor is connected between the source of the seventh N-type power transistor and the drain of the eighth N-type power transistor; the drain of the fourteenth P-type power transistor is connected to the source of the seventh N-type power transistor; the source of the fourteenth P-type power transistor is connected between the drain of the twelfth P-type power transistor and the drain of the seventh N-type power transistor; and the gate of the fourteenth P-type power transistor is used to connect to the bias voltage.

8. The control circuit for a light-emitting diode according to claim 7, characterized in that, The gate of the fourteenth P-type power transistor is connected between the gate of the eighth P-type power transistor and the gate of the seventh P-type power transistor.

9. The control circuit for a light-emitting diode according to claim 1, characterized in that, The differential switch sub-branch includes a first inverter and a second inverter, a fifteenth P-type power transistor, a sixteenth P-type power transistor, a tenth N-type power transistor, an eleventh N-type power transistor, and a third resistor. The source of the tenth N-type power transistor, the drain of the fifteenth P-type power transistor, the drain of the sixteenth P-type power transistor, and the source of the eleventh N-type power transistor are all connected to the first terminal of the second digital bias current source. The gate of the tenth N-type power transistor and the gate of the sixteenth P-type power transistor are connected. The drain of the tenth N-type power transistor and the source of the fifteenth P-type power transistor are connected to the first terminal of the third resistor. The second terminal of the third resistor is connected to the first terminal of the first resistor. Between the first electrical node and the source of the sixteenth P-type power transistor and the drain of the eleventh N-type power transistor, the source of the sixteenth P-type power transistor and the drain of the eleventh N-type power transistor are connected between the second end of the first resistor and the first end of the first constant current source; the gate of the eleventh N-type power transistor is connected between the output of the second inverter and the gate of the fifteenth P-type power transistor, the gate of the fifteenth P-type power transistor is connected to the output of the second inverter, the input of the second inverter is connected to the output of the first inverter, the output of the first inverter is also connected between the gate of the tenth N-type power transistor and the gate of the sixteenth P-type power transistor, and the input of the first inverter is used to receive the PWM signal.

10. A light emitting device, characterized in that, The control circuit for the light-emitting diode as described in any one of claims 1 to 9.

Images