Semiconductor device and method of manufacturing the same, memory, storage system

Abstract

The disclosure provides a semiconductor device and a preparation method thereof, a memory and a storage system, and relates to the technical field of semiconductor chips, and aims at the storage density of the semiconductor device. The semiconductor device comprises a plurality of device units arranged in a first direction. The device unit comprises a first semiconductor structure, a second semiconductor structure and an interconnection layer. The first semiconductor structure comprises a peripheral circuit. The second semiconductor structure is coupled to one side of the first semiconductor structure in the first direction, and the second semiconductor structure comprises a storage array connected with the peripheral circuit. The interconnection layer is located on the side of the first semiconductor structure away from the second semiconductor structure; the interconnection layer is connected with the peripheral circuit. The semiconductor device further comprises a connecting structure, and the semiconductor device comprises a first surface on one side in the first direction, and one connecting structure is located between the first surface and the interconnection layer of one device unit. The above semiconductor device is applied to a memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method, a memory, and a storage system. Background Technology

[0002] Planar semiconductor devices (such as memory) can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. 3D semiconductor device architectures can address some of the density limitations in planar semiconductor devices, such as flash memory devices.

[0003] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and vertically interconnecting them. Compared with conventional planar semiconductor devices, 3D semiconductor devices have smaller size and higher density, thus achieving performance improvements. Summary of the Invention

[0004] On one hand, a semiconductor device is provided. The semiconductor device includes: a plurality of device units stacked along a first direction, the first direction being the thickness direction of the semiconductor device. Each device unit includes a first semiconductor structure, a second semiconductor structure, and an interconnect layer. The first semiconductor structure includes peripheral circuitry. The second semiconductor structure is coupled to one side of the first semiconductor structure along the first direction, and the second semiconductor structure includes a memory array connected to the peripheral circuitry. The interconnect layer is located on the side of the first semiconductor structure away from the second semiconductor structure; the interconnect layer is connected to the peripheral circuitry. The semiconductor device further includes a connection structure disposed on one side of the peripheral circuitry and the memory array along a second direction, the second direction intersecting the first direction. The semiconductor device includes a first surface on one side of the first direction, and a connection structure is located between the first surface and the interconnect layer of one device unit.

[0005] In some embodiments, the semiconductor device includes a core region and a peripheral region arranged along a second direction; a memory array and peripheral circuits of multiple device units are disposed in the core region; and multiple connection structures are disposed in the peripheral region.

[0006] In some embodiments, the connection structure extends through the first semiconductor structure and the second semiconductor structure of the target device cell and is connected to the interconnect layer of the target device cell. The peripheral circuitry and memory array of the target device cell are disposed on one side of the connection structure along the second direction.

[0007] In some embodiments, the connection structure is disposed on the side of the first semiconductor structure and the second semiconductor structure of the target device unit near the first surface; along the first direction, the connection structure has a spacing with the peripheral circuit of the target device unit, and the connection structure has a spacing with the memory array of the target device unit.

[0008] In some embodiments, the first semiconductor structure further includes: a first dielectric portion disposed on one side of the peripheral circuit along a second direction and penetrating the first semiconductor structure along a first direction. The second semiconductor structure further includes: a second dielectric portion disposed on one side of the memory array along the second direction and penetrating the second semiconductor structure along the first direction. The second dielectric portions of the plurality of device units at least partially overlap with the first dielectric portions of the plurality of device units along the first direction. The connection structure penetrates at least one of the plurality of first dielectric portions and the plurality of second dielectric portions; or, the first dielectric portions and second dielectric portions of the plurality of device units are disposed on the side of the connection structure away from the first surface.

[0009] In some embodiments, in the same device unit, the first semiconductor structure is closer to the first surface than the second semiconductor structure; or, in the same device unit, the second semiconductor structure is closer to the first surface than the first semiconductor structure.

[0010] In some embodiments, the semiconductor device further includes a first bonding layer disposed between two adjacent device cells. The connection structure extends through the first bonding layer located on the side of the target device cell closest to the first surface.

[0011] In some embodiments, the device unit further includes a first dielectric layer located on the side of the interconnect layer away from the peripheral circuit. The connection structure extends through the first dielectric layer of the target device unit; or, the connection structure is located on the side of the first dielectric layer of the target device unit closer to the first surface.

[0012] In some embodiments, the first semiconductor structure further includes a second bonding layer located on the side of the peripheral circuit near the second semiconductor structure. The second bonding layer includes a plurality of second bonding contacts that penetrate the second bonding layer along a first direction. The second semiconductor structure further includes a third bonding layer located on the side of the memory array near the first semiconductor structure. The third bonding layer includes a plurality of third bonding contacts that penetrate the third bonding layer along a first direction; one third bonding contact is connected to one second bonding contact. The connection structure penetrates the second and third bonding layers on the side of the interconnect layer of the target device cell near the first surface, and avoids the second and third bonding contacts.

[0013] In some embodiments, the first semiconductor structure further includes a substrate layer located between the peripheral circuit and the interconnect layer. The substrate layer includes a connection contact; the connection contact extends through the substrate layer along a first direction, with one end of the connection contact connected to the peripheral circuit and the other end connected to the interconnect layer.

[0014] In some embodiments, the interconnect layer includes interconnects connected to the connection structure, and the material of the interconnects includes a metallic material.

[0015] On the other hand, a memory is provided. The memory includes a logic chip and a semiconductor device as described above. The logic chip is coupled to the semiconductor device.

[0016] In some embodiments, the first surface of the semiconductor device faces the logic chip; one end of the connection structure near the first surface is connected to the logic chip.

[0017] In some embodiments, the semiconductor device further includes a fourth bonding layer. The fourth bonding layer includes a plurality of fourth bonding contacts that penetrate the fourth bonding layer along a first direction; one fourth bonding contact is connected to one end of a connection structure near the first surface. The logic chip includes a fifth bonding layer. The fifth bonding layer includes a plurality of fifth bonding contacts that penetrate the fifth bonding layer along a first direction; one fifth bonding contact is connected to one fourth bonding contact.

[0018] In another aspect, a storage system is provided. The storage system includes a controller and a memory as described above. The controller is coupled to the memory.

[0019] In another aspect, a method for fabricating a semiconductor device is provided. The method includes: forming a device unit. Forming the device unit includes: forming a first semiconductor structure, the first semiconductor structure including peripheral circuitry; forming a second semiconductor structure and coupling the second semiconductor structure to one side of the first semiconductor structure along a first direction, the first direction being the thickness direction of the semiconductor device, the second semiconductor structure including a memory array connected to the peripheral circuitry; and forming an interconnect layer on the side of the first semiconductor structure away from the second semiconductor structure, the interconnect layer being connected to the peripheral circuitry. The fabrication method further includes: stacking a plurality of device units along the first direction; forming a connection structure on one side of the peripheral circuitry and the memory array along a second direction, the second direction intersecting the first direction. The semiconductor device includes a first surface on one side of the first direction, and a connection structure is located between the first surface and the interconnect layer of a device unit.

[0020] In some embodiments, stacking multiple device units along a first direction includes: sequentially connecting multiple device units along the first direction using a direct bonding process.

[0021] In some embodiments, during the formation of a connection structure on one side of the peripheral circuit and the memory array along the second direction, the connection structure penetrates the first semiconductor structure and the second semiconductor structure of the target device unit until it is connected to the interconnect layer of the target device unit; or, the connection structure is connected to the interconnect layer of the target device unit but does not penetrate the first semiconductor structure and the second semiconductor structure of the target device unit.

[0022] In some embodiments, forming the first semiconductor structure further includes: forming a first dielectric portion on one side of the peripheral circuit along a second direction, the first dielectric portion penetrating the first semiconductor structure along a first direction. Forming the second semiconductor structure further includes: forming a second dielectric portion on one side of the memory array along a second direction, the second dielectric portion penetrating the second semiconductor structure along a first direction. The second dielectric portions of the plurality of device units at least partially overlap with the first dielectric portions of the plurality of device units along the first direction.

[0023] In some embodiments, after stacking multiple device units along a first direction, within the same device unit, a first semiconductor structure is located on a second semiconductor structure, and the upper surface of the uppermost first semiconductor structure forms a first surface. The fabrication method further includes, after stacking multiple device units along the first direction, etching a first dielectric portion and a second dielectric portion of the multiple device units from the first surface to form contact holes; forming a connection structure in the contact holes; flipping the multiple device units; and connecting a logic chip to the first surface.

[0024] In some embodiments, after stacking multiple device units along a first direction, within the same device unit, a first semiconductor structure is located on a second semiconductor structure, and the bottom surface of the lowermost second semiconductor structure forms a first surface. The fabrication method further includes: flipping the multiple device units so that the first surface faces upward; etching a first dielectric portion and a second dielectric portion of the multiple device units from the first surface to form contact holes; forming a connection structure in the contact holes; flipping the multiple device units; and connecting a logic chip to the first surface.

[0025] In some embodiments, after forming an interconnect layer on the side of the first semiconductor structure away from the second semiconductor structure, the fabrication method further includes forming a first dielectric layer on the side of the interconnect layer away from the first semiconductor structure.

[0026] In some embodiments, forming a first semiconductor structure includes: forming a peripheral circuit on a first substrate; and forming a second bonding layer on a side of the peripheral circuit away from the first substrate. The second bonding layer includes a plurality of second bonding contacts that penetrate the second bonding layer along a first direction; the second bonding contacts avoid connection structures to be formed. Forming a second semiconductor structure includes: forming a memory array on a second substrate; and forming a third bonding layer on a side of the memory array away from the second substrate. The third bonding layer includes a plurality of third bonding contacts that penetrate the third bonding layer along a first direction; the third bonding contacts avoid connection structures to be formed. Coupling the second semiconductor structure to a side of the first semiconductor structure along the first direction includes: connecting the second bonding layer and the third bonding layer such that one second bonding contact is connected to one third bonding contact.

[0027] In some embodiments, before forming an interconnect layer on the side of the first semiconductor structure away from the second semiconductor structure, the fabrication method further includes: forming a connection contact that penetrates the first substrate, so that the connection contact is connected to a peripheral circuit. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0029] Figure 1 This is a structural diagram of a memory provided according to some embodiments;

[0030] Figure 2 This is a structural diagram of a device unit provided according to some embodiments;

[0031] Figure 3 This is a structural diagram of a storage array provided according to some embodiments;

[0032] Figure 4A This is an equivalent circuit diagram of a semiconductor device provided according to some embodiments;

[0033] Figure 4B This is yet another equivalent circuit diagram of a semiconductor device provided according to some embodiments;

[0034] Figure 5 This is a structural diagram of a semiconductor device provided according to some embodiments;

[0035] Figure 6 This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0036] Figure 7A This is a structural diagram of a memory provided according to some embodiments;

[0037] Figure 7B This is yet another structural diagram of a memory provided according to some embodiments;

[0038] Figure 8A This is a structural diagram of a storage system provided according to some embodiments;

[0039] Figure 8B This is another structural diagram of a storage system provided according to some embodiments;

[0040] Figure 9This is a structural diagram of an electronic device provided according to some embodiments;

[0041] Figure 10 This is yet another structural diagram of an electronic device provided according to some embodiments;

[0042] Figure 11 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0043] Figures 12A to 13E This diagram illustrates some steps in a method for fabricating a semiconductor device according to some embodiments. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0046] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0047] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0048] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0049] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0050] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0051] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0052] It should be noted that the labels "A~B" in the attached diagram indicate that structure / region A belongs to structure / region B. That is, the structure referred to by the label is both structure A and structure B. For example, Figure 3 The term "221-220" refers to the structure indicated by the number, which is memory array 221. Memory array 221 belongs to the second semiconductor structure 220.

[0053] The semiconductor structures disclosed herein are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device structure may include memory, including but not limited to Dynamic Random Access Memory (DRAM). The following description uses DRAM as an example only. However, it should be noted that the following descriptions of DRAM are merely illustrative of some embodiments of this disclosure and are not intended to limit the scope of those embodiments.

[0054] Figure 1 This is a possible structural diagram of the semiconductor device 300 in some embodiments. (Refer to...) Figure 1 The semiconductor device 300 includes a plurality of device units 200 stacked along a first direction X, which is the thickness direction of the semiconductor device 300. In this case, the semiconductor device 300 is a 3D semiconductor device with a smaller size and higher storage density.

[0055] When the semiconductor device 300 includes multiple device units 200, the memory including the semiconductor device 300 can be a high-bandwidth memory (HBM).

[0056] Figure 2 This is a possible structural diagram of device unit 200 in some embodiments. (Refer to...) Figure 2 The device unit 200 includes a first semiconductor structure 210 and a second semiconductor structure 220. The first semiconductor structure 210 includes peripheral circuitry 211. The second semiconductor structure 220 is coupled to one side of the first semiconductor structure 210 along a first direction X, and the second semiconductor structure 220 includes a memory array 221, which is connected to the peripheral circuitry 211.

[0057] Based on the above structure, peripheral circuitry 211 is electrically connected to memory array 221. Peripheral circuitry 211 is configured to control and sense memory array 221. Peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of semiconductor device 300, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., Programmable Logic Device, PLD, processor, and programmable logic device) or memory circuitry (e.g., Static random-access memory, SRAM).

[0058] Figure 3 Here is a possible structural diagram of the storage array 221 in some embodiments, with reference to Figure 3 The storage array 221 includes a plurality of storage cells 100 arranged in an array. Each storage cell 100 includes a transistor 110 and a capacitor 120, and the stacking direction of the transistors 110 and capacitors 120 is, for example, a first direction X.

[0059] In some embodiments, refer to Figure 3 A transistor 110 and a capacitor 120 constitute a storage cell 100. At this time, the semiconductor device 300 has an architecture of one transistor (T) and one capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor 120, or the high and low voltage difference across the capacitor 120, to represent the logical 1 and 0.

[0060] For example, the unit cell size of storage cell 100 is, for example, 4F2 (2F×2F, also known as 4F2 cell size), that is, the cell configuration size of storage cell 100 is greater than or equal to 4 times the square of the minimum feature size F. In other words, storage array 221 can be arranged in an orthogonal layout with a cross-point orthogonal layout having a 4F2 cell size.

[0061] With a unit cell size of 4F2, the storage density can be improved compared to when the unit cell size of the storage cell 100 is 8F2 or 6F2.

[0062] In some embodiments, the capacitor 120 includes a first electrode structure, a second electrode structure, and a first dielectric layer. The first electrode structure and the second electrode structure are at least partially disposed opposite to each other, and the first dielectric layer is located between the opposing portions of the first electrode structure and the second electrode structure.

[0063] For example, the materials of the first electrode structure and / or the second electrode structure may include at least one selected from tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), tantalum nitride (TaN), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium oxide (RuO), and the rare metal gold (Au). Furthermore, the materials of the first electrode structure and the second electrode structure may be the same or different.

[0064] For example, the material of the first dielectric layer may include at least one of silicon oxide, silicon nitride, and high-k dielectrics, wherein the high-k dielectrics include, but are not limited to, aluminum oxide, hafnium oxide, tantalum pentoxide, zirconium oxide, titanium oxide, or any combination thereof.

[0065] In some embodiments, refer to Figure 3 The transistor 110 includes a channel structure 111, a gate dielectric layer 112, and a gate structure 113. The channel structure 111 extends along a first direction X. The gate structure 113 is disposed around the channel structure 111. The gate dielectric layer 112 is disposed between the channel structure 111 and the gate structure 113.

[0066] For example, the material of the channel structure 111 may include silicon or indium gallium zinc oxide (IGZO), etc.

[0067] Based on the above structure, transistor 110 includes a vertical gate, enabling semiconductor device 300 to have a vertical channel array transistor (VCAT) architecture, which can achieve higher storage density compared to other memory architectures (e.g., buried channel array transistor (BCAT)).

[0068] For example, the gate structure 113 can be used to apply a gate voltage to the transistor 110; the gate dielectric layer 112 can be used to isolate the gate structure 113 from the channel structure 111; thus, the control of the transistor 110 being turned on or off can be realized.

[0069] Here, the gate structure 113 is disposed around the channel structure 111, meaning that the gate structure 113 can surround at least a portion of the channel structure 111; for example, one or more sides of the channel structure 111 can be surrounded by the gate structure 113. In some examples, see... Figure 3 In transistor 110, the channel structure 111 is surrounded by a ring-shaped gate structure 113. Therefore, transistor 110 can also be referred to as a gate all-around transistor. In some examples, the gate structure 113 of transistor 110 is located on three sides of the channel structure 111, and in this case, transistor 110 can also be called a tri-gate transistor; in some examples, the gate structure 113 of transistor 110 is located on both sides of the channel structure 111, and in this case, transistor 110 can also be called a double-gate transistor; in some examples, the gate structure 113 of transistor 110 is located on one side of the channel structure 111, and in this case, transistor 110 can also be called a single-gate transistor; in some examples, the channel structures 111 of adjacent transistors 110 are separated by an isolation structure, and the gate structure 113 is located on the side of the channel structure 111 away from the isolation structure, and the gate structures 113 of adjacent transistors 110 are mirror-symmetrically distributed, and in this case, transistor 110 can also be called a mirror single-gate transistor.

[0070] Exemplarily, the gate structure 113 may include a gate electrode on and in contact with the gate dielectric layer 112. The gate electrode may comprise any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode may comprise doped polysilicon, which is a form of gate polysilicon. In some examples, the gate electrode may comprise multiple conductive layers (e.g., a W layer over a TiN layer).

[0071] For example, the gate dielectric layer 112 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon nitride oxide, or a high-k dielectric.

[0072] In some examples, refer to Figure 3 The transistor 110 also includes a source terminal 111a and a drain terminal 111b. The source terminal 111a and the drain terminal 111b are respectively located at two opposite ends of the channel structure 111 in the first direction X. One of the first electrode structure and the second electrode structure can be coupled to the source terminal 111a or the drain terminal 111b, and the other can be coupled to a reference voltage (e.g., coupled to ground). In this case, the capacitor 120 and its corresponding transistor 110 can constitute a memory cell 100.

[0073] For example, the source 111a and / or drain 111b can be formed by doping the channel structure 111; for example, by doping the channel structure 111 with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-dopant (e.g., phosphorus (P) or arsenic (As)).

[0074] In some embodiments, refer to Figure 2 and Figure 3 The semiconductor device 300 also includes bit lines 230 and gate lines 240, which are electrically connected to peripheral circuits 211, and gate structure 113 is electrically connected to gate lines 240.

[0075] Reference Figure 3 When transistor 110 includes a vertical gate, the area occupied by transistor 110 can be reduced, the layout of gate line 240 and bit line 230 can be simplified, and bit line 230 and capacitor 120 can be located on opposite sides of transistor 110, so that the process margin of bit line 230 is less restricted.

[0076] Transistor 110, capacitor 120, gate line 240 and bit line 230 can form a circuit structure to realize read or write operations of memory (e.g., dynamic random access memory).

[0077] The working principle of the circuit structure consisting of transistor 110, capacitor 120, gate line 240 and bit line 230 will be explained by way of example below.

[0078] Figure 4A This is an equivalent circuit diagram of a semiconductor device provided in some embodiments, the semiconductor device employing a 1T1C architecture. (Refer to...) Figure 4A One of the drain and source terminals of transistor T is electrically connected to the bit line BL, and the other is electrically connected to one of the electrode structures of capacitor C. The other electrode structure of capacitor C can be connected to a reference voltage. The gate structure of transistor T is connected to the gate line WL (also called the word line). By applying a voltage to the gate line WL, transistor T is controlled to be turned on or off. The bit line BL is used to perform read or write operations on the information stored in capacitor C when transistor T is turned on. In other words, the on and off states of transistor T determine whether reading and writing of the information stored in capacitor C is allowed or prohibited. Capacitor C is used to store data written to the memory cell.

[0079] although Figure 4AAn equivalent circuit diagram of a semiconductor device employing a 1T1C architecture is shown. However, it should be understood that this disclosure does not limit the architecture of the semiconductor device 300. For example, in other examples, the architecture of the semiconductor device 300 can be 1TnC, nT1C, 2TnC, or mTnC, where m and n can be the same or different; in other words, the semiconductor device 300 can be in a 1TnC, nT1C, 2TnC, or mTnC configuration. For example, refer to... Figure 4B In a 1TnC configuration, the memory cell of a semiconductor device may include n capacitors C-1, C-2, ..., Cn coupled to either the source or drain of a transistor T. That is, one electrode of each capacitor C-1, C-2, ..., Cn may be coupled to the same source / drain of the transistor T, and the other electrode of each capacitor C-1, C-2, ..., Cn may be coupled to a corresponding plate line among n plate lines CL-1, CL-2, ..., CL-n, such that each capacitor C-1, C-2, ..., or Cn can be individually controlled by the corresponding plate line CL-1, CL-2, ..., CL-n.

[0080] In some embodiments, to realize the storage function of the semiconductor device 300, the peripheral circuit 211 is connected to an external circuit structure located outside the semiconductor device 300 to realize signal transmission. For example, refer to Figure 1 Peripheral circuit 211 (see also) Figure 2 The logic chip 410 can be coupled to the logic circuit in the logic chip 410. In this case, the logic circuit is configured, for example, to receive data signals generated by the peripheral circuit 211, process and calculate the data signals, and / or to provide control signals to the peripheral circuit 211. Exemplarily, in practical applications, the logic chip 410 can be stacked on and coupled to the intermediate plate 520. In this case, control signals can be provided to the logic chip 410 through conductive bumps 521 on the side of the intermediate plate 520 away from the logic chip 410. After the logic circuit processes the control signals, they are transmitted to the semiconductor device 300.

[0081] In some embodiments, combined with Figure 2 , refer to Figure 1 The semiconductor device 300 also includes a front interconnect layer 224 disposed on the side of the second semiconductor structure 220 away from the first semiconductor structure 210. The front interconnect layer 224 includes front interconnect lines (not shown in the figure), and signal transmission between the external circuit structure and the peripheral circuit 211 is achieved through the front interconnect lines.

[0082] In some cases, in addition to the front interconnects, the front interconnect layer 224 also includes a front circuit structure, such as a memory control circuit coupled to the memory array 221. In this case, because there is a gap between the front interconnects and the front circuit structure in the front interconnect layer 224, the area of ​​the front interconnect layer 224 is larger, resulting in a larger area of ​​the semiconductor device 300. This is not conducive to the size compression of the semiconductor device 300, and the memory density of the semiconductor device 300 is lower. Moreover, there may be some interference between the signals transmitted by the front interconnects and the signals of the front circuit structure, which may affect the reliability of signal transmission between the external circuit structure and the peripheral circuit 211, thereby affecting the signal transmission effect.

[0083] In some embodiments, combined with Figure 2 , refer to Figure 1 The device unit 200 also includes a plurality of through contacts K1 (e.g., through silicon vias, TSVs) extending along a first direction X. The plurality of through contacts K1 overlapping in the first direction X are sequentially connected along the first direction X to form a signal transmission channel. Signal transmission between the external circuit structure and the peripheral circuit 211 is achieved through the through contacts K1 and the front interconnect. The through contacts K1 are connected to the front interconnect, for example, through bonding contacts K2 disposed on the same layer as the front interconnect. In some cases, multiple device units 200 (e.g., four device units 200) share the same signal transmission channel, resulting in slower signal transmission efficiency between the external circuit structure and the peripheral circuit 211, which may affect the signal transmission effect.

[0084] Based on this, some embodiments of this disclosure provide a semiconductor device 300, with reference to... Figure 5 and Figure 6 The device unit 200 includes an interconnect layer 250 located on the side of the first semiconductor structure 210 away from the second semiconductor structure 220; the interconnect layer 250 is connected to the peripheral circuit 211. The semiconductor device 300 also includes a connection structure 310 disposed on the side of the peripheral circuit 211 and the memory array 221 along a second direction Y, which intersects with the first direction X. The semiconductor device 300 includes a first surface 300a on the side along the first direction X, and a connection structure 310 is located between the first surface 300a and the interconnect layer 250 of the device unit 200.

[0085] For example, the second direction Y is perpendicular to the first direction X.

[0086] In some examples, the cross-sectional morphology of the semiconductor device 300 can be detected by semiconductor failure analysis (FA) slicing, and / or the structure of the semiconductor device 300 can be detected by scanning electron microscopy (SEM) to detect the interconnect layer 250 and the connection structure 310 in the semiconductor device 300.

[0087] In some examples, the number of connection structures 310 between the first surface 300a and the interconnect layer 250 of a device cell 200 is one; in other examples, the number of connection structures 310 between the first surface 300a and the interconnect layer 250 of a device cell 200 is multiple (e.g., two).

[0088] When a connection structure 310 is located between the first surface 300a and the interconnect layer 250 of a device unit 200, the end of the connection structure 310 away from the first surface 300a can be electrically connected to the interconnect layer 250; thus, the electrical connection between the connection structure 310 and the interconnect layer 250 can be achieved through a self-aligned contact (SCT) architecture. Furthermore, when the interconnect layer 250 is connected to the peripheral circuit 211, signal transmission between the external circuit structure and the peripheral circuit 211 can be achieved through the connection structure 310 and the interconnect layer 250.

[0089] Understandably, by positioning the interconnect layer 250 on the side of the first semiconductor structure 210 away from the second semiconductor structure 220, it is possible for the interconnect layer 250 to perform the function of a front-side interconnect in some embodiments, thereby eliminating the need for a front-side interconnect layer 224 (see reference). Figure 1 The structure of the front interconnects in the semiconductor device 300 reduces the area of ​​the front interconnect layer 224, which is beneficial for the size compression of the semiconductor device 300 and the higher storage density of the semiconductor device 300. Secondly, it can bring the interconnect layer 250 closer to the peripheral circuit 211, making the signal transmission distance between the external circuit structure and the peripheral circuit 211 shorter, which is beneficial for improving signal transmission efficiency and making the data transmission bandwidth wider (for example, the bandwidth can reach 2048). Thirdly, it can make the interconnect layer 250 relatively far away from other circuit structures. For example, the interconnect layer 250 is far away from the storage control circuit in the front interconnect layer 224. In this way, the signal interference between the interconnect layer 250 and other circuit structures can be reduced, which is beneficial for improving the reliability of signal transmission.

[0090] Furthermore, by setting a connection structure 310 between the first surface 300a and the interconnect layer 250 of a device unit 200, the connection structure 310 is connected to the interconnect layer 250 of the device unit 200. In other words, the connection structure 310 connected to the interconnect layers 250 of multiple device units 200 is independently set. In this way, multiple device units 200 can be independently connected to external circuit structures, enabling signals between multiple device units 200 and external circuit structures to be transmitted independently. This can improve the signal transmission efficiency between device units 200 and external circuit structures. For example, it can improve the transmission efficiency of control signals from the external circuit structure to the peripheral circuit 211; and for example, it can improve the transmission efficiency of data signals from the peripheral circuit 211. Thus, the data transmission bandwidth can be wider.

[0091] There are no restrictions on the connection method between the connection structure 310 and the interconnection layer 250.

[0092] In some embodiments, refer to Figure 5 and Figure 6 The interconnect layer 250 includes interconnect lines 251 connected to the connection structure 310.

[0093] For example, the interconnect layer 250 further includes one or more interlayer dielectric layers (ILDs), and one or more interconnect lines 251 are distributed in the interlayer dielectric layers.

[0094] When the interconnect layer 250 includes the interconnect line 251 described above, signal transmission between the device unit 200 and the external circuit structure can be achieved through the connection structure 310 and the interconnect line 251, thereby improving the feasibility of data transmission between the device unit 200 and the external circuit structure.

[0095] For example, the material of interconnect 251 may include any suitable conductive material, such as non-metallic conductor material, such as polysilicon.

[0096] In some embodiments, refer to Figure 5 and Figure 6 The material of interconnect 251 includes metallic materials.

[0097] For example, the metal material included in interconnect 251 may include at least one of tungsten (W), copper (Cu) and aluminum (Al).

[0098] Compared to non-metallic conductor materials, metallic materials have better thermal conductivity. Therefore, through the above arrangement, the heat generated by the first semiconductor structure 210 can be thermally conducted to the interconnect 251 and dissipated through the interconnect 251. In this way, the heat dissipation performance of the semiconductor device 300 can be improved, thereby enhancing the performance of the semiconductor device 300.

[0099] This disclosure does not limit the connection method between the peripheral circuit 211 and the interconnect layer 250. For example, the interconnect layer 250 can be in contact with the layer where the peripheral circuit 211 is located, in which case the interconnect layer 250 and the peripheral circuit 211 are directly connected.

[0100] In some embodiments, refer to Figure 5 and Figure 6 The first semiconductor structure 210 further includes a substrate layer 212 located between the peripheral circuit 211 and the interconnect layer 250. The substrate layer 212 includes a connection contact 2121; the connection contact 2121 extends through the substrate layer 212 along a first direction X, one end of the connection contact 2121 is connected to the peripheral circuit 211, and the other end is connected to the interconnect layer 250.

[0101] In some examples, the material of the substrate 212 can be monocrystalline silicon, or other suitable materials such as silicon-germanium, germanium, or silicon-on-insulator thin film.

[0102] Exemplarily, the connection contact 2121 includes one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some embodiments, the connection contact 2121 also includes an insulator (e.g., a dielectric material layer) to make the connection contact 2121 electrically insulated from the substrate layer 212.

[0103] For example, the peripheral circuit 211 may include peripheral transistors 2111 (e.g., multiple, see reference) formed on the substrate layer 212. Figure 2 In this process, all or part of the peripheral transistor 2111 is formed in the substrate 212 and / or directly on the substrate 212.

[0104] For example, the base layer 212 also includes at least one of a P-well region, an N-well region, and a depletion region.

[0105] For example, when the interconnect layer 250 includes interconnect line 251, the end of the connection contact 2121 that is away from the peripheral circuit 211 can be electrically connected to the interconnect line 251.

[0106] In some examples, the base layer 212 includes multiple interconnect contacts 2121, and the interconnect layer 250 includes multiple interconnect lines 251. In this case, an interconnect line 251 can be connected to a single interconnect contact 2121, and different interconnect contacts 2121 can be connected to different locations of the peripheral circuitry 211 (e.g., to different peripheral transistors 2111).

[0107] With the above configuration, the peripheral circuit 211 and the interconnect layer 250 can be connected through the connection contact 2121. At this time, signal transmission between the device unit 200 and the external circuit structure can be achieved through the connection structure 310, the interconnect layer 250, and the connection contact 2121, improving the feasibility of data transmission between the device unit 200 and the external circuit structure. Moreover, by including a substrate layer 212 in the first semiconductor structure 210, the process feasibility of forming the peripheral circuit 211 (e.g., including multiple peripheral transistors 2111) can be improved.

[0108] In some embodiments, refer to Figure 5 and Figure 6 The semiconductor device 300 includes a core region AA and a peripheral region SS arranged along the second direction Y; a memory array 221 of multiple device units 200 and peripheral circuits 211 are disposed in the core region AA; and multiple connection structures 310 are disposed in the peripheral region SS.

[0109] For example, refer to Figure 5 and Figure 6 The area where the storage array 221 is located and the area where the peripheral circuit 211 is located are overlapped in the first direction X.

[0110] With the above configuration, the arrangement space of the storage array 221, peripheral circuit 211 and connection structure 310 can be optimized, which can improve the structural compactness of the semiconductor device 300 and make the storage density of the semiconductor device 300 higher.

[0111] It should be understood that when the semiconductor device 300 includes multiple device units 200, the semiconductor device 300 includes multiple first semiconductor structures 210 and multiple second semiconductor structures 220.

[0112] The present disclosure does not limit the arrangement of the plurality of first semiconductor structures 210 and the plurality of second semiconductor structures 220.

[0113] In some embodiments, refer to Figure 5 and Figure 6Along the first direction X, the first semiconductor structures 210 and second semiconductor structures 220 of the plurality of device units 200 are arranged alternately. At this time, of the two surfaces of the semiconductor device 300 along the first direction X, the surface of the first semiconductor structure 210 located at the edge position, away from the second semiconductor structure 220, can be referred to as the front surface of the semiconductor device 300 (e.g., the front side). Figure 5 The bottom surface of the semiconductor device 300, for example, is Figure 6 The top surface of the semiconductor device 300; correspondingly, the surface of the interconnect layer 250 located at the edge position on the side away from the second semiconductor structure 220, can be referred to as the back surface of the semiconductor device 300 (e.g., the back surface of the semiconductor device 300). Figure 5 The top surface of the semiconductor device 300, for example, is Figure 6 (The bottom surface of the semiconductor device 300 in the middle).

[0114] Understandably, the first surface 300a can be either the front or back surface of the semiconductor device 300. That is, the connection structure 310 can be located between the front surface of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X, or it can be located between the back surface of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X. The target device unit 200X refers to the device unit 200 among a plurality of device units 200 that is connected to the connection structure 310.

[0115] The following will provide examples of the two scenarios. First, we will provide an example of the scenario where the connection structure 310 is located between the front side of the semiconductor device 300 and the interconnect layer 250 of the target device cell 200X.

[0116] In some embodiments, refer to Figure 5 In the same device unit 200, the second semiconductor structure 220 is closer to the first surface 300a than the first semiconductor structure 210.

[0117] At this time, in the same device unit 200, the first semiconductor structure 210 and the second semiconductor structure 220 are further away from the first surface 300a than the interconnect layer 250.

[0118] For example, refer to Figure 5 The device unit 200A includes a first semiconductor structure 210A, a second semiconductor structure 220A, and an interconnect layer 250A. The second semiconductor structure 220A is closer to the first surface 300a than the first semiconductor structure 210A. Moreover, the interconnect layer 250A is farther away from the first surface 300a than the first semiconductor structure 210A and the second semiconductor structure 220A.

[0119] In this case, in order to achieve the connection between the connection structure 310 and the interconnect layer 250 of the target device unit 200X, the connection structure 310 will penetrate the portion of the target device unit 200X located in the interconnect layer 250 near the first surface 300a.

[0120] Therefore, in some embodiments, reference is made to Figure 5 The connection structure 310 passes through the first semiconductor structure 210 and the second semiconductor structure 220 of the target device unit 200X and is connected to the interconnect layer 250 of the target device unit 200X. The peripheral circuit 211 and the memory array 221 of the target device unit 200X are disposed on one side of the connection structure 310 along the second direction X.

[0121] With the above configuration, the connection structure 310 can penetrate a portion of the semiconductor device 300 from the front side until it connects with the interconnect layer 250 of the target device unit 200X, thereby realizing signal transmission between the external circuit structure and the peripheral circuit 211 of the target device unit 200X.

[0122] The following example illustrates the case where the connection structure 310 is located between the back side of the semiconductor device 300 and the interconnect layer 250 of the target device cell 200X.

[0123] In some embodiments, refer to Figure 6 In the same device unit 200, the first semiconductor structure 210 is closer to the first surface 300a than the second semiconductor structure 220.

[0124] At this time, in the same device unit 200, the first semiconductor structure 210 and the second semiconductor structure 220 are closer to the first surface 300a than the interconnect layer 250.

[0125] For example, refer to Figure 5 The device unit 200B includes a first semiconductor structure 210B, a second semiconductor structure 220B, and an interconnect layer 250B. The first semiconductor structure 210B is closer to the first surface 300a than the second semiconductor structure 220B. Moreover, the interconnect layer 250B is closer to the first surface 300a than the first semiconductor structure 210B and the second semiconductor structure 220B.

[0126] In this case, the connection structure 310 can be connected to the interconnect layer 250 without penetrating the first semiconductor structure 210 and the second semiconductor structure 220 of the target device unit 200X.

[0127] Therefore, in some embodiments, reference is made to Figure 6The connection structure 310 is disposed on the side of the first semiconductor structure 210 and the second semiconductor structure 220 of the target device unit 200X near the first surface 300a; along the first direction X, the connection structure 310 and the peripheral circuit 211 of the target device unit 200X are spaced apart, and the connection structure 310 and the memory array 221 of the target device unit 200X are spaced apart.

[0128] With the above configuration, the connection structure 310 can extend from the back side of the semiconductor device 300 to the target device unit 200X and connect to the interconnect layer 250 of the target device unit 200X, thereby realizing signal transmission between the external circuit structure and the peripheral circuit 211 of the target device unit 200X.

[0129] Reference Figure 5 and Figure 6 Except for the connection structure 310 located between the back side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X, and the connection structure 310C (see reference) Figure 6 ) and the interconnect layer 250C located at the edge (see reference) Figure 6 In the absence of a connection, the connection structure 310 will penetrate at least one of the plurality of first semiconductor structures 210 and the plurality of second semiconductor structures 220 until it is connected to the interconnect layer 250 of the target device unit 200X.

[0130] In some examples, the first semiconductor structure 210 is formed on a first silicon substrate, and the second semiconductor structure 220 is formed on a second silicon substrate. The method for forming the interconnect structure 310 is as follows: first, a plurality of positioning holes are etched, some of which penetrate the first silicon substrate and / or the second silicon substrate; then, the plurality of positioning holes are filled to form the interconnect structure 310.

[0131] In this case, since the peripheral circuit 211 is formed on the first silicon substrate and the memory array 221 is formed on the second silicon substrate, during the etching process to form the positioning hole through the first silicon substrate and / or the second silicon substrate, the silicon substrate in the area where the peripheral circuit 211 and / or the memory array 221 are located may be etched, which will affect the peripheral circuit 211 and / or the memory array 221. Moreover, silicon material is more difficult to etch than other materials (e.g., silicon oxide), making the silicon substrate more difficult to etch, which may increase the process difficulty of forming the interconnect structure 310.

[0132] Here, in some embodiments, reference is made to Figure 5 and Figure 6The first semiconductor structure 210 further includes a first dielectric portion 213 disposed on one side of the peripheral circuit 211 along the second direction Y and penetrating the first semiconductor structure 210 along the first direction X. The second semiconductor structure 220 further includes a second dielectric portion 222 disposed on one side of the memory array 221 along the second direction Y and penetrating the second semiconductor structure 220 along the first direction X. The second dielectric portions 222 of the plurality of device units 200 at least partially overlap with the first dielectric portions 213 of the plurality of device units 200 along the first direction X.

[0133] In some examples, refer to Figure 6 The connection structure 310 is located between the back side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X, and the connection structure 310C is connected to the interconnect layer 250C located at the edge. At this time, the first dielectric portion 213 and the second dielectric portion 222 of the plurality of device units 200 are provided on the side of the connection structure 310C away from the first surface 300a.

[0134] In yet another example, refer to Figure 5 and Figure 6 The connection structure 310 is located between the back side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X, and the connection structure 310 is connected to the interconnect layer 250 located in the middle; or, the connection structure 310 is located between the front side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X; in both cases, the connection structure 310 passes through at least one of the plurality of first dielectric portions 213 and the plurality of second dielectric portions 222.

[0135] For example, the material of the first dielectric portion 213 is silicon oxide. For example, the material of the second dielectric portion 222 is silicon oxide.

[0136] For example, refer to Figure 5 and Figure 6 The second dielectric portion 222 of the plurality of device units 200 completely overlaps with the first dielectric portion 213 of the plurality of device units 200 along the first direction X.

[0137] With the above settings, during the formation of the connection structure 310, by controlling the etching parameters, the etching area can be limited to the area where the first dielectric portion 213 and the second dielectric portion 222 are located. In this way, the influence of the etching process on the area where the peripheral circuit 211 and / or the memory array 221 are located can be avoided. Moreover, when the material of the first dielectric portion 213 and / or the second dielectric portion 222 is silicon oxide, the process difficulty of forming the above-mentioned positioning hole can be reduced, thereby reducing the process difficulty of forming the connection structure 310.

[0138] The following will provide an exemplary description of the connection methods between the plurality of device units 200 in the semiconductor device 300, and the connection methods between the first semiconductor structure 210 and the second semiconductor structure 220.

[0139] In some embodiments, refer to Figure 5 and Figure 6 The semiconductor device 300 further includes a first bonding layer 320 disposed between two adjacent device units 200. The connection structure 310 penetrates the first bonding layer 320 located on the side of the target device unit 200X near the first surface 300a.

[0140] For example, the first bonding layer 320 is a direct bonding layer, and its material is a dielectric material. For example, the material of the first bonding layer 320 includes at least one of silicon oxide, silicon nitride, and silicon nitride carbon.

[0141] For example, the first bonding layer 320 is a hybrid bonding layer, the material of which includes a dielectric material and a conductor material, wherein the dielectric material includes at least one of silicon oxide, silicon nitride and silicon nitride carbon, and the conductor material includes at least one of tungsten (W), cobalt (Co), copper (Cu) and aluminum (Al).

[0142] The semiconductor device 300 also includes a first bonding layer 320, through which two adjacent device units 200 can be connected. This improves the feasibility of forming 3D memory (e.g., high-bandwidth memory). Furthermore, when the first bonding layer 320 is a direct bonding layer, its thickness is relatively thin, allowing for a thinner overall thickness of the semiconductor device 300. This reduces the limitation imposed by the thickness (or stacking height) of the semiconductor device 300 on the number of stacked layers of the device units 200, enabling a larger number of stacked layers and increasing the storage density and data transmission bandwidth of the semiconductor device 300.

[0143] In some examples, the fabrication method of the semiconductor device 300 includes other steps after the interconnect layer 250 is formed. Since the interconnect layer 250 is located on the side of the first semiconductor structure 210 away from the second semiconductor structure 220, and thus at the edge of the device cell 200, other steps after the interconnect layer 250 may affect the material of the interconnect layer 250.

[0144] For example, interconnect layer 250 includes interconnect lines 251, and the material of interconnect lines 251 includes, for example, a metallic material. Moreover, after forming interconnect layer 250, the method for fabricating semiconductor device 300 further includes forming a first bonding layer 320 using a bonding process. In this case, the bonding process may affect the metallic material in interconnect layer 250.

[0145] Therefore, in some embodiments, reference is made to Figure 5 and Figure 6 The device unit 200 further includes a first dielectric layer 260 located on the side of the interconnect layer 250 away from the peripheral circuit 211.

[0146] In some examples, refer to Figure 6 The connection structure 310 is located between the back side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X, and the connection structure 310 penetrates the first dielectric layer 260 of the target device unit 200X.

[0147] In yet another example, refer to Figure 5 The connection structure 310 is located between the front side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X. The connection structure 310 is located on the side of the first dielectric layer 260 of the target device unit 200X near the first surface 300a.

[0148] With the above configuration, the first dielectric layer 260 can cover the interconnect layer 250, encapsulating the material of the interconnect layer 250 (e.g., metal material), preventing the material of the interconnect layer 250 from being exposed in subsequent processes (e.g., bonding processes), thereby avoiding the impact of subsequent processes on the material of the interconnect layer 250. In this way, the conductivity of the interconnect layer 250 can be guaranteed, so as to achieve a reliable connection between the connection structure 310 and the peripheral circuit 211.

[0149] In some examples, the material of the first dielectric layer 260 includes silicon oxide.

[0150] Since the first dielectric layer 260 may be etched during the etching process to form the positioning hole, the process difficulty of forming the positioning hole can be reduced by using silicon oxide as the material of the first dielectric layer 260, thereby reducing the process difficulty of forming the connection structure 310.

[0151] In some embodiments, refer to Figure 5 and Figure 6The first semiconductor structure 210 further includes a second bonding layer 214, located on the side of the peripheral circuit 211 near the second semiconductor structure 220. The second bonding layer 214 includes a plurality of second bonding contacts 2141, which penetrate the second bonding layer 214 along a first direction X. The second semiconductor structure 220 further includes a third bonding layer 223, located on the side of the memory array 221 near the first semiconductor structure 210. The third bonding layer 223 includes a plurality of third bonding contacts 2231, which penetrate the third bonding layer 223 along the first direction X; one third bonding contact 2231 is connected to one second bonding contact 2141. The connection structure 310 penetrates the second bonding layer 214 and the third bonding layer 223 on the side of the interconnect layer 250 of the target device cell 200X near the first surface 300a, and avoids the second bonding contact 2141 and the third bonding contact 2231.

[0152] For example, the semiconductor device 300 includes a core region AA and a peripheral region SS. The second bonding layer 214 also includes a second dielectric layer 2142, which is located in the core region AA and the peripheral region SS. A plurality of second bonding contacts 2141 penetrate the second dielectric layer 2142 located in the core region AA. In this way, the connection structure 310 located in the peripheral region SS can avoid the second bonding contacts 2141.

[0153] For example, the semiconductor device 300 includes a core region AA and a peripheral region SS. The third bonding layer 223 also includes a third dielectric layer 2232. The third dielectric layer 2232 is located in the core region AA and the peripheral region SS. A plurality of third bonding contacts 2231 penetrate the third dielectric layer 2232 located in the core region AA. In this way, the connection structure 310 located in the peripheral region SS can avoid the third bonding contacts 2231.

[0154] For example, the materials of the second bonding contact 2141 and / or the third bonding contact 2231 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. Furthermore, the materials of the second bonding contact 2141 and the third bonding contact 2231 may be the same or different.

[0155] For example, the materials of the second dielectric layer 2142 and / or the third dielectric layer 2232 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Furthermore, the materials of the second dielectric layer 2142 and the third dielectric layer 2232 may be the same or different.

[0156] With the above configuration, a hybrid bonding interface can be formed between the first semiconductor structure 210 and the second semiconductor structure 220. Utilizing the third bonding contact 2231 and the second bonding contact 2141, coupling can be achieved between the peripheral circuit 211 and the memory array 221, enabling the transmission of signals within the device cell 200 (e.g., signals transmitted to the gate line 240 and / or bit line 230). By avoiding the second bonding contact 2141 and the third bonding contact 2231 in the connection structure 310, interference between the signals transmitted by the connection structure 310 and the signals transmitted between the third bonding contact 2231 and the second bonding contact 2141 can be avoided, thus improving the reliability of signal transmission in the semiconductor device 300.

[0157] Some embodiments of this disclosure also provide a memory 400. (See also...) Figure 7A and Figure 7B The memory 400 includes a logic chip 410 and a semiconductor device 300 provided in any of the above embodiments. The logic chip 410 is coupled to the semiconductor device 300.

[0158] For example, the logic chip 410 includes logic circuits, which can be integrated circuits used to perform logical operations and control functions. These circuits contain various logic gates (such as AND gates, OR gates, NOT gates, etc.), which perform operations according to preset logical relationships to achieve data storage and access control. For instance, the logic circuits in a dynamic random access memory (DRAM) implement data read and write operations through different physical structures (such as capacitors and transistors). These physical structures, through the combination of logic gates and control signals, ensure stable data storage and efficient access.

[0159] For example, the logic chip 410 may be a microcontroller unit (MCU), which may include one or more processing cores that can execute firmware to operate the device unit 200 for reading, erasing, or programming.

[0160] It is understood that the beneficial effects of the memory provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor devices described above, and will not be repeated here.

[0161] In some embodiments, refer to Figure 7A and Figure 7B The first surface 300a of the semiconductor device 300 faces the logic chip 410; the end of the connection structure 310 near the first surface 300a is connected to the logic chip 410.

[0162] Through the above settings, the connection between the connection structure 310 and the logic chip 410 can be realized. In this way, the logic chip 410 can be used to process and calculate the data of the semiconductor device 300 to realize the data reading function of the semiconductor device 300. Moreover, the logic chip 410 can also be used to connect control signals to the peripheral circuit 211 to realize functions such as erasing the semiconductor device 300. Thus, stable storage and efficient access of the semiconductor device 300 can be achieved.

[0163] This disclosure does not limit the connection method between the connection structure 310 and the logic chip 410. For example, the logic chip 410 may include a pad structure facing the semiconductor device 300, and the end of the connection structure 310 near the first surface 300a may be in direct contact with the pad structure.

[0164] In some embodiments, refer to Figure 7A and Figure 7B The semiconductor device 300 further includes a fourth bonding layer 330. The fourth bonding layer 330 includes a plurality of fourth bonding contacts 331, which penetrate the fourth bonding layer 330 along a first direction X; one fourth bonding contact 331 is connected to one end of a connection structure 310 near the first surface 300a. The logic chip 410 includes a fifth bonding layer 411. The fifth bonding layer 411 includes a plurality of fifth bonding contacts 4111, which penetrate the fifth bonding layer 411 along a first direction X; one fifth bonding contact 4111 is connected to one fourth bonding contact 331.

[0165] For example, the material of the fourth bonding contact 331 and / or the fifth bonding contact 4111 may include a conductive material, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. Furthermore, the materials of the fourth bonding contact 331 and the fifth bonding contact 4111 may be the same or different.

[0166] Exemplarily, the fourth bonding layer 330 further includes a fourth dielectric layer 332, through which a plurality of fourth bonding contacts 331 penetrate. The fourth dielectric layer 332 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0167] For example, the fifth bonding layer 411 further includes a fifth dielectric layer 4112, through which a plurality of fifth bonding contacts 4111 extend. The fifth dielectric layer 4112 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0168] With the above settings, the fourth bonding contact 331 and the fifth bonding contact 4111 can be used to achieve coupling between the semiconductor device 300 and the logic chip 410, thereby improving the reliability of signal transmission between the semiconductor device 300 and the logic chip 410.

[0169] Some embodiments of this disclosure also provide a storage system 500. (See also...) Figure 8A and Figure 8B The storage system 500 includes a controller 510 and a memory 400 provided in any of the above embodiments. The controller 510 is coupled to the memory 400.

[0170] For example, controller 510 can be used to control memory 400 to store data.

[0171] In some embodiments, refer to Figure 8A The storage system 500 includes a memory 400, which can be integrated into a memory card.

[0172] Memory cards include, for example, any of the following: PC card (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0173] The storage system 500 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 500 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0174] In yet other embodiments, reference is made to Figure 8BThe storage system 500 includes a controller 510 and multiple storage devices 400, which can be integrated into solid state drives (SSDs).

[0175] In some embodiments, the controller 510 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0176] In other embodiments, controller 510 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0177] In some embodiments, the controller 510 may be configured to manage data stored in the semiconductor device 300 and communicate with external devices (e.g., a host).

[0178] In some embodiments, the controller 510 may also be configured to control the operation of the memory 400, such as read, erase and program operations.

[0179] In some embodiments, the controller 510 may also be configured to manage various functions relating to data stored or to be stored in the memory 400, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling.

[0180] In some embodiments, the controller 510 is also configured to process error correction codes for data read from or written to the memory 400.

[0181] Of course, controller 510 can also perform any other suitable function, such as formatting memory; for example, controller 510 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0182] Here, the interface protocol may include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0183] It is understood that the beneficial effects of the storage system provided in the above embodiments of this disclosure can be referred to the beneficial effects of the memory described above, and will not be repeated here.

[0184] Some embodiments of this disclosure also provide an electronic device 600, see reference 1 Figure 9 The electronic device 600 includes a storage system 500.

[0185] The electronic device 600 includes, but is not limited to, any one of the following: mobile phone, tablet, laptop, television, personal digital assistant (PDA), ultra-mobile personal computer (UMPC), netbook, wearable device (e.g., smartwatch, smart bracelet, smart glasses). This application embodiment does not limit the type of electronic device.

[0186] Electronic device 600 may include the storage system 500 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0187] In some embodiments, refer to Figure 9 The electronic device 600 also includes a circuit board 610 (e.g., a printed circuit board), which is coupled to the storage system 500.

[0188] In some embodiments, circuit board 610 may be a printed circuit board. For example, circuit board 610 may be a multilayer printed circuit board.

[0189] It is understood that the beneficial effects of the electronic device provided by the above embodiments of this disclosure can be referred to the beneficial effects of the storage system described above, and will not be repeated here.

[0190] Figure 10 This is a possible cross-sectional view of an electronic device 600 that includes a storage system 500 in some embodiments, and can also be understood as a possible system block diagram of the electronic device 600. (Refer to...) Figure 10 The storage system 500 may also include an intermediate board 520. One or more memories 400 may be integrated on the intermediate board 520.

[0191] although Figure 10 The storage system 500 is shown to include two memories 400, but the concept of this disclosure is not limited thereto. For example, the storage system 500 may include one memory 400, or it may include three or more memories 400.

[0192] In some examples, the storage system 500 also includes a semiconductor chip 530 integrated on an interposer 520. The semiconductor chip 530 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In this case, the controller 510 may be a controller contained within the semiconductor chip 530.

[0193] The storage system 500 may further include a molding layer 540 surrounding the side surfaces of the memory 400 and the semiconductor chip 530. The molding layer 540 may include, for example, EMC (electromagnetic compatibility). In some embodiments, the molding layer 540 may cover the top surfaces of the memory 400 and the semiconductor chip 530. In some other embodiments, the molding layer 540 may not cover the top surfaces of the memory 400 and the semiconductor chip 530.

[0194] Exemplarily, the electronic device may also include a heat dissipation component. The heat dissipation component may be attached to the memory 400 and the semiconductor chip 530 using an intervening thermal interface material (TIM) layer. The TIM layer may be, for example, mineral oil, grease, sealant, phase change gel, phase change material pads, or particulate-filled epoxy resin. The heat dissipation component may be, for example, a heat sink, a heat pipe, or a liquid-cooled cold plate.

[0195] The following will provide an exemplary description of the fabrication method of the semiconductor device 300.

[0196] Figure 11 A flowchart illustrating a method for fabricating a semiconductor device 300 provided for some embodiments of this disclosure. Figures 12A to 13E The fabrication steps of the semiconductor device 300 provided for some embodiments of this disclosure are described below. Figure 11 and Figures 12A to 13E It should be understood that the operations shown in the preparation method are not exhaustive, and other operations may be performed before, after, or between any of the operations shown.

[0197] In the following embodiments, the deposition process includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or electroplating.

[0198] Some embodiments of this disclosure also provide a method for fabricating a semiconductor device 300, combined with Figure 5 and Figure 6 , refer to Figure 11 , including S1 to S3.

[0199] S1: Forming device unit 200.

[0200] For example, a device unit 200 (i.e., S1) is formed, including S1.1 to S1.3.

[0201] S1.1: Reference Figure 12A This forms a first semiconductor structure 210, which includes peripheral circuits 211.

[0202] S1.2: Reference Figure 12B and Figure 12C A second semiconductor structure 220 is formed and coupled to one side of the first semiconductor structure 210 along the first direction X, where the first direction X is the thickness direction of the semiconductor device 300. The second semiconductor structure 220 includes a memory array 221, which is connected to the peripheral circuit 211.

[0203] For example, a second semiconductor structure 220 is formed and coupled to one side of the first semiconductor structure 210 along the first direction X (i.e., S1.2), including S1.2.1 to S1.2.2.

[0204] S1.2.1: Reference Figure 12B This forms a second semiconductor structure 220.

[0205] S1.2.2: Reference Figure 12C The second semiconductor structure 220 is coupled to one side of the first semiconductor structure 210 along the first direction X.

[0206] S1.3: Reference Figure 12G or Figure 13A An interconnect layer 250 is formed on the side of the first semiconductor structure 210 away from the second semiconductor structure 220, and the interconnect layer 250 is connected to the peripheral circuit 211.

[0207] S2: Reference Figure 12H or Figure 13B Multiple device units 200 are stacked along the first direction X.

[0208] S3: Reference Figure 12I or Figure 13D A connection structure 310 is formed on one side of the peripheral circuit 211 and the memory array 221 along the second direction Y, which intersects the first direction X. The semiconductor device 300 includes a first surface 300a on one side of the first direction X, and a connection structure 310 is located between the first surface 300a and the interconnect layer 250 of a device cell 200.

[0209] It is understood that the beneficial effects that the semiconductor device 300 fabrication method provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor device 300 described above, and will not be repeated here.

[0210] In some embodiments, a first semiconductor structure 210 is formed (i.e., S1.1), referring to... Figure 12A This includes S1.1.1 and S1.1.2.

[0211] S1.1.1: A peripheral circuit 211 is formed on the first substrate 201.

[0212] For example, the material of the first substrate 201 may be single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0213] For example, forming the peripheral circuit 211 includes forming a plurality of peripheral transistors 2111 on the first substrate 201 (see reference). Figure 2 Multiple peripheral transistors 2111 form a peripheral circuit 211. Exemplarily, the process of forming multiple peripheral transistors 2111 on the first substrate 201 can be photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (CMP), and any other suitable process.

[0214] S1.1.2: A second bonding layer 214 is formed on the side of the peripheral circuit 211 away from the first substrate 201. The second bonding layer 214 includes a plurality of second bonding contacts 2141, which penetrate the second bonding layer 214 along the first direction X; the second bonding contacts 2141 avoid the connection structure 310 to be formed (see reference). Figure 5 ).

[0215] Exemplarily, the process for forming the second bonding contact 2141 may be as follows: first, dry etching and / or wet etching (such as reactive ion etching (RIE)) is used to etch contact openings (such as trenches) through the second bonding layer 214. Then, one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) are used to deposit conductive material on the second bonding layer 214 and into the contact openings to form an adhesive / barrier layer and a contact core filling each contact opening. In some embodiments, a planarization process (such as etching and / or CMP) is performed to remove excess conductive material and planarize the top surfaces of the second bonding layer 214 and the second bonding contact 2141.

[0216] In some embodiments, refer to Figure 12B This forms a second semiconductor structure 220 (i.e., S1.2.1), including S1.2.1.1 and S1.2.1.2.

[0217] S1.2.1.1: Reference Figure 12B A memory array 221 is formed on the second substrate 202.

[0218] For example, the material of the second substrate 202 may be single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0219] For example, forming a storage array 221 includes: a plurality of storage cells 100 forming an array distribution (see reference 100). Figure 3 ).

[0220] In some examples, storage unit 100 is formed, including R1 and R2.

[0221] R1: Forms transistor 110.

[0222] In some examples, transistor 110 includes a vertical gate, in which case transistor 110 (i.e., R1) is formed in conjunction with... Figure 2 and Figure 3 , refer to Figure 12B This includes R1.1 to R1.4.

[0223] R1.1: A channel structure 111 is formed on the second substrate 202.

[0224] Exemplarily, the process of forming the channel structure 111 may include: firstly depositing a stack of silicon oxide, silicon nitride and silicon oxide layers on a second substrate 202; then forming a plurality of openings arranged in an array, each opening extending vertically through the stack to the second substrate 202, such that a portion of the second substrate 202 can be exposed from the openings; and then forming the channel structure 111 in the plurality of openings, wherein the channel structure 111 can be epitaxially grown from the corresponding exposed portion of the second substrate 202 in the corresponding opening.

[0225] For example, the process of forming multiple openings may include one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) to etch openings through the silicon oxide layer, silicon nitride layer and silicon oxide layer until stopped by the silicon substrate.

[0226] For example, the process of epitaxially growing the channel structure 111 may include, but is not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combination thereof.

[0227] R1.2: A gate dielectric layer 112 is formed on one or more sides of the channel structure 111.

[0228] For example, the process of forming the gate dielectric layer 112 may include a thin film deposition process.

[0229] R1.3: A conductive material is deposited on the side of the gate dielectric layer 112 away from the channel structure 111 to form the gate structure 113.

[0230] For example, the process of depositing conductive materials may include one or more thin film deposition processes.

[0231] R1.4: Doping the two ends of each channel structure 111 to form a source end 111a and a drain end 111b.

[0232] For example, the doping methods of the source end 111a and the drain end 111b include ion implantation or diffusion processes, but are not limited thereto.

[0233] R2: A capacitor 120 is formed on one side of transistor 110.

[0234] In some examples, capacitor 120 is formed, combined with Figure 2 and Figure 3 , refer to Figure 12B This includes R2.1 to R2.3.

[0235] R2.1: A second dielectric layer is formed on one side of transistor 110.

[0236] For example, one or more deposition processes may be used to form the second dielectric layer.

[0237] R2.2: Forms a capacitor hole that penetrates the second dielectric layer, with one end of the capacitor hole connected to the source terminal 111a or the drain terminal 111b of transistor 110.

[0238] For example, multiple capacitor holes penetrating the second dielectric layer can be formed by dry etching, wet etching, or acid etching.

[0239] R2.3: A capacitor 120 is formed inside the capacitor hole.

[0240] For example, materials for a first electrode, a first dielectric layer, and a second electrode can be sequentially deposited within the capacitor hole to form a capacitor 120.

[0241] S1.2.1.2: Reference Figure 12B A third bonding layer 223 is formed on the side of the memory array 221 away from the second substrate 202. The third bonding layer 223 includes a plurality of third bonding contacts 2231, which penetrate the third bonding layer 223 along a first direction X; the third bonding contacts 2231 avoid the connection structure 310 to be formed (see reference). Figure 5 ).

[0242] Here, the process for forming the third bonding contact 2231 is similar to the process for forming the second bonding contact 2141. Therefore, for an understanding of the process for forming the third bonding contact 2231, please refer to the description of the process for forming the second bonding contact 2141 in the preceding section. It will not be repeated here.

[0243] In some embodiments, refer to Figure 12C The second semiconductor structure 220 is coupled to one side of the first semiconductor structure 210 along the first direction X (i.e., S1.2.2), which includes: connecting the second bonding layer 214 and the third bonding layer 223, so that a second bonding contact 2141 is connected to a third bonding contact 2231.

[0244] As described above, the third bonding contact 2231 and the second bonding contact 2141 can be used to couple the peripheral circuit 211 with the memory array 221, thereby enabling signal transmission within the device unit 200. Furthermore, interference between the signal transmitted through the connection structure 310 and the signal transmitted between the third bonding contact 2231 and the second bonding contact 2141 can be avoided, thus improving the reliability of signal transmission in the semiconductor device 300.

[0245] In some embodiments, after coupling the second semiconductor structure 220 to one side of the first semiconductor structure 210 along the first direction X (i.e., S1.2.2), the fabrication method further includes S1.2.3 to S1.2.5.

[0246] S1.2.3: Reference Figure 12D Thinning or removing the second substrate 202.

[0247] S1.2.4: Reference Figure 12E The first carrier plate Q1 is connected to the second semiconductor structure 220.

[0248] S1.2.5: Reference Figure 12F The first semiconductor structure 210 and the second semiconductor structure 220 are flipped, and the first substrate 201 is thinned.

[0249] For example, in S1.2.5, the thinned first substrate 201 forms a base layer 212.

[0250] In some embodiments, the fabrication method further includes S1.3F before forming an interconnect layer 250 (i.e., S1.3) on the side of the first semiconductor structure 210 away from the second semiconductor structure 220.

[0251] S1.3F: Reference Figure 12FThis forms a connection contact 2121 that penetrates the first substrate 201, so that the connection contact 2121 is connected to the peripheral circuit 211.

[0252] For example, S1.3F can be performed after S1.2.5 and before S1.3.

[0253] For an understanding of the connection contact point 2121, please refer to the description of the connection contact point 2121 in the previous section, which will not be repeated here.

[0254] As mentioned above, through the above configuration, the peripheral circuit 211 and the interconnect layer 250 can be connected through the connection contact 2121, which improves the feasibility of data transmission between the device unit 200 and the external circuit structure (e.g., logic circuit 410).

[0255] In some embodiments, after forming an interconnect layer 250 on the side of the first semiconductor structure 210 away from the second semiconductor structure 220 (i.e., S1.3), the fabrication method further includes S1.3A.

[0256] S1.3A: Reference Figure 12G or Figure 13A A first dielectric layer 260 is formed on the side of the interconnect layer 250 away from the first semiconductor structure 210.

[0257] For an understanding of the first dielectric layer 260, please refer to the description of the first dielectric layer 260 in the preceding section, which will not be repeated here.

[0258] With the above configuration, the first dielectric layer 260 can cover the interconnect layer 250, encapsulating the material of the interconnect layer 250 (e.g., a metal material), preventing the material of the interconnect layer 250 from being exposed in subsequent processes (e.g., the direct bonding process in S2 described in detail below), thus ensuring the conductivity of the interconnect layer 250 and achieving a reliable connection between the connection structure 310 and the peripheral circuit 211.

[0259] In some embodiments, refer to Figure 12H or Figure 13B Stacking multiple device units 200 along a first direction X (i.e., S2) includes: using a direct bonding process to sequentially connect multiple device units 200 along the first direction X.

[0260] For example, a first bonding layer 320 was formed using a direct bonding process.

[0261] Direct bonding, also known as wafer direct bonding, is a process that directly connects two wafers, resulting in a strong bond. It primarily utilizes mechanical force and high temperatures (e.g., above 700°C) to bond the two wafers together. When multiple device units 200 are connected via direct bonding, firstly, the connection between the multiple device units 200 is stronger, and the connection process is simplified; secondly, the thickness of the first bonding layer 320 formed by direct bonding is relatively thin, resulting in a thinner overall thickness of the semiconductor device 300. This allows for a greater number of stacked layers of device units 200, which is beneficial for increasing the storage density of the semiconductor device 300 and providing a wider data transmission bandwidth.

[0262] In some embodiments, refer to Figure 12A This forms a first semiconductor structure 210 (i.e., S1.1), and also includes S1.1.X.

[0263] S1.1.X: A first dielectric portion 213 is formed on one side of the peripheral circuit 211 along the second direction Y, and the first dielectric portion 213 penetrates the first semiconductor structure 210 along the first direction X.

[0264] For example, the method of forming the first dielectric portion 213 may be: forming a trench on the first substrate 201 and filling the trench with a material (e.g., silicon oxide) of the first dielectric portion 213.

[0265] For example, S1.1.X can be performed before S1.1.1, or after S1.1.1 and before S1.1.2.

[0266] For example, if the preparation method includes S1.1.X, S1.2.5 may be: thinning the first substrate 201 until the first dielectric portion 213 is exposed.

[0267] In some embodiments, refer to Figure 12B This forms a second semiconductor structure 220 (i.e., S1.2.1), and also includes S1.2.1.X.

[0268] S1.2.1.X: A second dielectric portion 222 is formed on one side of the memory array 221 along the second direction Y, and the second dielectric portion 222 penetrates the second semiconductor structure 220 along the first direction X. (Refer to...) Figure 12C The second dielectric portion 222 of the plurality of device units 200 at least partially overlaps with the first dielectric portion 213 of the plurality of device units 200 along the first direction X.

[0269] For example, the method of forming the second dielectric portion 222 may be: forming a trench on the first substrate 201 and filling the trench with a material (e.g., silicon oxide) of the second dielectric portion 222.

[0270] For example, S1.2.1.X can be performed before S1.2.1.1, or after S1.2.1.1 and before S1.2.1.2.

[0271] For example, if the preparation method includes S1.2.1.X, S1.2.3 may be: thinning or removing the second substrate 202 until the second dielectric portion 222 is exposed.

[0272] For an understanding of the first medium section 213 and the second medium section 222, please refer to the description of the first medium section 213 and the second medium section 222 in the foregoing section, which will not be repeated here.

[0273] With the above-described configuration, during the process of forming the connection structure 310 (e.g., U1 or V2 described in detail below), the impact of the etching process on the area where the peripheral circuit 211 and / or the memory array 221 are located can be avoided; moreover, when the material of the first dielectric portion 213 and / or the second dielectric portion 222 is silicon oxide, the formation of contact holes H (see reference) can be reduced. Figure 12I or Figure 13D This reduces the difficulty of the process when forming the connection structure 310, thereby reducing the difficulty of the process.

[0274] As mentioned above, the connection structure 310 can be located between the front side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X, or it can be located between the back side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X.

[0275] The following will illustrate the differences in the fabrication methods of the semiconductor device 300 under the two cases described above. First, an example will be given when the connection structure 310 is located between the back side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X.

[0276] In some embodiments, refer to Figure 12I During the process of forming a connection structure 310 (i.e. S3) on one side of the peripheral circuit 211 and the memory array 221 along the second direction Y, the connection structure 310 is connected to the interconnect layer 250 of the target device unit 200X, and does not penetrate the first semiconductor structure 210 and the second semiconductor structure 220 of the target device unit 200X.

[0277] For example, when the device unit 200 includes a first dielectric portion 213 and a second dielectric portion 222, the connection structure 310 does not penetrate the first dielectric portion 213 and the second dielectric portion 222 of the target device unit 200X.

[0278] In some embodiments, refer to Figure 12HAfter stacking multiple device units 200 along the first direction X (i.e. S2), in the same device unit 200, the first semiconductor structure 210 is located on the second semiconductor structure 220, and the upper surface of the uppermost first semiconductor structure 210 forms the first surface 300a.

[0279] After stacking multiple device units 200 along the first direction X (i.e., S2), U1 to U4.

[0280] U1: Reference Figure 12I From the first surface 300a, the first dielectric portion 213 and the second dielectric portion 222 of the plurality of device units 200 are etched to form contact holes H.

[0281] For example, the process of forming contact hole H may include one or more dry etching and / or wet etching processes (e.g. reactive ion etching) to pass through the first dielectric portion 213 and the second dielectric portion 222 of the plurality of device cells 200 to the interconnect layer 250 of the target device cell 200X.

[0282] U2: Reference Figure 12I A connection structure 310 is formed in the contact hole H.

[0283] For example, the connection structure 310 is formed by filling the contact hole H with a material (e.g., a metallic material) to form the connection structure 310.

[0284] U3: Reference Figure 12J , flip multiple device units 200.

[0285] U4: Reference Figure 12J The logic chip 410 is connected to the first surface 300a.

[0286] For example, during process U1, multiple device units 200 are stacked on the second carrier plate Q2. In this case, after U3 and before U4, the fabrication method further includes removing the second carrier plate Q2.

[0287] It should be understood that during the processes U1 to U2, a connection structure 310 is formed on one side of the peripheral circuit 211 and the memory array 221 along the second direction Y, thus realizing S3. During the processes U3 to U4, the connection between the semiconductor device 300 and the logic chip 410 is realized.

[0288] The following example illustrates the case where the connection structure 310 is located between the front side of the semiconductor device 300 and the interconnect layer 250 of the target device unit 200X.

[0289] In some embodiments, refer to Figure 13DDuring the process of forming a connection structure 310 (i.e. S3) on one side of the peripheral circuit 211 and the memory array 221 along the second direction Y, the connection structure 310 penetrates the first semiconductor structure 210 and the second semiconductor structure 220 of the target device unit 200X until it is connected to the interconnect layer 250 of the target device unit 200X.

[0290] For example, when the device unit 200 includes a first dielectric portion 213 and a second dielectric portion 222, the connection structure 310 passes through the first dielectric portion 213 and the second dielectric portion 222 of the target device unit 200X.

[0291] In some embodiments, refer to Figure 13B and Figure 13C After stacking multiple device units 200 along the first direction X (i.e. S2), in the same device unit 200, the first semiconductor structure 210 is located on the second semiconductor structure 220, and the bottom surface of the second semiconductor structure 220 located at the bottommost side forms the first surface 300a.

[0292] After stacking multiple device units 200 along the first direction X (i.e., S2), the fabrication method also includes V1 to V5.

[0293] V1: Reference Figure 13D Flip multiple device units 200 so that the first surface 300a faces upward.

[0294] For example, in S2, refer to Figure 13B Multiple device units 200 are stacked on the third carrier board Q3; in this case, refer to Figure 13C Before V1, it also included: removing the third carrier board Q3.

[0295] V2: Reference Figure 13D From the first surface 300a, the first dielectric portion 213 and the second dielectric portion 222 of the plurality of device units 200 are etched to form contact holes H.

[0296] V3: Reference Figure 13D A connection structure 310 is formed in the contact hole H.

[0297] V4: Reference Figure 13E , flip multiple device units 200.

[0298] V5: Reference Figure 13E The logic chip 410 is connected to the first surface 300a.

[0299] For an understanding of the method of forming the contact hole H and the method of forming the connection structure 310, please refer to the description of the method of forming the contact hole H and the method of forming the connection structure 310 in the foregoing section, which will not be repeated here.

[0300] It should be understood that the processes V1 to V3 form a connection structure 310 between the peripheral circuit 211 and the memory array 221 on one side along the second direction Y, thus realizing S3. The processes V4 to V5 realize the connection between the semiconductor device 300 and the logic chip 410.

[0301] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Multiple device units stacked along a first direction, wherein the first direction is the thickness direction of the semiconductor device; The device unit includes: The first semiconductor structure includes peripheral circuitry; A second semiconductor structure is coupled to one side of the first semiconductor structure along the first direction, the second semiconductor structure including a memory array connected to the peripheral circuit. An interconnect layer is located on the side of the first semiconductor structure away from the second semiconductor structure; the interconnect layer is connected to the peripheral circuit. The semiconductor device further includes: A connection structure is provided on one side of the peripheral circuit and the storage array along a second direction, the second direction intersecting the first direction; The semiconductor device includes a first surface on one side in the first direction, and a connection structure is located between the first surface and an interconnect layer of the device unit.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a core region and a peripheral region arranged along the second direction; the memory array and peripheral circuits of the plurality of device units are located in the core region; and the plurality of connection structures are located in the peripheral region.

3. The semiconductor device according to claim 1, characterized in that, The connection structure penetrates the first semiconductor structure and the second semiconductor structure of the target device unit and is connected to the interconnect layer of the target device unit. The peripheral circuitry and storage array of the target device unit are located on one side of the connection structure along the second direction.

4. The semiconductor device according to claim 1, characterized in that, The connection structure is disposed on the side of the first semiconductor structure and the second semiconductor structure of the target device unit closer to the first surface; Along the first direction, the connection structure is spaced from the peripheral circuit of the target device unit, and the connection structure is spaced from the memory array of the target device unit.

5. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: a first dielectric portion disposed on one side of the peripheral circuit along the second direction and penetrating the first semiconductor structure along the first direction; The second semiconductor structure further includes: a second dielectric portion disposed on one side of the memory array along the second direction and penetrating the second semiconductor structure along the first direction; The second dielectric portion of the plurality of device units overlaps at least partially with the first dielectric portion of the plurality of device units along the first direction; The connection structure extends through at least one of the plurality of first medium portions and the plurality of second medium portions; or... The first dielectric portion and the second dielectric portion of the plurality of device units are disposed on the side of the connection structure away from the first surface.

6. The semiconductor device according to claim 1, characterized in that, In the same device unit, the first semiconductor structure is closer to the first surface than the second semiconductor structure; or, In the same device unit, the second semiconductor structure is closer to the first surface than the first semiconductor structure.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A first bonding layer is disposed between two adjacent device units; the connection structure extends through the first bonding layer located on the side of the target device unit closer to the first surface.

8. The semiconductor device according to claim 1, characterized in that, The device unit further includes: The first dielectric layer is located on the side of the interconnect layer away from the peripheral circuit. Wherein, the connection structure penetrates the first dielectric layer of the target device unit; or, The connection structure is located on the side of the first dielectric layer of the target device unit near the first surface.

9. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: a second bonding layer located on the side of the peripheral circuit closer to the second semiconductor structure; the second bonding layer includes a plurality of second bonding contacts, the second bonding contacts penetrating the second bonding layer along the first direction; The second semiconductor structure further includes: a third bonding layer located on the side of the memory array closer to the first semiconductor structure; the third bonding layer includes a plurality of third bonding contacts, the third bonding contacts penetrating the third bonding layer along the first direction; one of the third bonding contacts is connected to one of the second bonding contacts; The connection structure penetrates the second and third bonding layers located on the side of the interconnect layer of the target device unit closer to the first surface, and avoids the second bonding contact and the third bonding contact.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, The first semiconductor structure further includes: A base layer is located between the peripheral circuit and the interconnect layer; the base layer includes a connection contact point; the connection contact point penetrates the base layer along the first direction, one end of the connection contact point is connected to the peripheral circuit, and the other end is connected to the interconnect layer.

11. The semiconductor device according to any one of claims 1 to 9, characterized in that, The interconnect layer includes interconnect lines connected to the connection structure, and the interconnect lines are made of a metallic material.

12. A memory, characterized in that, include: The semiconductor device as described in any one of claims 1 to 11; A logic chip, coupled to the semiconductor device.

13. The memory according to claim 12, characterized in that, The first surface of the semiconductor device faces the logic chip; one end of the connection structure near the first surface is connected to the logic chip.

14. The memory according to claim 13, characterized in that, The semiconductor device further includes: a fourth bonding layer; the fourth bonding layer includes a plurality of fourth bonding contacts, the fourth bonding contacts penetrating the fourth bonding layer along the first direction; one of the fourth bonding contacts is connected to one end of the connection structure near the first surface; The logic chip includes: a fifth bonding layer; the fifth bonding layer includes a plurality of fifth bonding contacts, the fifth bonding contacts penetrating the fifth bonding layer along the first direction; one of the fifth bonding contacts is connected to one of the fourth bonding contacts.

15. A storage system, characterized in that, It includes a memory as described in any one of claims 12 to 14, and a controller coupled to said memory.

16. A method for fabricating a semiconductor device, characterized in that, include: Forming device units; The forming device unit includes: A first semiconductor structure is formed; the first semiconductor structure includes peripheral circuitry. A second semiconductor structure is formed and coupled to one side of the first semiconductor structure along a first direction, the first direction being the thickness direction of the semiconductor device; the second semiconductor structure includes a memory array, the memory array being connected to the peripheral circuitry; An interconnect layer is formed on the side of the first semiconductor structure away from the second semiconductor structure; the interconnect layer is connected to the peripheral circuit. Stack the multiple device units along the first direction; A connection structure is formed on one side of the peripheral circuit and the memory array along a second direction, which intersects the first direction; the semiconductor device includes a first surface located on one side of it in the first direction, and one of the connection structures is located between the first surface and an interconnect layer of one of the device cells.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, The stacking of the plurality of device units along the first direction includes: Using a direct bonding process, multiple device units are sequentially connected along the first direction.

18. The method for fabricating a semiconductor device according to claim 16, characterized in that, During the process of forming a connection structure between the peripheral circuit and the memory array on one side along the second direction, The connection structure penetrates the first semiconductor structure and the second semiconductor structure of the target device unit until it is connected to the interconnect layer of the target device unit. or, The connection structure is connected to the interconnect layer of the target device unit, but does not penetrate the first semiconductor structure and the second semiconductor structure of the target device unit.

19. The method for fabricating a semiconductor device according to claim 16, characterized in that, The formation of the first semiconductor structure further includes: forming a first dielectric portion on one side of the peripheral circuit along the second direction, wherein the first dielectric portion penetrates the first semiconductor structure along the first direction; The method of forming the second semiconductor structure further includes: forming a second dielectric portion on one side of the memory array along the second direction, wherein the second dielectric portion penetrates the second semiconductor structure along the first direction; The second dielectric portion of the plurality of device units overlaps at least partially with the first dielectric portion of the plurality of device units along the first direction.

20. The method for fabricating a semiconductor device according to claim 19, characterized in that, After stacking the plurality of device units along the first direction, in the same device unit, the first semiconductor structure is located on the second semiconductor structure, and the upper surface of the uppermost first semiconductor structure forms the first surface; After stacking the plurality of device units along the first direction, the fabrication method further includes: From the first surface, the first dielectric portion and the second dielectric portion of a plurality of device units are etched to form contact holes; The connection structure is formed in the contact hole; Flip multiple of the device units; The logic chip is connected to the first surface.

21. The method for fabricating a semiconductor device according to claim 19, characterized in that, After stacking the plurality of device units along the first direction, in the same device unit, the first semiconductor structure is located on the second semiconductor structure, and the bottom surface of the second semiconductor structure located at the bottommost side forms the first surface; After stacking the plurality of device units along the first direction, the fabrication method further includes: Flip the plurality of device units so that the first surface faces upward; From the first surface, the first dielectric portion and the second dielectric portion of a plurality of device units are etched to form contact holes; The connection structure is formed in the contact hole; Flip multiple of the device units; The logic chip is connected to the first surface.

22. The method for fabricating a semiconductor device according to any one of claims 16 to 21, characterized in that, After forming an interconnect layer on the side of the first semiconductor structure away from the second semiconductor structure, the fabrication method further includes: A first dielectric layer is formed on the side of the interconnect layer away from the first semiconductor structure.

23. The method for fabricating a semiconductor device according to any one of claims 16 to 21, characterized in that, The formation of the first semiconductor structure includes: forming the peripheral circuit on a first substrate; and forming a second bonding layer on a side of the peripheral circuit away from the first substrate, the second bonding layer including a plurality of second bonding contacts, the second bonding contacts penetrating the second bonding layer along the first direction; the second bonding contacts avoiding the connection structure to be formed; The formation of the second semiconductor structure includes: forming the memory array on a second substrate; and forming a third bonding layer on a side of the memory array away from the second substrate, the third bonding layer including a plurality of third bonding contacts, the third bonding contacts penetrating the third bonding layer along the first direction; the third bonding contacts avoiding the connection structure to be formed. The step of coupling the second semiconductor structure to one side of the first semiconductor structure along the first direction includes: The second bonding layer is connected to the third bonding layer, such that one second bonding contact is connected to one third bonding contact.

24. The method for fabricating a semiconductor device according to claim 23, characterized in that, Before forming an interconnect layer on the side of the first semiconductor structure away from the second semiconductor structure, the fabrication method further includes: A connection contact is formed that penetrates the first substrate, so that the connection contact is connected to the peripheral circuit.

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