Semiconductor structure, method of manufacturing thereof and semiconductor device

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor structure, a preparation method thereof and a semiconductor device. The provided semiconductor structure comprises a plurality of transistors arranged in a first direction in sequence; wherein each transistor comprises a semiconductor column and a first gate and a second gate respectively located on opposite sides of the semiconductor column; two first gates in two adjacent transistors are arranged in a second direction, the first direction intersects the second direction, and the second direction is the extension direction of the semiconductor column; and the second gate serves as a shared gate of the two adjacent transistors. The application can avoid interference between two adjacent word lines, reduce static leakage of the device in use, reduce parasitic capacitance, improve storage speed and density, and optimize the layout of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, its fabrication method, and a semiconductor device. Background Technology

[0002] In the semiconductor manufacturing industry, semiconductor devices serve as memory devices for storing information. Their main function is to store programs and various data, and to perform high-speed, automatic access to programs or data during computer operation. Taking DRAM (Dynamic Random Access Memory) as an example, DRAM typically includes multiple memory cells, each consisting of a transistor and a capacitor. One end of the transistor is connected to the capacitor, and the other end is connected to the bit line. With the rapid development of mobile computing, artificial intelligence, and the Internet of Things (IoT) applications, DRAM memory faces the triple challenges of higher density, lower power consumption, and smaller area. Traditional 6F... 2 While the cell design boasts mature technology, its large cell area makes it difficult to meet the extreme storage density demands of advanced manufacturing processes. Against this backdrop, 4F... 2 DRAM cell design emerged as a key technological path to overcome the bottleneck of memory density. As process technology shrinks to below 10nm, planar architectures face bottlenecks such as process integrity, leakage current, and interference. 4F 2 The architecture integrates more units within the same silicon wafer area by changing the stacking of transistors (source, gate, and drain) from horizontal to vertical, achieving advantages such as an area reduction of about 30%, a reduction of about 60% in leakage interference, and a 50% reduction in EUV lithography costs.

[0003] In related technologies, 4F 2 DRAM technology, especially 4F with back gate structure 2 DRAM technology still suffers from significant drawbacks. The inherent floating body effect of the vertical channel structure leads to a decrease in transistor threshold voltage, resulting in a significant increase in off-state leakage current and a deterioration in data retention time, becoming a major factor affecting memory reliability. In 4F... 2 In the designed structure, parasitic capacitance forms between adjacent word lines. This causes the voltage of one word line to rise rapidly, and the voltage of the other word line to rise rapidly as soon as the voltage of one word line rises, resulting in a large leakage current. Furthermore, 4F 2 In this structure, the word lines are exposed and closer to the bit lines, leading to increased parasitic capacitance at the bit line-word line (BL-WL) and word line-memory node contact (WL-NC). The inter-word line capacitance becomes the most significant parasitic capacitance component, affecting transistor gate control. In back-gate DRAM devices, the increased back gate electrode exacerbates the impact of parasitic capacitance.

[0004] Therefore, how to avoid interference between two adjacent word lines in order to reduce static leakage current during the use of the device is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor structure, its fabrication method, and a semiconductor device that can at least alleviate the interference between two adjacent word lines in current semiconductor devices, which easily causes static leakage current during device use. This invention can reduce static leakage current, lower parasitic capacitance, and improve the performance and reliability of the device.

[0006] To solve the above-mentioned technical problems, this application is implemented as follows: In a first aspect, this application provides a semiconductor structure, the semiconductor structure comprising: Multiple transistors arranged sequentially along a first direction; among them, Each of the transistors includes a semiconductor pillar and a first gate and a second gate located on opposite sides of the semiconductor pillar; The two first gates of two adjacent transistors are staggered in a second direction, the first direction intersecting the second direction, and the second direction being the extension direction of the semiconductor pillar; The second gate serves as the shared gate for two adjacent transistors.

[0007] Optionally, in the second direction, in two adjacent transistors, the bottom surface of the first gate of one of them is flush with or higher than the top surface of the first gate of the other.

[0008] Optionally, in some of the transistors, in the second direction, the top surface of the first gate is higher than the top surface of the second gate, and the bottom surface of the first gate is higher than the bottom surface of the second gate; or, in the remaining transistors, in the second direction, the top surface of the second gate is higher than the top surface of the first gate, and the bottom surface of the second gate is higher than the bottom surface of the first gate.

[0009] Optionally, the semiconductor structure further includes a gate dielectric layer located between the two first gates of two adjacent transistors, wherein the gate dielectric layer is disposed above the top surface of the first gate and below the bottom surface of the first gate.

[0010] Optionally, in the second direction, the heights of the plurality of second gates in the plurality of transistors are consistent.

[0011] Optionally, the first gate is made of metal or metal nitride.

[0012] Optionally, the material of the second gate includes metal and / or metal nitride.

[0013] Secondly, this application provides a method for fabricating a semiconductor structure, the method comprising: Provide a base; A plurality of transistors are formed on the substrate in a first direction; wherein each transistor includes a semiconductor pillar and a first gate and a second gate located on opposite sides of the semiconductor pillar respectively; two of the first gates of two adjacent transistors are staggered in a second direction, the first direction intersecting the second direction, the second direction being the extension direction of the semiconductor pillar; the second gate serves as a common gate for two adjacent transistors.

[0014] Optionally, providing the substrate includes: providing a substrate, wherein a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on a first surface of the substrate, and a fourth dielectric layer is formed on a second surface of the substrate; the first surface and the second surface are disposed opposite to each other along a second direction; wherein the first dielectric layer and the third dielectric layer are made of the same material, and the first dielectric layer, the second dielectric layer and the fourth dielectric layer are made of different materials.

[0015] Optionally, forming a plurality of transistors arranged sequentially along a first direction on the substrate includes: forming a plurality of trenches spaced apart along the first direction by etching the third dielectric layer, the second dielectric layer, the first dielectric layer, the substrate, and a portion of the fourth dielectric layer, wherein each trench extends along a second direction; forming a second gate within the trenches; and forming a deep trench structure by etching the first dielectric layer, the substrate, and a portion of the fourth dielectric layer, wherein the first gate is formed in the deep trench structure.

[0016] Optionally, forming the second gate within the trench includes: depositing a first dielectric layer on the sidewalls and bottom wall of the trench, the first dielectric layer filling a portion of the trench; depositing a second gate material within the trench, the second gate material contacting the first dielectric layer; etching back the second gate material so that the top surface of the second gate material is lower than a first surface of the substrate; depositing the first dielectric layer within the trench; removing the first dielectric layer and the third dielectric layer located above the second dielectric layer, and removing the second dielectric layer, forming the first dielectric layer and a first axial structure formed by the first dielectric layer on the substrate, and forming an initial second gate within the trench.

[0017] Optionally, forming a deep trench structure by etching the first dielectric layer, the substrate, and a portion of the fourth dielectric layer includes: depositing the first dielectric layer on the surface of the first axial structure to form a second axial structure; using the second axial structure as a mask, sequentially etching the first dielectric layer, the substrate, and a portion of the fourth dielectric layer to form a deep trench structure penetrating the first dielectric layer, the substrate, and a portion of the fourth dielectric layer.

[0018] Optionally, forming the first gate in the deep trench structure includes: depositing a first gate material on the sidewalls and bottom wall of the deep trench structure, the first gate material filling a portion of the deep trench structure; depositing a gate dielectric layer in the deep trench structure to fill the deep trench structure; performing back etching on the first gate material so that the top surface of the first gate material is lower than the first surface of the substrate and higher than the top surface of the initial second gate; depositing a gate dielectric layer in the trench region formed after back etching to fill the deep trench structure again; performing planarization on the gate dielectric layer so that the top surface of the gate dielectric layer is flush with the top surface of the first dielectric layer; and processing the first gate material to form the first gate.

[0019] Optionally, depositing a first gate material on the sidewalls and bottom wall of the deep trench structure includes: first depositing a first dielectric layer material on the sidewalls and bottom wall of the deep trench structure, and then depositing the first gate material on the first dielectric layer material, wherein the first gate material fills a portion of the deep trench structure.

[0020] Optionally, processing the first gate material to form the first gate includes: flipping the substrate, thinning the fourth dielectric layer until the initial second gate is exposed, etching back the initial second gate, and filling the area formed after the back etching with the first dielectric layer to form the second gate in the trench; defining the first gate material located on one side of the gate dielectric layer as a first region and the first gate material located on the other side of the gate dielectric layer as a second region using photolithographic alignment patterns; protecting the second region with a photolithographic mask, opening the first region, and processing the first gate material in the first region using dry etching to form a first gate with a first preset height; then protecting the first region with a photolithographic mask again, opening the second region, and processing the first gate material in the second region using dry etching to form a first gate with a second preset height, wherein the first gate with the first preset height and the first gate with the second preset height are staggered in a second direction.

[0021] Thirdly, this application provides a semiconductor device, the semiconductor device comprising: The aforementioned semiconductor structure, and / or the semiconductor structure prepared by the aforementioned preparation method; The first word line is used to form an electrical connection with the first gate; The second word line is used to form an electrical connection with the second gate.

[0022] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects: The semiconductor structure and fabrication method of this application, by setting a first gate and a second gate in the transistor, wherein the first gate can be a front gate (front gate) and the second gate can be a back gate (back gate), that is, the front gate and the back gate are respectively set on opposite sides of the semiconductor pillar, and the front gates of two adjacent transistors are staggered in the extension direction of the semiconductor pillar. Therefore, by staggering the front gates of two closely spaced adjacent transistors in the extension direction of the semiconductor pillar, electric field coupling and interference caused by direct word line opposition between adjacent active groups are avoided, thus reducing interference between adjacent transistors and effectively reducing static leakage current during device use.

[0023] Meanwhile, the front gates in two adjacent transistors are staggered in the extension direction of the semiconductor pillar to form a segmented gate control structure, which can more uniformly cover the channel region of the semiconductor pillar, improve the gate's control over the channel potential, and help suppress short-channel effects and subthreshold leakage current. In other words, it optimizes the gate's control over the channel and the electric field distribution.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the semiconductor structure provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of step S10 in the method for preparing a semiconductor structure provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of step S20 in the semiconductor structure fabrication method provided in the embodiment of the present invention; Figure 4AA schematic diagram of step S310 in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 4B A schematic diagram of step S320 in the semiconductor structure fabrication method provided in the embodiment of the present invention; Figure 4C This is a schematic diagram of step S330 in the method for preparing a semiconductor structure provided in an embodiment of the present invention; Figure 4D A schematic diagram of step S340 in the method for preparing a semiconductor structure provided in an embodiment of the present invention; Figure 4E A schematic diagram of step S350 in the method for preparing a semiconductor structure provided in an embodiment of the present invention; Figure 4F A schematic diagram of step S360 in the method for preparing a semiconductor structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of step S40 in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of step S50 in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of step S60 in the method for preparing a semiconductor structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of step S70 in the method for preparing a semiconductor structure provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of step S80 in the semiconductor structure fabrication method provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of step S90 in the semiconductor structure fabrication method provided in the embodiment of the present invention.

[0027] Explanation of reference numerals in the attached figures: 100 - Substrate; 101 - Semiconductor pillar; 110 - First dielectric layer; 120 - Second dielectric layer; 130 - Third dielectric layer; 140 - Fourth dielectric layer; 150 - Channel / groove; 160 - First axis structure; 170 - Deep trench structure; 180 - Gate dielectric layer; 200 - First gate; 210 - First gate material; 211 - Front gate A; 212 - Front gate B; 300 - Second gate; 310 - Second gate material; 311 - Initial second gate. Detailed Implementation

[0028] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings.

[0030] In related technologies, a specific layout design is employed for bit lines (BL), semiconductor patterns, word lines (WL), and interconnect structures. This semiconductor device improves integration density by extending semiconductor patterns along a second direction perpendicular to the upper surface of the substrate on the bit lines to form a three-dimensional arrangement of semiconductor patterns. Simultaneously, by creating gaps between interconnect structures, interference between adjacent interconnect structures is reduced, improving the device's electrical performance. A vertical transistor arrangement with alternating gate orientations is used, featuring a common source and independent drains. The word lines consist of alternating front and back gates, providing 4F of memory cells. 2 The small size layout and improved retention characteristics are achieved. In DRAM devices, the back gate structure was proposed to independently adjust the channel potential through the back gate voltage, thereby achieving precise control of the threshold voltage.

[0031] However, the current 4F with back-gate structure 2 DRAM technology still has some shortcomings, such as in 4F... 2 In the designed structure, parasitic capacitance forms between adjacent word lines. This causes the voltage of one word line to rise rapidly, and the voltage of the other word line to rise rapidly as soon as the voltage of one word line rises, resulting in a large leakage current. Furthermore, 4F 2 In this structure, the word lines are exposed and closer to the bit lines, leading to an increase in the parasitic capacitances of BL-WL and word WL-NC. The inter-word line capacitance becomes the most significant parasitic capacitance component, affecting transistor gate control. In back-gate DRAM devices, the increased number of back gate electrodes exacerbates the impact of parasitic capacitance.

[0032] In view of this, in order to alleviate the current 4F 2 Interference between adjacent word lines in the structural design can easily lead to static leakage current problems during device use. This application provides a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor device including the semiconductor structure. By improving the arrangement of the word line structure, better optimization of inter-word line capacitance is achieved, effectively reducing static leakage current, lowering parasitic capacitance, and improving storage speed and density. Simultaneously, optimizing the semiconductor structure layout facilitates the realization of high-performance, high-reliability 4F... 2DRAM memory. Specific technical solutions are described below.

[0033] refer to Figure 1 As shown in the embodiment of this application, a semiconductor structure is provided, which includes: a plurality of transistors arranged sequentially along a first direction; wherein each transistor includes a semiconductor pillar 101 and a first gate 200 and a second gate 300 located on opposite sides of the semiconductor pillar 101; the two first gates 200 of two adjacent transistors are staggered in a second direction, the first direction intersects the second direction, and the second direction is the extension direction of the semiconductor pillar 101; the second gate 300 serves as a common gate for two adjacent transistors.

[0034] The semiconductor structure provided in this embodiment can be used in semiconductors with 4F 2 In semiconductor devices with misaligned gate architectures, such as those used in 4F... 2 In transistor devices.

[0035] On the 4th floor 2 In a vertical gate (VG) structure, word lines (WLs) are transformed from a traditional horizontal arrangement to a vertical stack. Adjacent WLs are closely arranged in three-dimensional space, leading to edge electric field coupling: the sidewall distance between adjacent WLs decreases drastically with process node shrinkage (down to below 10nm), and the electric fields penetrate each other through the dielectric layer, forming significant parasitic capacitance. 4F 2 The leakage current problem caused by parasitic capacitance between word lines (WL) in the architecture is a physical limit that must be overcome in the process of high-density DRAM moving towards 3D stacking. Therefore, how to avoid interference between two adjacent word lines to reduce the static leakage current of the device is an urgent problem to be solved.

[0036] Based on this, this embodiment improves the arrangement of the gate structure (word line structure) to achieve better optimization of the capacitance between gates (word lines), thereby effectively reducing static leakage current, lowering parasitic capacitance, and improving storage speed and density, while also optimizing the semiconductor structure layout. This embodiment can effectively solve the aforementioned parasitic capacitance problem and achieve high performance and high reliability 4F. 2 DRAM memory.

[0037] In this embodiment, the first direction can be the x-axis direction, the second direction can be the z-axis direction, and the second direction is the extension direction of the semiconductor pillar 101, that is, the semiconductor pillar 101 extends in the z-axis direction; in addition, the third direction can be the y-axis direction; the first direction x, the second direction z and the third direction y intersect each other.

[0038] In this embodiment, the semiconductor structure may include a substrate 100, which has multiple active groups spaced apart and arranged in an array along a first direction, i.e., an array device composed of multiple repeating devices. Specifically, the semiconductor structure includes multiple transistors, which may be arranged sequentially along the first direction, or the transistors may be arranged in an array within a plane formed by the first and second directions. Alternatively, the multiple transistors arranged sequentially along the first direction may be multiple transistors arranged with only one row of spacing along the first direction, or multiple transistors arranged with multiple rows of spacing along the first direction, i.e., multiple transistors spaced apart along a third direction are also included. In other words, the multiple transistors are also arranged in an array within a plane formed by the first and third directions. Thus, the semiconductor structure can be a stacked structure in which transistors are distributed in three-dimensional space.

[0039] Optionally, the semiconductor structure in this embodiment may include one or more transistor layers, each transistor layer including a plurality of transistors arranged sequentially. For example, it includes multiple transistor layers spaced apart, and the transistor layers are insulated from each other, for example, there may be an insulating material between the transistor layers. The insulating material serves to prevent electrical conduction between the transistor layers.

[0040] In this embodiment, each transistor includes a semiconductor pillar 101 and a gate. The semiconductor pillar 101 can also be referred to as an active pillar. Exemplarily, each active pillar may include a source, a channel, and a drain connected sequentially along a third direction. The gate in each transistor may surround the channel of the active pillar in the transistor. The gate in each transistor includes a first gate 200 and a second gate 300. In this embodiment, the first gate 200 may be a front gate, and the second gate 300 may be a back gate. The first gate 200 and the second gate 300 are located on opposite sides of the semiconductor pillar 101. The first gate 200, the second gate 300, and the semiconductor pillar 101 may all extend along a second direction. In this embodiment, the first gate 200 is the front gate and plays the main switching role. The second gate 300 is the back gate and can be used as a gate for adjusting the threshold voltage, suppressing leakage current, or assisting in charge storage. The second gate 300 may be a shared gate for two adjacent transistors, that is, the second gates 300 of the two transistors are physically made of the same conductive material. The two first gates 200 of two adjacent transistors, i.e., the front gates, are arranged close to each other, and there is an insulating material between the two first gates 200; and, more notably, the two first gates 200 of the two adjacent transistors are staggered in the second direction, i.e., in the extension direction of the semiconductor pillar 101. For example, the degree of staggering can be completely staggered, i.e., the projections of the two in the first direction or the third direction do not overlap.

[0041] Therefore, the semiconductor structure provided in this application embodiment can avoid interference between two adjacent word lines, thereby reducing static leakage current during device use. Specifically, by staggering the first gates 200 of two closely spaced adjacent transistors (i.e., the front gates) along the extension direction of the semiconductor pillar 101, electric field coupling and interference caused by direct word line opposition between adjacent active groups are avoided, thus reducing interference between adjacent transistors and effectively reducing static leakage current during device use. Simultaneously, the front gates in the two adjacent transistors are staggered and superimposed along the extension direction of the semiconductor pillar 101, forming a segmented gate control structure. This structure can more uniformly cover the channel region of the semiconductor pillar 101, improving the gate's control over the channel potential and helping to suppress short-channel effects and subthreshold leakage current, thereby optimizing the gate's control capability over the channel and the electric field distribution.

[0042] Furthermore, the staggered arrangement of the front gates in two adjacent transistors along the extension direction of the semiconductor pillar 101 reduces interference between word lines in adjacent active groups and lowers parasitic capacitance between adjacent word lines. This reduces the impact of parasitic capacitance on the charging and discharging speed of the device, thus improving the storage speed of the semiconductor structure. This embodiment also allows for a more rational layout of the semiconductor structure, effectively increasing its storage density.

[0043] In this embodiment, the semiconductor structure can be a dual-gate structure with vertical channel transistors. The first gate 200, also known as the front gate, can be connected to the main word line (MWL) and is responsible for the main switching control of the transistor, with a gate voltage range of -1.5V to +1.5V. The second gate 300, also known as the back gate (BG), can be connected to the back gate bias line, providing independent DC bias or dynamic bias, with a voltage range of -2.0V to +1.0V. A single back gate is shared by two adjacent memory cells, i.e., two adjacent transistors, and is located in the bottom region of the silicon pillar between the two word line trenches. The back gate window can be defined by a self-aligned spacer layer process.

[0044] In some embodiments, in the second direction, in two adjacent transistors, the bottom surface of one first gate 200 is flush with or higher than the top surface of the other first gate 200.

[0045] In this embodiment, a first gate 200 and a second gate 300, i.e., a front gate and a back gate, are respectively disposed on opposite sides of the semiconductor pillar 101. The first gate 200 is staggered in the extension direction (perpendicular to the substrate direction) of the semiconductor pillar 101, together forming the control gate / control word line of the semiconductor pillar 101. As an example, the spatial arrangement of the first gate 200 is such that the front gates of adjacent transistors have a clear positional offset in the vertical direction, i.e., the second direction, rather than being at the same height. That is, the semiconductor structure has adjacent first gates 200, i.e., front gates, that are staggered vertically. As an example, in the second direction of the two first gates 200 of the two adjacent transistors, the bottom surface of one first gate 200 can be flush with or approximately flush with the top surface of the other first gate 200, or the bottom surface of one first gate 200 can be slightly higher than the top surface of the other first gate 200. That is, there can be a distance difference (gap) between the two adjacent first gates 200, and this distance difference should not be too large, such as not exceeding 50nm.

[0046] Therefore, by making the bottom surface of one of the first gates 200 of two adjacent transistors flush with or higher than the top surface of the other first gate 200, the interference between adjacent transistors can be significantly reduced, static leakage current can be reduced, and the gate's control capability over the channel and electric field distribution can be optimized.

[0047] Optionally, the length of the first gate 200 in each transistor can be consistent in the second direction. That is, the size of the first gate 200 in each transistor can be consistent, except that the first gates 200 in adjacent transistors are staggered vertically in the second direction.

[0048] In some embodiments, in the second direction, the heights of the plurality of second gates 300 in the plurality of transistors are consistent.

[0049] In the semiconductor structure of this embodiment, the second gates 300 in the plurality of transistors can be correspondingly arranged. That is, the size of the second gates 300 in each transistor can be the same. The second gates 300 in each transistor are arranged at the same height in the second direction, that is, in the extension direction of the semiconductor pillar 101. The projections of the second gates 300 in the first direction or the third direction can overlap.

[0050] In some embodiments, in some transistors, in the second direction, the top surface of the first gate 200 is higher than the top surface of the second gate 300, and the bottom surface of the first gate 200 is higher than the bottom surface of the second gate 300; or, in the remaining transistors, in the second direction, the top surface of the second gate 300 is higher than the top surface of the first gate 200, and the bottom surface of the second gate 300 is higher than the bottom surface of the first gate 200.

[0051] In the semiconductor structure of this embodiment, the lengths of the first gate 200 and the second gate 300 in the second direction can be different; for example, the length of the first gate 200 is less than the length of the second gate 300. Since adjacent first gates 200 are staggered, their heights are different. Therefore, the top surface of some first gates 200 is higher than the top surface of the second gate 300, and the bottom surface of some first gates 200 is higher than the bottom surface of the second gate 300; while the top surface of other first gates 200 is lower than the top surface of the second gate 300, and the bottom surface of other first gates 200 is lower than the bottom surface of the second gate 300.

[0052] In some embodiments, the semiconductor structure further includes a gate dielectric layer 180 located between two first gates 200 in two adjacent transistors, and the gate dielectric layer 180 is disposed above the top surface of the first gate 200 and below the bottom surface of the first gate 200.

[0053] The gate dielectric layer 180 is located between the metal electrodes and can be used to isolate two adjacent first gates 200. A suitable gate dielectric layer 180 material can ensure that smaller parasitic capacitance is generated.

[0054] This embodiment does not specifically limit the material of the gate dielectric layer 180. As an example, the material of the gate dielectric layer 180 may include, but is not limited to, low dielectric constant (low k) materials such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), organosilicon glass (OSG), carbon-doped silicon oxide (SiCOH), or combinations thereof.

[0055] In some embodiments, the first gate 200 is made of metal and metal nitride.

[0056] In some embodiments, the second gate 300 is made of metal and / or metal nitride.

[0057] In this embodiment, the materials of the first gate 200 and the second gate 300 are not specifically limited. For example, the materials of both the first gate 200 and the second gate 300 can be a combination of metal and metal nitride, or the material of the second gate 300 can also be one of metal or metal nitride. Typically, but not limitingly, the metal can be one or more of tungsten (W), molybdenum (Mo), or titanium (Ti), and the metal nitride can be one or more of titanium nitride (TiN) or tantalum nitride (TaN).

[0058] The manufacturing method of the above-mentioned semiconductor structure will be described in detail below with reference to specific embodiments.

[0059] In some embodiments, a method for fabricating a semiconductor structure is provided, the method comprising: Provide a base; A plurality of transistors are formed on a substrate and arranged sequentially along a first direction; wherein each transistor includes a semiconductor pillar 101 and a first gate 200 and a second gate 300 located on opposite sides of the semiconductor pillar 101 respectively; the two first gates 200 of two adjacent transistors are staggered in a second direction, the first direction intersects the second direction, and the second direction is the extension direction of the semiconductor pillar 101; the second gate 300 serves as a common gate for two adjacent transistors.

[0060] The semiconductor structure and its fabrication method provided in this embodiment can avoid interference between two adjacent word lines, thereby reducing static leakage current during device use.

[0061] It should be understood that the "method for preparing a semiconductor structure" in this application is based on the same inventive concept as the aforementioned "semiconductor structure", and therefore has at least all the features and advantages of the aforementioned "semiconductor structure", which will not be repeated here.

[0062] In some embodiments, the substrate includes: A substrate 100 is provided, on which a first dielectric layer 110, a second dielectric layer 120 and a third dielectric layer 130 are sequentially formed, and a fourth dielectric layer 140 is formed on the second surface of the substrate 100; the first surface and the second surface are disposed opposite to each other along a second direction; The first dielectric layer 110 and the third dielectric layer 130 are made of the same material, while the first dielectric layer 110, the second dielectric layer 120 and the fourth dielectric layer 140 are made of different materials.

[0063] In some specific embodiments, the method for fabricating the semiconductor structure specifically includes the following steps S10 to S90: Reference Figure 2 As shown, step S10, providing a substrate, includes: providing a substrate 100, sequentially forming a first dielectric layer 110, a second dielectric layer 120, and a third dielectric layer 130 on a first surface of the substrate 100, and forming a fourth dielectric layer 140 on a second surface of the substrate 100; the first surface and the second surface are disposed opposite to each other along a second direction; wherein, the first dielectric layer 110 and the third dielectric layer 130 are made of the same material, and the first dielectric layer 110, the second dielectric layer 120, and the fourth dielectric layer 140 are made of different materials.

[0064] The first surface of the substrate 100 can be the front surface of the substrate 100 (i.e., the device formation surface), and the second surface can be the back surface of the substrate 100. A first dielectric layer 110, a second dielectric layer 120, and a third dielectric layer 130 are sequentially formed on the front surface of the substrate 100, wherein the first dielectric layer 110 and the third dielectric layer 130 are identical, that is, the first dielectric layer 110, the second dielectric layer 120, and the first dielectric layer 110 are sequentially formed on the front surface of the substrate 100, and a fourth dielectric layer 140 is formed on the back surface of the substrate 100. The fourth dielectric layer 140 is deposited on the back surface of the substrate 100 and can serve as a stop layer for subsequent backside chemical mechanical polishing (CMP); the first dielectric layer 110 (and the third dielectric layer 130) serve as a support layer for the subsequent axial structure, and the second dielectric layer 120 serves as a formation layer for the subsequent groove region.

[0065] The first dielectric layer 110 (third dielectric layer 130), the second dielectric layer 120, and the fourth dielectric layer 140 are made of different materials. For example, the first dielectric layer 110 (third dielectric layer 130), the second dielectric layer 120, and the fourth dielectric layer 140 are insulating dielectric materials with different etching selectivity ratios. As an example, the first dielectric layer 110 (third dielectric layer 130), the second dielectric layer 120, and the fourth dielectric layer 140 can be made of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, as long as they are insulating dielectric materials with different etching selectivity ratios.

[0066] In this embodiment, the material of the substrate 100 is not specifically limited. The substrate 100 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. The substrate 100 can be a single-layer structure or a multi-layer structure. As examples, the substrate 100 may include silicon (Si) substrates, silicon-germanium (SiGe) substrates, silicon-germanium-carbon (SiGeC) substrates, silicon carbide (SiC) substrates, gallium arsenide (GaAs) substrates, indium arsenide (InAs) substrates, indium phosphide (InP) substrates, or other III / V semiconductor substrates or II / VI semiconductor substrates; or, the substrate 100 may be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Those skilled in the art can select the substrate type according to the type of transistors formed on the substrate, therefore, the type of substrate should not limit the scope of protection of this application.

[0067] For example, in this embodiment, the substrate 100 is a P-type single-crystal silicon substrate with a resistivity of 1~10 Ω·cm.

[0068] Optionally, before depositing the first dielectric layer 110, the second dielectric layer 120, the third dielectric layer 130 and the fourth dielectric layer 140, the substrate 100 is thinned to a preset thickness before the deposition process is performed.

[0069] Reference Figure 3 As shown, step S20, forming trenches 150, includes: forming a plurality of trenches 150 spaced apart along a first direction by etching a third dielectric layer 130, a second dielectric layer 120, a first dielectric layer 110, a substrate 100 and a portion of a fourth dielectric layer 140, and each trench 150 extending along a second direction.

[0070] In step S20, word line trench patterns can be defined on the surface of the third dielectric layer 130 using self-aligned double patterning (SADP) or extreme ultraviolet (EUV) lithography. For example, a photoresist layer is deposited on the third dielectric layer 130, and the photoresist layer is exposed and developed to form a word line trench pattern, which is then transferred to the third dielectric layer 130. Then, the second dielectric layer 120 and the first dielectric layer 110 are etched using the third dielectric layer 130 as a mask, and the substrate 100 is etched using the third dielectric layer 130, the second dielectric layer 120, and the first dielectric layer 110 as masks. After etching the substrate 100, the fourth dielectric layer 140 is etched, thereby forming a plurality of trenches 150 extending along the second direction.

[0071] In this embodiment, when performing the above etching process, the etching ratio of silicon to the second dielectric layer 120 needs to be greater than 50:1 to ensure the verticality of the sidewalls of the trench 150 and the uniformity of the bottom morphology.

[0072] Reference Figures 4A-4F As shown, step S30, forming the initial second gate 311 and forming the first axial structure 160, includes: refer to Figure 4A S310, deposit a first dielectric layer 110 on the sidewall and bottom wall of the trench 150, the first dielectric layer 110 filling part of the trench 150; refer to Figure 4B S320, deposit a second gate material 310 in the trench 150, the second gate material 310 being in contact with the first dielectric layer 110; refer to Figure 4C S330, the second gate material 310 is etched back so that the top surface of the second gate material 310 is lower than the first surface of the substrate 100; refer to Figure 4D S340, Deposit the first medium layer 110 in the trench 150; refer to Figure 4E S350, Remove the first dielectric layer 110 and the third dielectric layer 130 located above the second dielectric layer 120; refer to Figure 4F S360, remove the second dielectric layer 120, form a first dielectric layer 110 and a first axial structure 160 formed by the first dielectric layer 110 on the substrate 100, and form an initial second gate 311 in the channel trench 150.

[0073] In step S30, step S310 is first performed, where a first dielectric layer 110 (third dielectric layer 130) is conformally deposited inside the trench 150 (word line trench). The first dielectric layer 110 (third dielectric layer 130) covers the exposed surface of the trench 150, that is, it covers the sidewalls and bottom wall of the trench 150, and can serve as a subsequent gate oxide layer. The first dielectric layer 110 (third dielectric layer 130) does not completely fill the trench 150. Then, step S320 is performed, where a second gate material 310 is deposited inside the trench 150 to fill the trench 150. It should be understood that the second gate material 310 is in contact with the first dielectric layer 110 (third dielectric layer 130) deposited in step S310.

[0074] Optionally, in step S320, the second gate material 310 can be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.

[0075] Optionally, the second gate material 310 can be at least one of a metal or a metal nitride. For example, the second gate material 310 can be one or more of tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN).

[0076] Then, step S330 is executed to perform an etch-back process on the second gate material 310 to form a back control gate electrode, i.e., to form the initial second gate 311. It is worth noting that when performing the etch-back process on the second gate material 310, the top surface of the second gate material 310 must be lower than the first surface of the substrate 100, i.e., lower than the front surface of the substrate 100. Then, step S340 is executed to deposit a first dielectric layer 110 (third dielectric layer 130) in the trench 150, i.e., to fill the area after the etch-back of the second gate material 310 with the first dielectric layer 110 (third dielectric layer 130) to fill the trench 150 again. Then, step S350 is executed to remove the first dielectric layer 110 (third dielectric layer 130) located above the second dielectric layer 120, such as by performing a chemical mechanical polishing (CMP) planarization process to remove excess dielectric layer on the surface of the second dielectric layer 120. Then, step S360 is executed to completely remove the second dielectric layer 120, forming a large-diameter groove-shaped region, leaving the first axial structure 160 composed of the first dielectric layer 110 (the third dielectric layer 130).

[0077] Reference Figure 5 As shown, step S40, forming the deep trench structure 170, includes: forming the deep trench structure 170 by etching the first dielectric layer 110, the substrate 100, and a portion of the fourth dielectric layer 140. Specifically, it includes: A first dielectric layer 110 is deposited on the surface of the first axial structure 160 to form a second axial structure; Using the second axial structure as a mask, the first dielectric layer 110, the substrate 100 and a portion of the fourth dielectric layer 140 are etched sequentially to form a deep trench structure 170 that penetrates the first dielectric layer 110, the substrate 100 and a portion of the fourth dielectric layer 140.

[0078] Optionally, an atomic layer deposition (ALD) technique is used to deposit a first dielectric layer 110 (a third dielectric layer 130) on the surface of the first axial structure 160.

[0079] In step S40, an additional dielectric layer, namely the supplementary first dielectric layer 110 (third dielectric layer 130), is grown on the surface of the first axial structure 160 using atomic layer deposition (ALD) technology, thereby expanding the lateral dimension of the first axial structure 160 to obtain the second axial structure. Then, using the expanded axial structure, i.e., the second axial structure, as a hard mask, pattern transfer etching is performed on the axial spacing region. This etching penetrates the first dielectric layer 110 (third dielectric layer 130), the substrate 100, and part of the fourth dielectric layer 140 in one pass, forming a deep trench structure 170. The remaining silicon region after etching can be used as a conductive channel for a semiconductor device.

[0080] Optionally, in step S40, isotropic inductively coupled plasma (ICP) etching or capacitively coupled plasma (CCP) etching can be used to etch the first dielectric layer 110 (third dielectric layer 130), the substrate 100, and a portion of the fourth dielectric layer 140. Since over-etching is used, the entire substrate 100 is completely etched, so a portion of the fourth dielectric layer 140 will also be etched.

[0081] Reference Figure 6 As shown, step S50, filling the deep groove structure 170, includes: A first dielectric layer 110 material is deposited on the sidewalls and bottom wall of the deep trench structure 170; A first gate material 210 is deposited on the first dielectric layer 110 material, the first gate material 210 filling a portion of the deep trench structure 170; A gate dielectric layer 180 is deposited in the deep trench structure 170 to fill the deep trench structure 170; Then, the excess first gate material 210 and gate dielectric layer 180 are removed.

[0082] In step S50, a first dielectric layer 110 is deposited on the exposed surface of the deep trench structure 170. Optionally, the thickness of the first dielectric layer 110 in the deep trench structure 170 is 2nm to 4nm, such as about 3nm. Then, a first gate material 210 is deposited on the first dielectric layer 110, which does not completely fill the deep trench structure 170. Subsequently, a gate dielectric layer 180 is deposited on the first gate material 210 to fill the deep trench structure 170.

[0083] Optionally, the first gate material 210 can be one or more of tungsten (W), molybdenum (Mo), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). For example, titanium (Ti), titanium nitride (TiN), or other conductive electrode materials can be deposited sequentially as the first gate material 210.

[0084] Alternatively, the first gate material 210 may be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes to ensure conformal coverage within the high aspect ratio structure.

[0085] Then, the deep trench structure 170 is filled with the gate dielectric layer 180, that is, the deep trench structure 170 is filled with the gate dielectric layer 180 to fill the deep trench structure 170.

[0086] Optionally, the gate dielectric layer 180 may be made of materials with low dielectric constant (low k), such as silicon oxide, silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), organosilicon glass (OSG), and carbon-doped silicon oxide (SiCOH), and is located between the metal electrodes to ensure that smaller parasitic capacitance is generated.

[0087] Alternatively, the gate dielectric layer 180 can be filled by chemical vapor deposition or spin coating.

[0088] Then, after the gate dielectric layer 180 is filled, chemical mechanical polishing (CMP) planarization can be performed to remove excess first gate material 210 and gate dielectric layer 180.

[0089] Reference Figure 7 As shown, step S60, forming an initial first gate 200 in the deep trench structure 170, includes: The first gate material 210 is etched back so that the top surface of the first gate material 210 is lower than the first surface of the substrate 100 and higher than the top surface of the initial second gate 311; A gate dielectric layer 180 is deposited in the groove region formed after the back etching to refill the deep trench structure 170; The gate dielectric layer 180 is planarized so that the top surface of the gate dielectric layer 180 is flush with the top surface of the first dielectric layer 110.

[0090] In step S60, the first gate material 210 is first etched back to form the preliminary structure of the front gate word line. It should be understood that during the etch-back of the first gate material 210, since the first gate material 210 is a metallic material, it has a certain selectivity ratio with other dielectric materials such as the gate dielectric layer 180 and the first dielectric layer 110. Therefore, the first gate material 210 can be etched primarily. Furthermore, a small portion of the gate dielectric layer 180 may experience some loss during this process, which can be compensated for by subsequent deposition of the gate dielectric layer 180. The requirement for etching back the first gate material 210 is that the top surface of the first gate material 210 must be lower than the first surface of the substrate 100, that is, lower than the front surface of the substrate 100, and higher than the top surface of the initial second gate 311.

[0091] Then, the gate dielectric layer 180 is filled into the trench 150, that is, the gate dielectric layer 180 is used to fill the groove area formed after etching to form an inter-gate isolation structure. Then, chemical mechanical polishing planarization is performed to remove excess gate dielectric layer 180 so that the top surface of the gate dielectric layer 180 is flush or approximately flush with the top surface of the first dielectric layer 110.

[0092] Reference Figure 8 As shown, step S70, processing the initial second gate 311 to form the second gate 300, includes: The substrate, i.e., the structure obtained in step S60, is flipped, and the fourth dielectric layer 140 is thinned until the initial second gate 311 is exposed. The initial second gate 311 is etched back, and the area formed after the etch back is filled with the first dielectric layer 110 to form the second gate 300 in the channel trench 150.

[0093] In step S70, the overall structure obtained in step S60, i.e., the entire wafer with the front-side process completed, is first flipped so that the back side of the substrate 100 faces upward, i.e., the fourth dielectric layer 140 faces upward. The fourth dielectric layer 140 deposited on the back side is then thinned, such as by chemical mechanical polishing, until the first dielectric layer 110 (third dielectric layer 130) and the initial second gate 311 are exposed on the surface. Then, the exposed initial second gate 311 is etched back, and the first dielectric layer 110 (third dielectric layer 130) is deposited in the groove formed in the etched area, so that the first dielectric layer 110 (third dielectric layer 130) fills the groove and is flush with the surrounding surface.

[0094] Optionally, in this step, the deposition of the first dielectric layer 110 (third dielectric layer 130) in the groove can be performed using an ALD or CVD process.

[0095] Thus, the remaining metal electrodes form the final 4F 2 The back gate region of the structure, that is, the second gate 300, i.e. the back gate, is formed in the channel trench 150. The back gate region is isolated from the conductive channel by the first dielectric layer 110 (the third dielectric layer 130). The second gate 300, i.e. the back gate, is used to independently control the threshold voltage of the conductive channel.

[0096] Reference Figure 9 As shown, step S80, forming a portion of the first gate 200, includes: Using photolithography alignment patterning, the first gate material 210 located on one side of the gate dielectric layer 180 is defined as a first region, and the first gate material 210 located on the other side of the gate dielectric layer 180 is defined as a second region. The second region is protected by a photolithography mask, the first region is opened, and the first gate material 210 in the first region is processed by dry etching to form a first gate (positioning front gate A 211) with a first preset height.

[0097] In step S80, a first region, i.e., a first front gate pattern region, can be defined using photolithography overlay technology. A second region, i.e., a second front gate region, is protected by a photoresist mask, while the first front gate region is preferentially opened. Anisotropic dry etching is then used to etch the first gate material 210 on the right side, such as the first region, to a predetermined depth.

[0098] Then, using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes, a gate dielectric layer 180 is deposited within the etched grooves, ensuring that the gate dielectric layer 180 fills the grooves and is flush with the surrounding surfaces. The remaining right-side metal, i.e., the first gate material 210 of the first region, forms a 4F layer. 2 The front gate A 211 of the transistor in the structure forms a first gate 200 with a first preset height.

[0099] Reference Figure 10 As shown, step S90, forming the remaining portion of the first gate 200, includes: The first region is then protected by a photolithography mask, the second region is opened, and the first gate material 210 in the second region is processed by dry etching to form a first gate 200 with a second preset height (positioned as front gate B 212). The first gate 200 with the first preset height and the first gate 200 with the second preset height are staggered in the second direction, that is, the front gate A 211 and the front gate B 212 are staggered in the second direction.

[0100] In step S90, a first front gate pattern region can be defined using photolithography overlay technology, opening the other front gate corresponding to the first front gate region in step S80, i.e., opening the second front gate region. Anisotropic dry etching is used to completely remove all the first gate material 210 in the second region, forming a deep trench structure. The depth of this deep trench structure is consistent with the etch-back depth described in step S80 to ensure the symmetry of the two front gates. Atomic layer deposition or chemical vapor deposition is used to deposit a gate dielectric layer 180 within the deep trench structure to the same height as the top of the opposite front gate A 211. During this process, an etch-deposition cycle process (Bosch-like process or similar technology) is used, i.e., after depositing a gate dielectric layer 180 of a certain thickness, isotropic etch-back is performed to reopen the deep trench opening, preventing premature closure of the deep trench during filling and ensuring complete filling of the bottom of the deep trench. Then, the first gate material 210 is deposited as the front gate B 212. The material, thickness, and deposition process of the front gate B 212 are the same as those of the front gate A 211. Optionally, the bottom surface height of the front gate B 212 is the same as the top surface height of the front gate A 211, with the deviation controlled within ±5 nm. Finally, the gate dielectric layer 180 is deposited using atomic layer deposition or chemical vapor deposition (CVD) to fill the remaining gaps, and chemical mechanical polishing is performed for planarization to complete the 4F process. 2 Fabrication of the dual front gate symmetric structure in the structure.

[0101] Therefore, by staggering the electrodes in adjacent transistors, the area of ​​the electrodes facing each other can be reduced, which can effectively reduce parasitic capacitance.

[0102] Therefore, this embodiment avoids electric field coupling and interference caused by direct word line opposition between adjacent active groups by vertically offsetting the front gates of two closely spaced adjacent transistors, thereby effectively reducing static leakage current during device use. Furthermore, the vertically offset superposition of the front gates of the two adjacent transistors forms a segmented gate control structure, which can more uniformly cover the channel region of the semiconductor pillar 101, improving the gate's control over the channel potential and helping to suppress short-channel effects and subthreshold leakage current.

[0103] Accordingly, in some embodiments, a semiconductor device is provided, the semiconductor device comprising: The aforementioned semiconductor structure, and / or the semiconductor structure prepared by the aforementioned preparation method; The first word line is used to form an electrical connection with the first gate 200; The second word line is used to form an electrical connection with the second gate 300.

[0104] In this embodiment, the semiconductor device includes a DRAM memory; further, the semiconductor device can be a 4F semiconductor device with a staggered gate.2 DRAM memory architecture.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that, include: Multiple transistors arranged sequentially along a first direction; among them, Each of the transistors includes a semiconductor pillar and a first gate and a second gate located on opposite sides of the semiconductor pillar; The two first gates of two adjacent transistors are staggered in a second direction, the first direction intersecting the second direction, and the second direction being the extension direction of the semiconductor pillar; The second gate serves as the shared gate for two adjacent transistors.

2. The semiconductor structure according to claim 1, characterized in that, In the second direction, in two adjacent transistors, the bottom surface of the first gate of one transistor is flush with or higher than the top surface of the first gate of the other transistor.

3. The semiconductor structure according to claim 1, characterized in that, In some of the transistors, in the second direction, the top surface of the first gate is higher than the top surface of the second gate, and the bottom surface of the first gate is higher than the bottom surface of the second gate; Alternatively, in the remaining portion of the transistor, in the second direction, the top surface of the second gate is higher than the top surface of the first gate, and the bottom surface of the second gate is higher than the bottom surface of the first gate.

4. The semiconductor structure according to claim 1, characterized in that, Also includes: A gate dielectric layer is located between the two first gates of two adjacent transistors, and the gate dielectric layer is disposed above the top surface of the first gate and below the bottom surface of the first gate.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, In the second direction, the heights of the plurality of second gates in the plurality of transistors are consistent.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The first gate is made of metal and metal nitride; And / or, the material of the second gate includes metal and / or metal nitride.

7. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A plurality of transistors are formed on the substrate in a first direction; wherein each transistor includes a semiconductor pillar and a first gate and a second gate located on opposite sides of the semiconductor pillar respectively; two of the first gates of two adjacent transistors are staggered in a second direction, the first direction intersecting the second direction, the second direction being the extension direction of the semiconductor pillar; the second gate serves as a common gate for two adjacent transistors.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The substrate provided includes: A substrate is provided, wherein a first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially formed on a first surface of the substrate, and a fourth dielectric layer is formed on a second surface of the substrate; the first surface and the second surface are disposed opposite to each other along a second direction. The first dielectric layer and the third dielectric layer are made of the same material, while the first dielectric layer, the second dielectric layer, and the fourth dielectric layer are made of different materials.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, A plurality of transistors are formed on the substrate, arranged sequentially along a first direction, including: By etching the third dielectric layer, the second dielectric layer, the first dielectric layer, the substrate, and a portion of the fourth dielectric layer, a plurality of trenches are formed at intervals along a first direction, and each trench extends along a second direction; The second gate is formed within the trench; The first gate is formed in the deep trench structure by etching the first dielectric layer, the substrate and a portion of the fourth dielectric layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The second gate is formed within the trench, including: The first dielectric layer is deposited on the sidewalls and bottomwalls of the trench, and the first dielectric layer fills a portion of the trench. A second gate material is deposited in the trench, and the second gate material is in contact with the first dielectric layer; The second gate material is etched back so that the top surface of the second gate material is lower than the first surface of the substrate. The first medium layer is deposited within the trench; Remove the first dielectric layer and the third dielectric layer located above the second dielectric layer, and remove the second dielectric layer, form the first dielectric layer and the first axial structure formed by the first dielectric layer on the substrate, and form an initial second gate in the channel trench.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, A deep trench structure is formed by etching the first dielectric layer, the substrate, and a portion of the fourth dielectric layer, including: The first dielectric layer is deposited on the surface of the first axial structure to form the second axial structure; Using the second axial structure as a mask, the first dielectric layer, the substrate, and a portion of the fourth dielectric layer are etched sequentially to form a deep trench structure penetrating the first dielectric layer, the substrate, and a portion of the fourth dielectric layer.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that, The first gate is formed in the deep trench structure, comprising: A first gate material is deposited on the sidewalls and bottomwalls of the deep trench structure, and the first gate material fills a portion of the deep trench structure. A gate dielectric layer is deposited in the deep trench structure to fill the deep trench structure; The first gate material is etched back so that the top surface of the first gate material is lower than the first surface of the substrate and higher than the top surface of the initial second gate. A gate dielectric layer is deposited in the groove region formed after the back etching to refill the deep trench structure; The gate dielectric layer is planarized so that the top surface of the gate dielectric layer is flush with the top surface of the first dielectric layer. The first gate material is processed to form the first gate.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, A first gate material is deposited on the sidewalls and bottom wall of the deep trench structure, including: First, a first dielectric layer material is deposited on the sidewalls and bottomwalls of the deep trench structure. Then, the first gate material is deposited on the first dielectric layer material, and the first gate material fills a portion of the deep trench structure. And / or, processing the first gate material to form the first gate includes: The substrate is flipped over, and the fourth dielectric layer is thinned until the initial second gate is exposed. The initial second gate is etched back, and the area formed after the etch back is filled with the first dielectric layer to form the second gate in the channel trench; Using photolithography alignment patterning, the first gate material located on one side of the gate dielectric layer is defined as a first region, and the first gate material located on the other side of the gate dielectric layer is defined as a second region. The second region is protected by a photolithography mask, the first region is opened, and the first gate material in the first region is processed by dry etching to form a first gate with a first preset height. The first region is then protected by a photolithography mask, the second region is opened, and the first gate material in the second region is processed by dry etching to form a first gate with a second preset height. The first gate with the first preset height and the first gate with the second preset height are staggered in the second direction.

14. A semiconductor device, characterized in that, The semiconductor device includes: The semiconductor structure as described in any one of claims 1 to 6, and / or the semiconductor structure prepared by the preparation method as described in any one of claims 7 to 13; The first word line is used to form an electrical connection with the first gate; The second word line is used to form an electrical connection with the second gate.

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