Ferroelectric memory structure, ferroelectric memory array and method for controlling crystal grain orientation thereof
By setting metal nitride intercalation in ferroelectric memory and utilizing the specific lattice structure matching the ferroelectric phase lattice, the orientation of ferroelectric phase grains can be controlled, thus solving the problem of inconsistent ferroelectric phase grain orientation in ferroelectric memory and improving the performance uniformity and stability of the memory array.
Patent Information
- Application Number
- CN202611109799.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-24
- Publication Date
- 2026-11-03
AI Technical Summary
In existing ferroelectric memories, the ferroelectric phase grains of the ferroelectric layer are not oriented in a uniform way, which leads to large performance differences between memory cells and severely limits the performance uniformity of large-scale memory arrays.
By incorporating metal nitride intercalations into ferroelectric memories and utilizing the matching relationship between their specific crystal structure and the ferroelectric phase crystal structure, the orientation of the ferroelectric phase grains can be controlled, thereby improving their uniformity.
By controlling the orientation of ferroelectric phase grains, the performance uniformity of ferroelectric memory arrays was significantly improved, the performance dispersion between memory cells was reduced, and the stability of large-scale memory arrays was enhanced.
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Abstract
Description
Technical Field
[0001] This invention relates to the field of ferroelectric memory technology, and more specifically, to a ferroelectric memory structure, a ferroelectric memory array, and a method for controlling the grain orientation of the ferroelectric memory. Background Technology
[0002] Ferroelectric RAM (FRAM) is considered one of the important development directions of next-generation memory technology due to its advantages such as non-volatility, low power consumption, and high read / write speed. The read / write speed and memory window of FRAM are closely related to the ferroelectric phase orientation of the ferroelectric material, and the consistency of the ferroelectric phase orientation directly affects the performance uniformity of large-scale memory arrays.
[0003] However, in existing ferroelectric memories, the ferroelectric layer is usually formed directly on top of the metal electrode or dielectric layer. Due to the lack of effective means to control the orientation of the ferroelectric phase grains, the orientation of the ferroelectric phase in different grains in the ferroelectric layer is often inconsistent, resulting in large performance differences between memory cells and severely limiting the performance uniformity of large-scale memory arrays.
[0004] Therefore, there is an urgent need for a ferroelectric memory structure that can effectively control the grain orientation of ferroelectric materials and improve the uniformity of ferroelectric phase orientation. Summary of the Invention
[0005] In view of this, the present invention provides a ferroelectric memory structure, a ferroelectric memory array, and a method for controlling the grain orientation of the ferroelectric memory.
[0006] One aspect of the present invention provides a ferroelectric memory structure, comprising: a multilayer ferroelectric dielectric layer; and a metal nitride intercalation layer disposed between every two adjacent ferroelectric dielectric layers in the multilayer ferroelectric dielectric layer; wherein the metal nitride intercalation layer has a specific crystal phase orientation, and the ferroelectric phase grain orientation of the multilayer ferroelectric dielectric layer matches the crystal lattice structure of the metal nitride intercalation layer, so that the ferroelectric phase orientation of the multilayer ferroelectric dielectric layer is consistent.
[0007] According to an embodiment of the present invention, the metal nitride intercalation is a multilayer structure, wherein the elemental composition of each metal nitride intercalation is independently adjustable.
[0008] According to an embodiment of the present invention, the ferroelectric memory device structure further includes: a first metal layer and a second metal layer, used as electrodes to apply voltage.
[0009] According to an embodiment of the present invention, the ferroelectric storage device structure is constructed as a planar capacitor structure; wherein, in the planar capacitor structure, a first metal layer, multiple ferroelectric dielectric layers, and a second metal layer are stacked sequentially from top to bottom, and a metal nitride intercalation layer is provided between each two adjacent ferroelectric dielectric layers.
[0010] According to an embodiment of the present invention, the ferroelectric storage device structure is constructed as a three-dimensional capacitor structure; wherein, in the three-dimensional capacitor structure, multiple ferroelectric dielectric layers are wrapped around the surface of the first metal layer or the second metal layer and one end thereof, with the first metal layer or the second metal layer as the central axis, and a metal nitride intercalation layer is provided between each two adjacent ferroelectric dielectric layers.
[0011] According to an embodiment of the present invention, the material for the metal nitride intercalation includes Ti. x N y W x N y Ta x N y At least one of them.
[0012] According to embodiments of the present invention, the material of the ferroelectric layer includes HfO2, ZrO2, and mixtures thereof.
[0013] According to an embodiment of the present invention, the ferroelectric dielectric layer is doped with at least one element selected from Si, Al, Ti, Nb, Yb, La, and Gd.
[0014] Another aspect of the present invention provides a ferroelectric memory array, comprising: multiple array-distributed ferroelectric memory device structures, wherein the ferroelectric memory device structures are as described above; wherein ferroelectric memory device structures located in the same row share a word line and are selected by a row decoder; ferroelectric memory device structures located in the same column share a bit line and are selected by a column decoder; all ferroelectric memory device structures share a board line to control signals; the selected ferroelectric memory device structure in the ferroelectric memory array can release charge when a read pulse is applied to the board line, and generate a voltage change on the corresponding bit line; wherein the voltage change is amplified to a logic level by a sensitive amplifier and output as read data, and is written back to the ferroelectric memory device structure by the sensitive amplifier.
[0015] Another aspect of the present invention provides a method for controlling the grain orientation of a ferroelectric memory structure, comprising: setting a metal nitride intercalation layer between every two adjacent ferroelectric dielectric layers in a multilayer ferroelectric dielectric layer; controlling the grain size and lattice orientation of the metal nitride intercalation layer through a metal nitride growth process; and using the lattice structure of the metal nitride intercalation layer to match and induce the ferroelectric phase grain orientation of the multilayer ferroelectric dielectric layer, so that the ferroelectric phase orientation of the multilayer ferroelectric dielectric layer is consistent.
[0016] The ferroelectric memory structure, ferroelectric memory array, and grain orientation control method provided in the embodiments of the present invention have at least the following beneficial effects:
[0017] (1) The ferroelectric memory structure, ferroelectric memory array, and grain orientation control method provided in the embodiments of the present invention improve the uniformity of ferroelectric phase orientation by setting metal nitride intercalation in the ferroelectric capacitor and utilizing the matching between the specific orientation lattice structure of the metal nitride and the lattice structure of the ferroelectric phase. Compared with the structure without metal nitride intercalation, the present invention can make the ferroelectric phase orientation highly consistent, significantly improving the performance uniformity of the ferroelectric memory array.
[0018] (2) The ferroelectric memory structure, ferroelectric memory array and its grain orientation control method provided in the embodiments of the present invention have independently adjustable elemental composition of multilayer metal nitride intercalation, and the material orientation of each layer of metal nitride can be precisely controlled through process regulation. Attached Figure Description
[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0020] Figure 1 A schematic diagram illustrating the structure of a ferroelectric memory according to an embodiment of the present invention is shown.
[0021] Figure 2 A schematic diagram of a planar capacitor structure according to an embodiment of the present invention is shown.
[0022] Figure 3 A schematic diagram of a three-dimensional capacitor structure according to an embodiment of the present invention is shown.
[0023] Figure 4 A schematic diagram of a ferroelectric memory array according to an embodiment of the present invention is shown.
[0024] Figure 5 A flowchart illustrating a method for controlling grain orientation in a ferroelectric memory structure according to an embodiment of the present invention is shown schematically.
[0025] Figure 6 The schematic diagram illustrates the grain orientation control principle of a ferroelectric memory structure according to an embodiment of the present invention. Detailed Implementation
[0026] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.
[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0028] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0029] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).
[0030] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.
[0031] Figure 1 A schematic diagram of a ferroelectric memory structure according to an embodiment of the present invention is shown.
[0032] like Figure 1 As shown, the ferroelectric memory structure may include, for example, a multilayer ferroelectric dielectric layer and a metal nitride intercalation layer disposed between every two adjacent ferroelectric dielectric layers in the multilayer ferroelectric dielectric layer.
[0033] The metal nitride intercalation has a specific crystal phase orientation, and the ferroelectric phase grain orientation of the multilayer ferroelectric dielectric layer matches the crystal lattice structure of the metal nitride intercalation, so that the ferroelectric phase orientation of the multilayer ferroelectric dielectric layer is consistent.
[0034] In this embodiment, the ferroelectric dielectric layer can be a ferroelectric material, and the metal nitride intercalation layer can be a metal nitride material with a specific crystal phase.
[0035] The ferroelectric memory structure provided in this invention improves the uniformity of ferroelectric phase orientation by incorporating metal nitride intercalations within ferroelectric capacitors and utilizing the matching between the specific orientation of the metal nitride lattice structure and the ferroelectric phase lattice structure to regulate the grain orientation of the upper ferroelectric layer. Compared to structures without metal nitride intercalations, this invention achieves highly consistent ferroelectric phase orientation, significantly improving the performance uniformity of the ferroelectric memory array.
[0036] According to an embodiment of the present invention, the metal nitride intercalation is a multilayer structure, wherein the elemental composition of each metal nitride intercalation is independently adjustable.
[0037] For example, in this embodiment, the elemental composition of each metal nitride intercalation layer in the ferroelectric capacitor may differ, and the material orientation of each metal nitride layer can be precisely controlled through process regulation.
[0038] According to an embodiment of the present invention, the ferroelectric memory device structure may further include, for example, a first metal layer and a second metal layer for applying voltage as electrodes.
[0039] For example, from Figure 1 Viewed from the indicated direction, the first metal layer can serve as the upper electrode of the ferroelectric capacitor and is located on the top layer of the device. The second metal layer can serve as the lower electrode of the ferroelectric capacitor and is located on the bottom layer of the device.
[0040] According to an embodiment of the present invention, the material of the metal nitride intercalation may, for example, include Ti. x N y W x N y Ta x N y At least one of them.
[0041] According to embodiments of the present invention, the material of the ferroelectric layer may include, for example, HfO2, ZrO2 and mixtures thereof (which may be doped with Si, Al, Ti, Nb, Yb, La, Gd, etc.).
[0042] According to embodiments of the present invention, the ferroelectric storage device structure can be constructed in two structural forms, such as a planar capacitor structure and a three-dimensional capacitor structure, as detailed below. Figure 2 and Figure 3 As shown.
[0043] Figure 2 A schematic diagram of a planar capacitor structure according to an embodiment of the present invention is shown.
[0044] like Figure 2 As shown, a first metal layer, multiple ferroelectric dielectric layers, and a second metal layer are stacked sequentially from top to bottom, with a metal nitride intercalation layer between each two adjacent ferroelectric dielectric layers.
[0045] For example, from Figure 2 Viewed from the indicated direction, the planar capacitor structure consists of, from top to bottom: a first metal layer, a ferroelectric dielectric layer, a metal nitride intercalation layer, a ferroelectric dielectric layer, a metal nitride intercalation layer, a ferroelectric dielectric layer, and a second metal layer.
[0046] Figure 3A schematic diagram of a three-dimensional capacitor structure according to an embodiment of the present invention is shown.
[0047] like Figure 3 As shown, in this three-dimensional capacitor structure, multiple ferroelectric dielectric layers are wrapped around the surface of the first metal layer or the second metal layer and one end of the first metal layer or the second metal layer, with the first metal layer or the second metal layer as the central axis. A metal nitride intercalation layer is provided between each two adjacent ferroelectric dielectric layers.
[0048] For example, from Figure 3 Viewed from the indicated direction, in this three-dimensional capacitor structure, the first metal layer can be used as the central axis, and then multiple ferroelectric dielectric layers are wrapped from the inside out. A metal nitride intercalation layer is provided between each two adjacent ferroelectric dielectric layers, and the outermost layer is the second metal layer.
[0049] Correspondingly, from Figure 3 Looking at the direction shown, in this three-dimensional capacitor structure, the second metal layer can be used as the central axis, and then multiple ferroelectric dielectric layers are wrapped from the inside to the outside. A metal nitride intercalation layer is provided between each two adjacent ferroelectric dielectric layers, and the outermost layer is the first metal layer.
[0050] Based on this ferroelectric memory structure, embodiments of the present invention also provide a ferroelectric memory array, as detailed below. Figure 4 As shown.
[0051] Figure 4 A schematic diagram of a ferroelectric memory array according to an embodiment of the present invention is shown.
[0052] like Figure 4 As shown, the ferroelectric memory array may, for example, include multiple ferroelectric memory device structures distributed in an array.
[0053] Ferroelectric storage devices located in the same row share a word line (WL), which is controlled and selected by the row decoder; ferroelectric storage devices located in the same column share a bit line (BL), which is controlled and selected by the column decoder; and all ferroelectric storage devices share a plate line (PL) to control the signal.
[0054] In this embodiment, the selected ferroelectric memory device structure in the ferroelectric memory array can release charge when a read pulse is applied to the board line and generate a voltage change on the corresponding bit line; wherein, the voltage change is amplified to a logic level by a sensitive amplifier and then output as read data, and is written back to the ferroelectric memory device structure by the sensitive amplifier.
[0055] Based on this ferroelectric memory structure, embodiments of the present invention also provide a method for controlling the grain orientation of the ferroelectric memory structure, as detailed in [link to details]. Figure 5 As shown.
[0056] Figure 5 A flowchart illustrating a method for controlling grain orientation in a ferroelectric memory structure according to an embodiment of the present invention is shown.
[0057] like Figure 5 As shown, the method for controlling the grain orientation of the ferroelectric memory structure may include steps S1 to S3.
[0058] S1, a metal nitride intercalation layer is provided between every two adjacent ferroelectric layers in the multilayer ferroelectric layer.
[0059] S2, through the metal nitride growth process, controls the grain size and lattice orientation of the metal nitride intercalation.
[0060] S3 utilizes the lattice structure matching of metal nitride intercalation to induce the orientation of ferroelectric phase grains in the multilayer ferroelectric dielectric layer, so as to make the ferroelectric phase orientation of the multilayer ferroelectric dielectric layer uniform.
[0061] The method for controlling the grain orientation of a ferroelectric memory structure provided in this invention improves the uniformity of the ferroelectric phase orientation by incorporating a metal nitride intercalation layer within the ferroelectric capacitor and utilizing the matching between the specific orientation of the metal nitride lattice structure and the ferroelectric phase lattice structure. Compared to structures without metal nitride intercalations, this invention achieves a highly consistent ferroelectric phase orientation, significantly improving the performance uniformity of the ferroelectric memory array.
[0062] Figure 6 The schematic diagram illustrates the grain orientation control principle of a ferroelectric memory structure according to an embodiment of the present invention.
[0063] like Figure 6 As shown, the principle of controlling the grain orientation of ferroelectric layers using metal nitride intercalation in ferroelectric memory structures is as follows: By pre-regulating the grain orientation of the metal nitride intercalation, it acts as a crystal orientation inducer, guiding adjacent ferroelectric layers (i.e., ferroelectric dielectric layers) to form a ferroelectric phase orientation with high consistency, thereby improving the performance uniformity of the ferroelectric memory array. This principle utilizes the matching relationship between the specific orientation lattice structure of the metal nitride and the lattice structure of the ferroelectric phase to control the growth direction of the ferroelectric grains.
[0064] Specifically, from Figure 6Viewed from the indicated direction, the ferroelectric memory structure includes multiple ferroelectric layers disposed between the lower and upper electrodes, and ultrathin metal nitride intercalation layers disposed between adjacent ferroelectric layers. These metal nitride intercalation layers do not merely serve as conductive functional layers, but rather as functional structural layers for controlling the orientation of the ferroelectric grains. By adjusting the growth conditions of the metal nitride, such as process parameters like temperature, oxygen partial pressure, deposition rate, and substrate orientation, the grain size and crystal orientation of the metal nitride intercalation layers can be controlled, resulting in a crystal structure with a specific crystal alignment direction.
[0065] Furthermore, such as Figure 6 As indicated by the arrows in the metal nitride intercalation diagram, the grains in the metal nitride intercalation layer have a relatively consistent orientation. When the ferroelectric material continues to grow on the surface of this metal nitride intercalation layer, due to the matching relationship between the lattice structure of the metal nitride and the lattice structure of the ferroelectric material, the metal nitride intercalation can induce the upper ferroelectric material grains to align along a specific direction, causing the ferroelectric phase orientation in the ferroelectric layer to gradually change from a random distribution to a more consistent orientation distribution.
[0066] like Figure 6 As shown on the right, without grain orientation control, the polarization direction within the ferroelectric layer exhibits significant randomness, easily leading to performance differences between different memory cells. However, after metal nitride intercalation, the polarization direction of the ferroelectric layer becomes more concentrated and consistent, resulting in a more uniform ferroelectric phase distribution. Since key performance parameters of ferroelectric memory cells, such as read / write speed and memory window, are closely related to the ferroelectric phase orientation, controlling the ferroelectric grain orientation can effectively reduce performance dispersion between memory cells and improve the consistency of large-scale memory arrays.
[0067] This ferroelectric memory structure can employ a configuration of alternating layers of ferroelectric layers and multiple layers of metal nitride intercalations. The metal nitride intercalations at different locations can utilize different elemental compositions. By adjusting the material composition and growth process of each metal nitride intercalation layer, the grain orientation of different ferroelectric layers can be independently controlled.
[0068] Furthermore, the grain orientation control principle of this ferroelectric memory structure is applicable not only to planar capacitor structures but also to three-dimensional capacitor structures. In both planar and three-dimensional ferroelectric memory structures, the grain orientation of the ferroelectric layer can be controlled by adjusting the grain size and orientation of the metal nitride intercalation layer and utilizing the lattice matching relationship between the metal nitride and the ferroelectric phase, thereby improving the uniformity of ferroelectric phase orientation and the stability of array performance.
[0069] In summary, the grain orientation control principle of this ferroelectric memory structure transforms the traditional random grain growth process of ferroelectric thin films into a tunable crystal epitaxial induction process by introducing metal nitride intercalations with specific crystal orientations, thus achieving uniform control of the ferroelectric phase orientation. Compared to traditional structures without metal nitride intercalations, this invention effectively improves the uniformity of polarization distribution in ferroelectric memories, reduces device performance dispersion, and enhances the overall uniformity of the memory array.
[0070] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.
Claims
1. A ferroelectric storage device structure, characterized in that, The structure includes: Multilayer ferroelectric dielectric layer; Metal nitride intercalations are provided between every two adjacent ferroelectric layers in the multilayer ferroelectric dielectric layer; The metal nitride intercalation layer has a specific crystal phase orientation, and the ferroelectric phase grain orientation of the multilayer ferroelectric dielectric layer matches the crystal lattice structure of the metal nitride intercalation layer, so that the ferroelectric phase orientation of the multilayer ferroelectric dielectric layer is consistent.
2. The structure according to claim 1, characterized in that, The metal nitride intercalation layer has a multilayer structure, wherein the elemental composition of each metal nitride intercalation layer is independently adjustable.
3. The structure according to claim 1, characterized in that, The ferroelectric storage device structure also includes: The first metal layer and the second metal layer are used as electrodes to apply voltage.
4. The structure according to claim 3, characterized in that, The ferroelectric storage device structure is constructed as a planar capacitor structure; In the planar capacitor structure, the first metal layer, the multilayer ferroelectric dielectric layer, and the second metal layer are stacked sequentially from top to bottom, and a metal nitride intercalation layer is provided between each two adjacent ferroelectric dielectric layers.
5. The structure according to claim 3, characterized in that, The ferroelectric storage device structure is constructed as a three-dimensional capacitor structure; In the three-dimensional capacitor structure, the multilayer ferroelectric dielectric layer is wrapped around the surface of the first metal layer or the second metal layer and one end of the first metal layer or the second metal layer, with the first metal layer or the second metal layer as the central axis, and the metal nitride intercalation layer is provided between each two adjacent ferroelectric dielectric layers.
6. The structure according to claim 1, characterized in that, The material of the metal nitride intercalation includes Ti. x N y W x N y Ta x N y At least one of them.
7. The structure according to claim 1, characterized in that, The materials of the ferroelectric dielectric layer include HfO2, ZrO2, and mixtures thereof.
8. The structure according to claim 7, characterized in that, The ferroelectric dielectric layer is doped with at least one element selected from Si, Al, Ti, Nb, Yb, La, and Gd.
9. A ferroelectric memory array, characterized in that, The ferroelectric memory array includes: A ferroelectric storage device structure with multiple arrays distributed, wherein the ferroelectric storage device structure is the ferroelectric storage device structure according to any one of claims 1 to 8; Ferroelectric storage devices located in the same row share a word line, which is controlled and selected by the row decoder; ferroelectric storage devices located in the same column share a bit line, which is controlled and selected by the column decoder; all ferroelectric storage devices share a board line to control the signal. The selected ferroelectric memory device structure in the ferroelectric memory array can release charge when a read pulse is applied to the plate line and generate a voltage change on the corresponding bit line; The voltage change is amplified to a logic level by a sensitive amplifier and then output as read data, which is then written back to the ferroelectric storage device structure by the sensitive amplifier.
10. A method for controlling grain orientation in a ferroelectric memory structure, characterized in that, The method includes: Metal nitride intercalation layers are disposed between every two adjacent ferroelectric dielectric layers in a multilayer ferroelectric dielectric layer; The grain size and lattice orientation of the metal nitride intercalation layer are controlled by the metal nitride growth process. The lattice structure of the metal nitride intercalation is used to match and induce the ferroelectric phase grain orientation of the multilayer ferroelectric dielectric layer, so that the ferroelectric phase orientation of the multilayer ferroelectric dielectric layer is consistent.