Transistor fabrication method and transistor thereof

Abstract

The present disclosure provides a transistor preparation method and a transistor thereof. The transistor preparation method comprises: preparing an epitaxial layer; preparing a gate on the epitaxial layer; preparing a passivation insulating layer covering the gate on the epitaxial layer; preparing a source and a drain on the passivation insulating layer, the source and the drain being in contact with the epitaxial layer through the passivation insulating layer, preparing a first field plate on the passivation insulating layer, the source being electrically connected with the first field plate; growing a silicon nitride field plate dielectric layer covering the first field plate on the passivation insulating layer by using an LPCVD process at a growth temperature of 650-700 DEG C; and forming a second field plate on the silicon nitride field plate dielectric layer, the second field plate being electrically connected with the source.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a transistor preparation method and a transistor thereof. BACKGROUND

[0002] High Electron Mobility Transistor (HEMT) is a kind of heterojunction field effect transistor, which is widely used in wireless communication, automotive electronics and other fields.

[0003] However, silicon-based GaN HEMT has long faced severe challenges in suppressing leakage current, especially the stability of saturation leakage current. Existing research shows that the technical difficulties mainly come from three aspects: first, due to the difference in material properties between the GaN epitaxial layer and the silicon substrate, high dislocation density and stress are generated in the epitaxial film, and these defects are prone to form parasitic leakage channels; second, during the high-voltage dynamic switching process of the device, the channel electrons are easily captured by the buffer layer and the energy state of the device surface, resulting in a sudden drop in saturation leakage current, i.e., a serious "current collapse" effect, which is a key factor restricting the output power of the device; third, the low thermal conductivity of the silicon substrate makes the device poor in heat dissipation, and thermal stress further activates defects and energy states, worsening the long-term reliability of leakage current.

[0004] To suppress the above effects, the technical means of introducing a field plate structure and cooperating with an insulating dielectric layer are generally used in the field to optimize the electric field distribution at the edge of the gate. In the prior art, a chemical vapor deposition process is usually used to prepare an insulating layer on the surface of the device, which serves as both a passivation layer and a field plate dielectric layer for dispersing the electric field and suppressing the abnormal injection of electrons into the buffer layer.

[0005] However, the inventors have found that the insulating dielectric prepared by conventional deposition process as a field plate dielectric layer has inherent technical bottlenecks. On the one hand, the thin film prepared by conventional deposition process has insufficient density, and there are many defects in the film and at the interface, which are prone to form leakage channels during long-term operation, resulting in that the isolated leakage current can only be maintained at a certain order of magnitude; on the other hand, due to the limitation of the preparation principle, some existing film preparation processes are prone to cause unintended damage to the surface of the underlying semiconductor barrier layer, which in turn introduces additional surface energy states, which to some extent aggravates the current collapse effect under dynamic conditions, and weakens the protective effect of the field plate structure.

[0006] To address the aforementioned issues of thin film density and interface damage, a few studies have attempted to use alternative deposition processes under high-temperature conditions to prepare insulating films with higher density. However, the excessively high deposition temperatures result in thermal budgets that approach or even exceed the thermal tolerance limits of the epitaxial layer and the formed electrode structure in GaN-based devices. High-temperature processes easily induce thermal decomposition and stress mismatch in the epitaxial layer, and damage the prepared source-drain ohmic contact characteristics. Therefore, how to prepare a field plate dielectric layer with both high density and low interface defects while avoiding high-temperature thermal damage, in order to simultaneously suppress unexpected surface energy states and buffer layer leakage, has become a pressing technical challenge that has remained unresolved for a long time. Summary of the Invention

[0007] This disclosure provides a transistor fabrication method and a transistor thereof, aiming to improve the density and interface quality of the field plate dielectric layer without introducing additional process damage, thereby effectively suppressing leakage current and current collapse effect, and significantly improving transistor yield. The technical solution is as follows: On one hand, a method for fabricating a transistor is provided, the method comprising: Fabricate the epitaxial layer; A gate is fabricated on the epitaxial layer; A passivation insulating layer covering the gate is formed on the epitaxial layer; A source and a drain are fabricated on the passivation insulating layer, and the source and the drain pass through the passivation insulating layer to contact the epitaxial layer; A first field plate is fabricated on the passivated insulating layer, and the source electrode is electrically connected to the first field plate; Using LPCVD process, a silicon nitride field plate dielectric layer covering the first field plate is grown on the passivation insulating layer at a growth temperature of 650~700℃. A second field plate is formed on the dielectric layer of the silicon nitride field plate, and the second field plate is electrically connected to the source electrode.

[0008] Optionally, a silicon nitride field plate dielectric layer covering the first field plate is grown on the passivation insulating layer, comprising: The silicon nitride field plate dielectric layer is grown under a pressure of 200-300 mtorr in an atmosphere of NH3 and dimethyldichlorosilane for a growth time of 60-150 min.

[0009] Optionally, the flow rate of NH3 is 100~300 sccm, and the flow rate of dimethyldichlorosilane is 20~60 sccm.

[0010] Optionally, the thickness of the silicon nitride field plate dielectric layer is 20~100nm.

[0011] Optionally, the method further includes: After the source and drain layers are fabricated, and before the silicon nitride dielectric layer of the first field plate is fabricated, an intermediate insulating layer, which is a silicon oxide layer, is fabricated on the passivation insulating layer using a CVD process.

[0012] Optionally, a second field plate is formed on the silicon nitride field plate dielectric layer, comprising: A groove is formed on the dielectric layer of the silicon nitride field plate; The second field plate is fabricated within the groove, and in a cross-section perpendicular to the surface of the silicon nitride field plate dielectric layer, the shape of the second field plate is Z-shaped.

[0013] Optionally, the method further includes: A protective layer, which is a silicon oxide layer, is formed on the dielectric layer of the silicon nitride field plate to cover the second field plate.

[0014] On the other hand, a transistor is provided, the transistor comprising: an epitaxial layer; A gate, the gate being located on the epitaxial layer; The passivation insulating layer is located in the epitaxial layer and covers the gate; The source and drain are located on the passivation insulating layer and extend through the passivation insulating layer to contact the epitaxial layer; The first field plate is located on the passivation insulating layer and is electrically connected to the source electrode; A silicon nitride field plate dielectric layer is located in the passivation insulating layer and covers the first field plate; The second field plate is located on the dielectric layer of the silicon nitride field plate, and the second field plate is electrically connected to the source electrode. The silicon nitride field plate dielectric layer is a silicon nitride layer grown using LPCVD process at a temperature of 650~700℃, and the refractive index of the silicon nitride field plate dielectric layer is 2.0~2.02.

[0015] Optionally, the transistor further includes a protective layer covering the second field plate, the protective layer being a silicon oxide layer.

[0016] Optionally, the silicon nitride field plate dielectric layer includes a groove; the second field plate is located in the groove, and in a cross section perpendicular to the surface of the silicon nitride field plate dielectric layer, the shape of the second field plate is Z-shaped.

[0017] The beneficial effects of the technical solutions provided in this disclosure are: The transistor in this scheme adopts a double-layer field plate system consisting of a first field plate, a second field plate, and a silicon nitride field plate dielectric layer located between the two. The silicon nitride field plate dielectric layer is a dense silicon nitride layer grown by LPCVD process at 650~700℃.

[0018] On one hand, the first field plate is located on the passivation insulating layer, and the second field plate is located on the LPCVD silicon nitride field plate dielectric layer. Both the first and second field plates are electrically connected to the source, forming a double-layer source-connected field plate structure. The first field plate initially disperses the peak electric field at the gate edge, while the second field plate extends towards the drain via the LPCVD silicon nitride field plate dielectric layer below it, further modulating the drain-side electric field. Through the spatial differences in the two field plates and the differences in the dielectric layers, multi-level, progressive modulation of the channel electric field is achieved, effectively suppressing the injection of electrons from the barrier layer into surface traps, thereby significantly improving the current collapse effect.

[0019] On the other hand, the silicon nitride field plate dielectric layer fabricated using LPCVD technology and the passivation insulating layer constitute a composite dielectric stack. The passivation insulating layer, as the first dielectric layer, provides basic device passivation and electrical isolation; the LPCVD silicon nitride field plate dielectric layer, as the second dielectric layer, has higher density and interface quality than the first dielectric layer. The LPCVD silicon nitride field plate dielectric layer is grown at a low temperature of 650–700°C, avoiding thermal damage to the epitaxial layer caused by high-temperature processes. Simultaneously, its dense film structure effectively blocks vertical tunneling leakage channels, and its low-defect interface reduces the trapping of channel electrons by surface traps. Thus, the first and second dielectric layers are functionally complementary—the first dielectric layer focuses on isolation and protection, while the second dielectric layer focuses on dense blocking and interface optimization—together forming a composite insulation system that combines isolation, passivation, and electric field modulation functions.

[0020] Based on the synergistic effect of the aforementioned double-layer field plate structure and composite dielectric stack, the transistors of this disclosure embodiment can simultaneously achieve a significant reduction in leakage current and effective suppression of current collapse without increasing the number of photomask layers or significantly increasing process complexity. Test results show that the drain current (Idss) of the transistor using the technical solution of this disclosure is reduced by an order of magnitude (from the 1E-10 level to the 1E-11 level) compared to the transistor using a single PECVD silicon nitride field plate dielectric layer. This improvement is not achieved by simply superimposing the functions of the first field plate, the second field plate, or the LPCVD silicon nitride field plate dielectric layer, but by the synergistic effect of the double-layer field plate modulating the electric field through dielectric layers of different densities, and the simultaneous suppression of leakage channels and surface traps by the composite dielectric stack. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure; Figure 2 This is a flowchart of another transistor fabrication method provided in this disclosure embodiment; Figure 3 This is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure; Figure 4 This is a comparison diagram of the leakage current of transistors fabricated according to embodiments of this disclosure and transistors fabricated using related technologies.

[0023] The attached figures are labeled as follows: 100: Substrate; 101: Epitaxial layer; 102: Gate; 103: Passivation insulating layer; 104: Source / drain layer; 105: First field plate; 106: Silicon nitride field plate dielectric layer; 107: Intermediate insulating layer; 108: Second field plate; 109: Protective layer; 1041: Source; 1042: Drain; 1000: Groove; 1011: Channel layer; 1012: Barrier layer; 1013: Buffer layer; 1014: p-GaN layer. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0025] Figure 1 This is a flowchart of a transistor fabrication method provided in an embodiment of this disclosure. See also... Figure 1 The method includes the following steps: S11, Create the epitaxial layer.

[0026] For example, the epitaxial layer includes a stacked channel layer and a barrier layer.

[0027] S12. A gate is fabricated on the epitaxial layer.

[0028] For example, the gate is used to control the turn-on and turn-off of the transistor.

[0029] S13. A passivation insulating layer covering the gate is formed on the epitaxial layer.

[0030] For example, the passivation insulating layer includes an AlN layer and a SiN layer.

[0031] S14. A source and a drain are formed on the passivation insulating layer, and the source and the drain pass through the passivation insulating layer and contact the epitaxial layer.

[0032] S15. A first field plate is fabricated on the passivated insulating layer, and the source electrode is electrically connected to the first field plate.

[0033] S16. Using LPCVD process, at a growth temperature of 650~700℃, a silicon nitride field plate dielectric layer covering the first field plate is grown on the passivation insulating layer.

[0034] S17. A second field plate is formed on the dielectric layer of the silicon nitride field plate, and the second field plate is electrically connected to the source electrode.

[0035] The transistor in this scheme adopts a double-layer field plate system consisting of a first field plate, a second field plate, and a silicon nitride field plate dielectric layer located between the two. The silicon nitride field plate dielectric layer is a dense silicon nitride layer grown by LPCVD process at 650~700℃.

[0036] On one hand, the first field plate is located on the passivation insulating layer, and the second field plate is located on the LPCVD silicon nitride field plate dielectric layer. Both the first and second field plates are electrically connected to the source, forming a double-layer source-connected field plate structure. The first field plate initially disperses the peak electric field at the gate edge, while the second field plate extends towards the drain via the LPCVD silicon nitride field plate dielectric layer below it, further modulating the drain-side electric field. Through the spatial differences in the two field plates and the differences in the dielectric layers, multi-level, progressive modulation of the channel electric field is achieved, effectively suppressing the injection of electrons from the barrier layer into surface traps, thereby significantly improving the current collapse effect.

[0037] On the other hand, the silicon nitride field plate dielectric layer fabricated using LPCVD technology and the passivation insulating layer constitute a composite dielectric stack. The passivation insulating layer, as the first dielectric layer, provides basic device passivation and electrical isolation; the LPCVD silicon nitride field plate dielectric layer, as the second dielectric layer, has higher density and interface quality than the first dielectric layer. The LPCVD silicon nitride field plate dielectric layer is grown at a low temperature of 650–700°C, avoiding thermal damage to the epitaxial layer caused by high-temperature processes. Simultaneously, its dense film structure effectively blocks vertical tunneling leakage channels, and its low-defect interface reduces the trapping of channel electrons by surface traps. Thus, the first and second dielectric layers are functionally complementary—the first dielectric layer focuses on isolation and protection, while the second dielectric layer focuses on dense blocking and interface optimization—together forming a composite insulation system that combines isolation, passivation, and electric field modulation functions.

[0038] Based on the synergistic effect of the aforementioned double-layer field plate structure and composite dielectric stack, the transistors of this disclosure embodiment can simultaneously achieve a significant reduction in leakage current and effective suppression of current collapse without increasing the number of photomask layers or significantly increasing process complexity. Test results show that the drain current (Idss) of the transistor using the technical solution of this disclosure is reduced by an order of magnitude (from the 1E-10 level to the 1E-11 level) compared to the transistor using a single PECVD silicon nitride field plate dielectric layer. This improvement is not achieved by simply superimposing the functions of the first field plate, the second field plate, or the LPCVD silicon nitride field plate dielectric layer, but by the synergistic effect of the double-layer field plate modulating the electric field through dielectric layers of different densities, and the simultaneous suppression of leakage channels and surface traps by the composite dielectric stack.

[0039] Figure 2 This is a flowchart of another transistor fabrication method provided in this disclosure. See also... Figure 2 The method includes the following steps: S21. Fabricate an epitaxial layer on the substrate.

[0040] In one example, the epitaxial layer includes a buffer layer, a channel layer, a barrier layer, and a p-GaN layer formed sequentially.

[0041] In another example, the epitaxial layer consists only of a buffer layer, a channel layer, and a barrier layer formed sequentially.

[0042] In this embodiment of the disclosure, the substrate can be any one of sapphire substrate, Si substrate, SiC substrate and GaN substrate, and the material of the substrate is not limited in this embodiment of the disclosure.

[0043] For example, the substrate is a Si substrate.

[0044] In this embodiment of the disclosure, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer are sequentially fabricated using metal-organic chemical vapor deposition (MOCVD).

[0045] In one example, step S21 includes: The first step is to fabricate a buffer layer on the substrate.

[0046] In this embodiment of the disclosure, the buffer layer can be a GaN buffer layer.

[0047] The second step is to create a channel layer on the buffer layer.

[0048] In this embodiment of the disclosure, the channel layer can be a GaN channel layer.

[0049] The third step is to create a barrier layer on top of the channel layer.

[0050] In this embodiment of the disclosure, the barrier layer can be an AlGaN barrier layer.

[0051] In this embodiment of the disclosure, the thickness of the barrier layer can be 10~50nm.

[0052] For example, the thickness of the barrier layer is 35 nm.

[0053] The fourth step is to fabricate a p-GaN layer on the barrier layer.

[0054] In this embodiment, the thickness of the p-GaN layer can be 70~100nm.

[0055] For example, the thickness of the p-GaN layer is 85 nm.

[0056] In another example, step four can also be omitted, that is, step S21 does not include fabricating a p-GaN layer on the barrier layer.

[0057] S22. Fabricate the gate on the epitaxial layer.

[0058] In this embodiment of the disclosure, the gate is fabricated using plasma-enhanced physical vapor deposition (PEPVD).

[0059] In this embodiment of the disclosure, the gate includes a first TiN layer, an AlN dielectric layer, a SiN dielectric layer, and a second TiN layer stacked sequentially.

[0060] In this implementation, inserting AlN and SiN layers into the TiN layer of the gate can improve the gate insulation strength, effectively reduce gate leakage current, and suppress current collapse.

[0061] In the embodiments disclosed herein, the thickness of the AlN dielectric layer is 1-5 nm, the thickness of the SiN dielectric layer is 5-100 nm, and the thickness of both the first TiN layer and the second TiN layer is 50-200 nm.

[0062] For example, the thickness of the AlN dielectric layer is 3 nm, the thickness of the SiN dielectric layer is 50 nm, and the thickness of the first TiN layer and the second TiN layer is 100 nm.

[0063] In other examples, the gate may consist of only a metal layer or a metal stack.

[0064] In one example, the gate is located on a p-GaN layer.

[0065] In another example, the gate is located on the barrier layer.

[0066] S23. A passivation insulating layer covering the gate is formed on the epitaxial layer.

[0067] In one example, step S23 includes: The first step is to grow the first passivation insulator layer on the epitaxial layer using the atomic layer deposition (ALD) process.

[0068] In this embodiment of the disclosure, the first passivated insulator layer may be an AlN layer.

[0069] In this embodiment of the disclosure, the thickness of the first passivation insulator layer can be 1~5nm.

[0070] For example, the thickness of the first passivation insulator layer can be 3 nm.

[0071] The second step involves growing a second passivated insulator layer on the first passivated insulator layer using a chemical vapor deposition (CVD) process. The first and second passivated insulator layers together constitute the passivated insulating layer.

[0072] In this embodiment of the disclosure, the second passivated insulator layer may be a SiN layer.

[0073] In this embodiment of the disclosure, the thickness of the second passivated insulator layer can be 5~100nm.

[0074] For example, the thickness of the second passivated insulator layer can be 50 nm.

[0075] In this implementation, a passivation insulating layer composed of AlN and SiN layers is used, which has excellent interface quality and high insulation strength, effectively reducing gate leakage current, suppressing current collapse, and improving device breakdown voltage and operating stability. Specifically, the AlN layer is grown using the ALD process, which can achieve an ultra-thin insulating film with excellent coverage, while the SiN layer is grown using the CVD process, which has good density and strong insulation, and can form good passivation on the transistor surface, reducing transistor surface defects and leakage channels, and improving the stability and withstand voltage of the gate insulation.

[0076] S24. A source-drain layer is fabricated on the passivation insulating layer, and the source-drain layer passes through the passivation insulating layer and contacts the epitaxial layer.

[0077] In this embodiment of the disclosure, the source and drain layers are fabricated using a PECVD process.

[0078] In this embodiment of the disclosure, the source and drain layers pass through the passivation insulating layer and the barrier layer to contact the channel layer.

[0079] In another embodiment, the source and drain layers can also contact the barrier layer through the passivation insulating layer.

[0080] Accordingly, step S24 includes: Holes are created in the passivation insulating layer and epitaxial layer by etching, extending to the channel layer or barrier layer; then source and drain layers are fabricated at the holes by patterning.

[0081] In this embodiment of the disclosure, the source and drain layers can be a Ti, AlSi, and TiN metal stack.

[0082] In other examples, the source and drain layers can also be other structures, such as TiN, Al, and TiN metal stacks.

[0083] In this embodiment of the disclosure, the source-drain layer includes a source and a drain.

[0084] For example, the first field plate is located between the drain and the gate.

[0085] S25. Fabricate a first field plate on the passivated insulating layer. The first field plate is electrically connected to the source in the source-drain electrode.

[0086] In this embodiment of the disclosure, the first field board and the source in the source-drain circuit can be connected by traces during packaging.

[0087] In this embodiment of the disclosure, the first field plate is located between the source and the drain.

[0088] For example, a first field plate is located between the drain and the gate. The width and length of the first field plate may both be smaller than the source or drain.

[0089] In other examples, the first field plate and the source can also be connected in other ways.

[0090] In this embodiment of the disclosure, a first field plate is fabricated on a passivated insulating layer using a PEPVD process.

[0091] In this implementation, the first field plate grown using PEPVD technology is electrically connected to the source in the source-drain electrode, which can effectively disperse the electric field at the gate edge, reduce the peak electric field, and improve the breakdown voltage of the device.

[0092] In this embodiment of the disclosure, the first field plate can be a TiN layer.

[0093] In this embodiment of the disclosure, the thickness of the first field plate can be 30~100nm.

[0094] For example, the thickness of the first field plate is 50 nm.

[0095] S26. An intermediate insulating layer is formed on the passivated insulating layer, and the intermediate insulating layer covers the source and drain layers.

[0096] In this embodiment of the disclosure, the intermediate insulating layer may be a SiO2 layer.

[0097] In this embodiment of the disclosure, an intermediate insulating layer is fabricated on a passivated insulating layer using a CVD process.

[0098] In this implementation, the SiO2 layer is fabricated using CVD technology. It has excellent insulation properties, a dense structure, and few defects, which can form good insulation and isolation for the underlying source and drain layers, thus avoiding short circuits.

[0099] In this embodiment, the thickness of the intermediate insulating layer is 50~100nm.

[0100] For example, the thickness of the intermediate insulating layer is 75 nm.

[0101] S27. At a temperature of 650~700℃, a silicon nitride field plate dielectric layer covering the first field plate is grown on the intermediate insulating layer using the LPCVD process.

[0102] In this embodiment of the present disclosure, a silicon nitride field plate dielectric layer covering the first field plate is grown in an atmosphere of NH3 and dimethyldichlorosilane, wherein the NH3 flow rate is 100~300 sccm and the dimethyldichlorosilane flow rate is 20~60 sccm.

[0103] In this implementation, controlling the NH3 flow rate to 100–300 sccm provides a sufficient nitrogen source, ensuring precise silicon nitride chemical proportions. Controlling the dimethyldichlorosilane flow rate to 20–60 sccm provides a stable silicon source, resulting in a moderate film growth rate and improved insulation performance of the silicon nitride field plate dielectric layer.

[0104] In this embodiment of the disclosure, the NH3 flow rate is 200 sccm and the dimethyldichlorosilane flow rate is 45 sccm.

[0105] In this implementation, the NH3 flow rate is 200 sccm and the dimethyldichlorosilane flow rate is 45 sccm, which balances the growth rate and the insulation performance of the film.

[0106] In this embodiment of the disclosure, a silicon nitride field plate dielectric layer is grown under a pressure of 200~300 mtorr for a growth time of 60~150 min.

[0107] In this implementation, the pressure is relatively low at 200~300 mtorr, which can improve the uniformity of the diffusion of the reactive gas, thereby improving the thickness uniformity of the silicon nitride field plate dielectric layer and further reducing the leakage current channel. The growth time is 60~150 min, which can obtain a silicon nitride field plate dielectric layer with moderate thickness and excellent uniformity, meeting the pressure resistance requirements of the field plate, while avoiding excessive stress due to excessive thickness.

[0108] In this embodiment of the disclosure, the silicon nitride field plate dielectric layer is grown under a pressure of 250 mtorr for a growth time of 100 min.

[0109] In this implementation, with a pressure of 250 mtorr and a growth time of 100 min, the thickness and pressure resistance can be guaranteed to the greatest extent.

[0110] In this embodiment of the disclosure, the thickness of the silicon nitride field plate dielectric layer is 20~100nm.

[0111] In this implementation, the dielectric layer thickness of the silicon nitride field plate is 20–100 nm, which balances withstand voltage, insulation, low stress and low parasitic capacitance, thereby improving device reliability and electrical performance.

[0112] For example, the thickness of the silicon nitride field plate dielectric layer is 50 nm.

[0113] S28. A second field plate is grown on the dielectric layer of the silicon nitride field plate, and the second field plate is connected to the source in the source-drain field.

[0114] In one example, step S28 includes: The first step is to create grooves on the dielectric layer of the silicon nitride field plate.

[0115] The second step is to fabricate a second field plate within the groove. In a cross-section perpendicular to the surface of the dielectric layer of the silicon nitride field plate, the shape of the second field plate is Z-shaped.

[0116] In this implementation, the second field plate is located within the groove, and the shape of the second field plate is Z-shaped. The second field plate can simultaneously adhere to the bottom surface of the groove and the sidewall of the dielectric layer of the silicon nitride field plate, dispersing leakage current from both horizontal and vertical dimensions, thereby comprehensively improving the reliability of the transistor.

[0117] The second field plate is prepared using the PEPVD process.

[0118] In this embodiment of the disclosure, the second field plate and the source of the source-drain layer can be connected by traces during packaging.

[0119] In other examples, the second field plate and the source can also be connected in other ways.

[0120] In this embodiment of the disclosure, the second field plate can be a TiN layer.

[0121] In this embodiment of the disclosure, the second field plate may be disposed above the gate.

[0122] In this embodiment of the disclosure, the leakage current can be further improved by setting a second field plate, thereby comprehensively improving the reliability of the transistor.

[0123] The silicon nitride field plate dielectric layer and the synergistic effect of the upper and lower layers combine to form a composite dielectric stack consisting of a passivation insulating layer, a silicon nitride field plate dielectric layer, a first field plate, and a second field plate. The passivation insulating layer is responsible for basic device passivation and electrical isolation, while the silicon nitride field plate dielectric layer is responsible for electric field dispersion and surface trap suppression of the field plate dielectric. The two layers form a functionally complementary composite dielectric structure.

[0124] S29. A protective layer is grown on the dielectric layer of the silicon nitride field plate, and the protective layer covers the second field plate.

[0125] The protective layer is prepared using the PECVD process.

[0126] In this implementation, a protective layer is grown on the silicon nitride field plate dielectric layer using the PECVD process. The deposition temperature is low, the process compatibility is strong, and it will not cause thermal damage to the underlying second field plate and the silicon nitride field plate dielectric layer.

[0127] In this embodiment of the disclosure, the protective layer may be a SiO2 layer.

[0128] In this embodiment, a protective layer is grown under the following conditions: pressure of 3000~5000mT, high-frequency power of 600~800W, SiH4 flow rate of 500~700sccm, NH3 flow rate of 160~230sccm, and electrode spacing (Gap Between Electrodes, GAP) of 12~14mm.

[0129] For example, a protective layer was grown under the following conditions: a pressure of 4000 mT, a high-frequency power of 700 W, a SiH4 flow rate of 600 sccm, an NH3 flow rate of 200 sccm, and an electrode spacing (GAP) of 13 mm.

[0130] This method is applicable to the fabrication of normally off or normally on GaN high electron mobility transistor (HEMT) devices.

[0131] Figure 3 This is a schematic diagram of a transistor structure provided in an embodiment of this disclosure. See also... Figure 3The transistor includes: an epitaxial layer 101; a gate 102 located on the epitaxial layer 101; a passivation insulating layer 103 located on the epitaxial layer 101 and covering the gate 102; a source 1041 and a drain 1042 located on the passivation insulating layer 103, extending through the passivation insulating layer 103 and contacting the epitaxial layer 101; and a first field plate 105 located on the passivation insulating layer 103, electrically connected to the source 1041. A silicon nitride field plate dielectric layer 106 is located on the passivation insulating layer 103 and covers the first field plate 105; a second field plate 108 is located on the silicon nitride field plate dielectric layer 106 and is electrically connected to the source 1041; the silicon nitride field plate dielectric layer 106 is a silicon nitride layer grown using LPCVD process at a temperature of 650~700℃, and the refractive index of the silicon nitride field plate dielectric layer 106 is 2.0~2.02.

[0132] The transistor in this scheme adopts a double-layer field plate system consisting of a first field plate, a second field plate, and a silicon nitride field plate dielectric layer located between the two. The silicon nitride field plate dielectric layer is a dense silicon nitride layer grown by LPCVD process at 650~700℃.

[0133] On one hand, the first field plate is located on the passivation insulating layer, and the second field plate is located on the LPCVD silicon nitride field plate dielectric layer. Both the first and second field plates are electrically connected to the source, forming a double-layer source-connected field plate structure. The first field plate initially disperses the peak electric field at the gate edge, while the second field plate extends towards the drain via the LPCVD silicon nitride field plate dielectric layer below it, further modulating the drain-side electric field. Through the spatial differences in the two field plates and the differences in the dielectric layers, multi-level, progressive modulation of the channel electric field is achieved, effectively suppressing the injection of electrons from the barrier layer into surface traps, thereby significantly improving the current collapse effect.

[0134] On the other hand, the silicon nitride field plate dielectric layer fabricated using LPCVD technology and the passivation insulating layer constitute a composite dielectric stack. The passivation insulating layer, as the first dielectric layer, provides basic device passivation and electrical isolation; the LPCVD silicon nitride field plate dielectric layer, as the second dielectric layer, has higher density and interface quality than the first dielectric layer. The LPCVD silicon nitride field plate dielectric layer is grown at a low temperature of 650–700°C, avoiding thermal damage to the epitaxial layer caused by high-temperature processes. Simultaneously, its dense film structure effectively blocks vertical tunneling leakage channels, and its low-defect interface reduces the trapping of channel electrons by surface traps. Thus, the first and second dielectric layers are functionally complementary—the first dielectric layer focuses on isolation and protection, while the second dielectric layer focuses on dense blocking and interface optimization—together forming a composite insulation system that combines isolation, passivation, and electric field modulation functions.

[0135] Based on the synergistic effect of the aforementioned double-layer field plate structure and composite dielectric stack, the transistors of this disclosure embodiment can simultaneously achieve a significant reduction in leakage current and effective suppression of current collapse without increasing the number of photomask layers or significantly increasing process complexity. Test results show that the drain current (Idss) of the transistor using the technical solution of this disclosure is reduced by an order of magnitude (from the 1E-10 level to the 1E-11 level) compared to the transistor using a single PECVD silicon nitride field plate dielectric layer. This improvement is not achieved by simply superimposing the functions of the first field plate, the second field plate, or the LPCVD silicon nitride field plate dielectric layer, but by the synergistic effect of the double-layer field plate modulating the electric field through dielectric layers of different densities, and the simultaneous suppression of leakage channels and surface traps by the composite dielectric stack.

[0136] In this embodiment, the first field plate 105 is located on the passivation insulating layer 103, and the first field plate 105 is connected to the source 1041 in the source-drain layer 104 through the wiring during packaging.

[0137] In this embodiment of the disclosure, the epitaxial layer 101 includes: a channel layer 1011, a barrier layer 1012, a buffer layer 1013, and a p-GaN layer 1014.

[0138] The buffer layer 1013, the channel layer 1011, the barrier layer 1012, and the p-GaN layer 1014 are stacked sequentially.

[0139] In this embodiment of the disclosure, the channel layer 1011 can be a GaN layer.

[0140] In this embodiment of the disclosure, the barrier layer 1012 can be an AlGaN layer.

[0141] In this embodiment of the disclosure, the thickness of the barrier layer 1012 can be 10~50nm.

[0142] For example, the thickness of the barrier layer 1012 is 35 nm.

[0143] In this embodiment of the disclosure, the buffer layer 1013 may be a GaN layer.

[0144] In this embodiment of the disclosure, the thickness of the p-GaN layer 1014 can be 70~100nm.

[0145] For example, the thickness of the p-GaN layer 1014 can be 85 nm.

[0146] In this embodiment of the disclosure, the transistor may further include a substrate 100.

[0147] A buffer layer 1013, a channel layer 1011, a barrier layer 1012, and a p-GaN layer 1014 are sequentially stacked on a substrate 100.

[0148] In this embodiment of the disclosure, the substrate 100 can be any one of sapphire substrate, Si substrate, SiC substrate and GaN substrate, and the material of the substrate 100 is not limited in this embodiment of the disclosure.

[0149] For example, substrate 100 is a Si substrate.

[0150] In this embodiment of the disclosure, the passivation insulating layer 103 may include a first passivation insulator layer and a second passivation insulator layer stacked sequentially.

[0151] In this embodiment of the disclosure, the first passivated insulator layer may be an AlN layer.

[0152] In this embodiment of the disclosure, the second passivated insulator layer may be a SiN layer.

[0153] In this embodiment of the disclosure, the thickness of the first passivation insulator layer can be 1~5nm.

[0154] For example, the thickness of the first passivation insulator layer can be 3 nm.

[0155] In this embodiment of the disclosure, the thickness of the second passivated insulator layer can be 5~100nm.

[0156] For example, the thickness of the second passivated insulator layer can be 50 nm.

[0157] In this embodiment of the present disclosure, the source-drain layer 104 includes a source 1041 and a drain 1042, which respectively pass through the passivation insulating layer 103 and contact the epitaxial layer 101.

[0158] In this embodiment of the disclosure, the source and drain layers 104 can be a Ti, AlSi and TiN metal stack.

[0159] In other examples, the source-drain layer 104 can also be other structures, such as a TiN, Al and TiN metal stack.

[0160] In this embodiment of the disclosure, the first field plate 105 can be a TiN layer.

[0161] In this embodiment of the disclosure, the thickness of the first field plate 105 can be 30~100nm.

[0162] For example, the thickness of the first field plate 105 is 50 nm.

[0163] In this embodiment of the present disclosure, the transistor may further include: an intermediate insulating layer 107 covering the source and drain layers 104, and a silicon nitride field plate dielectric layer 106 located on the intermediate insulating layer 107.

[0164] In this embodiment of the disclosure, the intermediate insulating layer 107 is a silicon oxide layer.

[0165] In this embodiment of the disclosure, the intermediate insulating layer 107 may be a SiO2 layer.

[0166] In this embodiment of the disclosure, the thickness of the intermediate insulating layer 107 can be 50~100nm.

[0167] For example, the thickness of the intermediate insulating layer 107 can be 80 nm.

[0168] In this embodiment of the disclosure, the transistor may further include a protective layer 109 covering the second field plate 108.

[0169] In this embodiment of the disclosure, the silicon nitride field plate dielectric layer 106 includes a groove 1000.

[0170] In this embodiment of the disclosure, the second field plate 108 is partially located within the groove 1000, and the shape of the second field plate 108 in a cross section perpendicular to the surface of the silicon nitride field plate dielectric layer 106 is Z-shaped.

[0171] In this implementation, the second field plate is located within the groove, and the shape of the second field plate is Z-shaped. The second field plate can simultaneously adhere to the bottom surface of the groove and the sidewall of the dielectric layer of the silicon nitride field plate, dispersing leakage current from both horizontal and vertical dimensions, thereby comprehensively improving the reliability of the transistor.

[0172] In this embodiment of the disclosure, the second field board 108 is connected to the source-drain layer 104 via traces during packaging.

[0173] In this embodiment of the disclosure, the second field plate 108 can be a TiN layer.

[0174] In this embodiment of the disclosure, the protective layer 109 may be a SiO2 layer.

[0175] In this embodiment of the disclosure, the thickness of the second field plate 108 can be 30~100nm.

[0176] For example, the thickness of the second field plate 108 is 50 nm.

[0177] In this embodiment of the disclosure, the thickness of the protective layer 109 can be 50~100nm.

[0178] For example, the thickness of the protective layer 109 can be 80 nm.

[0179] It is worth noting that, Figure 3 This only shows the hierarchical relationship of the various film layers in a transistor, and does not represent the actual shape of each film layer. For example, some film layers (such as metal layers) may only be located in the central region, while the edges are covered by other dielectric layers.

[0180] Figure 4 This is a comparison chart of leakage current of transistors fabricated according to embodiments of this disclosure and transistors fabricated using related technologies. See also... Figure 4 The horizontal axis represents the drain voltage (Vd), in volts (V), and the vertical axis represents the off-state leakage current (Idss), in amperes (A). Solid lines represent transistors provided in this embodiment (with a passivation insulating layer fabricated using LPCVD technology), while dashed lines represent transistors fabricated using related technologies (with a passivation insulating layer fabricated using PECVD technology, and the relevant parameters differ during fabrication). Figure 4 It can be seen that the leakage current of the transistor provided by the related technology increases significantly when the voltage is 12V. The off-state source leakage current level of the transistor fabricated in the embodiments of this disclosure is 1×10⁻⁶. -11 A. The high density of LPCVD deposition allows transistors fabricated using related techniques to achieve off-state source-drain current levels of 1×10⁻⁶. -10 A. The off-state source leakage current of the transistor produced in this embodiment is reduced by an order of magnitude compared with the off-state source leakage current of the transistor provided by related technologies, thereby improving the reliability and stability of the transistor.

[0181] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for fabricating a transistor, characterized in that, The transistor fabrication method includes: Create the epitaxial layer (101); A gate (102) is fabricated on the epitaxial layer (101); A passivation insulating layer (103) covering the gate (102) is formed on the epitaxial layer (101). A source (1041) and a drain (1042) are fabricated on the passivation insulating layer (103), and the source (1041) and the drain (1042) pass through the passivation insulating layer (103) and contact the epitaxial layer (101); A first field plate (105) is fabricated on the passivation insulating layer (103), and the source electrode (1041) is electrically connected to the first field plate (105); Using LPCVD process, a silicon nitride field plate dielectric layer (106) covering the first field plate (105) is grown on the passivation insulating layer (103) at a growth temperature of 650~700℃. A second field plate (108) is formed on the silicon nitride field plate dielectric layer (106), and the second field plate (108) is electrically connected to the source (1041).

2. The transistor fabrication method according to claim 1, characterized in that, A silicon nitride field plate dielectric layer (106) covering the first field plate (105) is grown on the passivation insulating layer (103), comprising: The silicon nitride field plate dielectric layer (106) is grown under a pressure of 200~300 mtorr in an atmosphere of NH3 and dimethyldichlorosilane for a growth time of 60~150 min.

3. The transistor fabrication method according to claim 2, characterized in that, The flow rate of NH3 is 100~300 sccm, and the flow rate of dimethyldichlorosilane is 20~60 sccm.

4. The transistor fabrication method according to any one of claims 1 to 3, characterized in that, The thickness of the silicon nitride field plate dielectric layer (106) is 20~100nm.

5. The transistor fabrication method according to any one of claims 1 to 3, characterized in that, The method further includes: After the source (1041) and drain (1042) are fabricated, and before the silicon nitride field plate dielectric layer (106) is fabricated, an intermediate insulating layer (107) is fabricated on the passivation insulating layer (103) using a CVD process. The intermediate insulating layer (107) is a silicon oxide layer.

6. The transistor fabrication method according to any one of claims 1 to 3, characterized in that, A second field plate (108) is formed on the silicon nitride field plate dielectric layer (106), including: A groove (1000) is formed on the dielectric layer (106) of the silicon nitride field plate. The second field plate (108) is fabricated in the groove (1000), and in a cross section perpendicular to the surface of the silicon nitride field plate dielectric layer (106), the shape of the second field plate (108) is Z-shaped.

7. The transistor fabrication method according to any one of claims 1 to 3, characterized in that, The method further includes: A protective layer (109) covering the second field plate (108) is formed on the silicon nitride field plate dielectric layer (106), and the protective layer (109) is a silicon oxide layer.

8. A transistor, characterized in that, include: Epitaxial layer (101); A gate (102) is located on the epitaxial layer (101); A passivation insulating layer (103) is located on the epitaxial layer (101) and covers the gate (102). The source (1041) and drain (1042) are located on the passivation insulating layer (103) and are in contact with the epitaxial layer (101) through the passivation insulating layer (103); The first field plate (105) is located on the passivation insulating layer (103) and is electrically connected to the source (1041); A silicon nitride field plate dielectric layer (106) is located in the passivation insulating layer (103) and covers the first field plate (105). The second field plate is located on the dielectric layer (106) of the silicon nitride field plate, and the second field plate is electrically connected to the source (1041); The silicon nitride field plate dielectric layer (106) is a silicon nitride layer grown using LPCVD process at a temperature of 650~700℃, and the refractive index of the silicon nitride field plate dielectric layer (106) is 2.0~2.

02.

9. The transistor according to claim 8, characterized in that, The transistor further includes a protective layer (109) that covers the second field plate (108), and the protective layer (109) is a silicon oxide layer.

10. The transistor according to claim 8 or 9, characterized in that, The silicon nitride field plate dielectric layer (106) includes a groove (1000); the second field plate (108) is located in the groove (1000), and in a cross section perpendicular to the surface of the silicon nitride field plate dielectric layer (106), the shape of the second field plate (108) is Z-shaped.

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