Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same. The method includes forming a channel region on a substrate, forming a source / drain region adjacent to the channel region, and forming a spacer structure in contact with the channel region and the source / drain region. The method further includes depositing a metal oxide (e.g., yttrium oxide) layer on the spacer structure, performing an anneal process to reduce oxygen vacancies in the spacer structure, and removing the metal oxide layer. The method further includes forming a gate structure on the channel region and the spacer structure. The semiconductor structure formed by the method improves the quality of the spacer structure.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for forming the semiconductor structure. Background Technology

[0002] With advancements in semiconductor technology, the demand for higher storage capacity, faster processing systems, higher efficiency, and lower cost continues to grow. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs, fin field-effect transistors (finFETs), and gate-all-around field-effect transistors (GAAFETs). This scaling down has increased the complexity of semiconductor manufacturing processes. Maintaining or improving the quality of scaled-down transistors is particularly challenging when reducing the size of critical components that directly affect transistor performance, such as the gate spacer and inner spacer. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a fin structure on a substrate; forming a plurality of channel regions in the fin structure; forming source / drain (S / D) regions adjacent to the plurality of channel regions; forming an inner spacer between the plurality of channel regions and in contact with the S / D regions; depositing a metal oxide layer on the inner spacer; annealing the metal oxide layer and the inner spacer; removing the metal oxide layer; and forming a gate structure surrounding the plurality of channel regions and in contact with the inner spacer.

[0004] According to some embodiments of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a fin structure on a substrate, wherein the fin structure includes first and second nanostructures; depositing a gate spacer on the fin structure; forming an inner spacer between the first and second nanostructures; depositing a metal oxide layer on the surface of the gate spacer and the inner spacer; increasing the oxygen concentration in the gate spacer and the inner spacer; removing the metal oxide layer; and forming a gate structure surrounding the first and second nanostructures.

[0005] According to some embodiments of this disclosure, a semiconductor structure is provided, the semiconductor structure comprising: a fin structure on a substrate, wherein the fin structure includes a first channel region and a second channel region above the first channel region; a source / drain (S / D) region on the fin structure and adjacent to the first and second channel regions; an inner spacer between the first and second channel regions and in contact with the S / D region; and a gate structure surrounding the first and second channel regions and in contact with the inner spacer, wherein the interface between the gate structure and the inner spacer comprises a rare earth element. Attached Figure Description

[0006] The nature of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to common industry practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of illustration and discussion.

[0007] Figure 1 This is an isometric view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0008] Figure 2 This is a cross-sectional view of a semiconductor device including a semiconductor transistor according to some embodiments.

[0009] Figure 3A and 3B According to some embodiments Figure 2 An enlarged cross-sectional view of the semiconductor device portion.

[0010] Figure 4A and 4B This is a flowchart of a method for forming a semiconductor transistor according to some embodiments.

[0011] Figure 5 and 6 An isometric view of an intermediate structure during the manufacture of a semiconductor transistor according to some embodiments.

[0012] Figure 7 , 8 1, 2, 3, 4, 5, 6, 7, 8, and 9 are cross-sectional views of an intermediate structure during the manufacture of a semiconductor transistor according to some embodiments.

[0013] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally indicate the same, functionally similar, and / or structurally similar elements. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature formed over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features are not in direct contact. In the context of this application, forming a first feature on a second feature means that the first feature is formed in direct contact with the second feature. Furthermore, reference numerals and / or letters may be repeated in various examples of this disclosure. This repetition itself does not specify a relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of explanation, this document may use spatial relative terms such as "under," "below," "below," "above," "on top," and similar terms to describe the relationship of one element or feature relative to another element(s) as illustrated in the accompanying drawings. Besides the orientations shown in the drawings, these spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

[0016] In some embodiments, the terms "about" and "substantially" may refer to a value of a given quantity that varies within 5% (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to be limiting. It should be understood that the terms "about" and "substantially" may refer to a percentage of the values ​​that, as interpreted by one of skill in the art, represent the teachings in this document.

[0017] It should be noted that the terms "an embodiment," "an exemplary embodiment," "an exemplary embodiment," and "exemplary" in this specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but different embodiments may not necessarily include that specific feature, structure, or characteristic. Furthermore, such terms do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly stated or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments will be within the knowledge of those skilled in the art.

[0018] It should be understood that the wording or terminology used in this document is for illustrative rather than restrictive purposes, and that the wording or terminology used in this specification should be interpreted by one of skill in the art in light of the teachings herein.

[0019] As an example, and not a limitation, nanostructured transistors with nanosheet (NS) or nanowire (NW) channel regions, such as GAA nanosheet (NS) or nanowire (NW) FETs (collectively referred to as "GAAFETs"), can be formed as follows: A fin structure having alternating silicon-germanium (SiGe) and silicon (Si) NS or NW layers is formed on a substrate (e.g., on a semiconductor substrate). A sacrificial gate structure is then formed on a middle portion of the fin structure to cover the top and sidewall surfaces of the fin structure, such that the edge portions of the fin structure are not covered by the sacrificial gate structure. A gate spacer structure having multiple gate spacers can then be formed above the side surfaces of the sacrificial gate structure to protect it from subsequent etching processes. The edge portions of the fin structure not covered by the sacrificial gate structure are removed. Subsequently, an inner spacer structure with multiple inner spacers is formed by depositing a dielectric material to fill the spaces formed by the etched portions of the SiGe NS or NW layer, with the edge portion of the SiGe NS or NW layer recessed relative to the edge portion of the SiGe NS or NW layer. Next, a source / drain (S / D) epitaxial structure is formed to abut (or contact) the edge portion of the fin-like structure, such that the S / D epitaxial structure contacts the SiGe NS or NW layer and is isolated (or separated) from the SiGe NS or NW layer by the inner spacers. The source / drain may be referred to individually or collectively as a source or a drain depending on the context. In a subsequent operation, the sacrificial gate structure is removed but the gate spacers are not removed to expose the top and sidewall surfaces of the fin-like structure. The SiGe NS or NW layer is selectively removed from the fin-like structure. During the selective removal process, the SiGe NS or NW layer and the inner spacers are not removed. Subsequently, a gate structure is formed to surround the SiGe NS or NW layer. Similar to the SiGe NS or NW layer prior to selective removal, the gate structure is isolated (or separated) from the S / D epitaxial structure by a gate spacer structure and an inner spacer structure. The gate structure includes an interface layer (IL) above the Si NS or NW layer, a gate dielectric layer on the IL, and a gate electrode including a suitable work function metal on the gate dielectric layer.

[0020] The structure of a GAAFET can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes that include dual or multiple patterning procedures. Dual or multiple patterning procedures combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be created compared to those achievable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A gate spacer structure is then formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the GAA transistor structure.

[0021] As semiconductor devices continue to scale down, in exemplary GAAFETs formed through the process described above, critical dimensions of the GAAFET, such as the length / width of the Si NS or NW layer serving as the channel and the metal gate structure, are reduced. Consequently, the dimensions of other GAAFET components, such as the gate spacer and inner spacer, also decrease. Highly sensitive to scaling down, the gate spacer and inner spacer become increasingly critical to the electrical performance and reliability of the GAAFET. The gate spacer and inner spacer can comprise polycrystalline or amorphous structures of dielectric materials, such as silicon nitride (SiN), silicon oxy-carbon-nitride (SiOCN), silicon carbon-nitride (SiCN), or silicon oxy-nitride (SiON). As the dimensions of the gate spacer and inner spacer decrease, the parasitic capacitance between the conductive elements adjacent to the gate spacer and inner spacer may increase, resulting in a longer RC delay, which may affect device performance. Furthermore, the quantum tunneling effect becomes increasingly pronounced when the gate spacer and inner spacer have smaller dimensions. Specifically, defects such as oxygen vacancies in the gate spacer and inner spacer can manifest as tunneling-assisted traps for leakage current, which may further affect and degrade the electrical performance of the GAAFET.

[0022] The embodiments described herein relate to overcoming the challenges mentioned above. In some embodiments, a structure of a semiconductor device may include a channel region, a gate structure on the channel region, and an S / D region adjacent to the channel region. The structure may further include a gate spacer on the channel region and isolating the gate structure and the S / D region. The structure may further include an inner spacer between the channel regions and isolating the gate structure and the S / D region. The gate spacer and the inner spacer may include a dielectric material having reduced oxygen vacancies and a dielectric constant close to about 3.9 (similar to the dielectric constant of silicon dioxide (SiO2)), such that leakage current between the channel region, the S / D region, and the gate structure can be appropriately suppressed and parasitic capacitance associated with the gate spacer and the inner spacer can be reduced. In some embodiments, a method of forming the structure may include forming the channel region, forming the gate spacer and the inner spacer, and forming the S / D region. The method may further include treating the gate spacer and the inner spacer by depositing a metal oxide (e.g., a rare earth oxide, such as yttrium oxide (Y₂O₃)) layer on the gate spacer and the inner spacer, performing an annealing process to reduce the density of oxygen vacancies in the gate spacer and the inner spacer, and removing the metal oxide layer. Specifically, during the annealing process, oxygen (O) atoms in the metal oxide layer may diffuse into the gate spacer and the inner spacer to replace oxygen vacancies therein, thereby increasing the oxygen concentration in the gate spacer and the inner spacer and improving dielectric properties. Furthermore, due to the reaction between the metal atoms (e.g., rare earth metal atoms) of the metal oxide layer and the Si atoms of the gate spacer and the inner spacer, the annealing process may form a silicate layer (e.g., a rare earth silicate) between the metal oxide layer and the gate spacer layer and between the metal oxide layer and the inner spacer layer. After removing the metal oxide layer, the silicate layer can then be removed, thereby reducing the thickness of the gate spacer and the inner spacer, consistent with a scale-down process. This method of processing the gate spacer and the inner spacer can also be applied to the fabrication processes of other semiconductor transistors, such as planar MOSFETs and finFETs. The method may further include forming a gate structure in contact with the processed gate spacer and the processed inner spacer.

[0023] According to some embodiments, a semiconductor device 100 having a plurality of transistors 105 formed above a substrate 102 is referenced. Figure 1 and 2 To illustrate. The semiconductor device 100 may be included in a microprocessor, memory cell or other integrated circuit (IC). Figure 1 An isometric view of a semiconductor device 100 is shown. Figure 2 Examples along Figure 1 A cross-sectional view (e.g., along the xz plane) of the semiconductor device 100 captured by line AB.

[0024] Reference Figure 1 The substrate 102 may be a semiconductor material, such as silicon. In some embodiments, the substrate 102 may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 102 may include (i) an elemental semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) an alloy semiconductor, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), gallium indium phosphide (InGaP), gallium indium arsenide (InGaAs), gallium indium arsenide phosphide (InGaAsP), aluminum indium arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); or (iv) combinations thereof. Additionally, the substrate 102 may be doped depending on design requirements (e.g., p-type or n-type substrate). In some embodiments, the substrate 102 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, a crystal orientation of the substrate 102 may be (100), (110), or (111).

[0025] Although Figure 1 and 2 The diagram shows a fin structure 110 housing two transistors 105, but any number of transistors 105 may be arranged along the fin structure 110. In some embodiments, the transistors 105 may include a plurality of fin structures 110 extending along a first horizontal direction (e.g., in the x-direction) and a gate structure 115 traversing the plurality of fin structures 110 along a second horizontal direction (e.g., in the y-direction). In some embodiments, a crystal orientation of the fin structure 110 may be the same as the crystal orientation of the substrate 102.

[0026] See Figure 1 and 2One or more nanosheet (NS) layers 120 may be disposed above the fin structure 110. Each NS layer 120 may be covered by a gate structure 115 to serve as a channel for a transistor 105. For example, a top surface, a side surface, and a bottom surface of each NS layer 120 may be surrounded by and in contact with the gate structure 115. The fin structure 110 and the NS layers 120 may be made of a material similar to (e.g., with a lattice mismatch of about 5%) the substrate 102. In some embodiments, a crystal orientation of the NS layer 120 may be the same as the crystal orientation of the fin structure 110. In some embodiments, each of the fin structure 110 and the NS layer 120 may be made of Si or SiGe. Each of the fin structure 110 and the NS layer 120 may be undoped, doped with a p-type dopant, doped with an n-type dopant, or doped with an intrinsic dopant. In some embodiments, the fin structure 110 and the NS layer 120 may be doped together with a p-type dopant or with an n-type dopant. In some embodiments, the thickness of each of the NS layers 120 may be between about 5 nm and about 10 nm. Although Figure 1 Each transistor 105 is shown to include four NS layers 120, and Figure 2 Each transistor 105 is shown to include three NS layers 120, but any number of NS layers 120 may be included in each transistor 105. For example, each transistor 105 may include one, two, five, or six NS layers 120.

[0027] See Figure 1 and 2 The gate structure 115 may be a multilayer structure that surrounds each NS layer 120 to regulate the transistor 105. The gate structure 115 may have a length Lc, which represents the channel length of the transistor 105. The length Lc may have any suitable horizontal (e.g., in the x-direction) dimension, such as about 3 nm to about 200 nm. In some embodiments, the height of the gate structure 115 above the fin structure 110 along a vertical direction (e.g., in the z-direction) may be between about 10 nm and about 20 nm. In some embodiments, the height of the gate structure 115 above the fin structure 110 may be greater than about 20 nm. In some embodiments, a thickness of the gate structure 115 adjacent to the NS layers 120 may be between about 5 nm and about 15 nm, corresponding to a spacing between adjacent NS layers 120. By way of example and not limitation, each gate structure 115 may include a dielectric stack formed of an IL 115a and a gate dielectric layer 115b. Additionally, each gate structure 115 may include a gate electrode 115c having a capping layer, one or more work function metal layers, and a metal filler, which are not shown separately for simplicity. Figure 1 middle.

[0028] IL 115a can be formed by oxidizing a surface of NS layer 120 in a thermal process or in a chemical solution. The thickness of IL 115a can be between about 0.2 nm and about 2 nm. For example, the thickness of IL 115a can be about 1 nm. In some embodiments, IL 115a may include a SiO2 layer having an O atom to Si atom ratio of about 2. Gate dielectric layer 115b may include any suitable dielectric material having any suitable thickness that provides channel regulation for transistor 105. In some embodiments, gate dielectric layer 115b may be made of a high-k dielectric material. For example, high-k dielectric materials may include hafnium oxide (HfO2), aluminum oxide (Al2O3), scandium oxide (ScO2), zirconium oxide (ZrO2), calcium oxide (CaO), magnesium oxide (MgO), zirconium silicate (ZrSiO4), or combinations thereof. In some embodiments, the gate dielectric layer 115b may include lanthanum oxide (La₂O₃) on a high-k dielectric to form an N-dipole in the gate dielectric layer 115b for tuning a threshold voltage of the transistor 105. In some embodiments, depositing the gate dielectric layer 115b may further include depositing an aluminum oxide (Al₂O₃) or zinc oxide (ZnO) layer to form a P-dipole in the gate dielectric layer 115b for tuning the threshold voltage of the transistor 105. In some embodiments, the carbon atom concentration in the gate dielectric layer 115b may be less than about 0.2%. In some embodiments, the gate dielectric layer 115b may have a thickness in the range of about 1 nm to about 5 nm. Other materials and thicknesses of the gate dielectric layer 115b are within the scope and spirit of this disclosure. The gate electrode 115c may be used as a gate terminal of the transistor 105. The gate electrode 115c may include any suitable conductive material that provides a suitable work function to tune the transistor 105. In some embodiments, the gate electrode 115c may be made of titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel. Other materials for the gate electrode 115c are within the scope and spirit of this disclosure, based on the disclosure herein.

[0029] See Figure 1 and 2The S / D epitaxial structure 125 may be disposed above each opposite side (e.g., along the x-direction) of the NS layer 120 to serve as the source and drain terminals of the transistor 105. The S / D epitaxial structure 125 may be disposed on the fin structure 110. The S / D epitaxial structure 125 may be made of an epitaxially grown semiconductor material similar to (e.g., with a lattice mismatch within about 5%) the NS layer 120. In some embodiments, the S / D epitaxial structure 125 may be made of Si, Ge, SiGe, InGaAs, or GaAs. The S / D epitaxial structure 125 may be doped with p-type dopant, n-type dopant, or intrinsic dopant. In some embodiments, the S / D epitaxial structure 125 may have a different doping type than the NS layer 120. In some embodiments, the n-type dopant in the S / D epitaxial structure 125 may include P, As, Sb, or combinations thereof. In some embodiments, the crystal orientation of the S / D epitaxial structure 125 may be the same as the crystal orientation of the NS layer 120.

[0030] See Figure 1 and 2 The semiconductor device 100 may further include an interlayer dielectric (ILD) layer 165 to provide electrical isolation for structural elements surrounded or covered by the ILD layer 165, such as the gate structure 115 and the S / D epitaxial structure 125. In some embodiments, the ILD layer 165 may be disposed on the S / D epitaxial structure 125. The ILD layer 165 may include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon oxycarbonate, silicon oxynitride, silicon oxycarbonitride, and silicon carbonitride. The ILD layer 165 may have any suitable thickness, such as from about 50 nm to about 200 nm, to provide electrical insulation. Based on the disclosure of this application, other insulating materials and thicknesses of the ILD layer 165 are within the scope and spirit of this disclosure.

[0031] Reference Figure 1 and 2The semiconductor device 100 may further include a gate spacer 135 formed between the gate structure 115 and the S / D epitaxial structure 125, which provides structural support during the formation of the gate structure 115. Furthermore, the gate spacer 135 provides electrical isolation and protection for the gate structure 115 during the formation of the S / D junction. In some embodiments, the gate spacer 135 may be disposed between the gate structure 115 and the ILD layer 165. The gate spacer 135 may be made of any suitable dielectric material. In some embodiments, the gate spacer 135 may be made of a silicon-based dielectric, such as silicon nitride (SiN), silicon oxy-carbon-nitride (SiOCN), silicon carbon-nitride (SiCN), or silicon oxy-nitride (SiON). In some embodiments, the gate spacer 135 may have any suitable thickness, such as between about 5 nm and about 15 nm. Based on the disclosure in this case, the other materials and thickness of the gate spacer 135 are within the scope and spirit of this disclosure.

[0032] Reference Figure 1 and 2 The semiconductor device 100 may include an inner spacer 130 that abuts (or contacts) a side surface of a gate structure 115. The inner spacer 130 may separate the gate structure 115 from the S / D epitaxial structure 125. For example, the inner spacer 130 may be formed along the channel direction of the transistor 105 (e.g., along the x-direction) on opposite sides of the gate structure 115 to separate the gate structure 115 from the S / D epitaxial structure 125. In some embodiments, the inner spacer 130 may be formed between two vertically (e.g., in the z-direction) adjacent NS layers 120. In some embodiments, the inner spacer 130 may be formed between a fin structure 110 and an NS layer 120. In some embodiments, the inner spacer 130 may include a silicon-based dielectric, such as SiN, SiOCN, SiCN, or SiON. In some embodiments, the inner spacer 130 may include a low-k material, such as a porous material, and a carbon-rich silicon oxide-based dielectric.

[0033] In some embodiments, the gate spacer 135 and the inner spacer 130 may be treated to improve dielectric quality. Figure 3A for Figure 2 An enlarged cross-sectional view of a region 300A surrounding a gate spacer 135. Figure 3B for Figure 2 An enlarged cross-sectional view of a region 300B surrounding an inner spacer 130. Unless otherwise noted, those with the same labeling are... Figure 1 and2 The discussion of the components in the text also applies to... Figure 3A and 3B .

[0034] See Figure 3A and 3B In some embodiments, the gate spacer 135 and the inner spacer 130 may be treated to increase the oxygen concentration and reduce the amount of oxygen vacancies. In some embodiments, the gate spacer 135 and the inner spacer 130 may be free of oxygen vacancies. In some embodiments, the gate spacer 135 and the inner spacer 130 may be free of Si dangling bonds, such that the Si atoms in the gate spacer 135 and the inner spacer 130 are in a Si... 4+ Valence state. As explained below, removing and / or reducing oxygen vacancies in the gate spacer 135 and the inner spacer 130 may involve forming a metal oxide (e.g., a rare earth oxide) layer on a surface 135s of the gate spacer 135 and a surface 130s of the inner spacer 130, followed by an annealing process that allows oxygen atoms in the metal oxide layer to diffuse into the gate spacer 135 and the inner spacer 130 and replace the oxygen vacancies therein. This metal oxide layer may then be removed before the formation of the gate dielectric layer 115b. However, residues of metal elements (e.g., rare earth elements) may remain on surfaces 135s and 130s. These rare earth elements may remain on surfaces 135s and 130s after the gate dielectric layer 115b is formed to contact the gate spacer 135 and the inner spacer 130. In some embodiments, the annealing process may cause the metal elements to react with Si atoms in the gate spacer 135 and inner spacer 130 to form silicates (e.g., rare-earth silicates). Subsequently, surfaces 135s and 130s may include residues of these silicates. In some embodiments, the metal elements and / or silicates may be detected by microscopic methods such as scanning electron microscopy (SEM) and energy-dispersive X-ray spectroscopy (EDS).

[0035] In some embodiments, the rare earth elements may include yttrium, scandium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium. In some embodiments, the rare earth silicates may include yttrium silicate, scandium silicate, lanthanum silicate, cerium silicate, praseodymium silicate, neodymium silicate, promethium silicate, samarium silicate, europium silicate, gadolinium silicate, terbium silicate, dysprosium silicate, holmium silicate, erbium silicate, thulium silicate, ytterbium silicate, or lutetium silicate.

[0036] In some embodiments, the aforementioned processing of the gate spacer 135 and inner spacer 130 may be performed after the formation of the S / D epitaxial structure 125 and the ILD layer 165, but before the gate structure 115. Therefore, the aforementioned metal oxide layer may be deposited on the exposed surfaces of the gate spacer 135 and inner spacer 130, such as surfaces 135s and 130s. However, this metal oxide layer is not deposited on the unexposed surfaces of the gate spacer 135 and inner spacer 130 that are in contact with the S / D epitaxial structure 125 and / or the ILD layer 165, respectively. Figure 3A and 3B Surfaces 135t and 130t are shown. Therefore, this annealing process can drive oxygen atoms to diffuse into the gate spacer 135 and inner spacer 130 in directions respectively from surfaces 135s and 130s toward surfaces 135t and 130t. This directional diffusion can cause an oxygen concentration gradient in the gate spacer 135 and inner spacer 130, as shown in... Figure 3A and 3B The oxygen concentration gradient is represented by varying gray levels. Specifically, a first portion of the gate spacer 135 adjacent to the gate structure 115 may have a greater oxygen concentration and fewer oxygen vacancies than a second portion of the gate spacer 135 adjacent to the ILD layer 165. Similarly, a first portion of the inner spacer 130 adjacent to the gate structure 115 may have a greater oxygen concentration and fewer oxygen vacancies than a second portion of the inner spacer 130 adjacent to the S / D epitaxial structure 125.

[0037] Reference Figure 1 The semiconductor device 100 may further include a shallow trench isolation (STI) region 138 configured to provide electrical isolation between fin structures 110. The STI region 138 may also provide electrical isolation between the transistor 105 and adjacent active and passive components integrated with or disposed on the substrate 102. The STI region 138 may include one or more dielectric material layers, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or other suitable insulating materials. Based on the disclosure herein, other dielectric materials for the STI region 138 are within the scope and spirit of this disclosure.

[0038] See Figure 1 and 2The semiconductor device 100 may further include dielectric layers 152, 154, and 156 on the transistor 105. In some embodiments, dielectric layers 152, 154, and 156 may include silicon oxide and / or silicon nitride. For example, dielectric layers 152 and 156 may be silicon oxide layers, and dielectric layer 154 may be a silicon nitride layer. In some embodiments, dielectric layers 152, 154, and 156 may be etch stop layers.

[0039] See Figure 1 and 2 The semiconductor device 100 may further include an S / D contact 163 that is in contact with the S / D epitaxial structure 125. The S / D contact 163 may be disposed on the S / D epitaxial structure 125 and surrounded by an ILD layer 165. In some embodiments, the S / D contact 163 may be disposed through one or more of dielectric layers 152, 154, and 156. In some embodiments, a silicide layer 164 may be disposed between the S / D contact 163 and the S / D epitaxial structure 125. In some embodiments, a height of the S / D contact 163 may be between about 10 nm and about 50 nm. The S / D contact 163 may include any suitable conductive material that provides low contact resistance with the S / D epitaxial structure 125. In some embodiments, the S / D contact 163 may be made of polysilicon, titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, nickel, or combinations thereof. Based on the disclosures in this case, other materials related to S / D contact 163 fall within the scope and spirit of these disclosures.

[0040] See Figure 1 and 2The semiconductor device 100 may further include one or more gate contact vias 167 that contact the gate electrode 115c. The gate contact vias 167 may be disposed on the gate structure 115 and pass through one or more of the dielectric layers 152, 154, and 156. In some embodiments, an interface between the gate contact via 167 and the gate electrode 115c may be substantially flat. In some embodiments, the interface between the gate contact via 167 and the gate electrode 115c may be curved. In some embodiments, a horizontal cross-section of the gate contact via 167 may have a rectangular shape or a cylindrical shape. In some embodiments, the gate contact via 167 may have a tapered shape, and a width of a top surface is greater than a width of a bottom surface. In some embodiments, the gate contact via 167 may have a uniform width from its top surface to its bottom surface. In some embodiments, the width of the top surface of the gate contact via 167 may be between about 2 nm and about 40 nm. In some embodiments, the width of the bottom surface of the gate contact via 167 may be between about 1 nm and about 40 nm. In some embodiments, the ratio of the width of the top surface of the gate contact via 167 to the width of the bottom surface of the gate contact via 167 may be between about 1 and about 3. In some embodiments, the height of the gate contact via 167 may be between about 10 nm and about 50 nm. In some embodiments, the aspect ratio of the gate contact via 167 may be between about 5:1 and about 20:1.

[0041] although Figure 1 , 2 And 3A exemplifies that transistor 105 is an embodiment of GAAFET, but it should be understood that, Figure 1 , 2 The gate spacer 135 described in 3A can be applied to other types of transistors, such as MOSFETs, FinFETs, complementary fin field-effect transistors (CFETs), or vertical fin field-effect transistors (VFETs).

[0042] According to some embodiments, Figure 4A and 4B Examples used to form Figure 1 2. A flowchart of a method 400 for transistor 105 shown in Figures 2, 3A, and 3B. This disclosure is not limited to this operational description and additional operations may be performed. Other manufacturing operations may be performed between various operations of method 400 and are omitted only for clarity. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in different ways. Figure 4A and 4BThe sequence shown is followed. In some embodiments, one or more other operations may be performed in addition to or in lieu of the operations currently described. For illustrative purposes, method 400 is referred to... Figure 5-19 The structure shown is used for illustration. Unless otherwise specified, those with the same labeling are... Figure 1 , 2 The discussion of components in 3A and 3B also applies to Figure 5-19 .

[0043] See Figure 4A Method 400 begins at operation 405, a procedure for forming a fin structure having channel regions on a substrate (e.g., substrate 102). In some embodiments, forming the fin structure may include forming a stack of alternating first and second NS layers on the substrate. Figure 5 This is an isometric view of a substrate 102 and a stack 520 forming alternating first and second NS layers 520a and 520b. In some embodiments, the first and second NS layers 520a and 520b are formed on an exposed top surface of the substrate 102. In some embodiments, the first NS layer 520a is a sacrificial NS layer that undergoes subsequent removal, and the second NS layer 520b corresponds to... Figure 1 and 2 The NS layer 120 is shown. In some embodiments, the material of the first NS layer 520a in the stack 520 is selected such that the first NS layer 520a can be selectively removed from the stack 520 by etching, without removing the second NS layer 520b. For example, the first NS layer 520a may be a SiGe NS layer, and the second NS layer 520b may be a Si NS layer.

[0044] The first and second NS layers 520a and 520b can be grown using any suitable method. For example, the first and second NS layers 520a and 520b can be grown using a chemical vapor deposition (CVD) process with a precursor gas such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), germanane (GeH4), digermanane (Ge2H6), other suitable gases, or combinations thereof. In some embodiments, the first NS layer 520a may include a Ge concentration between about 20% and about 30%, while the second NS layer 120 is substantially free of germanium—for example, having a Ge concentration of less than about 1%. In some embodiments, the second NS layer 520b, which corresponds to... Figure 1 and 2 The second NS layer 120 forms the channel region of transistor 105 and can be lightly doped or intrinsic (e.g., undoped). If lightly doped, the doping level of the second NS layer 520b is less than about 10. 13 atoms / cm 3The first and second NS layers 520a and 520b can be deposited sequentially without vacuum interruption (e.g., in situ) to avoid the formation of any interposer layer. In some embodiments, in a subsequent etching operation, the first NS layer 520a may be doped to increase its etch selectivity compared to the second NS layer 520b.

[0045] In some embodiments, the thickness of the first NS layer 520a controls the spacing between each interval of the second NS layers 520b in the stack 520. The thicknesses of the first and second NS layers 520a and 520b can range, for example, from about 3 nm to about 15 nm. Since the first and second NS layers 520a and 520b are grown individually, the thickness of each NS layer can be adjusted independently, for example, based on the deposition time. In some embodiments, additional or fewer numbers of the first and second NS layers 520a and 520b can be formed in the stack 520. In some embodiments, the total number of NS layers can be 2n, where n is the number of first NS layers 520a or the number of second NS layers 520b in the stack 520. In some embodiments, n can be 1, 2, 3, 4, 5, 6, or any integer greater than 6.

[0046] See Figure 4A Operation 405 may further include a process of patterning the stack 520 to form a fin structure. In some embodiments, the stack 520 is patterned to form a fin structure having a width along the y-direction and a length along the x-direction. The fin structure can be formed by patterning using any suitable method. For example, the fin structure can be patterned using one or more photolithography processes including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes can combine photolithography and self-alignment processes, allowing patterns with, for example, smaller pitches to be created compared to those obtained by using a single direct photolithography process in other ways. In some embodiments, a sacrificial layer is formed on the stack 520 and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a masking structure to pattern the fin structure.

[0047] As an example, not a limitation. Figure 6This is an isometric view of the fin structure 620 formed from the stack 520 using the aforementioned patterning process. In some embodiments, the fin structure 620 can be formed by etching the first and second NS layers 520a and 520b into the first and second NS layers 620a and 620b. In some embodiments, the aforementioned patterning process does not terminate on the top surface of the substrate 102, but continues to etch a top portion of the substrate 102 to form the fin structure 110 from the substrate 102 below the fin structure 620. Since the fin structure 620 and the fin structure 110 are formed using the same patterning process, the fin structure 620 and the fin structure 110 are substantially aligned with each other. For example, the sidewall surfaces of the fin structure 620 in the xz plane and the yz plane are substantially aligned with the respective sidewall surfaces of the fin structure 110, such as... Figure 6 As shown in the image.

[0048] Additional fin structures, such as fin structure 620, may be formed on the substrate 102 in the same or different regions of the substrate 102. For simplicity, these additional fin structures are not shown on the substrate 102. Figure 6 As shown in the figure. As an example and not a limitation, each fin structure 620 has a width along the y-direction between about 15 nm and about 150 nm.

[0049] In some embodiments, NS layers 620a and 620b are referred to as "nanosheets" when their width along the y-direction is substantially different from their height along the z-direction—for example, when their width is greater than / narrower than their height. In some embodiments, NS layers 620a and 620b may also be referred to as "nanowires" when their width along the y-direction is substantially equal to their height along the z-direction. In some embodiments, NS layers 620a and 620b are deposited as nanosheets and subsequently patterned to form nanowires with substantially equal height and width. By way of example and not limitation, NS layers 620a and 620b are illustrated in the context of nanosheet (NS) layers. Nanowires (NW) are within the spirit and scope of this disclosure for the purposes of this disclosure. Additionally, for illustrative purposes and without limiting the scope of this disclosure, the first and second NS layers 620a and 620b in method 400 are illustrated in the context of SiGe and Si NS layers, respectively.

[0050] In some embodiments, after the fin structure 620 is formed, an STI region 138 may be formed on an etched or recessed portion of the substrate 102 to cover the sidewall surface of the fin structure 110. In some embodiments, the STI region 138 may electrically isolate the fin structure 110 and include one or more silicon oxide-based dielectrics. By way of example and not limitation, the STI region 138 may be formed as follows: An isolation structure material (e.g., a silicon oxide-based dielectric) is blanket-deposited over the fin structure 620 and the substrate 102. The deposited isolation structure material is planarized (e.g., using a chemical mechanical polishing (CMP) process) such that the top surface of the isolation structure material is substantially coplanar with the top surface of the fin structure 620. The planarized isolation structure material is then etched back such that the resulting STI region 138 has a height substantially similar to that of the fin structure 110, such as Figure 6 As shown in the figure. In some embodiments, the fin structure 620 protrudes from the STI region 138 such that the STI region 138 does not cover the sidewall portion of the fin structure 620, as shown in the figure. Figure 6 As shown in the image.

[0051] Reference Figure 4A Method 400 can then proceed to operation 410 and a process of forming a gate spacer on the fin structure. Operation 410 can begin a process of forming a sacrificial gate structure on the fin structure. For example, a sacrificial gate structure 700 can be formed on the fin structure 620, as shown in reference... Figure 7 As illustrated. In some embodiments, the sacrificial gate structure 700 is formed, and its length is along the y-direction—for example, perpendicular to the x-axis. Figure 6 The isometric view shows the fin structure 620—and its width along the x-direction. This is an example, not a limitation. Figure 7 For the sample taken along the cutting line AB Figure 6 A cross-sectional view. Figure 7 The sacrificial gate structure 700 is shown formed on a portion of the fin structure 620. Because Figure 7 This is a cross-sectional view, not an isometric view, therefore the portion of the sacrificial gate structure 700 covering the sidewall portion of the fin structure 620 is not shown. Additionally, in Figure 7 In the cross-sectional view, only Figure 6 One of the fin structures 620. In some embodiments, portions of the sacrificial gate structure 700 are formed between and within the fin structures 620. Figure 6 The STI region 138 is shown.

[0052] In some embodiments, the sacrificial gate structure 700 may cover the top and sidewall portions of the fin structure 620. During a subsequent gate replacement procedure, the sacrificial gate structure 700 is then replaced with... Figure 1The gate structure 115 is shown. The sacrificial gate structure 700 may include a sacrificial gate electrode 700a formed on a sacrificial gate dielectric, which is not shown for simplicity. Figure 7 The sacrificial gate structure 700 may also include a capping layer 705 formed on the top surface of the sacrificial gate structure 700. In some embodiments, the capping layer 705 may protect the sacrificial gate electrode 700a from subsequent etching operations.

[0053] During this manufacturing stage, the gate spacer 135 may be formed on the side surface of the sacrificial gate structure 700, as shown in reference. Figure 7 As explained above, the gate spacer 135 is not removed during the gate replacement procedure; rather, the gate spacer 135 facilitates... Figure 1 The gate structure 115 shown is formed. In some embodiments, the gate spacer 135 can be formed by depositing a dielectric material, such as SiN, SiOCN, SiCN, or SiON, in a CVD process, a plasma-enhanced CVD process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a thermal ALD process, or a plasma ALD process.

[0054] By way of example and not limitation, the sacrificial gate structure 700 can be formed by depositing and patterning a sacrificial gate electrode 700a over the fin structure 620. In some embodiments, the sacrificial gate structure 700 is formed over a plurality of fin structures 620. Figure 7 As shown, a portion of the fin structure 620 is not covered by the sacrificial gate structure 700. This is because the width of the sacrificial gate structure 700 is narrower than the length of the fin structure 620 along the x-direction. In some embodiments, the sacrificial gate structure 700 serves as a masking structure in subsequent etching operations to define... Figure 1 The channel region of transistor 105 is shown. For this reason, the lateral dimensions (e.g., width and length) of the sacrificial gate structure 700 and the gate structure 115 are substantially similar.

[0055] See Figure 4A Operation 410 may further include a procedure of removing a portion of the fin structure exposed by the sacrificial gate structure, as described in reference to... Figure 8 As explained. See also Figure 8The removal process can remove portions of the fin structure 620 not covered by the sacrificial gate structure 700. In some embodiments, the removal process involves a dry etching process, a wet etching process, or a combination thereof. The removal process is selective for the first NS layer 620a and the second NS layer 620b, shaping them into the first NS layer 820a and NS layer 120, respectively. The removal process can further remove portions of the fin structure 110. In some embodiments, the dry etching process includes an etchant having the following components: an oxygen-containing gas; a fluorine-containing gas (e.g., carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), difluoromethane (CH2F2), trifluoromethane (CHF3), and / or hexafluoroethane (C2F6)); a chlorine-containing gas (e.g., chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), and / or boron trichloride (BCl3)); a bromine-containing gas (e.g., hydrogen bromide (HBr) and / or bromoform (CHBr3)); an iodine-containing gas; other suitable etching gases and / or plasma; or combinations thereof. Wet etching chemistry may include diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), acetic acid (CH3COOH); or combinations thereof.

[0056] In some embodiments, the etchant used in the aforementioned etching process does not substantially etch the sacrificial gate structure 700—which is protected by the capping layer 705 and the gate spacer 135—and Figure 6 The STI region 138 is shown. This is because the capping layer 705, the gate spacer 135, and the STI region 138 comprise materials with low etch selectivity, such as silicon nitride-based materials (e.g., silicon nitride, silicon carbonitride, and silicon carbonitride-oxide) or silicon oxide-based materials. In some embodiments, Figure 6 The STI region 138 shown is used as an etch stop layer in the above etch process.

[0057] After removing portions of the fin structures 620 not covered by the sacrificial gate structure 700, openings 840 are formed in each fin structure 620, such as... Figure 8 As shown, opening 840 divides each fin structure 620 into separate portions, each portion being covered by a sacrificial gate structure 700. Each portion may include a first NS layer 820a as a sacrificial layer and a stack of NS layers 120 as channel regions.

[0058] Reference Figure 4A Method 400 can then proceed to operation 415, wherein inner spacers are formed between the channel regions. For example, as shown in reference... Figure 9 and 10As explained, the inner spacer 130 may be formed in the opening 840. The process of forming the inner spacer may include (i) selectively etching the edge portion of the first NS layer 820a to form a recess structure 945, as shown in the reference. Figure 9 As explained, and (ii) the formation of an inner spacer 130 in the recessed structure 945, as shown in reference Figure 10 As described. According to some embodiments, Figure 9 The exposed edge of the first NS layer 820a is shown after being laterally etched (e.g., recessed) along the x-direction and becoming the first NS layer 920a. Figure 8 The structure. According to some embodiments, the exposed edge of the first NS layer 820a is along, as shown in the figure. Figure 9 The amount of recessed (e.g., partially etched) in the x-direction range from about 3 nm to about 10 nm is shown to form a recessed structure 945.

[0059] In some embodiments, selective etching of the first NS layer 820a can be achieved using a dry etching process selective for SiGe. For example, halogen-based chemistry exhibits high etch selectivity for Ge and low etch selectivity for Si. Therefore, halogen gases etch Ge-containing layers, such as the first NS layer 820a, at a higher etch rate than substantially Ge-free layers (such as NS layer 120). In some embodiments, halogen-based chemistry includes fluorine-based and / or chlorine-based gases. Alternatively, a wet etching chemical with high selectivity for SiGe can be used. By way of example and not limitation, a wet etching chemical may include a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), or a mixture of ammonium hydroxide, H2O2, and water (APM). The aforementioned etching process is timed to remove the desired amount of SiGe.

[0060] In some embodiments, the first NS layer 820a with a higher Ge atom concentration has a higher etch rate than the NS layer 120 with a lower or zero Ge atom concentration. Therefore, the etch rate of the aforementioned etching process can be adjusted by regulating the Ge atom concentration (e.g., Ge content) in the first NS layer 820a. As discussed above, the Ge content in the first NS layer 820a can be in the range of about 20% to about 30%. A SiGe nanosheet layer with about 20% Ge can be etched more slowly than a SiGe nanosheet layer with about 30% Ge. Therefore, the Ge concentration can be adjusted accordingly to achieve the desired etch rate and selectivity between the first NS layer 820a and the NS layer 120.

[0061] Reference Figure 9 and 10 Once the recessed structure (945) is formed, a dielectric layer can be deposited in a blanket-like manner. Figure 9The portion of the dielectric layer above the entire structure, and outside the recess structure 945, can be removed, leaving the inner spacer 130 filling the recess structure 945, as shown in the reference. Figure 10 As described above. In some embodiments, the inner spacer 130 may be formed by depositing a dielectric material, such as SiN, SiOCN, SiCN or SiON, in a CVD process, a plasma-enhanced CVD process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a thermal ALD process or a plasma ALD process.

[0062] Reference Figure 4A Method 400 can then proceed to operation 420, wherein a source / drain (S / D) region is formed adjacent to the channel region. For example, as shown in reference... Figure 11 As explained, the S / D epitaxial structure 125 can be formed by epitaxially growing a semiconductor material in the opening 840 and adjacent to the NS layer 120.

[0063] In some embodiments, such as reference Figure 11 As explained, the S / D epitaxial structure 125 can be epitaxially grown using a CVD process, which is similar to the process used in operation 405 to form the first and second NS layers 520a and 520b, as shown in the reference. Figure 5As described above. In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the side surface of the second NS layer 120 in a horizontal direction (e.g., along the x-axis). In some embodiments, the S / D epitaxial structure 125 may be epitaxially grown on the top surface of the fin structure 110 in a vertical direction (e.g., along the z-axis). In some embodiments, the S / D epitaxial structure 125 may be grown using a plasma-enhanced CVD (PECVD) process. In some embodiments, a precursor gas (e.g., SiH4, SiH2Cl2, SiHCl3, or a combination thereof) may be used to grow a semiconductor material (e.g., Si) having the same or similar crystalline structure as the NS layer 120. In some embodiments, an etching gas (e.g., hydrogen chloride (HCl)) may be used to selectively remove the semiconductor material having an amorphous structure formed on the dielectric surface (e.g., the side surfaces of the inner spacer 130 and the gate spacer 135). Removing the semiconductor material with an amorphous structure ensures that the crystalline structure of the S / D epitaxial structure 125 is crystalline. In some embodiments, a dopant precursor gas, such as phosphine (PH3), arsine (AsH3), antimonyane (SbH3), or a combination thereof, may be used in a CVD or PECVD process to dope the S / D epitaxial structure 125. In some embodiments, after the S / D epitaxial structure 125 is formed, an ILD layer 165 may be formed by depositing a dielectric material layer to fill the space in the opening 840 and above the S / D epitaxial structure 125.

[0064] Reference Figure 4A Method 400 can proceed to operation 425, wherein an interface layer (IL) is formed on the channel region. Prior to the formation of the IL, the surface of the channel region can be exposed by removing the sacrificial gate structure 700 and the first NS layer 920a, as shown in the reference. Figure 12 As described above. In some embodiments, removing the sacrificial gate structure 700 may include removing the capping layer 705 to expose the sacrificial gate electrode 700a, and subsequently removing the sacrificial gate electrode 700a to expose the fin structure 620 between the S / D epitaxial structures 125. In some embodiments, removing the first NS layer 920a may include selectively etching the first NS layer 920a without removing the NS layer 120, as described above. Figure 12 As explained.

[0065] After the surface of the channel region is exposed, IL can form on the channel region. For example, see reference... Figure 13As explained, IL115a can be formed on the exposed surface of the NS layer 120. In some embodiments, IL 115a can be formed by exposing the surface of the NS layer 120 to a chemical solution, such as deionized water (DI water), carbonated DI water (DICO2), ozonated DI water (DIO3), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), chloric acid (HCl), ammonia (NH4OH), or combinations thereof. In some embodiments, the chemical solution can be heated to a temperature above room temperature. For example, the temperature of the chemical solution can be about 50 °C. In some embodiments, Si atoms at the surface of the NS layer 120 can be oxidized by the chemical solution to form IL 115a. In some embodiments, IL 115a can be formed by exposing the surface of the NS layer 120 to a gas mixture, such as a gas mixture including nitrogen (N2), oxygen (O2) and hydrogen (H2), nitrogen dioxide (N2O), nitrous oxide (NO2), and / or water vapor (H2O), in a thermal process. In some embodiments, the pressure of the gas mixture can be controlled between about 0.1 Torr and about 2.3 x 10⁻⁶. 4 Between [specific locations]. In some embodiments, during the thermal process, the temperature of the NS layer 120 may be raised to between approximately 400 °C and approximately 1000 °C. In some embodiments, the duration of exposure of the NS layer 120 to the gas mixture may be controlled between approximately 100 ns and approximately 1 hour. In some embodiments, Si atoms at the surface of the NS layer 120 may be oxidized by the gas mixture to form IL 115a.

[0066] Reference Figure 4B Method 400 can then proceed to operation 430, the process of depositing a metal oxide layer on the gate spacer and the inner spacer. For example, see reference... Figure 14 As described, a metal oxide layer 1415 may be deposited on the exposed surfaces of the gate spacer 135 and the inner spacer 130. In some embodiments, the metal oxide layer 1415 may also be deposited on the exposed surfaces of the IL115a and the ILD layer 165. In some embodiments, depositing the metal oxide layer 1415 may include depositing a rare earth oxide material, such as yttrium oxide, scandium oxide, lanthanum oxide, cerium oxide, praseodymium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, lutetium oxide, and / or combinations thereof. For example, depositing the metal oxide layer 1415 may include depositing yttrium oxide (Y2O3). In some embodiments, the metal oxide layer 1415 may be deposited using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process to conformally cover the exposed surfaces of the gate spacer 135 and the inner spacer 130. In some embodiments, the thickness of the metal oxide layer 1415 may be controlled to be between about 5 nm and about 20 nm.

[0067] Reference Figure 4B Method 400 can then proceed to operation 435, annealing the gate spacer and the inner spacer. This annealing process promotes the diffusion of oxygen atoms from the metal oxide layer into the gate spacer and the inner spacer and reduces the amount of oxygen vacancies in the gate spacer and the inner spacer. Figure 15A and 15B Examples respectively Figure 14 The magnified areas 1400A and 1400B are shown in the image. Figure 15A and 15B Also respectively correspond to Figure 3A and 3B .like Figure 15A and 15B As shown, the deposited gate spacer 135 and inner spacer 130 may include oxygen vacancies 1570, which can be sufficiently removed during the annealing process. In some embodiments, the temperature of the annealing process may be between about 400 °C and about 1000 °C. In some embodiments, the duration of the annealing process may be between about 100 ns and about 1 hour. (See reference...) Figure 16A and 16B As explained, the annealing process can promote the diffusion of oxygen atoms 1670 in the metal oxide layer 1415 into the gate spacer 135 and the inner spacer 130 and replace oxygen vacancies 1570 by bonding with Si atoms in an unsaturated valence state.

[0068] The annealing process may also form a silicate layer between the gate spacer and the metal oxide layer, and between the inner spacer and the metal oxide layer. For example, see reference... Figure 16A and 16B As explained, during this annealing process, the metal oxide layer 1415 can react with silicon oxide in the gate spacer 135 and the inner spacer 130 to form a silicate layer 1635. For example, the Y2O3 in the metal oxide layer 1415 can react with silicon oxide in the reaction Y2O3 + SiO2. x →Y2(SiO x ) + 3O to SiO x The reaction releases approximately 53 ± 5 kJ / mol of energy. The energy released in the reaction can further promote the diffusion of additional oxygen atoms produced in the reaction into the gate spacer 135 and the inner spacer 130 and reduce the amount of oxygen vacancies 1570.

[0069] Because the formation of the silicate layer 1635 consumes some silicon oxide from the gate spacer 135, this annealing process allows for flexibility in the thickness of the gate spacer 135. Figure 15A The d1 shown is reduced to, as Figure 16AAs shown in d1'. Similarly, after annealing, the thickness of the inner spacer 130 can be freely adjusted. Figure 15B The d2 shown is reduced to, as Figure 16B As shown in the figure, d2'. In some embodiments, the thickness reduction Δd1 = d1 - d1' and Δd2 = d2 - d2' can be between about 0.1 nm and about 0.5 nm. In some embodiments, the ratio between the thickness reduction Δd1 and the thickness d1 can be between about 5% and about 20%. Similarly, the ratio between the thickness reduction Δd2 and the thickness d2 can be between about 5% and about 20%.

[0070] In some embodiments, the annealing process can be followed by post-processing, such as ultraviolet curing or plasma treatment. After this annealing process, the amount of oxygen vacancies 1570 in the gate spacer 135 and inner spacer 130 can be significantly reduced, especially in the portions adjacent to surfaces 135s and 130s, such as... Figure 17A and 17B As shown. In some embodiments, oxygen vacancies 1570 in the gate spacer 135 and inner spacer 130 can be completely removed. In some embodiments, after the annealing process, the oxygen concentration in the gate spacer 135 and inner spacer 130 can be greater than about 50%. As represented by the changing grayscale of the gate spacer 135 and inner spacer 130, an oxygen concentration gradient can be established in the gate spacer 135 and inner spacer 130. Specifically, the oxygen concentration in the gate spacer 135 can decrease along the direction from the surface 135s toward the ILD layer 165. Similarly, the oxygen concentration in the inner spacer 130 can decrease along the direction from the surface 130s toward the S / D epitaxial structure 125. In some embodiments, after the annealing process, the dielectric constant of the gate spacer 135 and inner spacer 130 can be about 3.9.

[0071] Reference Figure 4B Method 400 can then proceed to operation 440, the process of removing the metal oxide layer. For example, such as Figure 16A and 16B The metal oxide layer 1415 shown can be removed, and the remaining layers are as shown in the reference. Figure 17A and 17BThe gate spacer 135 and inner spacer 130 are described. In some embodiments, the silicate layer 1635 may also be removed. In some embodiments, removing the metal oxide layer 1415 and the silicate layer 1635 may include performing a wet etching process in a chemical solution. In some embodiments, the chemical solution may include DI water, H2O2, HCl, DiCO2, or a combination thereof. For example, the chemical solution may include a mixture of H2O2, HCl, and DI water. In some embodiments, the temperature of the chemical solution may be at or above room temperature. For example, the temperature of the chemical solution may be about 50 °C. In some embodiments, after removing the silicate layer 1635, residues of the metal element (e.g., Y) or silicate may be present on the surface 135s of the gate spacer 135 and / or the surface 130s of the inner spacer 130. In some embodiments, the metal element and / or silicate may be completely removed without leaving any residue on the surfaces 135s and 130s.

[0072] Reference Figure 4B Method 400 can then proceed to operation 445, the process of depositing a gate dielectric layer and a gate electrode on the gate dielectric layer to form a gate structure. For example, see reference... Figure 18 , 3AAs described in 3B, the gate dielectric layer 115b may be deposited on IL 115a and contact the gate spacer 135 and the inner spacer 130, and the gate electrode 115c may be deposited on the gate dielectric layer 115b to form a metal gate structure 115. As discussed above, the gate structure 115 is electrically isolated from the S / D epitaxial structure 125 by the inner spacer 130 and the gate spacer 135. In some embodiments, depositing the gate dielectric layer 115b may include depositing a high-k dielectric material (e.g., HfO2, Al2O3, ScO2, ZrO2, CaO, MgO and / or ZrSiO4) in a CVD process or an ALD process. In some embodiments, depositing the gate dielectric layer 115b may further include depositing a lanthanum oxide (La2O3) or yttrium oxide (Y2O3) layer to form an N-dipole in the gate dielectric layer 115b for tuning the threshold voltage of the transistor 105. In some embodiments, the deposited gate dielectric layer 115b may further include depositing an aluminum oxide (Al2O3) or zinc oxide (ZnO) layer to form a P-dipole in the gate dielectric layer 115b for tuning the threshold voltage of the transistor 105. In some embodiments, the deposited gate electrode 115c may include depositing one or more work function metal layers and an electrode contact layer (e.g., titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel) in a CVD process or an ALD process. In some embodiments, one or more of the dielectric layers 152, 154, and 156 may be formed over the metal gate structure 115 and the ILD layer 165 by sequentially depositing dielectric layers such as silicon oxide and silicon nitride, as shown in the figure. Figure 19 As explained.

[0073] Reference Figure 4B Method 400 can then proceed to operation 450, the process of forming contact structures on the gate electrode and the S / D region. For example, a gate contact via 167 can be formed on the gate electrode 115c, and an S / D contact 163 can be formed on the S / D epitaxial structure 125, as shown in reference. Figure 2 As explained.

[0074] In some embodiments, forming the gate contact via 167 may include (i) forming an opening through one or more of the dielectric layers 152, 154 and 156 to expose the gate electrode 115c; and (ii) depositing a metallic material (e.g., W, Cu and / or Mo) in the opening.

[0075] In some embodiments, forming the S / D contact 163 may include (i) forming an opening through one or more of the dielectric layers 152, 154 and 156 and through the ILD layer 165 to expose the S / D epitaxial structure 125, (ii) forming a silicide layer 164 on the S / D epitaxial structure 125, and (iii) depositing a metal material (e.g., W, Cu and / or Mo) in the opening.

[0076] The embodiments described herein relate to the structure of a semiconductor device and a method of forming the structure. The structure may include a transistor on a substrate. The transistor may include a fin structure having first and second channel regions, a gate spacer on the fin structure, and an inner spacer between the first and second channel regions. The structure may further include a source / drain region adjacent to the channel region and a gate structure on the channel region. The gate structure and the source / drain region may be in contact with the inner spacer and the gate spacer, wherein a metal element (e.g., a rare earth element) is present at the contact interface. The inner spacer and the gate spacer may have an oxygen concentration greater than about 50% and may be free of dangling bonds and oxygen vacancies. The method of forming the structure may include forming a gate spacer on the fin structure, forming the inner spacer between the first and second channel regions, depositing a metal oxide layer on the gate spacer and the inner spacer, and performing an annealing process to promote the diffusion of oxygen atoms from the metal oxide layer into the gate spacer and the inner spacer. The annealing process can improve the quality of the gate spacer and the inner spacer by reducing or removing oxygen vacancies in the gate spacer and the inner spacer. The method may further include removing the metal oxide layer and forming a gate structure in contact with the gate spacer and the inner spacer.

[0077] In some embodiments, a method includes forming a fin structure on a substrate, forming a channel region in the fin structure, forming a source / drain (S / D) region adjacent to the channel region, forming an inner spacer between the channel regions and in contact with the S / D region, depositing a metal oxide layer on the inner spacer, annealing the metal oxide layer and the inner spacer, removing the metal oxide layer, and forming a gate structure surrounding the channel region and in contact with the inner spacer.

[0078] In some embodiments, annealing the metal oxide layer and the inner spacer involves forming a silicate layer between the metal oxide layer and the inner spacer.

[0079] In some embodiments, the method includes removing the silicate layer after removing the metal oxide layer.

[0080] In some embodiments, annealing the metal oxide layer and the inner spacer includes allowing oxygen atoms to diffuse from the metal oxide to the inner spacer.

[0081] In some embodiments, annealing the metal oxide layer and the inner spacer involves increasing the oxygen-to-silicon ratio in the inner spacer.

[0082] In some embodiments, depositing the metal oxide layer includes depositing the metal oxide layer through an atomic layer deposition process.

[0083] In some embodiments, the method includes depositing a gate spacer on the fin structure, wherein depositing the metal oxide layer includes depositing the metal oxide layer on the gate spacer.

[0084] In some embodiments, a method includes forming a fin structure on a substrate. The fin structure includes first and second nanostructures. The method further includes depositing a gate spacer on the fin structure, forming an inner spacer between the first and second nanostructures, depositing a metal oxide layer on the surfaces of the gate spacer and the inner spacer, increasing the oxygen concentration in the gate spacer and the inner spacer, removing the metal oxide layer, and forming a gate structure surrounding the first and second nanostructures.

[0085] In some embodiments, depositing the metal oxide layer includes depositing yttrium oxide, scandium oxide, lanthanum oxide, cerium oxide, praseodymium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, or lutetium oxide.

[0086] In some embodiments, increasing the oxygen concentration includes forming a silicate layer between the metal oxide layer and the gate spacer and between the metal oxide layer and the inner spacer.

[0087] In some embodiments, the method further includes removing the silicate layer after removing the metal oxide layer.

[0088] In some embodiments, increasing the oxygen concentration includes reducing the thickness of the gate spacer and the inner spacer by about 5% to about 20%.

[0089] In some embodiments, increasing the oxygen concentration includes removing oxygen vacancies in the gate spacer and the inner spacer.

[0090] In some embodiments, increasing the oxygen concentration includes performing an annealing process to process the gate spacer, the inner spacer, and the metal oxide layer.

[0091] In some embodiments, a structure includes a fin structure on a substrate. The fin structure includes a first channel region and a second channel region above the first channel region. The structure further includes a source / drain (S / D) region on the fin structure and adjacent to the first and second channel regions; an inner spacer between the first and second channel regions and in contact with the S / D region; and a gate structure surrounding the first and second channel regions and in contact with the inner spacer. An interface between the gate structure and the inner spacer includes a metal element.

[0092] In some embodiments, the rare earth elements include yttrium, scandium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium.

[0093] In some embodiments, the interface comprises rare earth silicates.

[0094] In some embodiments, the structure further includes a gate spacer on the fin structure, wherein another interface between the gate structure and the gate spacer contains the rare earth element.

[0095] In some embodiments, the inner spacer includes a first portion in contact with the S / D region and a second portion in contact with the gate structure, wherein a first oxygen concentration of the first portion is less than a second oxygen concentration of the second portion.

[0096] In some embodiments, the oxygen concentration of the inner spacer increases from the interface between the S / D region and the inner spacer to the interface between the gate structure and the inner spacer.

[0097] It will be understood that the detailed description section, rather than the summary section of this disclosure, is intended to be used to interpret the claims. The summary section of this disclosure may set forth one or more, but not all, possible embodiments of this disclosure as conceived by the inventors, and is therefore not intended to limit the appended claims in any way.

[0098] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as the basis for designing or modifying other programs and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this application without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: Fin structures are formed on the substrate; Multiple channel regions are formed in this fin structure; Form source / drain regions adjacent to the multiple channel regions; An inner spacer is formed between the plurality of channel regions and in contact with the source / drain region; A metal oxide layer is deposited on the inner spacer; Anneal the metal oxide layer and the inner spacer. Remove the metal oxide layer; as well as A gate structure is formed that surrounds the plurality of channel regions and is in contact with the inner spacer.

2. The method according to claim 1, characterized in that, Annealing the metal oxide layer and the inner spacer involves forming a silicate layer between the metal oxide layer and the inner spacer.

3. The method according to claim 1, characterized in that, Annealing the metal oxide layer and the inner spacer includes causing oxygen atoms to diffuse from the metal oxide layer to the inner spacer.

4. The method according to claim 1, characterized in that, Annealing the metal oxide layer and the inner spacer involves increasing the oxygen-to-silicon ratio in the inner spacer.

5. A method for forming a semiconductor structure, characterized in that, The method includes: A fin structure is formed on a substrate, wherein the fin structure comprises a first nanostructure and a second nanostructure; Deposit gate spacers on the fin structure; An inner spacer is formed between the first nanostructure and the second nanostructure; A metal oxide layer is deposited on the surface of the gate spacer and the inner spacer; Increase the oxygen concentration in the gate spacer and the inner spacer; Remove the metal oxide layer; as well as A gate structure is formed that surrounds the first nanostructure and the second nanostructure.

6. The method according to claim 5, characterized in that, The deposition of the metal oxide layer includes the deposition of yttrium oxide, scandium oxide, lanthanum oxide, cerium oxide, praseodymium oxide, neodymium oxide, promethium oxide, samarium oxide, europium oxide, gadolinium oxide, terbium oxide, dysprosium oxide, holmium oxide, erbium oxide, thulium oxide, ytterbium oxide, or lutetium oxide.

7. The method according to claim 5, characterized in that, The increase in oxygen concentration includes forming a silicate layer between the metal oxide layer and the gate spacer, and between the metal oxide layer and the inner spacer.

8. A semiconductor structure, characterized in that, The semiconductor structure includes: A fin structure on a substrate, wherein the fin structure includes a first channel region and a second channel region above the first channel region; Source / drain regions are located on the fin structure and are adjacent to the first channel region and the second channel region; An inner spacer is located between the first channel region and the second channel region and is in contact with the source / drain region; as well as A gate structure that surrounds the first channel region and the second channel region and contacts the inner spacer, wherein the interface between the gate structure and the inner spacer contains rare earth elements.

9. The structure according to claim 8, characterized in that, The rare earth elements include yttrium, scandium, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, or lutetium.

10. The structure according to claim 8, characterized in that, It further includes a gate spacer on the fin structure, wherein another interface between the gate structure and the gate spacer contains the rare earth element.

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