Method of forming a semiconductor structure
Patent Information
- Application Number
- CN202611328809.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-28
- Publication Date
- 2026-11-03
AI Technical Summary
In the prior art, the parasitic capacitance between the gate structure and the source/drain doped layers of the fully enclosed gate transistor is relatively large and difficult to reduce further, which affects the performance of the semiconductor structure.
By introducing an air gap in the semiconductor structure, a high etching selectivity is formed by utilizing the sidewall material layer of the dielectric material and the second sacrificial layer of the metal material. The second sacrificial layer in the trench is removed, while the inner sidewall of the dielectric material is retained, forming an air gap between the source/drain doped layer and the inner sidewall, thereby reducing parasitic capacitance.
It effectively reduces the parasitic capacitance between the source/drain doped layers and the subsequently formed gate structure, improves the uniformity of the local electrical properties of the semiconductor structure, enhances high-frequency characteristics, suppresses leakage current, and improves operating performance.
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Figure CN123035741A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.
[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress short-channel effects. Summary of the Invention
[0004] The problem addressed by the embodiments of this disclosure is to provide a method for forming a semiconductor structure, which is beneficial to improving the uniformity of the local electrical properties of the semiconductor structure.
[0005] To address the aforementioned problems, this disclosure provides a method for forming a semiconductor structure, comprising: providing a stacked structure including a first sacrificial layer and a channel layer alternately stacked longitudinally; removing a portion of the width of the first sacrificial layer from the end of the stacked structure to form a trench surrounded by the channel layer and the remaining first sacrificial layer; forming a sidewall material layer conformally covering the end of the channel layer and the inner wall surface of the trench, wherein the sidewall material layer is made of a dielectric material; forming a second sacrificial layer covering the sidewall material layer and filling the trench, wherein the second sacrificial layer is made of a metallic material; removing the end of the channel layer and the second sacrificial layer and the sidewall material layer outside the trench, wherein the remaining sidewall material layer in the trench serves as an inner sidewall; removing the second sacrificial layer in the trench to expose the remaining trench surrounded by the inner sidewall; forming a source / drain doped layer at the end of the stacked structure, wherein the source / drain doped layer seals the trench to form an air gap between the inner sidewall and the source / drain doped layer.
[0006] Optionally, in the step of forming a sidewall material layer that conformally covers the end of the trench layer, as well as the surface of the trench layer and the surface of the first sacrificial layer in the trench, the thickness of the sidewall material layer is 3 nm to 300 nm.
[0007] Optionally, in the step of forming a second sacrificial layer that covers the sidewall material layer and fills the trench, the material of the second sacrificial layer includes one or more of titanium nitride, tantalum nitride, tungsten, cobalt, and molybdenum.
[0008] Optionally, an atomic layer deposition process is used to form a second sacrificial layer that covers the sidewall material layer and fills the trench.
[0009] Optionally, in the step of removing the second sacrificial layer from the trench, the etching selectivity ratio of the second sacrificial layer to the sidewall material layer is greater than or equal to 50.
[0010] Optionally, an anisotropic dry etching process can be used to remove the second sacrificial layer and sidewall material layer at the end of the trench layer.
[0011] Optionally, an isotropic wet etching process can be used to remove the second sacrificial layer in the trench.
[0012] Optionally, in the step of providing the stacked structure, a pseudo-gate structure spanning the stacked structure is further formed on the stacked structure, the pseudo-gate structure covering part of the sidewalls and part of the top of the stacked structure, and exposing both ends of the stacked structure; in the step of removing a portion of the width of the first sacrificial layer from the ends of the stacked structure, a portion of the width of the first sacrificial layer is removed from the ends of the stacked structure exposed by the pseudo-gate structure; in the step of forming a sidewall material layer conformally covering the ends of the channel layer, as well as the surface of the channel layer and the surface of the first sacrificial layer in the trench, the sidewall material layer also conformally covers the top and sidewalls of the pseudo-gate structure; in the step of removing the second sacrificial layer and the sidewall material layer from the ends of the channel layer, the second sacrificial layer and the sidewall material layer covering the top and sidewalls of the pseudo-gate structure are also removed; in the step of forming a source / drain doped layer at the ends of the stacked structure, the source / drain doped layer is formed at the ends of the stacked structure exposed by the pseudo-gate structure.
[0013] Optionally, after forming source / drain doped layers at the ends of the stacked structure, the method further includes: removing the dummy gate structure; removing the remaining first sacrificial layer to expose a plurality of channel layers spaced longitudinally and to expose inner walls covering the first sacrificial layer; and forming a gate structure that spans the plurality of channel layers and surrounds and covers the inner walls exposed between the channel layers.
[0014] Optionally, in the step of providing the laminated structure, the laminated structure protrudes from the substrate; in the step of forming a sidewall material layer that conformally covers the end of the channel layer and the surface of the channel layer and the surface of the first sacrificial layer in the trench, the sidewall material layer also conformally covers the top surface of the substrate; in the step of removing the second sacrificial layer and the sidewall material layer at the end of the channel layer, the second sacrificial layer and the sidewall material layer covering the top surface of the substrate are also removed.
[0015] Compared with the prior art, the technical solution of the present disclosure has the following advantages: In the formation method provided in this embodiment, a second sacrificial layer is first used to occupy space in the trench, then the second sacrificial layer is removed to expose the remaining trench surrounded by the inner sidewall, and finally a source / drain doped layer sealing the trench is formed at the end of the stacked structure to create an air gap between the source / drain doped layer and the inner sidewall. Since the dielectric constant of air is less than that of the dielectric material, introducing an air gap between the source / drain doped layer and the inner sidewall can effectively reduce the parasitic capacitance between the source / drain doped layer and the subsequently formed gate structure, thereby improving the performance of the semiconductor structure. Furthermore, the sidewall material layer is a dielectric material, and the second sacrificial layer is a metal material. When the metal and dielectric materials can form a high etching selectivity, the removal of the second sacrificial layer in the trench is ensured to be completely clean while minimizing damage to the inner sidewalls. This results in high-quality inner sidewalls with good surface uniformity, leading to better spatial consistency of the remaining trenches enclosed by each inner sidewall. Consequently, the shape and size of the air gap between the inner sidewalls and the source / drain doped layers are more consistent, which in turn improves the uniformity of the local electrical performance of the semiconductor structure. This further reduces the overlap capacitance (Cov) between the gate structure and the source / drain doped layers, improves high-frequency characteristics, and suppresses leakage current. Furthermore, the high quality of the inner sidewall film helps prevent the gate structure material from penetrating the inner sidewalls and overflowing into the air gap when the gate structure is subsequently formed at the location of the first sacrificial layer. This prevents leakage risks between the gate structure and the source / drain doped layers, ultimately improving the performance of the semiconductor structure. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a semiconductor structure. Figures 2 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure disclosed herein. Detailed Implementation
[0017] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a particular semiconductor structure needs further improvement.
[0018] Figure 1 This is a schematic diagram of a semiconductor structure.
[0019] refer to Figure 1The semiconductor structure includes: a substrate 10; one or more channel layers 23 spaced apart and suspended above the substrate 10; a gate structure 70 located on the substrate 10, the gate structure 70 spanning and surrounding the channel layer 23; source / drain doped layers 60 located on the substrate 10 on both sides of the gate structure 70 and in contact with the ends of the channel layer 23; and inner sidewalls 34 located between adjacent channel layers 23 and between the channel layer 23 and the substrate 10, and between the gate structure 70 and the source / drain doped layers 60.
[0020] Research has shown that while gate-all-around (GAA) transistors increase the operating current, they also significantly increase the parasitic capacitance between the gate structure 70 and the source / drain doped layers 60. Furthermore, the dielectric constant of the inner sidewall 34 between the gate structure 70 and the source / drain doped layers 60 is difficult to further reduce, making it difficult to reduce the parasitic capacitance between the gate structure 70 and the source / drain doped layers 60, and consequently, difficult to improve the performance of the semiconductor structure.
[0021] To address the technical problem, this disclosure provides a method for forming a semiconductor structure, comprising: providing a stacked structure including a first sacrificial layer and a channel layer alternately stacked along a longitudinal direction; removing a portion of the width of the first sacrificial layer from the end of the stacked structure to form a trench surrounded by the channel layer and the remaining first sacrificial layer; forming a sidewall material layer conformally covering the end of the channel layer, as well as the surface of the channel layer and the surface of the first sacrificial layer in the trench, wherein the sidewall material layer is made of a dielectric material; forming a second sacrificial layer covering the sidewall material layer and filling the trench, wherein the second sacrificial layer is made of a metallic material; removing the second sacrificial layer and the sidewall material layer from the end of the channel layer, and retaining the remaining sidewall material layer in the trench as an inner sidewall; removing the second sacrificial layer in the trench to expose the remaining trench surrounded by the inner sidewall; forming a source / drain doped layer at the end of the stacked structure, wherein the source / drain doped layer seals the trench to form an air gap between the inner sidewall and the source / drain doped layer.
[0022] In the formation method provided in this embodiment, a second sacrificial layer is first used to occupy space in the trench, then the second sacrificial layer is removed to expose the remaining trench surrounded by the inner sidewall, and finally a source / drain doped layer sealing the trench is formed at the end of the stacked structure to create an air gap between the source / drain doped layer and the inner sidewall. Since the dielectric constant of air is less than that of the dielectric material, introducing an air gap between the source / drain doped layer and the inner sidewall can effectively reduce the parasitic capacitance between the source / drain doped layer and the subsequently formed gate structure, thereby improving the performance of the semiconductor structure. Furthermore, the sidewall material layer is a dielectric material, and the second sacrificial layer is a metal material. When the metal and dielectric materials can form a high etching selectivity, the removal of the second sacrificial layer in the trench is ensured to be completely clean while minimizing damage to the inner sidewalls. This results in high-quality inner sidewalls with good surface uniformity, leading to better spatial consistency of the remaining trenches enclosed by each inner sidewall. Consequently, the shape and size of the air gap between the inner sidewalls and the source / drain doped layers are more consistent, which in turn improves the uniformity of the local electrical performance of the semiconductor structure. This further reduces the overlap capacitance (Cov) between the gate structure and the source / drain doped layers, improves high-frequency characteristics, and suppresses leakage current. Furthermore, the high quality of the inner sidewall film helps prevent the gate structure material from penetrating the inner sidewalls and overflowing into the air gap when the gate structure is subsequently formed at the location of the first sacrificial layer. This prevents leakage risks between the gate structure and the source / drain doped layers, ultimately improving the performance of the semiconductor structure.
[0023] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0024] Figures 2 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure disclosed herein.
[0025] refer to Figure 2 Provides a stacked structure 240, including along the longitudinal direction (e.g. Figure 2 (As shown in the Z-direction) Alternating stacked first sacrificial layer 220 and channel layer 230.
[0026] In this context, "longitudinal" refers to the direction perpendicular to the top surface of the stacked structure 240.
[0027] In this embodiment, the stacked structure 240 is used to subsequently form a plurality of channel layers 230 arranged longitudinally at intervals. The channel layers 230 in the stacked structure 240 serve as channels for the semiconductor structure, and the first sacrificial layer 220 provides a process basis for the subsequent floating arrangement of the channel layers 230 and also occupies space for the subsequently formed gate structure. In subsequent processes, the first sacrificial layer 220 is removed, leaving the channel layers 230 floating, and a gate structure is formed between adjacent channel layers 230.
[0028] In some embodiments, the surface of the channel layer 230 covered by the gate structure is used as a channel, and the top, bottom and sidewalls of the channel layer 230 can all serve as channels, thereby increasing the area of the channel layer 230 used as a channel and thus increasing the operating current of the semiconductor structure.
[0029] In some embodiments, the material of the channel layer 230 may include silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, the material of the channel layer 230 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.
[0030] In some embodiments, the material of the first sacrificial layer 220 may include silicon germanide.
[0031] Among them, silicon germanide and silicon can form a large etching selectivity, which is beneficial for the subsequent removal of the first sacrificial layer 220 and reduces damage to the channel layer 230.
[0032] In other embodiments, the first sacrificial layer may be selected from materials that have an etch selectivity ratio suitable for the channel layer, so as to reduce damage to the channel layer when the first sacrificial layer is removed subsequently.
[0033] In some embodiments, during the step of providing the stacked structure 240, the stacked structure 240 protrudes from the substrate 100.
[0034] The substrate 100 provides the basis for the process operation of forming the semiconductor structure. The semiconductor structure includes a fully enclosed gate transistor.
[0035] In some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate material may be suitable for process requirements or easy to integrate.
[0036] In some embodiments, during the step of providing the stacked structure 240, a pseudo-gate structure 300 is also formed on the stacked structure 240, which covers part of the sidewalls and part of the top of the stacked structure 240 and exposes both ends of the stacked structure 240.
[0037] In this embodiment, the pseudo-gate structure 300 is used to occupy space for the subsequent formation of the gate structure.
[0038] Specifically, the pseudo-gate structure 300 is a stacked film layer, which may include a pseudo-gate oxide layer and a pseudo-gate layer covering the pseudo-gate oxide layer.
[0039] As an example, the pseudo-gate oxide layer is made of silicon oxide, and the pseudo-gate layer is made of polycrystalline silicon.
[0040] In some embodiments, the pseudo-gate structure 300 has a gate sidewall 330 formed on its sidewall, and the gate sidewall 330 is flush with the end of the channel layer 230.
[0041] After the gate structure is formed, the gate sidewall 330 is used to protect the sidewall of the gate structure. In the step of forming the stacked structure 240, the stacked structure 240 is obtained by etching along the gate sidewall 330. The gate sidewall 330 is flush with the end of the channel layer 230. Moreover, the fact that the gate sidewall 330 is flush with the end of the channel layer 230 also helps to increase the process window for forming the air gap.
[0042] In some embodiments, the gate sidewall 330 can be a single-layer structure or a multilayer structure, and the material of the gate sidewall 330 may include one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 330 is a single-layer structure, and the material of the gate sidewall 330 is silicon nitride.
[0043] In some embodiments, a mask layer 310 is formed on the top of the dummy gate structure 300.
[0044] In some embodiments, the mask layer 310 is used as an etching mask for forming the dummy gate structure 300, and also for protecting the top of the dummy gate structure 300 when forming the gate sidewall 330.
[0045] In some embodiments, the material of the mask layer 310 may include one or more of silicon oxide and silicon nitride. As an example, the material of the mask layer 310 is silicon nitride.
[0046] refer to Figure 3 A first sacrificial layer 220 with a portion of its width is removed from the end of the laminated structure 240 to form a trench 250 surrounded by a channel layer 230 and the remaining first sacrificial layer 220.
[0047] The groove 250 is used to provide space for the subsequent formation of the inner wall and air gap.
[0048] In some embodiments, an isotropic etching process is used to remove a portion of the sacrificial layer 220 to form a trench 250.
[0049] In some embodiments, the isotropic etching process is a wet etching process, and the etching solution may include a hydrochloric acid solution.
[0050] In the above embodiments, the hydrochloric acid solution has a good etching selectivity for silicon germanide and silicon, which is beneficial to reduce damage to the channel layer 230 during the removal of a portion of the sacrificial layer 220.
[0051] In some embodiments, in the step of removing a portion of the width of the first sacrificial layer 220 from the end of the stacked structure 240, a portion of the width of the first sacrificial layer 220 is removed from the end of the stacked structure 240 exposed by the dummy gate structure 300.
[0052] Specifically, along the direction perpendicular to the sidewall of the pseudo-gate structure 300, a portion of the sacrificial layer 220 is removed to form a trench 250 surrounded by the channel layer 230 and the remaining sacrificial layer 220.
[0053] refer to Figure 4 A sidewall material layer 400 is formed to conformally cover the end of the channel layer 230, as well as the surface of the channel layer 230 and the surface of the first sacrificial layer 220 in the trench 250, and the material of the sidewall material layer 400 is a medium material.
[0054] In the above embodiments, the sidewall material layer 400 is used to form the inner sidewall, and the material of the sidewall material layer 400 is a dielectric material to form the inner sidewall of the dielectric material, thereby achieving electrical isolation between the subsequently formed gate structure and the source / drain doped layer.
[0055] In some embodiments, in the step of forming a sidewall material layer 400 that conformally covers the end of the channel layer 230 and the surface of the channel layer 230 and the surface of the first sacrificial layer 220 in the trench 250, the material of the sidewall material layer 400 includes silicon nitride, silicon oxynitride, or silicon oxycarbonate.
[0056] In the above embodiments, silicon nitride, silicon oxynitride, or silicon oxycarbonate can effectively isolate the growth of the source and drain doped layers, thus providing a good isolation effect. Moreover, since the subsequent inner sidewall is located between the gate structure and the source and drain doped layers, the k-value of silicon nitride, silicon oxynitride, or silicon oxycarbonate is relatively small, which is more conducive to reducing the parasitic capacitance between the gate structure and the source and drain doped layers.
[0057] In some embodiments, in the step of forming a sidewall material layer 400 that conformally covers the end of the channel layer 230 and the surface of the channel layer 230 and the surface of the first sacrificial layer 220 in the trench 250, the thickness d of the sidewall material layer 400 is 3 nm to 300 nm.
[0058] In the above embodiments, the thickness d of the sidewall material layer 400 is 3nm to 300nm, so that the subsequently formed inner sidewall has sufficient thickness to achieve good isolation performance, and so that after the sidewall material layer 400 is formed in the trench 250, there is still enough space in the trench 250 to form an air gap.
[0059] In some embodiments, an atomic layer deposition (ALD) process is used to form a sidewall material layer 400 that conformally covers the ends of the channel layer 230, as well as the surfaces of the channel layer 230 and the first sacrificial layer 220 in the trench 250.
[0060] In the above embodiments, the sidewall material layer 400 formed by atomic layer deposition has good thickness uniformity and good step coverage ability, which enables the sidewall material layer 400 to cover the end of the channel layer 230, as well as the surface of the channel layer 230 and the surface of the first sacrificial layer 220 in the trench 250 in good conformal manner, and is also conducive to obtaining an inner sidewall with good thickness uniformity.
[0061] Accordingly, in some embodiments, in the step of forming a sidewall material layer 400 that conformally covers the end of the channel layer 230 and the surface of the channel layer 230 and the surface of the first sacrificial layer 220 in the trench 250, the sidewall material layer 400 also conformally covers the top and sidewalls of the pseudo-gate structure 300.
[0062] Specifically, the sidewall material layer 400 conformally covers the gate sidewall 330 of the dummy gate structure 300 and the mask layer 310 on top of the dummy gate structure 300. The gate sidewall 330 can protect the side of the dummy gate structure 300, and the mask layer 310 can protect the top of the dummy gate structure 300, so that the dummy gate structure 300 is not affected by the formation and removal of the sidewall material layer 400, thus ensuring the space for the subsequent formation of the gate structure.
[0063] Accordingly, in some embodiments, in the step of forming a sidewall material layer 400 that conformally covers the end of the channel layer 230 and the surface of the channel layer 230 and the surface of the first sacrificial layer 220 in the trench 250, the sidewall material layer 400 also conformally covers the top surface of the substrate 100.
[0064] refer to Figure 5 A second sacrificial layer 410 is formed, which covers the sidewall material layer 400 and fills the groove 250, and the material of the second sacrificial layer 410 is a metal material.
[0065] The second sacrificial layer 410 is used to occupy space for the subsequent formation of an air gap.
[0066] In some embodiments, the sidewall material layer 400 is a dielectric material, and the second sacrificial layer 410 is a metallic material. The metallic material and the dielectric material can achieve a high etching selectivity. Therefore, when removing the second sacrificial layer 410 from the trench 250, it is ensured that the second sacrificial layer 410 is completely removed while minimizing damage to the inner sidewalls formed by the sidewall material layer 400. This results in high-quality inner sidewalls with good surface uniformity, leading to better spatial consistency in the remaining trench 250 enclosed by each inner sidewall. Consequently, the shape and size of the air gaps between the subsequently formed inner sidewalls and the source / drain doped layers are more consistent, which in turn improves the uniformity of the local electrical performance of the semiconductor structure and further reduces the overlap capacitance between the subsequently formed gate structure and the source / drain doped layers. Capacitance (Cov) improves high-frequency characteristics and suppresses leakage current. At the same time, the high quality of the inner sidewall film also helps to prevent the material of the gate structure from penetrating the inner sidewall and overflowing into the air gap when the gate structure is formed at the position of the first sacrificial layer 220, thus affecting the gate length of the gate structure. This helps to prevent leakage risk between the gate structure and the source / drain doped layers, thereby improving the working performance of the semiconductor structure.
[0067] In some embodiments, in the step of forming a second sacrificial layer 410 covering the sidewall material layer 400 and filling the trench 250, the material of the second sacrificial layer 410 includes one or more of titanium nitride, tantalum nitride, tungsten, cobalt and molybdenum.
[0068] The second sacrificial layer 410, formed from one or more metallic materials selected from titanium nitride, tantalum nitride, tungsten, cobalt, and molybdenum, can form a large etching selectivity with the sidewall material layer 400 of silicon nitride, silicon oxynitride, or silicon oxycarbonate. As a result, the damage to the inner sidewalls can be controlled within 1 nm when the second sacrificial layer 410 is subsequently removed, thereby improving the overall quality uniformity of multiple inner sidewalls and thus improving the performance uniformity of the device, effectively improving the problem of device local mismatch.
[0069] In some embodiments, an atomic layer deposition process is used to form a second sacrificial layer 410 that covers the sidewall material layer 400 and fills the trench 250.
[0070] The second sacrificial layer 410 formed by atomic layer deposition has good thickness uniformity and good step coverage ability, which enables the second sacrificial layer 410 to cover the sidewall material layer 400 in a good conformal manner and fill the trench 250 well.
[0071] refer to Figure 6 Remove the second sacrificial layer 410 and the sidewall material layer 400 at the end of the trench layer 230, and retain the remaining sidewall material layer 400 in the trench 250 as the inner sidewall 420.
[0072] The second sacrificial layer 410 and the sidewall material layer 400 at the end of the channel layer 230 are removed to expose the end of the channel layer 230 in preparation for the subsequent formation of the source and drain doped layers. In addition, the remaining sidewall material layer 400 in the trench 250 is retained as the inner sidewall 420, and the second sacrificial layer 410 in the trench 250 is exposed in preparation for the removal of the second sacrificial layer 410.
[0073] In some embodiments, an anisotropic dry etching process is used to remove the second sacrificial layer 410 and the sidewall material layer 400 at the end of the trench layer 230.
[0074] The anisotropic dry etching process makes the etching more directional, which can remove the second sacrificial layer 410 and the sidewall material layer 400 together along the end of the channel layer 230, reduce damage to the channel layer 230, and help improve the sidewall morphology quality at the end of the channel layer 230.
[0075] Accordingly, in some embodiments, the second sacrificial layer 410 and sidewall material layer 400 at the end of the trench layer 230 are also removed from the top and sidewalls of the dummy gate structure 300.
[0076] The second sacrificial layer 410 and sidewall material layer 400 covering the top and sidewalls of the dummy gate structure 300 are removed to prepare for the subsequent removal of the dummy gate structure 300 to form the gate structure.
[0077] Specifically, in some embodiments, the dummy gate structure 300 has a gate sidewall 330 formed on its sidewall, and the end of the channel layer 230, as well as the second sacrificial layer 410 and the sidewall material layer 400 covering the top and sidewall of the dummy gate structure 300 are removed along the sidewall of the gate sidewall 330.
[0078] Accordingly, in some embodiments, the second sacrificial layer 410 and sidewall material layer 400 covering the top surface of the substrate 100 are also removed in the step of removing the second sacrificial layer 410 and sidewall material layer 400 at the end of the trench layer 230.
[0079] The second sacrificial layer 410 and the sidewall material layer 400 covering the top surface of the substrate 100 are removed to expose the top of the substrate 100 in preparation for the subsequent formation of source and drain doped layers.
[0080] refer to Figure 7 Remove the second sacrificial layer 410 in the trench 250 to expose the remaining trench 250 enclosed by the inner wall 420.
[0081] Remove the second sacrificial layer 410 in the trench 250 to expose the remaining trench 250 surrounded by the inner sidewall 420, so that the subsequent inner sidewall 420 and the source / drain doped layer form an air gap.
[0082] In some embodiments, in the step of removing the second sacrificial layer 410 in the trench 250, the etching selectivity ratio of the second sacrificial layer 410 to the sidewall material layer 400 is greater than or equal to 50.
[0083] The etching selectivity ratio of the second sacrificial layer 410 to the sidewall material layer 400 is greater than or equal to 50, which ensures that the sidewall material layer 400 is not damaged as much as possible during the removal of the second sacrificial layer 410. This further results in higher quality and better surface uniformity of the multiple inner sidewalls 420, which in turn results in better spatial consistency of the remaining trench 250 enclosed by each inner sidewall 420. Consequently, the shape and size of the air gap between the subsequent inner sidewalls 420 and the source / drain doped layers are more consistent, which further helps to improve the uniformity of the local electrical performance of the semiconductor structure.
[0084] In some embodiments, an isotropic wet etching process is used to remove the second sacrificial layer 410 in the trench 250.
[0085] The process parameters of the isotropic wet etching process are easy to control, which is beneficial to better control the etching amount. Moreover, the isotropic wet etching process can be used without a mask, saving process costs. The isotropic wet etching process can also achieve a larger etching selectivity, thereby reducing damage to the inner sidewall 420 and the trench layer 230 during the removal of the second sacrificial layer 410.
[0086] For example, in some embodiments, the inner sidewall 420 is made of silicon oxide, the second sacrificial layer 410 is made of titanium nitride, and a sulfuric acid-hydrogen peroxide mixture (SPM) is used as the etching solution to remove the second sacrificial layer 410 in the trench 250, with an etching selectivity ratio of the second sacrificial layer 410 to the sidewall material layer 400 greater than 500:1; the inner sidewall 420 is made of silicon oxide, the second sacrificial layer 410 is made of tantalum nitride, and an ammonia-hydrogen peroxide mixture is used as the etching solution to remove the second sacrificial layer 410 in the trench 250, with an etching selectivity ratio of the second sacrificial layer 410 to the sidewall material layer 400 greater than 100:1; the inner sidewall 420 is made of silicon oxide, the second sacrificial layer 410 is made of tungsten, and a phosphoric acid solution is used as the etching solution to remove the second sacrificial layer 410 in the trench 250, with an etching selectivity ratio of the second sacrificial layer 410 to the sidewall material layer 400 greater than 100:1.
[0087] refer to Figure 8A source / drain doped layer 600 is formed at the end of the stacked structure 240. The source / drain doped layer 600 seals the trench 250 to form an air gap 210 between the inner sidewall 420 and the source / drain doped layer 600.
[0088] The source / drain doped layer 600 is used as the source or drain region of the formed transistor.
[0089] Specifically, the source / drain doped layer 600 is epitaxially grown using the channel layer 230 as the epitaxial growth base. The inner sidewall 420 covers the surface of the channel layer 230 and the surface of the sacrificial layer 220 in the trench 250, so that the source / drain doped layer 600 will not grow on the surface of the channel layer 230 and the sacrificial layer 220 in the trench 250. Therefore, in the step of forming the source / drain doped layer 600, the source / drain doped layer 600 is in contact with the end of the channel layer 230 and seals the trench 250 into an air gap 210.
[0090] In some embodiments, the doping type of the source / drain doped layer 600 is the same as the channel conductivity type of the corresponding transistor. Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source / drain doped layer 600 are N-type ions, including P ions, As ions, or Sb ions; when the substrate 100 is used to form a PMOS transistor, the doping ions in the source / drain doped layer 600 are P-type ions, including B ions, Ga ions, or In ions.
[0091] The air gap 210 serves to isolate the subsequently formed gate structure from the source / drain doped layer 600, thereby reducing the parasitic capacitance between the device gate structure and the source / drain doped layer 600.
[0092] In some embodiments, a second sacrificial layer 410 is first used to occupy space in the trench 250, then the second sacrificial layer 410 is removed to expose the remaining trench 250 surrounded by the inner sidewall 420, and finally a source / drain doped layer 600 is formed at the end of the stacked structure 240 to seal the trench 250, so as to form an air gap 210 between the source / drain doped layer 600 and the inner sidewall 420. The dielectric constant of air is less than that of the dielectric material. Therefore, introducing an air gap 210 between the source / drain doped layer 600 and the inner sidewall 420 can effectively reduce the parasitic capacitance between the source / drain doped layer 600 and the subsequently formed gate structure, thereby improving the performance of the semiconductor structure.
[0093] Accordingly, in some embodiments, in the step of forming the source / drain doped layer 600 at the end of the stacked structure 240, the source / drain doped layer 600 is formed at the end of the stacked structure 240 exposed by the dummy gate structure 300.
[0094] refer to Figure 9 After forming the source / drain doped layer 600 at the end of the stacked structure 240, the method further includes: removing the dummy gate structure 300.
[0095] Removing the dummy gate structure 300 provides space for the subsequent formation of the gate structure, and at the same time prepares for the removal of the sacrificial layer 220.
[0096] Specifically, in some embodiments, before removing the dummy gate structure 300, the mask layer 310 is removed to expose the dummy gate structure 300, so as to facilitate the removal of the dummy gate structure.
[0097] In some embodiments, the first sacrificial layer 220 is removed to expose a plurality of longitudinally spaced channel layers 230 and to expose the inner wall 420 covering the first sacrificial layer 220.
[0098] Remove the sacrificial layer 220 to expose the surfaces of the channel layer 230, so that the gate structure formed subsequently surrounds and covers the channel layer 230, and blocks the gate structure from overflowing toward the source / drain doped layer 600 by the inner sidewall 420 covering the first sacrificial layer 220.
[0099] In some embodiments, a gate structure 700 is formed that spans a plurality of channel layers 230 and surrounds and covers the channel layers 230 and the inner sidewalls 420 exposed between the channel layers 230.
[0100] The gate structure 700 is used to control the opening or closing of the transistor's channel.
[0101] Specifically, if the gate structure 700 covers the channel layer 230, then the top, bottom and sidewalls of the channel layer 230 can all serve as channels, increasing the area in the channel layer 230 used as channels, thereby increasing the operating current of the semiconductor structure.
[0102] In some embodiments, the inner sidewall 420 has a high film quality, which helps to prevent the material of the gate structure 700 from penetrating the inner sidewall 420 and overflowing into the air gap 210 during the formation of the gate structure 700, thereby affecting the gate length of the gate structure 700 and thus helping to prevent leakage risk between the gate structure 700 and the source / drain doped layer 600.
[0103] In some embodiments, the gate structure 700 includes a gate dielectric layer surrounding the channel layer 230 along the extending direction of the gate structure 700, and a gate electrode layer located on the gate dielectric layer.
[0104] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 230, and the gate electrode layer from the substrate 100.
[0105] Specifically, the gate dielectric layer material includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In some embodiments, the gate dielectric layer includes a high-k gate dielectric layer, and the high-k gate dielectric layer material includes a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the high-k gate dielectric layer material includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.
[0106] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 230. Specifically, the material of the gate oxide layer can be silicon oxide.
[0107] In some embodiments, the gate structure 700 is a metal gate structure, therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.
[0108] Specifically, the gate electrode layer includes a work function layer and an electrode layer located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.
[0109] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.
[0110] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A laminated structure is provided, comprising a first sacrificial layer and a channel layer stacked alternately in the longitudinal direction; A portion of the width of the first sacrificial layer is removed from the end of the stacked structure to form a trench surrounded by the channel layer and the remaining first sacrificial layer; A sidewall material layer is formed to conformally cover the end of the channel layer and the inner wall of the trench, and the material of the sidewall material layer is a dielectric material; A second sacrificial layer is formed to cover the sidewall material layer and fill the trench, wherein the material of the second sacrificial layer is a metallic material; Remove the end of the trench layer, as well as the second sacrificial layer and sidewall material layer outside the trench, and the remaining sidewall material layer in the trench serves as the inner sidewall; Remove the second sacrificial layer in the trench to expose the remaining trench enclosed by the inner wall; A source / drain doped layer is formed at the end of the stacked structure, and the source / drain doped layer seals the trench to form an air gap between the inner sidewall and the source / drain doped layer.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a sidewall material layer that conformally covers the end of the channel layer, as well as the surface of the channel layer and the surface of the first sacrificial layer in the trench, the thickness of the sidewall material layer is 3 nm to 300 nm.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming a second sacrificial layer that covers the sidewall material layer and fills the trench, the material of the second sacrificial layer includes one or more of titanium nitride, tantalum nitride, tungsten, cobalt, and molybdenum.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, A second sacrificial layer is formed by using atomic layer deposition (ALD) to cover the sidewall material layer and fill the trench.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of removing the second sacrificial layer from the trench, the etching selectivity ratio of the second sacrificial layer to the sidewall material layer is greater than or equal to 50.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, An anisotropic dry etching process is used to remove the second sacrificial layer and sidewall material layer at the end of the trench layer.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second sacrificial layer in the trench is removed using an isotropic wet etching process.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the stacked structure, a pseudo-gate structure is also formed on the stacked structure, which covers part of the sidewalls and part of the top of the stacked structure and exposes both ends of the stacked structure. In the step of removing a portion of the width of the first sacrificial layer from the end of the stacked structure, a portion of the width of the first sacrificial layer is removed from the end of the stacked structure exposed by the pseudo-gate structure. In the step of forming a sidewall material layer that conformally covers the end of the trench layer, as well as the surface of the trench layer and the surface of the first sacrificial layer in the trench, the sidewall material layer also conformally covers the top and sidewalls of the pseudo-grid structure. In the step of removing the second sacrificial layer and sidewall material layer at the end of the trench layer, the second sacrificial layer and sidewall material layer covering the top and sidewall of the pseudo-grid structure are also removed. In the step of forming a source / drain doped layer at the end of the stacked structure, the source / drain doped layer is formed at the end of the stacked structure exposed by the dummy gate structure.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming source / drain doped layers at the ends of the stacked structure, the method further includes: Remove the pseudo-gate structure; Remove the remaining first sacrificial layer to expose a plurality of channel layers arranged longitudinally at intervals, and expose the inner wall covering the first sacrificial layer. A gate structure is formed that spans multiple said channel layers, surrounds and covers the channel layers, and covers the inner sidewalls exposed between the channel layers.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the laminated structure, the laminated structure protrudes from the substrate; In the step of forming a sidewall material layer that conformally covers the end of the trench layer, as well as the surface of the trench layer and the surface of the first sacrificial layer in the trench, the sidewall material layer also conformally covers the top surface of the substrate; In the step of removing the second sacrificial layer and sidewall material layer at the end of the trench layer, the second sacrificial layer and sidewall material layer covering the top surface of the substrate are also removed.