Integrated circuit chip based on two-dimensional material field effect transistor and preparation method thereof

Abstract

The application belongs to the technical field of nanometer semiconductor integrated circuit devices, and particularly relates to an integrated circuit chip based on a two-dimensional material field effect transistor and a preparation method thereof. The chip comprises a substrate, an isolation dielectric layer, a CMOS transistor array, a device isolation trench, an interlayer interconnection structure and a peripheral circuit module; the CMOS transistor array adopts a complementary structure constructed by N-type MoS2 and P-type WSe2 two-dimensional semiconductors, is matched with a high-k top gate dielectric and a van der Waals contact electrode; an isolation trench completely penetrating through a two-dimensional film is arranged between the transistors and is filled with an insulating dielectric, so that high-suppression-ratio device isolation is achieved; the interlayer interconnection adopts a metal-two-dimensional composite structure, and the overall process temperature is ≤450 ℃. The application effectively suppresses short channel effect and off-state leakage, the device switching ratio is more than 10 7 , the array crosstalk suppression is greater than 60 dB, is compatible with high performance and silicon-based CMOS process, and can be applied to the fields of high-density low-power-consumption logic, storage and edge AI chips.

Description

Technical Field

[0001] This invention belongs to the field of nano-semiconductor integrated circuit device technology, and particularly relates to an integrated circuit chip based on a two-dimensional material field-effect transistor. Background Technology

[0002] As Moore's Law continues to advance, silicon-based CMOS processes are shrinking towards 2nm and 1nm nodes. When the silicon transistor channel is shortened to its limit, a severe short-channel effect occurs, gate control capability decreases, off-state leakage current increases sharply, and chip power consumption, leakage current, and heat generation problems become difficult to suppress. The silicon material itself has reached its physical scaling limit.

[0003] Two-dimensional transition metal dichalcogenides (TMDs) possess atomically thin channel thicknesses and naturally exhibit excellent gate electrostatic control capabilities, significantly suppressing short-channel effects. They represent a highly promising channel material for next-generation integrated circuits in the post-Moore's Law era. While significant progress has been made in the performance of laboratory-scale two-dimensional transistor devices, several bottlenecks remain for large-scale integrated circuit chip integration: First, high-density complementary integration of N-type and P-type two-dimensional transistors is difficult, leading to severe leakage crosstalk between devices; second, high contact resistance between source / drain metals and two-dimensional semiconductors limits chip operating speed; third, numerous defects at the gate dielectric interface reduce device on / off ratio and mobility; and fourth, high interconnect process temperatures hinder large-scale array integration, making it difficult to form fully functional integrated circuit chips.

[0004] Most existing technologies only focus on research on individual two-dimensional field-effect transistor devices, lacking a complete and large-scale integrated CMOS integrated circuit chip architecture, and cannot be directly used in high-performance logic processor chips. Therefore, there is an urgent need to provide a high-performance chip solution for two-dimensional material field-effect transistor integrated circuits that can achieve high density, low power consumption, and high speed. Summary of the Invention

[0005] This invention addresses the technical problems of severe short-channel effect and high leakage power consumption in silicon-based chip miniaturization nodes, as well as the large crosstalk, high contact resistance, numerous gate dielectric interface defects, and difficulty in achieving CMOS complementary array integration when two-dimensional devices are integrated on a large scale. It proposes a well-designed two-dimensional CMOS integrated circuit chip with high density, low leakage current, and high mobility, which is suitable for high-performance computing and edge AI chip applications in the post-Moore era. The invention also includes a high-performance integrated circuit chip based on two-dimensional material field-effect transistors and its fabrication method.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is an integrated circuit chip based on a two-dimensional material field-effect transistor, including a substrate;

[0007] An isolation dielectric layer formed on the substrate;

[0008] A CMOS transistor array integrated on the isolation dielectric layer, the CMOS transistor array comprising N-type two-dimensional field-effect transistors and P-type two-dimensional field-effect transistors arranged in an array;

[0009] Device isolation trenches are etched into a two-dimensional semiconductor thin film layer to achieve electrical isolation between adjacent transistors;

[0010] Interlayer interconnect structure is used to realize circuit interconnection between the source, drain and gate of each transistor; peripheral circuit module is electrically connected to CMOS transistor array;

[0011] The channel layer of the N-type two-dimensional field-effect transistor is an N-type two-dimensional transition metal chalcogenide semiconductor, and the channel layer of the P-type two-dimensional field-effect transistor is a P-type two-dimensional transition metal chalcogenide semiconductor. Both the N-type and P-type two-dimensional field-effect transistors adopt a top-gate structure, including a source, a drain, a high-k gate dielectric layer, and a top-gate electrode. The source, drain, and two-dimensional channel layer form a van der Waals contact interface.

[0012] Preferably, the channel material of the N-type two-dimensional field-effect transistor is a single layer or few layers of MoS2; the channel material of the P-type two-dimensional field-effect transistor is a single layer or few layers of WSe2; and the channel thickness is 0.65nm~5nm.

[0013] Furthermore, the median field-effect electron mobility of the N-type MoS2 field-effect transistor at room temperature reaches 160 cm⁻¹. 2 V -1 s -1 The median hole mobility of the P-type WSe2 field-effect transistor reaches 38 cm⁻¹. 2 V -1 s -1 Both types of devices have an on / off ratio exceeding 10. 7 The source-drain contact resistance is as low as 70~100Ω. μm.

[0014] Preferably, the high-k gate dielectric layer is made of Al2O3, HfO2 or HfAlO composite dielectric, with a thickness controlled between 2nm and 8nm, and is prepared by atomic layer deposition (ALD) process; the top gate electrode is made of nickel, gold, molybdenum or nickel-gold composite metal.

[0015] Preferably, the source and drain electrodes are made of van der Waals contact metal, with no alloy diffusion layer between the source / drain electrodes and the two-dimensional semiconductor channel, resulting in a contact resistance of less than 200Ω. μm.

[0016] Preferably, the device isolation trench is dry etched, the trench depth completely penetrates the two-dimensional semiconductor thin film, and the inside of the trench is filled with an insulating medium to eliminate lateral leakage crosstalk between devices.

[0017] Preferably, the interlayer interconnect structure includes multiple metal wiring layers, and a two-dimensional conductive transition layer is provided between the metal wiring and the two-dimensional device electrode to achieve low-temperature interconnection, with a process temperature not exceeding 450°C.

[0018] Preferably, the peripheral circuit module includes input / output I / O circuits, electrostatic discharge protection circuits, and bias circuits, which together with the CMOS transistor array constitute a logic operation unit, a storage unit, or a processor core.

[0019] The present invention also provides a method for manufacturing the above-mentioned chip, comprising the following steps:

[0020] S1: Provide a substrate and deposit an isolation dielectric layer on the substrate surface;

[0021] S2: Using CVD growth or dry transfer process, N-type two-dimensional semiconductor thin film and P-type two-dimensional semiconductor thin film are sequentially transferred to the surface of the isolation dielectric layer;

[0022] S3: Photolithography and dry etching form device isolation trenches, and the trenches are filled with insulating dielectric to complete device area isolation;

[0023] S4: Photolithography patterning, metal evaporation, and stripping to form the source and drain of N-type and P-type transistors;

[0024] S5: Atomic layer deposition grows a high-k gate dielectric layer to cover the channel region;

[0025] S6: Photolithography and vapor deposition are used to form the top gate electrode;

[0026] S7: Fabricate the interlayer dielectric layer, photolithographically create vias, deposit a two-dimensional composite metal interconnect layer, and complete the internal interconnection of the transistor array;

[0027] S8: Fabricate peripheral circuit modules, complete the interconnection, passivation, and dicing of the entire chip, and obtain a high-performance integrated circuit chip.

[0028] Preferably, after the source and drain electrodes are prepared in step S4, they are subjected to low-temperature annealing in a vacuum atmosphere at a temperature of 150°C to 300°C to optimize the van der Waals contact interface and reduce the contact resistance.

[0029] As a preferred option, the maximum temperature of all two-dimensional device fabrication processes is ≤450℃, which is compatible with silicon-based CMOS wafer heterogeneous integration.

[0030] Compared with existing technologies, the advantages and positive effects of the integrated circuit chip based on two-dimensional material field-effect transistors provided by this invention are as follows:

[0031] 1. Superior device performance, breaking through the physical limits of silicon: MoS2 and WSe2 are used as N-channel and P-channel two-dimensional semiconductors, respectively, to construct a complete CMOS complementary transistor array; atomically thin channel greatly suppresses short-channel effects, significantly reduces device off-state leakage current, and achieves an on / off ratio exceeding 10. 7 The median electron mobility of N-type devices can reach 160 cm⁻¹. 2 cm 2 V -1 s -1 The median hole mobility of P-type devices can reach 38 cm⁻¹. 2 V -1 s -1 It can support chip miniaturization to sub-2nm equivalent nodes.

[0032] 2. Isolation structure effectively suppresses array crosstalk: Isolation trenches that completely penetrate the two-dimensional semiconductor thin film and are filled with an insulating medium effectively block lateral conductive channels between devices. Experimental verification shows that this structure can suppress lateral leakage current between adjacent devices to 10%. -14 With an A-level crosstalk suppression ratio exceeding 60dB, it solves the isolation problem of large-scale array integration of two-dimensional materials.

[0033] 3. Combining low contact resistance and high gate control capability: Employing van der Waals contact source and drain electrodes, coupled with a low-temperature vacuum annealing process, the source and drain contact resistance can be as low as 70~100Ω. μm; combined with the ultrathin high-k gate dielectric prepared by ALD, the interface defect density is low, the gate control capability is strong, and the subthreshold swing is close to the theoretical limit, effectively improving the carrier mobility and chip operating frequency.

[0034] 4. Low-temperature process compatible with existing silicon-based production lines: The highest temperature of the entire device fabrication process does not exceed 450℃. This temperature window matches the thermal budget requirements of silicon-based CMOS back-end processes, avoiding copper interconnect failure, low-k dielectric degradation and doping diffusion problems.

[0035] 5. Complete chip architecture adaptable to diverse applications: The chip integrates a CMOS transistor array with peripheral I / O, ESD protection, and bias circuits to form a complete functional integrated circuit, which can realize logic operation, storage, and processor core, targeting application scenarios such as low-power high-performance computing and edge AI sensing chips. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of the overall cross-sectional structure of a high-performance integrated circuit chip based on a two-dimensional material field-effect transistor provided by the present invention;

[0038] Figure 2 This is a partially enlarged cross-sectional schematic diagram of the CMOS transistor array provided by the present invention;

[0039] Figure 3 Flowchart of the method for fabricating high-performance integrated circuit chips according to the present invention;

[0040] Figure 4 Box plots of field-effect mobility for the N-type MoS2 and P-type WSe2 devices of this invention;

[0041] Figure 5 This is a comparison curve of the transfer characteristics of the N-type MoS2 and P-type WSe2 transistors of the present invention;

[0042] Figure 6 This is a comparison curve showing the variation of lateral leakage current of adjacent devices with and without the isolation trench structure of the present invention as a function of device spacing;

[0043] Figure 7 This is a voltage transfer characteristic curve of the two-dimensional material CMOS inverter of the present invention;

[0044] Figure 8 This is a stability test curve of the normalized on-state current of the device of the present invention as a function of the highest process temperature.

[0045] Figure 9 This is a graph showing the total normalized resistance as a function of channel length in the transmission line model (TLM) test of the device before and after annealing according to the present invention.

[0046] In the above figures, 1. Substrate; 2. Isolation dielectric layer; 3. N-type two-dimensional field-effect transistor; 4. P-type two-dimensional field-effect transistor; 5. Device isolation trench; 6. Source; 7. Drain; 8. Two-dimensional channel layer; 9. High-k gate dielectric layer; 10. Top gate electrode; 11. Interlayer interconnect structure; 12. Peripheral circuit module. Detailed Implementation

[0047] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0048] Numerous specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways than those described herein, and therefore the invention is not limited to the specific embodiments disclosed in the following specification.

[0049] Example 1: This example provides an integrated circuit chip based on a two-dimensional material field-effect transistor and its fabrication method, particularly including the overall chip architecture and its fabrication method, as described in detail below:

[0050] like Figure 1 As shown, this embodiment provides a high-performance integrated circuit chip based on two-dimensional material field-effect transistors, which includes, from bottom to top: a substrate 1, an isolation dielectric layer 2, an N-type two-dimensional field-effect transistor 3 and a P-type two-dimensional field-effect transistor 4, a device isolation trench 5, an interlayer interconnect structure 11, and a peripheral circuit module 12. The substrate 1 is a high-resistivity silicon substrate; the isolation dielectric layer 2 is a 200nm thick SiO2 layer; in the CMOS transistor array, the channel of the N-type two-dimensional field-effect transistor 3 is a single layer of MoS2, and the channel of the P-type two-dimensional field-effect transistor 4 is a single layer of WSe2; the channel length is 50nm; the device isolation trench 5 is prepared by reactive ion dry etching, and the trench depth completely penetrates the two-dimensional thin film, and the trench is filled with an Al2O3 insulating dielectric.

[0051] like Figure 2 As shown, Figure 2 for Figure 1A partially magnified cross-sectional view of the CMOS transistor array clearly shows the internal structure of a single N-type transistor 3 and P-type transistor 4, including the source 6, drain 7, two-dimensional channel layer 8, high-k gate dielectric layer 9, and top gate electrode 10. Specifically, the device isolation trench 5 completely penetrates the two-dimensional channel layer 8 to reach the surface of the isolation dielectric layer 2, and the trench is filled with an insulating dielectric. In the above description: the transistor has a top-gate structure; the high-k gate dielectric layer 9 is 5nm thick HfO2, deposited using an ALD process; the top gate electrode 10 is a Ni / Au composite metal; and the source 6 and drain 7 are made of Ni metal. A van der Waals contact interface is formed with the two-dimensional channel layer 8; after fabrication, it is annealed at 220℃ in a vacuum environment to optimize the contact interface characteristics; the interlayer interconnect structure 11 adopts Cu metal wiring, and graphene is introduced at the through-hole as a two-dimensional conductive transition layer to reduce the interconnect contact resistance; the peripheral circuit module 12 integrates I / O interface and ESD electrostatic protection circuit, and the whole constitutes an 8-bit logic operation chip. This physical structure completely blocks the lateral conductive path between adjacent transistors, which intuitively reflects the design intention and technical effect of the isolation structure in physically blocking the lateral leakage path between adjacent transistors.

[0052] like Figure 3 As shown, this embodiment also provides a method for fabricating the chip, and the flowchart includes eight key steps from S1 to S8:

[0053] S1: Prepare and planarize the isolation dielectric layer 2 on the substrate;

[0054] S2: N-type MoS2 thin films and P-type WSe2 thin films are prepared on the isolation dielectric layer 2 by van der Waals transfer or CVD growth to form a two-dimensional channel layer 8;

[0055] S3: A high-k gate dielectric layer 9 is deposited using atomic layer deposition (ALD) technology, followed by the deposition of a metal gate and patterning to form the top gate electrode 10;

[0056] S4: Using a selective etching process, trenches that completely penetrate the two-dimensional channel layer are etched between adjacent transistors and filled with insulating dielectric to form device isolation trenches 5;

[0057] S5: Define the source and drain contact windows, deposit metal electrodes through thermal evaporation or electron beam evaporation, and then strip them to form source 6 and drain 7;

[0058] S6: Low-temperature annealing at 220°C is performed to optimize the contact resistance of the metal-two-dimensional semiconductor interface;

[0059] S7: Deposited interlayer dielectric layer, with contact holes formed by photolithography and etching, and filled with metal to form interlayer interconnect structure 11;

[0060] S8: Complete the metal wiring and packaging of the peripheral circuit module 12 to obtain the final high-performance chip.

[0061] Multiple performance tests were performed on the chip and device prepared in this embodiment, and the results are as follows: 1. Carrier mobility performance: such as Figure 4 As shown, statistical analysis of a batch of devices reveals that N-type MoS2 field-effect transistors exhibit excellent n-type transport characteristics at room temperature, with a median field-effect electron mobility of 160 cm⁻¹. 2 cm 2 V -1 s -1 The data distribution is concentrated, and the process consistency is good; the median hole mobility of the P-type WSe2 field-effect transistor reaches 38 cm⁻¹. 2 cm 2 V -1 s -1 Up to 85cm 2 cm 2 V -1 s -1 The mobility level fully meets the driving requirements of high-performance PMOS; the above proves that the mobility levels of the two types of devices are highly matched, which can provide balanced driving capability for complementary logic circuits and are suitable for building high-performance complementary logic circuits.

[0062] 2. Transistor switching and gate control characteristics: such as Figure 5 As shown in the transfer characteristic curves, N-type MoS2 and P-type WSe2 transistors exhibit typical complementary transport characteristics: N-type devices turn on at a positive gate voltage, while P-type devices turn on at a negative gate voltage. The off-state leakage current of both types of devices is less than 10 Ω. -12 A / μm, on / off ratio both exceed 10 7 In terms of subthreshold swing, the P-type WSe2 transistor can achieve a swing as low as 65 mV / decade, while the N-type MoS2 transistor can approach the theoretical limit at room temperature. These results verify the strong gate control capability of atomically thin two-dimensional channels and high-k top-gate structures, which can effectively suppress short-channel effects and achieve low-power off-state characteristics.

[0063] Under the conditions of VDS=1V and gate overdrive voltage of 2.5V, the on-state current density of the N-type MoS2 transistor can reach 942μA / μm, and the on-state current density of the P-type WSe2 transistor can reach 421μA / μm, which meets the driving requirements of high-speed circuits.

[0064] 3. Optimization effect of low-temperature annealing on contact resistance: The source-drain contact resistance was characterized using the transmission line model (TLM) test method, and the test results are as follows: Figure 9 As shown.

[0065] In the graph, the horizontal axis represents the channel length, the vertical axis represents the normalized total resistance, and the intercept of the curve with the vertical axis corresponds to the source-drain contact resistance. Before annealing, the source-drain contact resistance of the device is approximately 400Ω. μm; After vacuum low-temperature annealing at 220℃, the van der Waals contact interface was effectively optimized, and the contact resistance was significantly reduced to 200Ω. Below μm, the optimal Ω can be as low as 70~100. μm. This result demonstrates that the low-temperature annealing process used in this invention can achieve low-resistance ohmic contacts within a thermal budget of no more than 450°C, without the need for a high-temperature activation step in traditional semiconductor processes.

[0066] 4. Verification of the isolation effect of the device isolation trench: To verify the electrical isolation effect of the isolation trench, two sets of control samples were prepared: the experimental group used the isolation trench structure of the present invention, and the control group did not have an isolation trench; all other process conditions were completely identical. The change in lateral leakage current between adjacent transistors with the device spacing was tested, and the results are as follows: Figure 6 As shown.

[0067] In the control group without isolation trenches, there was a clear lateral leakage path between adjacent devices, with the lateral leakage current at 10. -9 ~10 -10 The value is on the order of A, and increases significantly as the device spacing decreases;

[0068] In the experimental group with isolation trenches, the lateral leakage current was suppressed to 10. -13 ~10 -14 The difference is on the order of magnitude A, which is 3-4 orders of magnitude lower than the control group, corresponding to a crosstalk suppression ratio of over 60dB, and a significant reduction in the sensitivity of leakage current to spacing changes. This comparative verification shows that isolation trenches that completely penetrate the two-dimensional semiconductor thin film can effectively block the lateral conductive channels between devices, significantly suppress leakage crosstalk problems in array integration, and support high-density device integration.

[0069] 5. CMOS Inverter Circuit Characteristics: Based on the N-type and P-type two-dimensional transistors of this embodiment, a CMOS inverter unit is constructed. Its voltage transfer characteristics are as follows: Figure 7 As shown.

[0070] The inverter output voltage can achieve a full swing output close to 0V to the power supply voltage, with a steep transition region, high voltage gain and good noise margin, exhibiting standard CMOS inverting logic characteristics.

[0071] The results verify that the two-dimensional transistors of the present invention can be successfully used to construct fully functional complementary logic circuits, demonstrating the feasibility of large-scale digital integrated circuit integration.

[0072] 6. Process Temperature Compatibility Verification: To verify the device performance stability within a process window of ≤450℃, the normalized on-state current of the device was tested at different maximum process temperatures. The results are as follows: Figure 8 As shown.

[0073] Below 200℃, the device's on-state current shows almost no decay; below 450℃, the device's normalized on-state current remains above 0.98, with performance degradation of less than 2%; when the temperature exceeds 450℃, the device's performance degradation rate accelerates significantly.

[0074] The experimental results match the thermal budget requirements of silicon-based CMOS back-end processes: standard silicon-based CMOS back-end processes typically limit the thermal budget to 400-450°C to protect copper interconnects, low-k dielectrics and doping distribution.

[0075] The maximum temperature of all two-dimensional device fabrication processes in this invention is ≤450℃, which can achieve heterogeneous integration with silicon-based CMOS wafers without significantly losing device performance and is compatible with existing semiconductor production line processes.

[0076] Example 2 is basically the same as Example 1, except that: the high-k gate dielectric layer is 4nm thick Al2O3; the channel is two layers of MoS2 and two layers of WSe2; the maximum process temperature is controlled at 300℃, which is used for heterogeneous integration with silicon-based CMOS wafers to build a high-performance chip with a two-dimensional silicon hybrid architecture.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. An integrated circuit chip based on a two-dimensional material field-effect transistor, characterized in that, include: Substrate; An isolation dielectric layer formed on the substrate; A CMOS transistor array integrated on an isolation dielectric layer, the CMOS transistor array comprising N-type two-dimensional field-effect transistors and P-type two-dimensional field-effect transistors arranged in an array, the channel layer of the N-type two-dimensional field-effect transistors being an N-type two-dimensional transition metal chalcogenide semiconductor, and the channel layer of the P-type two-dimensional field-effect transistors being a P-type two-dimensional transition metal chalcogenide semiconductor; both the N-type and P-type two-dimensional field-effect transistors adopt a top-gate structure, including a source, a drain, a high-k gate dielectric layer and a top-gate electrode, and a van der Waals contact interface is formed between the source, drain and the two-dimensional channel layer; Device isolation trenches are etched into a two-dimensional semiconductor thin film layer. The trenches are deeply penetrated into the two-dimensional semiconductor thin film and are filled with an insulating medium to achieve electrical isolation between adjacent transistors. Interlayer interconnect structure is used to realize the circuit interconnection between the source, drain and gate of each transistor; The peripheral circuit module is electrically connected to the CMOS transistor array.

2. The integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 1, characterized in that, The channel material of the N-type two-dimensional field-effect transistor is a single layer or few layers of MoS2, and the channel material of the P-type two-dimensional field-effect transistor is a single layer or few layers of WSe2, with a channel layer thickness of 0.65nm~5nm.

3. An integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 1, characterized in that, The high-k gate dielectric layer is made of Al2O3, HfO2 or HfAlO composite dielectric, with a thickness of 2nm to 8nm, and is prepared by atomic layer deposition. The top gate electrode is made of nickel, gold, molybdenum or nickel-gold composite metal.

4. An integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 1, characterized in that, The contact resistance of the source and drain is less than 200Ω. μm, the source and drain electrodes are prepared and then subjected to vacuum low-temperature annealing to optimize the van der Waals contact interface.

5. An integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 1, characterized in that, The isolation trenches of the device are prepared by dry etching, and the crosstalk suppression ratio between adjacent devices is greater than 60dB.

6. An integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 1, characterized in that, The interlayer interconnect structure includes multiple metal wiring layers, and a two-dimensional conductive transition layer is provided between the metal wiring and the two-dimensional device electrode. The overall chip fabrication process temperature is ≤450℃, which is compatible with silicon-based CMOS wafer heterogeneous integration.

7. An integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 1, characterized in that, The peripheral circuit module includes input / output I / O circuits, electrostatic discharge protection circuits, and bias circuits, which together with the CMOS transistor array constitute a logic operation unit, a storage unit, or a processor core.

8. An integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 2, characterized in that, The median field-effect electron mobility of N-type MoS2 field-effect transistors at room temperature reaches 160 cm⁻¹. 2 V -1 s -1 The median hole mobility of the P-type WSe2 field-effect transistor reaches 38 cm⁻¹. 2 V -1 s -1 Both types of devices have an on / off ratio exceeding 10. 7 The source-drain contact resistance is as low as 70~100Ω. μm.

9. A method for fabricating an integrated circuit chip based on a two-dimensional material field-effect transistor, characterized in that, Fabricating an integrated circuit chip based on a two-dimensional material field-effect transistor as described in any one of claims 1 to 7 includes the following steps: S1: Provide a substrate and deposit an isolation dielectric layer on the substrate surface; S2: Using CVD growth or dry transfer process, N-type two-dimensional semiconductor thin film and P-type two-dimensional semiconductor thin film are sequentially formed on the surface of the isolation dielectric layer; S3: Device isolation trenches are formed by photolithography and dry etching, and the trenches are filled with insulating medium to complete the device area isolation; S4: Photolithography patterning, metal deposition and stripping to form the source and drain of N-type and P-type transistors; S5: A high-k gate dielectric layer is grown using atomic layer deposition (ALD) to cover the channel region; S6: Photolithography, metal evaporation and stripping to form the top gate electrode; S7: Fabricate the interlayer dielectric layer, form vias by photolithography, deposit the metal and two-dimensional composite interconnect layer, and complete the internal interconnection of the transistor array; S8: Fabricate peripheral circuit modules, complete the interconnection, passivation and dicing of the entire chip, and obtain a high-performance integrated circuit chip.

10. The method for fabricating an integrated circuit chip based on a two-dimensional material field-effect transistor according to claim 9, characterized in that, After the source and drain electrodes are prepared in step S4, they are subjected to low-temperature annealing in a vacuum atmosphere. The annealing temperature is 150℃~300℃, and the highest temperature of the entire preparation process is ≤450℃.

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