A method for manufacturing a stacked package structure of an LED array and a CMOS driving chip

Abstract

The present application relates to the technical field of optoelectronic packaging, and particularly relates to a stacked packaging structure of an LED array and a CMOS driving chip and a manufacturing method thereof, which comprises the following steps: providing a silicon wafer, forming a fiber lead-in groove array in the top layer silicon of the silicon wafer; manufacturing a light beam shaping structure on the bottom layer of the silicon wafer, and vertically aligning the light beam shaping structure and the fiber lead-in groove array in the thickness direction of the silicon wafer through a double-sided photolithography process; providing an LED array core particle, which comprises a plurality of light emitting units, and each light emitting unit has an electrode. The present application pre-integrates the LED array core particle and the CMOS driving chip into a three-dimensional stacked functional unit, and then integrally bonds the three-dimensional stacked functional unit to the silicon wafer, so that the electrical interconnection path is greatly shortened, the parasitic parameter is reduced, and through the double-sided alignment integrated design of the fiber lead-in groove and the light beam shaping structure on the silicon wafer, high-precision passive alignment coupling of the LED light source and the fiber array is realized, and the coupling efficiency and the array consistency are improved.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic packaging technology, and more specifically to a method for manufacturing a stacked packaging structure of an LED array and a CMOS driver chip. Background Technology

[0002] With the rapid development of technologies such as big data, cloud computing, and artificial intelligence, the demand for data transmission rates within data centers and between boards and chips is increasing dramatically. Traditional electrical interconnects face physical bottlenecks in terms of bandwidth density, power consumption, and transmission distance. Optical interconnects, due to their advantages such as high bandwidth, low loss, and resistance to electromagnetic interference, are gradually becoming an important solution for short-distance, high-speed interconnects. At the optical emitter, vertical-cavity surface-emitting lasers (VCSELs) are currently the mainstream light source for multi-channel parallel optical modules, and with the help of CMOS driver chips, modulation rates of tens of Gbps per channel can be achieved. However, VCSELs are temperature-sensitive, costly, and have performance limitations in short-distance (<100m) applications. In contrast, LED light sources have advantages such as low cost, high reliability, low temperature drift, and good linearity, and have broad application prospects in cost-sensitive applications such as short-distance optical interconnects, industrial optical sensing, and automotive optical communication.

[0003] However, existing LED light emitting modules have the following shortcomings in terms of packaging and integration: Firstly, the separate arrangement of LEDs and driver chips results in large parasitic parameters, which restricts high-frequency performance. In traditional solutions, the LED array chip and CMOS driver chip are mounted separately on a PCB or ceramic substrate, and electrically connected via gold wire bonding or substrate wiring. This two-dimensional planar layout leads to long interconnect paths, introducing large parasitic inductance and capacitance, which severely limits the modulation bandwidth and switching speed of the LED, making it difficult to meet the high-speed driving requirements of Gbps and above. Although there are reports of using flip-chip bonding to interconnect the LED chip and driver chip, this usually still requires the use of an adapter board or interposer, failing to achieve true three-dimensional stacking, and there is still room for optimization of the signal path.

[0004] Secondly, fiber coupling alignment relies on active processes, resulting in high packaging costs and low efficiency. LED emitted light has a large divergence angle (typically >60°), requiring beam-shaping elements such as microlenses and mirrors for effective coupling into the optical fiber. Current processes mostly employ active alignment methods for aligning the fiber to the LED light-emitting unit. This involves adjusting the fiber position using a six-axis precision displacement stage after the LED is lit until maximum coupling power is achieved, followed by adhesive bonding. This process is time-consuming, with alignment time for each channel reaching several minutes, and requires expensive equipment, making it difficult to meet the demands of array-based, mass production. Even with passive alignment solutions such as V-grooves, the V-grooves are typically fabricated on separate silicon or ceramic substrates, separate from the beam-shaping elements, requiring secondary assembly and resulting in significant accumulation of alignment tolerances.

[0005] Third, the beam shaping elements and fiber coupling structure are discretely integrated, resulting in complex optical paths and significant insertion losses. To achieve collimation, deflection, and mode matching of the LED emitted light, discrete components such as microlenses, mirrors, and gratings are typically required sequentially. Each component is fabricated on different substrates or assembled multiple times, resulting in numerous optical interfaces and introducing additional Fresnel reflections and coupling losses. Furthermore, the assembly tolerances of these discrete components overlap, leading to poor consistency across channels and significant fluctuations in coupling efficiency, which is detrimental to the mass production and performance uniformity control of multi-channel parallel optical modules.

[0006] Fourth, existing SOI-based optical platforms are mostly designed for lasers or modulators, lacking compatibility with LEDs. Silicon-on-insulator (SOI) materials, due to their excellent waveguide properties and mature CMOS-compatible processes, are widely used in passive optical paths and fiber coupling structures in silicon photonics chips. However, existing SOI optical platforms are typically designed for lasers or external modulators. Structures such as fiber guide slots and coupling gratings are geared towards the 1550nm or 1310nm communication bands with narrow input beams. They lack integrated beam shaping and mode field matching designs for the large divergence angle and wide-spectrum emission characteristics of LEDs, and lack a complete solution for three-dimensional stacking integration with LEDs and CMOS chips.

[0007] Fifth, the existing "mount-then-interconnect" process sequence results in an excessively long optical alignment tolerance chain. In the traditional process, the fiber guide structure and beam shaping element are fabricated on the substrate first, followed by multiple mounting and alignment operations between the LED chip and the driver chip and the substrate. Since the light emission port of the LED light-emitting unit must be precisely aligned with the fiber guide groove in the final optical path, the alignment errors introduced by discrete mounting accumulate step by step, eventually leading to significant fluctuations in coupling efficiency, which usually necessitates active alignment for compensation.

[0008] To address the above problems, this invention provides a stacked packaging structure of an LED array and a CMOS driver chip, and a method for manufacturing the same. Summary of the Invention

[0009] This invention aims to overcome at least one of the following problems in existing LED light emitting modules: the separate arrangement of LEDs and driver chips leads to large parasitic parameters and limited high-frequency performance; the reliance on active alignment for fiber coupling results in high packaging costs and low efficiency; the discrete integration of beam shaping elements and fiber coupling structures leads to complex optical paths and large insertion losses; and existing SOI-based optical platforms do not have an integrated design for the large divergence angle characteristics of LEDs and lack a three-dimensional stacking integration scheme with LEDs and CMOS chips. The invention provides a stacked packaging structure for LED arrays and CMOS driver chips and its manufacturing method.

[0010] To address the above problems, this invention provides a method for manufacturing a stacked packaging structure of an LED array and a CMOS driver chip, comprising the following steps: A silicon wafer is provided, and an array of fiber guide grooves is formed in the top silicon layer of the silicon wafer; A beam shaping structure is fabricated on the bottom layer of the silicon wafer, and the beam shaping structure and the fiber guide groove array are vertically aligned in the thickness direction of the silicon wafer using a double-sided photolithography process. An LED array chip is provided, comprising multiple light-emitting units, each of which has an electrode; A CMOS driver chip is provided, and the LED array chip is stacked with the CMOS driver chip in a vertical direction, and stacked interconnection is achieved by bonding and a vertical interconnection structure located between the two. The stacked LED array chip and the CMOS driver chip are bonded to one side of the beam shaping structure of the silicon wafer with the light-emitting surface of the LED array chip, so that the light-emitting port of the LED array chip is aligned with the fiber guide groove array in the vertical direction via the silicon wafer. The fiber array is placed into the fiber guide groove array, so that the optical receiving end of the fiber array is aligned and coupled with the light output port of the beam shaping structure.

[0011] Optionally, the step of forming the fiber guide groove array includes: A silicon wafer is provided, which consists of a top silicon layer, a buried oxide layer and a bottom silicon layer; A hard mask is deposited on the upper or lower surface of the silicon wafer using a chemical vapor deposition process; Using the buried oxide layer of the silicon wafer as an etching stop layer, a fiber guide groove array is formed in the top silicon layer of the silicon wafer by deep reactive ion etching. The angle between the sidewall of the fiber guide groove and the vertical direction is less than 5°.

[0012] Optionally, the step of forming the beam shaping structure includes: An opaque mask pattern is formed on the lower surface of the silicon wafer; A V-shaped reflective groove is formed on the lower surface of the silicon wafer using an etching process; The opening of the V-shaped reflective groove is located on the lower surface of the silicon wafer, and its bottom narrows towards the upper surface, so that the width of the V-shaped reflective groove in the longitudinal section gradually decreases from the lower surface to the upper surface. A reflective layer is formed on the reflective surface; In this process, a light-blocking surface is formed by a mask between two adjacent V-shaped reflective grooves. The light-blocking surface is used to block stray light scattered between adjacent light-emitting units.

[0013] Optionally, the reflective metal layer is selected from any one of the following materials: titanium / gold stack, silver layer, aluminum layer, tungsten layer, and tungsten silicide layer.

[0014] Optionally, when the electrodes of each light-emitting unit of the LED array chip are respectively disposed on the upper and lower surfaces of the light-emitting unit: The lower surface electrode of the LED array chip is electrically connected to the corresponding pad of the CMOS driver chip through the vertical interconnect structure; The upper surface electrode of the LED array chip is connected to the system-level interconnect layer above through a first conductive via penetrating the LED array chip or penetrating the dielectric layer; The pads of the CMOS driver chip are connected to the system-level interconnect layer through the through-silicon vias; The upper surface electrode of the LED array chip is electrically connected to the pad of the CMOS driver chip through the system-level interconnect layer to form a complete driving circuit.

[0015] Optionally, the method further includes the step of fabricating a system-level interconnect layer on the back side of the silicon wafer: thinning and polishing the back side of the silicon wafer, fabricating a redistribution layer on the back side, wherein the redistribution layer is electrically connected to the driving circuit array through the through-silicon vias of the CMOS driver chip.

[0016] Optionally, the step of forming the beam shaping structure further includes: using an etching process to etch a V-shaped curved reflective groove array on the lower surface of the silicon wafer, wherein the reflective surface of the V-shaped curved reflective groove array is a non-planar curved surface, and its surface shape is part of a parabola or ellipsoid, used to reflect and concentrate the emitted light from the LED array chip.

[0017] Optionally, the step of forming the beam shaping structure further includes: Microlenses corresponding to each of the light-emitting units are formed on the lower surface of the silicon wafer using a photolithography process. These microlenses are used to collimate or focus the emitted light from the LED array chips.

[0018] A stacked packaging structure for an LED array and a fiber optic array, comprising: A silicon wafer has an array of fiber guide grooves in its top silicon layer and a beam shaping structure in its bottom layer, wherein the beam shaping structure is perpendicularly aligned with the array of fiber guide grooves. The LED array chip includes multiple light-emitting units. The light-emitting surface of the light-emitting unit in the LED array chip is bonded to the side of the beam shaping structure closest to the silicon wafer. Each light-emitting unit is vertically opposite to the corresponding beam shaping structure and the fiber guide groove array. An optical fiber array is disposed in the optical fiber guide groove array, and the optical receiving end of the optical fiber array is aligned and coupled with the light output port of the beam shaping structure.

[0019] A stacked package structure of an LED array and a CMOS driver chip, comprising: A silicon wafer has an array of fiber guide grooves in its top silicon layer and a beam shaping structure in its bottom layer, wherein the beam shaping structure is perpendicularly aligned with the array of fiber guide grooves. The LED array chip includes multiple light-emitting units. The light-emitting surface of the light-emitting unit in the LED array chip is bonded to the side of the beam shaping structure closest to the silicon wafer. Each light-emitting unit is vertically opposite to the corresponding beam shaping structure and the fiber guide groove array. A CMOS driver chip is bonded above or below the LED array chip along the vertical direction of the LED array chip 20. A vertical interconnect structure is disposed between the LED array chip and the CMOS driver chip, for electrically connecting each electrode to the corresponding pad; An optical fiber array is disposed in the optical fiber guide groove array, and the optical receiving end of the optical fiber array is aligned and coupled with the light output port of the beam shaping structure.

[0020] The present invention has at least the following beneficial effects: 1. This solution pre-integrates the LED array chip and CMOS driver chip into a three-dimensional stacked functional unit before packaging them into the SOI optical platform, so that the vertical interconnect distance between the LED and CMOS is only on the order of the height of a microbump, thus meeting the requirements of high-speed optical interconnect.

[0021] 2. This solution forms an optical fiber guide groove array by aligning the front side of the SOI wafer and a beam shaping structure by aligning the back side. The pre-integrated overall structure is then bonded to the SOI wafer in one step. This simplifies the multi-step tolerance accumulation of LED mounting, CMOS mounting, and optical component alignment in traditional solutions into a single alignment. It achieves high-precision passive alignment and coupling between the LED light source and the optical fiber array, and can obtain stable coupling efficiency without active alignment, thus significantly reducing packaging costs.

[0022] 3. This solution can flexibly adapt to different packaging requirements by setting two optional LED electrode configurations: same-side electrode and opposite-side electrode. The same-side electrode configuration achieves an extremely short interconnect path through flip-chip, resulting in the highest heat dissipation efficiency, which is especially suitable for high-density and ultra-high-speed modulation scenarios. The opposite-side electrode configuration achieves uniform light emission through vertical current injection and improves light extraction efficiency by reducing the shading of the upper surface electrode. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure for forming the optical fiber guide groove array in this invention; Figure 2This is a schematic diagram of the structure for fabricating the beam shaping structure in this invention; Figure 3 This is a schematic diagram of the structure of the LED array chip in this invention; Figure 4 This is a schematic diagram of the CMOS driver chip in this invention; Figure 5 This is a schematic diagram of the structure in this invention for bonding LED array chips to a CMOS driver chip; Figure 5A This is a schematic diagram of the structure for assembling the non-planar electrodes in this invention; Figure 6 This is a schematic diagram of the structure in this invention where stacked LED array chips and CMOS driver chips are bonded to a silicon wafer.

[0024] Icon labels: 10-Silicon wafer; 11-Fiber optic guide groove array; 12-Reflective groove; 13-Fiber optic array; 14-Light blocking surface; 20-LED array chip; 21-Light emitting unit; 22-P electrode; 23-N electrode; 30-CMOS driver chip; 31-Pad; 32-Through silicon via; 33-Bonding layer; 40-Micro metal bump; 50-Microlens array. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Example 1

[0027] like Figure 1 As shown, this embodiment provides a method for manufacturing a stacked package structure of an LED array and a CMOS driver chip 30, including the following steps: A silicon wafer 10 is provided, and an array of fiber guide grooves 11 is formed in the top silicon layer of the silicon wafer 10; Reference Figure 1 As shown, specifically, a silicon wafer 10 is provided. The silicon wafer 10 is composed of a top silicon layer, a buried oxide layer, and a bottom silicon layer.

[0028] A 200 nm silicon nitride hard mask layer was deposited on the upper surface of silicon wafer 10 using plasma-enhanced chemical vapor deposition (PECVD). Photoresist was spin-coated, and the pattern for the fiber guide groove array 11 (12 rectangular windows, 130 μm wide, 5 mm long, with an adjacent center-to-center distance of 250 μm) was defined by photolithography. Reactive ion etching (RIE) was used to remove the silicon nitride in the window areas, exposing the top silicon surface.

[0029] A patterned silicon nitride hard mask was used as the etching mask, and deep reactive ion etching (DRIE) was employed on the top silicon layer to an etching depth of 130 μm. A buried oxide layer was used as the etching stop layer, automatically stopping the etching process when the buried oxide layer was reached. After etching, the groove cross-section was trapezoidal, with a top width of 130 μm, a bottom width of 110 μm, and an angle of less than 5° between the sidewalls and the vertical direction. Using the buried oxide layer as the DRIE etching stop layer in this step allows for precise control of the etching depth of each channel groove to within 130 μm ± 0.5 μm, ensuring that the bottom surfaces of all grooves in the fiber guide groove array 11 are on the same horizontal plane. This avoids inconsistent fiber end-face heights due to inconsistent groove depths, which could affect the consistency of coupling efficiency. Residual silicon nitride was removed, and the area was cleaned and dried to form the fiber guide groove array 11.

[0030] A beam shaping structure is fabricated on the bottom layer of the silicon wafer 10, and the beam shaping structure is vertically aligned with the fiber guide groove array 11 in the thickness direction of the silicon wafer 10 by double-sided photolithography. Reference Figure 2 As shown, specifically, an opaque mask pattern is formed on the lower surface of the silicon wafer 10. Specifically, a 200nm thick chromium / gold stack is deposited on the lower surface of the silicon wafer using magnetron sputtering as the opaque mask layer. Using the pattern of the front fiber guide groove array 11 as alignment marks, a double-sided lithography machine is used for back-side alignment exposure, ensuring precise vertical alignment between the lithographic pattern on the lower surface and the groove array on the front surface. Through lithography and etching processes, the opening regions of V-shaped reflective grooves 12 are defined on the opaque mask layer, ensuring that the mask layer between two adjacent V-shaped reflective grooves 12 is completely preserved.

[0031] After alignment, beam shaping structures are sequentially fabricated on the lower surface of silicon wafer 10, including: refer to Figure 6 As shown, the microlens array 50 is formed as follows: a spherical photoresist pattern is formed on the lower surface of the silicon wafer 10 using grayscale photolithography or photoresist thermal melting. The pattern is then transferred to the underlying silicon surface via RIE (Radio Interchange Electrode), forming a convex microlens array 50, which corresponds one-to-one with each light-emitting unit 21 for collimating or focusing the emitted light. Through the synergistic effect of the beam shaping structure and the microlens array 50, efficient coupling of the large divergence angle LED beam to the fiber array 13 is achieved.

[0032] Formation of the reflective groove 12: Below the microlens array 50, near the light-emitting part of the LED array chip 20, a V-shaped reflective groove 12 is formed by anisotropic wet etching (potassium hydroxide, concentration 30%, temperature 80℃). Utilizing the difference in etching rate between the (100) and (111) crystal planes of silicon, a V-shaped groove with a 54.7° slope is naturally formed. Sputtering a reflective metal layer on the groove surface of the V-shaped groove: First, 20nm titanium is sputtered as an adhesion layer, and then 200nm gold is sputtered as a reflective layer.

[0033] The cross-sectional width of the V-shaped reflector gradually decreases from the lower surface to the upper surface of the silicon wafer 10, making the reflective surface tilted towards the LED array core 20. When the large divergence angle beam emitted from the LED light-emitting unit 21 is incident on this tilted reflective surface, its divergence angle is compressed while being reflected and focused, and the propagation direction of the reflected beam changes to vertically upward, thereby achieving mode field matching from the large-area divergent light source to the small-diameter fiber end face.

[0034] refer to Figure 2 and Figure 6 As shown, in the photolithography step of forming the V-shaped reflective groove 12, the mask layer between two adjacent V-shaped reflective grooves 12 is retained without removal. This retained mask area forms a light-blocking surface 14 between adjacent light-emitting units during subsequent etching. The light-blocking surface 14 is located between the light-emitting side of the LED light-emitting unit 21 and the fiber guide groove 11, laterally separating two adjacent independent optical path channels. The LED light-emitting unit 21 has a large light divergence angle, and some stray light will propagate laterally and obliquely to adjacent optical path channels. The light-blocking surface 14 can directly intercept such scattered stray light, blocking the transmission path of stray light into the fiber guide groove 11 of non-corresponding channels, avoiding optical crosstalk between different light-emitting channels, and ensuring independent optical signal transmission for each channel. Alternatively, the above etching process can also be formed using dry etching.

[0035] It should be noted that in other embodiments, the reflective groove 12 may also be U-shaped, and the reflective metal layer may be any one of tungsten, tungsten silicide, titanium / gold stack, aluminum layer, or silver layer. For materials such as gold, silver, and aluminum, the reflective layer may be formed directly on the surface of the reflective groove by magnetron sputtering. For tungsten or tungsten silicide, chemical vapor deposition (CVD) may be used to form the reflective layer to ensure good step coverage and adhesion.

[0036] Through the above steps, the beam shaping structure (microlens array 50 and reflector groove 12) and the fiber guide groove array 11 on the front side are vertically aligned in the thickness direction of the silicon wafer 10. Stray light with a large divergence angle from the LED array chip 20 is reflected and focused by the reflector groove, achieving beam shaping. After collimation by the microlens array 50, the beam is precisely coupled into the fiber array 13 in the fiber guide groove array 11.

[0037] Optical path description: Taking the upward emission of light from the LED light-emitting chip as an example, the light beam is emitted vertically upward from the LED light-emitting unit 21 and enters the bottom layer of the silicon wafer 10. It first reaches the inclined reflective surface of the V-shaped reflective groove 12. Since the reflective surface gradually decreases in size from bottom to top and faces the LED array core 20, the scattered light emitted by the LED array is reflected and focused, and the beam propagation direction remains vertically upward. At the same time, the beam divergence angle is significantly compressed, realizing beam shaping. The beam after reflection and focusing is then further collimated by the microlens array 50. Finally, the shaped beam enters vertically upward into the optical receiving end face of the optical fiber array 13 in the optical fiber guide groove of the silicon wafer 10, completing the optical coupling.

[0038] An LED array chip 20 is provided, comprising a plurality of light-emitting units 21, each of the light-emitting units 21 having electrodes; Reference Figure 3 As shown, specifically, an LED array chip 20 is provided. The LED array chip 20 is fabricated based on a gallium nitride on silicon (GaN-on-Si) epitaxial wafer. An n-GaN layer, an InGaN / GaN multi-quantum-well light-emitting layer, and a p-GaN layer are sequentially epitaxially grown on the silicon substrate. Multiple light-emitting units 21 are formed by mesa etching (MESA). Each light-emitting unit 21 is arranged in a one-dimensional linear array. The center-to-center distance between adjacent units is consistent with the spacing of the fiber guide groove array 11, which is 250 μm.

[0039] Each light-emitting unit 21 has an electrode, including an N electrode 23 and a P electrode 22. For the same-surface electrode configuration, both the P electrode 22 and the N electrode 23 are disposed on the upper surface of the light-emitting unit 21. The electrode material is titanium / gold or chromium / gold, and it is formed by electron beam evaporation deposition and photolithography etching. The size of both the P electrode 22 and the N electrode 23 is 50μm×50μm, and the spacing is 20μm.

[0040] For the non-surface electrode configuration, the P electrode 22 is located on the upper surface of the light-emitting unit 21, and the N electrode 23 is located on the lower surface (substrate side) of the light-emitting unit 21. The lower surface N electrode 23 is a metal layer (Ti / Au) covering the bottom of the entire light-emitting unit 21, which is used to electrically connect with the corresponding pad 31 of the CMOS driver chip 30.

[0041] A CMOS driver chip 30 is provided, which integrates a driver circuit array and a through-silicon via 32. The CMOS driver chip 30 has pads 31 that correspond one-to-one with each of the electrodes. refer to Figure 4As shown, specifically, a CMOS driver chip 30 is provided. The CMOS driver chip 30 is manufactured using standard CMOS technology and integrates a driver circuit array. The driver circuit array consists of multiple driver units, each of which corresponds to a light-emitting unit 21 of the LED array chip 20 and is used to independently control the switching, brightness, and modulation rate of the corresponding light-emitting unit 21.

[0042] The upper surface of the CMOS driver chip 30 is provided with pads 31 that correspond one-to-one with the electrodes of each light-emitting unit 21. The pads 31 are made of aluminum or copper, and the spacing between the pads 31 is consistent with the electrode spacing of the LED array chip 20, so as to facilitate subsequent vertical interconnection.

[0043] The CMOS driver chip 30 also integrates a through-silicon via (TSV) 32. The TSV 32 penetrates the substrate of the CMOS driver chip 30, and its fabrication process is as follows: the TSV is formed using Bosch deep reactive ion etching (DRIE) with a diameter of 10 μm and a depth of 100~200 μm; a SiO2 insulating layer (0.5 μm thick) is deposited on the inner wall of the TSV; a Ti / Cu seed layer is sputtered; copper is electroplated to fill the TSV; and excess copper on the surface is removed by chemical mechanical polishing, so that the upper end of the TSV 32 is electrically connected to the pad 31, and the lower end is exposed on the back side of the CMOS driver chip 30, which is used to fan out the drive signals or power / ground signals from the front side to the back side of the chip.

[0044] The back of the CMOS driver chip 30 also has system-level I / O interconnect pads 31 (such as a solder ball array) for electrical connection with subsequent system-level interconnect layers or packaging substrates. The specific fabrication process of the system-level I / O interconnect pads 31 is as follows: a Ti / Cu seed layer is sputtered on the back of the CMOS driver chip 30, and metal pads 31 electrically connected to the lower end of the through-silicon via 32 are formed by photolithography and electroplating. The material of the pads 31 is copper or nickel / gold multilayer, the diameter of the pads 31 is 50~100μm, and the pitch of the pads 31 is 100~200μm; solder paste is printed or solder balls are placed on the surface of the pads 31, and a solder ball array is formed by reflow soldering. The solder ball material is tin-silver-copper (SAC) or tin-lead, and the diameter of the solder balls is 80~150μm.

[0045] In other embodiments, the filling material for the through-silicon via 32 may also be at least one of aluminum, nickel, tungsten, and doped polycrystalline silicon.

[0046] The LED array chip 20 and the CMOS driver chip 30 are stacked in a vertical direction, and stacked interconnection is achieved by low temperature bonding and a vertical interconnection structure located between the two. refer to Figure 5As shown, specifically, the LED array chip 20 and the CMOS driver chip 30 are placed in a bonding device, and an optical alignment system is used to align the electrodes of each light-emitting unit 21 of the LED array chip 20 with the corresponding pads 31 on the upper surface of the CMOS driver chip 30. The alignment accuracy is controlled within ±1μm.

[0047] Depending on the electrode configuration of the LED array chip 20, different stacking interconnection methods are adopted: Configuration 1: Coplanar Electrodes refer to Figure 5 As shown, for the LED array chip 20 where both P electrode 22 and N electrode 23 are located on the upper surface of the light-emitting unit 21, the LED array chip 20 is flip-chip mounted above the CMOS driver chip 30, so that the upper surface electrode of the LED array chip 20 is face-to-face with the corresponding pad 31 of the CMOS driver chip 30. A vertical interconnect structure is formed between the upper surface electrode and the corresponding pad 31 to achieve electrical connection.

[0048] Configuration 2: Off-plane electrodes

[0049] refer to Figure 5A As shown, for the LED array chip 20 with P electrode 22 located on the upper surface of the light-emitting unit 21 and N electrode 23 located on the lower surface of the light-emitting unit 21, the LED array chip 20 is disposed above the CMOS driver chip 30 with its front facing upwards, so that the N electrode 23 on the lower surface of the LED array chip 20 is electrically connected to the corresponding pad 31 of the CMOS driver chip 30 through a vertical interconnect structure; the P electrode 22 on the upper surface of the LED array chip 20 is connected to the upper system-level interconnect layer through a first conductive via that subsequently penetrates the LED array chip 20 or the dielectric layer.

[0050] Compared to the scheme where P electrode 22 and N electrode 23 are arranged side by side on the upper surface in the same-surface electrode configuration, the opposite-surface electrode configuration has the following advantages: N electrode 23 covers the entire bottom of the light-emitting unit 21, and P electrode 22 is set on the upper surface. The current passes vertically through the entire epitaxial layer structure in the longitudinal direction, and the current distribution is more uniform. This can effectively avoid the current congestion effect caused by the lateral current flow in the same-surface electrode and improve the light emission uniformity of each area of ​​the light-emitting unit 21. The N electrode 23 on the lower surface also serves as a reflective layer, which can reflect the downward emitted light upward, while only the P electrode 22 with a smaller area needs to be set on the upper surface, which reduces the obstruction of the light-emitting surface and helps to improve the light extraction efficiency.

[0051] The vertical interconnect structure can be formed in any of the following ways: Microbump bonding: Microbumps, such as AuSn, CuSn solder bumps, with a diameter of 10~50μm, are fabricated on the electrodes of the LED array chip 20 or the pads 31 of the CMOS driver chip 30. The microbumps electrically connect the electrodes to the corresponding pads 31 through thermo-press bonding.

[0052] Hybrid bonding: Cu / SiO2 hybrid bonding interfaces are fabricated on the electrodes of the LED array chip 20 and the pads 31 of the CMOS driver chip 30, respectively. Electrical and mechanical connections are achieved simultaneously through Cu-Cu hot-press bonding and SiO2-SiO2 fusion bonding.

[0053] Selective growth: The LED array chip 20 and the CMOS driver chip 30 are placed opposite each other, forming a gap of 1~10μm between the electrodes and the corresponding pads 31. The component is immersed in a chemical plating solution (copper sulfate or nickel sulfate solution), and metal (such as copper or nickel) is selectively deposited on the metal surfaces of the electrodes and pads 31, allowing the metal to grow from the two electrode surfaces towards each other, ultimately forming micro-metal bumps 40 in situ within the gap. This method eliminates the need for external solder, allows interconnection to be completed at low temperatures, and avoids damage to LED luminous efficiency and CMOS circuit performance caused by high temperatures.

[0054] During the low-temperature bonding process, heating and pressurization enable the vertical interconnect structure to form a reliable metallurgical bond with the electrode and pad 31, while simultaneously achieving mechanical fixation between the LED array chip 20 and the CMOS driver chip 30.

[0055] In this embodiment, the bonding temperature is controlled at 200~250°C, and the bonding pressure is 10~30MPa. Low-temperature bonding avoids the adverse effects of high temperatures on LED luminous efficiency and CMOS circuit performance.

[0056] After stacking, the LED array chip 20 and the CMOS driver chip 30 are connected by a vertical interconnect structure to achieve a one-to-one electrical connection between each light-emitting unit 21 and the corresponding driving channel in the driving circuit array, and each light-emitting unit 21 can be driven independently.

[0057] The stacked LED array chip 20 and the CMOS driver chip 30 are bonded to the front side of the silicon wafer 10, so that the light outlet of the LED array chip 20 is aligned with the optical fiber guide groove array 11 in the vertical direction via the silicon wafer 10. refer to Figure 6As shown, specifically, a bonding dielectric layer is spin-coated on the front side of the silicon wafer 10. The bonding dielectric layer material is benzocyclobutene (BCB) or high-density silicon oxide, with a thickness of 1~5μm. The stacked LED-CMOS structure is placed on top of the front side of the silicon wafer 10. Optical alignment marks are formed on the front side of the silicon wafer 10 using a double-sided photolithography process, aligning the light-emitting ports of each light-emitting unit 21 of the LED array chip 20 with the fiber guide groove array 11 in the top silicon layer of the silicon wafer 10 in the vertical direction. The alignment accuracy is controlled within ±1μm.

[0058] It should be noted that in this embodiment, the LED array chip 20 is bonded to the front side of the silicon wafer 10 (i.e., the side opposite to the lower surface where the beam shaping structure is located). Bonding the light-emitting surface of the LED array chip to one side of the beam shaping structure of the silicon wafer means that the light-emitting surface of the LED array chip 20 is bonded to the front side of the silicon wafer 10. At this time, the light-emitting surface of the LED array chip 20 faces the front side of the silicon wafer 10. The light beam enters the interior of the silicon wafer 10 through the front side, is reflected and focused by the underlying beam shaping structure, and is then aligned and coupled with the fiber array 13 in the fiber guide groove array 11.

[0059] After alignment, the LED-CMOS stacked structure is pressed onto the front side of silicon wafer 10 using thermocompression bonding at a temperature of 150~250°C and a bonding pressure of 10~30MPa. During bonding, the bonding dielectric layer solidifies, firmly fixing the LED-CMOS stacked structure onto the front side of silicon wafer 10. The bonding temperature of 150~250°C is selected to avoid adverse effects of high temperatures on LED luminous efficiency and the performance of CMOS driver chip 30.

[0060] After bonding, the light outlet of the LED array chip 20 is aligned vertically with the fiber guide groove array 11 in the silicon wafer 10. That is, after the light emitted by the light-emitting unit 21 enters the silicon wafer 10 vertically downward, it is focused and aligned by the bottom beam shaping structure (V-shaped reflector groove 12 → microlens array 50). Its light outlet position coincides with the fiber end face position in the fiber guide groove array 11, thereby realizing the precise coupling of the optical signal from the LED to the fiber array 13.

[0061] The fiber array 13 is placed into the fiber guide groove array 11, so that the optical receiving end of the fiber array 13 is aligned and coupled with the light output port of the beam shaping structure.

[0062] refer to Figure 6 As shown, specifically, a ribbon fiber array 13 is provided, such as a 12-core single-mode fiber with a cladding diameter of 125μm and a center-to-center distance of 250μm between adjacent fibers, which matches the center-to-center distance of the fiber guide groove array 11.

[0063] The fiber array 13 is inserted one by one into the fiber guide groove array 11. The cross-section of the fiber guide groove array 11 is trapezoidal, with a top width of 130 μm and a bottom width of 110 μm, slightly larger than the fiber diameter of 125 μm, allowing the fiber to be inserted smoothly, while leaving a gap of about 2.5~10 μm on both sides. After the fiber is inserted, the bottom of the fiber contacts the bottom of the groove, and the top of the fiber is about 5 μm lower than the upper surface of the silicon wafer 10. Since the angle between the sidewall of the groove and the vertical direction is less than 5°, the fiber is precisely limited in both the lateral and depth directions within the groove, achieving passive alignment coupling between the fiber array 13 and the light outlet of the beam shaping structure without active alignment.

[0064] The position of the optical receiving end face of the fiber array 13 is precisely defined by the mechanical positioning of the fiber guide groove array 11—when the fiber end face abuts against the positioning surface at the end of the groove, the fiber end face is exactly at the focal point of the light outlet of the beam shaping structure. At this time, the light emitted from the LED array core 20 is focused and collimated by the beam shaping structure (V-shaped reflector 12 → microlens array 50) and precisely coupled into the optical receiving end face of the fiber array 13.

[0065] After the optical fiber is inserted, UV-curable or thermosetting adhesive, such as refractive index matching adhesive with a refractive index of approximately 1.51, is filled into the fiber guide groove. The adhesive is then cured by UV irradiation or heating, fixing the fiber array 13 within the groove. The fiber end face position is precisely defined by the mechanical positioning of the groove, achieving stable optical coupling efficiency without the need for active alignment.

[0066] This invention also proposes a stacked packaging structure for LED arrays and fiber optic arrays, in which only the LED array chips 20 are directly bonded to the front side of the silicon wafer 10, without including the stacking and integration of the CMOS driver chip 30, comprising: A silicon wafer 10 has an optical fiber guide groove array 11 disposed in its top silicon layer and a beam shaping structure disposed in its bottom layer. The beam shaping structure is perpendicularly aligned with the optical fiber guide groove array 11. LED array chip 20 includes multiple light-emitting units 21, each of which is provided with an electrode. The light-emitting surface of the light-emitting unit 21 in the LED array chip 30 is bonded to the side of the beam shaping structure close to the silicon wafer 10, and each of the light-emitting units 21 is respectively opposite to the corresponding beam shaping structure and the fiber guide groove array 11 in the vertical direction. An optical fiber array 13 is disposed in the optical fiber guide groove array 11, and the optical receiving end of the optical fiber array 13 is aligned and coupled with the light output port of the beam shaping structure.

[0067] This structure, which does not contain a driver chip, has the following advantages: First, the packaging process is significantly simplified, eliminating the stacking and bonding and vertical interconnection processes between the LED array chip 20 and the CMOS driver chip 30, avoiding warpage and stress problems caused by thermal mismatch, and improving packaging yield. Second, the package thickness is significantly reduced. Without the thickness contribution of the CMOS driver chip 30, the total package thickness can be reduced by 30% to 50%, meeting the requirements of ultra-thin integration. Third, the driving method is flexible. The electrodes of the LED array chip 20 are directly exposed on the surface of the package structure, allowing for connection via wire bonding. The discrete driver chip connected to the PCB can also be interconnected with the system-level driver module through a flexible circuit board, adapting to various application scenarios; fourth, the optical alignment accuracy is not affected. The core optical architecture is completely consistent with the solution containing the driver chip, and the alignment accuracy can also reach within ±1μm. Efficient optical coupling can be achieved without active alignment; fifth, the heat dissipation path is shorter. The LED array chip 20 is directly mounted on the front side of the silicon wafer 10. Heat can be directly conducted downward through the bulk silicon of the silicon wafer 10 without passing through the intermediate thermal resistance layer of the CMOS driver chip 30, which can effectively reduce the junction temperature and improve long-term reliability.

[0068] The present invention also proposes a stacked packaging structure of an LED array and a CMOS driver chip 30, comprising: A silicon wafer 10 has an optical fiber guide groove array 11 disposed in its top silicon layer and a beam shaping structure disposed in its bottom layer. The beam shaping structure is perpendicularly aligned with the optical fiber guide groove array 11. LED array chip 20 includes multiple light-emitting units 21, each of which is provided with an electrode. The light-emitting surface of the light-emitting unit 21 in the LED array chip 30 is bonded to the side of the beam shaping structure close to the silicon wafer 10, and each of the light-emitting units 21 is respectively opposite to the corresponding beam shaping structure and the fiber guide groove array 11 in the vertical direction. A CMOS driver chip 30 is bonded to the LED array chip 20 above or below the LED array chip 20 along the vertical direction of the LED array chip 20. It integrates a driver circuit array and a through-silicon via 32. The CMOS driver chip 30 is provided with pads 31 that correspond one-to-one with each of the electrodes. A vertical interconnect structure is disposed between the LED array chip 20 and the CMOS driver chip 30, for electrically connecting each electrode to the corresponding pad 31; An optical fiber array 13 is disposed in the optical fiber guide groove array 11, and the optical receiving end of the optical fiber array 13 is aligned and coupled with the light output port of the beam shaping structure.

[0069] Example 2

[0070] The difference between this embodiment and Embodiment 1 is that the reflective groove in the beam shaping structure uses a curved reflective groove array instead of the V-shaped planar reflective groove 12 in Embodiment 1. The reflecting surface of the curved reflective groove is a non-planar curved surface (part of a parabola or ellipsoid), which can simultaneously achieve the dual functions of optical path deflection and beam focusing in a single structure, eliminating the need to fabricate a separate microlens array 50 and simplifying the manufacturing process of the beam shaping structure. The remaining steps are the same as in Embodiment 1, and therefore will not be repeated here.

[0071] Taking the upward emission of light from the LED array core 20 as an example, the light beam is emitted vertically upward from the LED light-emitting unit 21 with a large divergence angle, and reaches the concave reflective surface of the V-shaped curved reflective groove. Since the concave reflective surface is part of a parabola or ellipsoid, the LED light-emitting unit 21 is located near the focal point of the parabola or one focal point of the ellipsoid. After being reflected by the concave reflective surface, the divergent light beam is focused and collimated by a single reflection. The beam propagation direction remains vertically upward, and the divergence angle is compressed to meet the requirements of the optical fiber receiving numerical aperture. The shaped light beam directly enters the optical receiving end face of the optical fiber array 13 in the optical fiber guide groove vertically upward, completing the optical coupling.

[0072] The V-shaped curved surface reflector utilizes the geometric characteristics of a non-planar curved surface to simultaneously perform the dual functions of a V-shaped reflector and a microlens array in a single element. This eliminates the need to fabricate a separate microlens array 50, simplifies the process steps and alignment times of the beam shaping structure, and reduces manufacturing costs.

[0073] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, such as the combination of technical features between embodiments, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for manufacturing a stacked package structure of an LED array and a CMOS driver chip, characterized in that, Includes the following steps: A silicon wafer is provided, and an array of fiber guide grooves is formed in the top silicon layer of the silicon wafer; A beam shaping structure is fabricated on the bottom layer of the silicon wafer, and the beam shaping structure and the fiber guide groove array are vertically aligned in the thickness direction of the silicon wafer using a double-sided photolithography process. An LED array chip is provided, comprising multiple light-emitting units, each of which has an electrode; A CMOS driver chip is provided, and the LED array chip is stacked with the CMOS driver chip in a vertical direction, and stacked interconnection is achieved by bonding and a vertical interconnection structure located between the two. The stacked LED array chip and the CMOS driver chip are bonded to one side of the beam shaping structure of the silicon wafer with the light-emitting surface of the LED array chip, so that the light-emitting port of the LED array chip is aligned with the fiber guide groove array in the vertical direction via the silicon wafer. The fiber array is placed into the fiber guide groove array, so that the optical receiving end of the fiber array is aligned and coupled with the light output port of the beam shaping structure.

2. The manufacturing method as described in claim 1, characterized in that, The steps for forming the fiber guide groove array include: A silicon wafer is provided, which consists of a top silicon layer, a buried oxide layer and a bottom silicon layer; A mask layer is deposited on the upper or lower surface of the silicon wafer using a chemical vapor deposition process; Using the buried oxide layer of the silicon wafer as an etching stop layer, a fiber guide groove array is formed in the top silicon layer of the silicon wafer by deep reactive ion etching. The angle between the sidewall of the fiber guide groove and the vertical direction is less than 5°.

3. The manufacturing method as described in claim 1, characterized in that, The steps for forming the beam shaping structure include: An opaque mask pattern is formed on the lower surface of the silicon wafer; A V-shaped reflective groove is formed on the lower surface of the silicon wafer using an etching process; The opening of the V-shaped reflective groove is located on the lower surface of the silicon wafer, and its bottom narrows towards the upper surface, so that the width of the V-shaped reflective groove in the longitudinal section gradually decreases from the lower surface to the upper surface. A reflective layer is formed on the reflective surface; In this process, a light-blocking surface is formed by a mask between two adjacent V-shaped reflective grooves. The light-blocking surface is used to block stray light scattered between adjacent light-emitting units.

4. The manufacturing method as described in claim 3, characterized in that, The reflective metal layer is selected from any one of the following materials: titanium / gold laminate, silver layer, aluminum layer, tungsten layer, and tungsten silicide layer.

5. The manufacturing method as described in claim 1, characterized in that, When the electrodes of each light-emitting unit of the LED array chip are respectively disposed on the upper and lower surfaces of the light-emitting unit: The lower surface electrode of the LED array chip is electrically connected to the corresponding pad of the CMOS driver chip through the vertical interconnect structure; The upper surface electrode of the LED array chip is connected to the system-level interconnect layer above through a first conductive via penetrating the LED array chip or penetrating the dielectric layer; The pads of the CMOS driver chip are connected to the system-level interconnect layer through the through-silicon vias; The upper surface electrode of the LED array chip is electrically connected to the pad of the CMOS driver chip through the system-level interconnect layer to form a complete driving circuit.

6. The manufacturing method as described in claim 1, characterized in that, The method also includes the step of fabricating a system-level interconnect layer on the back side of the silicon wafer: thinning and polishing the back side of the silicon wafer, fabricating a redistribution layer on the back side, wherein the redistribution layer is electrically connected to the driving circuit array through the through-silicon vias of the CMOS driver chip.

7. The manufacturing method as described in claim 1, characterized in that, The step of forming the beam shaping structure further includes: using an etching process to etch a V-shaped curved reflective groove array on the lower surface of the silicon wafer. The reflective surface of the V-shaped curved reflective groove array is a non-planar curved surface, and its surface shape is part of a parabola or ellipsoid, which is used to reflect and concentrate the emitted light from the LED array chip.

8. The manufacturing method as described in claim 3, characterized in that, The step of forming the beam shaping structure further includes: Microlenses corresponding to each of the light-emitting units are formed on the lower surface of the silicon wafer using a photolithography process. These microlenses are used to collimate or focus the emitted light from the LED array chips.

9. A stacked packaging structure for an LED array and a fiber optic array, characterized in that, include: A silicon wafer has an array of fiber guide grooves in its top silicon layer and a beam shaping structure in its bottom layer, wherein the beam shaping structure is perpendicularly aligned with the array of fiber guide grooves. The LED array chip includes multiple light-emitting units. The light-emitting surface of the light-emitting unit in the LED array chip is bonded to the side of the beam shaping structure closest to the silicon wafer. Each light-emitting unit is vertically opposite to the corresponding beam shaping structure and the fiber guide groove array. An optical fiber array is disposed in the optical fiber guide groove array, and the optical receiving end of the optical fiber array is aligned and coupled with the light output port of the beam shaping structure.

10. A stacked packaging structure of an LED array and a CMOS driver chip, characterized in that, include: A silicon wafer has an array of fiber guide grooves in its top silicon layer and a beam shaping structure in its bottom layer, wherein the beam shaping structure is perpendicularly aligned with the array of fiber guide grooves. The LED array chip includes multiple light-emitting units, each of which is provided with an electrode. The light-emitting surface of the light-emitting unit in the LED array chip is bonded to the side of the beam shaping structure closest to the silicon wafer. Each of the light-emitting units is vertically opposite to the corresponding beam shaping structure and the fiber guide groove array. A CMOS driver chip is bonded above or below the LED array chip along the vertical direction of the LED array chip. A vertical interconnect structure is disposed between the LED array chip and the CMOS driver chip, for electrically connecting each electrode to the corresponding pad; An optical fiber array is disposed in the optical fiber guide groove array, and the optical receiving end of the optical fiber array is aligned and coupled with the light output port of the beam shaping structure.

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