A method for manufacturing a bonded wafer and a bonded wafer

Abstract

The application provides a bonded wafer preparation method and bonded wafer, and relates to the technical field of semiconductor manufacturing. The method comprises the following steps: forming a dielectric film at a thin film deposition temperature on a side to be bonded of a first substrate; after the dielectric film is formed and before the first substrate is bonded with a second substrate, pre-annealing the first substrate with the dielectric film formed thereon at a pre-annealing temperature; bonding the first substrate with the second substrate to form a bonded wafer; and performing a post-bonding annealing process on the bonded wafer at a post-bonding annealing temperature. The pre-annealing temperature is higher than the thin film deposition temperature, and the post-bonding annealing temperature is lower than the pre-annealing temperature. Through the above process, at least part of the residual gas in the dielectric film is released before wafer bonding, the accumulation of residual gas at the bonding interface during the post-bonding annealing process is reduced, and thus the formation of bubbles at the bonding interface is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a bonding wafer and the bonding wafer itself. Background Technology

[0002] Wafer bonding is one of the most commonly used processes in semiconductor manufacturing. In some wafer bonding processes, a dielectric film is formed on the side of the wafer to be bonded, and then the wafer with the dielectric film is bonded to another wafer.

[0003] During the formation of dielectric thin films, reactive gases, carrier gases, unreacted substances, or gaseous components generated during the reaction may remain inside the film. For example, when forming SiO2 or SiN thin films using plasma-enhanced chemical vapor deposition (PECVD), gaseous components such as H2 and N2 may be generated during the deposition process, and some of these gaseous components may remain inside the film.

[0004] After a wafer with a dielectric film is bonded to another wafer, the dielectric film is located near the bond interface. During subsequent heat treatment, gaseous components remaining in the dielectric film may desorb and diffuse. Because a bond interface has already formed between the wafers, the released gas is difficult to escape and tends to accumulate at the bond interface, forming bubbles. This can affect the bonding state of the bond interface and, in severe cases, may cause film peeling or device failure.

[0005] Therefore, how to reduce the accumulation of residual gas in the dielectric film at the bonding interface and the formation of bubbles during the heat treatment after wafer bonding is a technical problem that needs to be solved in the wafer bonding process. Summary of the Invention

[0006] This application provides a method for fabricating a bonding wafer, comprising: forming a dielectric film on the bonding side of a first substrate at a thin film deposition temperature; after forming the dielectric film and before bonding the first substrate with a second substrate, pre-annealing the first substrate with the dielectric film at a pre-annealing temperature; bonding the pre-annealed first substrate with the second substrate to form a bonding wafer; and heat-treating the bonding wafer at a post-bonding annealing temperature; wherein the pre-annealing temperature is higher than the thin film deposition temperature, and the post-bonding annealing temperature is lower than the pre-annealing temperature.

[0007] By performing pre-annealing after the dielectric film is formed but before the wafer bonding interface is formed, the dielectric film undergoes annealing while the bonding interface is not yet closed and gas still has an outward escape path. This allows at least some of the residual gas in the dielectric film to be released before wafer bonding. Furthermore, since the pre-annealing temperature is higher than the film deposition temperature, the dielectric film can undergo annealing conditions higher than those during the film deposition stage after formation, which is beneficial for promoting the desorption and diffusion of residual gas. At the same time, since the post-bonding annealing temperature is lower than the pre-annealing temperature, the possibility of the dielectric film continuing to release gas during subsequent post-bonding annealing processes is reduced. Thus, the release and accumulation of residual gas at the bonding interface after it is closed is reduced, thereby reducing the formation of bubbles at the bonding interface.

[0008] This application also provides a bonding wafer. The bonding wafer includes a first substrate, a second substrate, and a dielectric film located between the first substrate and the second substrate. The dielectric film is formed on the bonding side of the first substrate at a film deposition temperature; after the dielectric film is formed and before the first substrate and the second substrate are bonded, the first substrate with the dielectric film is pre-annealed; after the first substrate and the second substrate are bonded to form the bonding wafer, the bonding wafer is post-bonding annealed. The pre-annealing temperature is higher than the film deposition temperature, and the post-bonding annealing temperature is lower than the pre-annealing temperature. The area ratio of bubble defects at the bonding interface of the bonding wafer is less than or equal to 0.1%, and the bonding energy at the bonding interface is greater than or equal to 2 J / m².

[0009] Based on the above structure and fabrication process, the dielectric film undergoes pre-annealing before the bonding interface forms. The pre-annealing temperature is higher than the film deposition temperature and also higher than the subsequent post-bonding annealing temperature. This allows at least some of the residual gas in the dielectric film to be released before the bonding interface forms, thereby reducing the migration and accumulation of residual gas at the bonding interface during the subsequent post-bonding annealing process. As a result, the bonded wafer can have a lower level of bonding interface bubble defects. Attached Figure Description

[0010] Figure 1 This is a schematic flowchart illustrating a method for fabricating a bonding wafer according to some embodiments of this application.

[0011] Figure 2 This is a schematic diagram illustrating the relationship between the thin film deposition temperature, the pre-annealing temperature, and the post-bonding annealing temperature, provided for some embodiments of this application.

[0012] Figure 3 This is a schematic diagram showing the temperature relationship between the thin film deposition temperature, the pre-annealing temperature, the post-bonding annealing temperature, and 500°C for some embodiments of this application.

[0013] Figure 4 This is a schematic diagram illustrating the temperature difference relationship between adjacent process temperatures provided for some embodiments of this application.

[0014] Figure 5 This is a schematic diagram of a process flow for some embodiments of this application, in which pre-annealing is performed before chemical mechanical polishing.

[0015] Figure 6 A schematic diagram of the process flow for some embodiments of this application, in which chemical mechanical polishing is performed before pre-annealing.

[0016] Figure 7 This is a schematic diagram of the dielectric thin film material and the pre-annealing environment provided for some embodiments of this application.

[0017] Figure 8 This is a schematic diagram illustrating the wafer surface treatment and vacuum bonding process provided for some embodiments of this application.

[0018] Figure 9 This is a schematic diagram of the layer structure of the first substrate and the second substrate before wafer bonding, provided for some embodiments of this application.

[0019] Figure 10 This is a schematic diagram of the cross-sectional structure of a bonding wafer provided for some embodiments of this application.

[0020] Figure 11 This is an ultrasonic scanning microscope image of a bonded wafer obtained by directly bonding a dielectric thin film after the wafer is formed, followed by annealing after bonding.

[0021] Figure 12 This is an ultrasonic scanning microscope image of a bonded wafer obtained using the pre-annealing process after bonding and subsequent annealing. Detailed Implementation

[0022] The technical solutions in this application will now be clearly and completely described with reference to the accompanying drawings.

[0023] like Figure 1 As shown, Figure 1 This is a schematic diagram of the overall process of a bonding wafer fabrication method, used to illustrate the process connection between the first substrate 300, the second substrate 200, the dielectric thin film 301 and the bonding wafer 400, as well as the sequential relationship between dielectric thin film formation, pre-annealing treatment, wafer bonding and post-bonding annealing treatment.

[0024] The first substrate 300 and the second substrate 200 are two wafer objects for subsequent wafer bonding. The first substrate 300 has a bonding side, and a dielectric thin film 301 is formed on the bonding side of the first substrate 300. The second substrate 200 is disposed opposite to the first substrate 300 during the wafer bonding stage, and together with the first substrate 300, they form a bonded wafer 400.

[0025] In this context, the bonding side refers to the side of a wafer that faces another wafer during subsequent wafer bonding and participates in forming the wafer bonding interface. For the first substrate 300, the bonding side is also the location where the dielectric thin film 301 is formed.

[0026] The bonding surface of the second substrate 200 is the exposed surface of the second substrate 200 that contacts the dielectric film 301 during bonding. When an oxide layer is formed on the side of the second substrate 200 facing the first substrate 300, the surface of the oxide layer facing away from the second substrate 200 constitutes the bonding surface of the second substrate 200.

[0027] The dielectric thin film 301 is a film layer formed on the bonding side of the first substrate 300 by a thin film deposition process. The dielectric thin film 301 is not limited to a specific deposition method; any film layer that may introduce or generate gaseous components during deposition and remain that can be released during subsequent heat treatment can be used as a dielectric thin film. Figure 1 The object being processed in the method shown. The dielectric thin film 301 includes SiO2, SiN, or other films formed based on PECVD technology, or other films in which residual gas components are introduced or generated during the deposition process.

[0028] When a dielectric thin film 301 is formed on the bonding side of the first substrate 300, a corresponding thin film deposition temperature is specified. The thin film deposition temperature is the process temperature corresponding to the deposition process of forming the dielectric thin film 301, used to characterize the thermal conditions experienced during the formation stage of the dielectric thin film 301. The thin film deposition temperature serves as a process temperature parameter for comparing the temperature relationship between the deposition stage and subsequent heat treatment stages.

[0029] After the dielectric film 301 is formed, the first substrate 300 is subjected to a pre-annealing process. The pre-annealing process occurs after the dielectric film 301 is formed and before the first substrate 300 and the second substrate 200 are wafer bonded.

[0030] The pre-annealing process is a heat treatment performed on the first substrate 300 on which the dielectric film 301 is formed, after the dielectric film 301 is formed but before the wafer bonding interface is sealed. "Before bonding" defines the time position of the heat treatment relative to wafer bonding, while "pre-annealing" distinguishes it from heat treatment performed after wafer bonding is complete. The process temperature corresponding to the pre-annealing process is the pre-annealing temperature.

[0031] After the pre-annealing process, the first substrate 300 and the second substrate 200 are wafer bonded. During the wafer bonding process, the bonding side of the first substrate 300 faces the bonding surface of the second substrate 200, and the two come into contact with each other to form a bonded wafer 400.

[0032] The bonding wafer 400 is a combined structure formed after the first substrate 300 and the second substrate 200 are bonded together. The bonding wafer 400 is used as the object for subsequent heat treatment.

[0033] After the bonding wafer 400 is formed, a post-bonding annealing process is performed on the bonding wafer 400. The post-bonding annealing process is a heat treatment performed on the bonding wafer 400 after the first substrate 300 and the second substrate 200 have completed wafer bonding; the corresponding process temperature for the post-bonding annealing process is the temperature of the post-bonding annealing process.

[0034] The pre-annealing temperature is higher than the thin film deposition temperature, and the post-bonding annealing temperature is lower than the pre-annealing temperature. This temperature relationship is used to define the relative thermal conditions between the dielectric thin film formation stage, the pre-annealing stage, and the post-bonding annealing stage.

[0035] During the formation of the dielectric thin film 301, gaseous components introduced by reactant gases, carrier gases, unreacted substances, or gaseous byproducts may remain inside the film. Before wafer bonding is completed, the dielectric thin film 301 is not yet in a closed wafer bonding interface; therefore, gases released during the pre-annealing process still have pathways to escape to the external environment. By performing heat treatment at this stage, at least some of the gaseous components that could be released during subsequent heating can be desorbed from the interior of the dielectric thin film 301 and migrate outward in advance. For specific films formed by PECVD, existing materials document the formation or retention of gaseous components such as H2 and N2 during deposition, as well as the desorption and diffusion of these gases during subsequent heating.

[0036] After the first substrate 300 and the second substrate 200 are wafer bonded, the gas venting conditions in the region where the dielectric film 301 is located change. If the residual gas is mainly released from the dielectric film 301 after wafer bonding is completed, the released gas tends to accumulate near the closed bonding interface, thereby forming bubbles. Since gas is difficult to effectively vent after wafer bonding, the high-temperature treatment after bonding cannot replace the pre-annealing treatment that occurs before wafer bonding.

[0037] When the pre-annealing temperature is higher than the thin film deposition temperature, the dielectric thin film 301 experiences thermal conditions higher than those of the thin film deposition stage after its formation, allowing at least some residual gas to desorb, diffuse, and migrate outward before wafer bonding. Furthermore, when the post-bonding annealing temperature is lower than the pre-annealing temperature, the dielectric thin film 301 experiences thermal conditions higher than those of the subsequent post-bonding annealing stage before the wafer bonding interface is sealed, allowing some gas that might be released in subsequent heat treatment stages to be released earlier. This reduces the likelihood of the dielectric thin film 301 continuing to release large amounts of gas and accumulating near the interface even after the bonding interface has been sealed.

[0038] It is understandable that the temperature of the post-bonding annealing treatment can also be set higher than the film deposition temperature, so that the post-bonding annealing treatment constitutes a subsequent heat treatment stage at a higher temperature relative to the formation stage of the dielectric film 301. In this embodiment, the temperature of the pre-annealing treatment, the temperature of the post-bonding annealing treatment, and the film deposition temperature further form a three-level temperature relationship.

[0039] therefore, Figure 1 The illustrated process, through the sequence of forming a dielectric film, pre-annealing, wafer bonding, and post-bonding annealing, and the temperature relationship between the three stages, ensures that the dielectric film 301 undergoes a high-temperature pre-annealing process before the bonding interface is sealed. This allows gases that can be released in advance to be released in a stage where there is still a path to escape, thereby reducing the possibility of residual gases in the dielectric film precipitating and forming bubbles at the bonding interface during the post-bonding annealing process.

[0040] like Figure 2 As shown, Figure 2 The thin film deposition temperature during the bonding wafer fabrication process is shown. Temperature of pre-annealing treatment and the temperature of post-bonding annealing The correspondence between the thin film deposition stage and its corresponding process stage is shown. The stages are sequentially illustrated along the process stage direction: thin film deposition, pre-annealing, wafer bonding, and post-bonding annealing. The thin film deposition stage corresponds to… The pre-annealing stage corresponds to The post-bonding annealing process corresponds to .

[0041] exist Figure 2 In the corresponding implementation, the following temperature relationship is satisfied between the three process stages:

[0042] in, Indicates the thin film deposition temperature. Indicates the temperature of the pre-annealing treatment. This indicates the temperature at which the bonding process is annealed.

[0043] Figure 2 The horizontal axis represents the process stage, not the actual duration of each stage; the vertical axis represents temperature. Black dots represent the temperature level corresponding to the respective process stage, and horizontal and vertical dashed lines are used to help illustrate the correspondence between temperature levels and process stages.

[0044] like Figure 3 As shown, in Figure 2 Based on the temperature relationships shown, the temperature for post-bonding annealing is... The film deposition temperature was further set to above 500°C. It was further set to below 500°C. This was combined with the temperature of the pre-annealing treatment. Temperature higher than the post-bonding annealing treatment The relationship is formed as follows:

[0045] Figure 3 exist and A horizontal dashed line at 500℃ is placed between the two process temperatures to indicate the positional relationship of 500℃ relative to the two process temperatures. The corresponding temperature point is above 500℃. The corresponding temperature point is below 500℃. Therefore, 500℃ is used to further distinguish the temperature range corresponding to the thin film deposition stage and the post-bonding annealing stage.

[0046] exist Figure 3 In the illustrated embodiment, thin film deposition is performed at temperatures below 500°C, while the heat treatment following wafer bonding is performed at temperatures above 500°C. This is due to the temperature of the pre-annealing process. Further above the temperature of post-bonding annealing. Therefore, the temperature at which the first substrate with the dielectric thin film undergoes pre-annealing before the bonding interface is formed is higher than the temperature at which the subsequent bonding wafer undergoes post-bonding annealing at temperatures above 500°C.

[0047] Furthermore, the post-bonding annealing time for the bonded wafer 400 is set to be greater than 1 hour. The post-bonding annealing is performed after the first substrate 300 and the second substrate 200 have formed an initial bond, so that the bonding interface 401 can further form an interface bond under the corresponding temperature and processing time conditions.

[0048] pass Figure 3The temperature levels shown allow the dielectric film to undergo thermal conditions at a temperature higher than that of the subsequent annealing treatment before wafer bonding. This helps to release at least some of the residual gas that could be released under the subsequent high-temperature conditions before the bonding interface is formed, reducing the accumulation of residual gas near the closed bonding interface during the reheating process after bonding.

[0049] For the verification results regarding the post-bonding annealing temperature around 500°C, please refer to Reference Example 4, Example 6 and Example 7 described below.

[0050] like Figure 4 As shown, in Figure 2 The thin film deposition temperature shown Temperature of pre-annealing treatment and the temperature of post-bonding annealing Based on the relative relationship, the temperature difference between two adjacent process temperatures is further limited.

[0051] Figure 4 middle, Indicates the temperature of the pre-annealing treatment Temperature of post-bonding annealing The temperature difference between them can be expressed as:

[0052] Indicates the temperature of the post-bonding annealing process. With thin film deposition temperature The temperature difference between them can be expressed as:

[0053] exist Figure 4 In the illustrated implementation, and Each satisfies ,as well as ;Right now ,and .

[0054] Therefore, the temperature of the pre-annealing treatment Not only higher than the temperature of post-bonding annealing Furthermore, there is a temperature difference of at least 50°C between the two; the temperature of the post-bonding annealing treatment. Not only higher than the thin film deposition temperature Moreover, there is a temperature difference of at least 50°C between the two.

[0055] For the pre-annealing stage Compared to the subsequent A temperature difference of at least 50°C allows the first substrate with the dielectric film to undergo higher heat treatment conditions before the bonding interface forms, which is beneficial for the early release of at least some of the residual gases that might be released at subsequent lower heat treatment temperatures. For the post-bonding annealing stage, Compared to A temperature difference of at least 50°C creates a distinct temperature rise condition for the post-bonding annealing stage compared to the film formation stage.

[0056] By using the two temperature difference conditions mentioned above, the dielectric film undergoes a higher heat treatment temperature than the subsequent post-bonding annealing before the bonding interface is formed. This helps to reduce the release and accumulation of residual gas near the bonding interface after wafer bonding is completed, thereby reducing the possibility of bubble formation at the bonding interface.

[0057] For the experimental verification results of the two lower limits of temperature difference mentioned above, please refer to Examples 4 to 7 and Reference Examples 3 and 4 described below.

[0058] like Figure 5 As shown, Figure 5 The diagram illustrates the process by which the first substrate 300 undergoes pre-annealing, chemical mechanical polishing, and wafer bonding after the formation of the dielectric thin film 301. This process is used to explain the sequential relationship between the pre-annealing and chemical mechanical polishing processes, as well as the surface state of the dielectric thin film 301 after chemical mechanical polishing.

[0059] The first substrate 300 has a bonding side, and a dielectric film 301 is formed on the bonding side of the first substrate 300. After the dielectric film 301 is formed, the first substrate 300 on which the dielectric film 301 is formed is first subjected to a pre-annealing treatment. For the specific temperature relationships of the pre-annealing treatment and the process position of the pre-annealing treatment relative to wafer bonding, please refer to [reference needed]. Figures 1 to 4 The corresponding implementation methods will not be repeated here.

[0060] After pre-annealing, the dielectric film 301 undergoes chemical mechanical polishing (CMP). CMP is a process that uses both chemical and mechanical actions to remove material and planarize the surface of the dielectric film 301. Figure 5 In the embodiment shown, CMP is performed after pre-annealing and before wafer bonding.

[0061] CMP can reduce the roughness of the surface of the dielectric film 301 to be bonded. Figure 5 In the illustrated embodiment, the profile arithmetic mean deviation of the surface roughness of the CMP-treated dielectric film 301 Less than 0.3 nm.

[0062] Among them, the arithmetic mean deviation of the profile Used to characterize the average deviation of the surface profile of dielectric film 301 from the baseline. The smaller the value, the lower the degree of microscopic undulation of the corresponding surface.

[0063] exist Figure 5 In the process sequence shown, pre-annealing is performed before CMP. Thus, at least some of the residual gas in the dielectric film 301 is released through pre-annealing before the wafer bonding interface is formed, and then the surface condition of the dielectric film 301 to be bonded is improved by CMP, followed by wafer bonding.

[0064] By adopting Figure 5 The process sequence shown allows for pre-annealing, which heats the dielectric film 301 before the bonding interface is formed, to reduce the accumulation of residual gas near the bonding interface during subsequent post-bonding annealing. Simultaneously, CMP, which follows pre-annealing, reduces the microscopic undulations of the dielectric film 301 to be bonded, enabling the dielectric film 301 after pre-annealing to obtain a surface state suitable for subsequent wafer bonding.

[0065] like Figure 6 As shown, a dielectric film 301 is formed on the bonding side of the first substrate 300. In this embodiment, after the dielectric film 301 is formed, CMP is first performed on the dielectric film 301, then the first substrate 300 on which the dielectric film 301 is formed is pre-annealed, and then wafer bonding is performed.

[0066] and Figure 5 The process sequences shown are different. Figure 6 Set CMP before the pre-annealing process. Therefore, Figure 6 The corresponding process sequence can be represented as: thin film deposition → CMP → pre-annealing → wafer bonding.

[0067] Specifically, after CMP is completed, the first substrate 300 undergoes pre-annealing. Although the order of CMP and pre-annealing is relatively... Figure 5 The process changes, but the pre-annealing process still occurs before wafer bonding. Therefore, during the pre-annealing process, a closed bonding interface has not yet been formed between the first substrate 300 and the second substrate, and at least some of the residual gas in the dielectric film 301 that can be released under the corresponding heat treatment conditions still has the potential to be discharged.

[0068] Therefore, pre-annealing can be performed either before or after CMP; as long as pre-annealing occurs before wafer bonding, gas release still occurs before the bonding interface is closed.

[0069] Figure 6 The order shown provides a comparison with Figure 5 Another parallel process organization method: first, the dielectric film 301 is subjected to CMP to obtain the corresponding surface roughness state, and then pre-annealing is performed before wafer bonding. Figure 6 The embodiments shown demonstrate that CMP and pre-annealing treatment have a certain degree of adjustability in process arrangement.

[0070] like Figure 7 As shown, the dielectric thin film can be formed by plasma-enhanced chemical vapor deposition (PECVD). PECVD activates the reactive gases involved in film formation using plasma, causing the reactive gases to react on the wafer surface and form a dielectric thin film. After forming the dielectric thin film using PECVD, the first substrate on which the dielectric thin film is formed can be pre-annealed according to the aforementioned embodiments.

[0071] Furthermore, the specific time for the pre-annealing treatment can be determined by considering the material and thickness of the dielectric film and the pre-annealing temperature (e.g., greater than 1 hour). By maintaining the appropriate treatment time at the pre-annealing temperature, sufficient time is provided for the desorption, diffusion, and outward migration of residual gases inside the dielectric film.

[0072] The dielectric thin film formed by PECVD can be a SiO2 thin film, a SiN thin film, or a SiCN thin film. For SiO2 and SiN thin films, PECVD deposition can be performed using a silicon-containing reactive gas and a corresponding oxygen- or nitrogen-containing reactive gas. For example, when forming a SiO2 thin film, SiH4 and N2O can be used as reactive gases, with a N2O to SiH4 ratio of 8:1 to 10:1; when forming a SiN thin film, SiH4 and NH3 or N2 can be used as reactive gases, with an NH3 to SiH4 ratio of 1:1 to 4:1. The thickness of the dielectric thin film formed by PECVD can be, for example, 30 nm to 3000 nm.

[0073] During PECVD film deposition, reactant gases may generate gaseous byproducts, and some unreacted gaseous components may also enter the interior of the dielectric film. For example, the formation of SiO2 films can generate gaseous components such as H2 and N2; the formation of SiN films can generate H2, and residual components such as SiH4 and NH3 may also be present. The pores and defects inside the PECVD film can provide space for these gaseous components. Therefore, performing pre-annealing after PECVD film deposition can provide thermal excitation conditions for the residual gases in the dielectric film 301, allowing at least some of the residual gases to migrate to the outside of the dielectric film 301 before wafer bonding.

[0074] like Figure 7As shown in the left branch, the pre-annealing process can be performed in an N2 atmosphere, an Ar atmosphere, a vacuum environment, or a low-pressure environment.

[0075] When N2 or Ar atmosphere is used for pre-annealing, a relatively stable pre-annealing environment is provided for the dielectric film, which is beneficial to controlling the degree of oxidation of the dielectric film during heat treatment. When vacuum or low-pressure environment is used for pre-annealing, the gas components in the dielectric film 301 can migrate to the surrounding low-pressure space, which is beneficial to the escape of residual gas from the inside of the dielectric film 301 to the outside, and at the same time, it is beneficial to reduce the introduction of new gaseous components into the dielectric film 301 by the heat treatment environment.

[0076] like Figure 7 As shown in the right-hand branch, when the dielectric film 301 is a SiO2 film, the pre-annealing treatment can also be carried out in an oxidizing atmosphere (e.g., O2 atmosphere). An oxidizing atmosphere is an atmosphere that can provide an oxidizing environment for the SiO2 film under pre-annealing conditions. Pre-annealing with an oxidizing atmosphere (e.g., O2 atmosphere) not only promotes the release of residual gases in the dielectric film 301, but also helps to repair oxygen vacancies or reduce dangling bonds in the SiO2 film, thereby adjusting the film state of the SiO2 film after pre-annealing.

[0077] Therefore, for Figure 7 The PECVD dielectric films shown can be pre-annealed in an environment that can be selected based on the dielectric film material and the corresponding process requirements. For example, SiO2 films can be pre-annealed in an environment of N2, Ar, vacuum, low pressure, or oxidizing atmosphere (e.g., O2); SiN and SiCN films can be pre-annealed in an environment of N2, Ar, vacuum, or low pressure.

[0078] Figure 7 Each pre-annealing environment can be implemented in combination with the aforementioned temperature relationship of the pre-annealing process. That is, after selecting the appropriate atmosphere, vacuum environment or low-pressure environment, the pre-annealing process is still carried out according to the temperature relationship provided in the embodiments of this application, so that the PECVD dielectric film completes the corresponding heat treatment before wafer bonding and releases at least part of the residual gas before the bonding interface is formed.

[0079] therefore, Figure 7 By further defining the PECVD thin film materials and the pre-annealing environment, a specific implementation path is formed from PECVD film formation to the selection of dielectric thin film materials and the selection of pre-annealing environment, thereby configuring corresponding pre-annealing implementation conditions for different dielectric thin film materials.

[0080] like Figure 8 As shown, Figure 8The process is shown in which the first substrate 300 and the second substrate 200 are sequentially subjected to plasma activation and hydrophilic treatment before wafer bonding, and the wafer bonding process is completed in the vacuum bonding cavity 500.

[0081] In conjunction with the aforementioned embodiments, a dielectric thin film 301 is formed on the bonding side of the first substrate 300. After completing the pre-annealing treatment and the corresponding surface treatment process, plasma activation can be performed on the bonding side of the first substrate 300 and the bonding surface of the second substrate 200.

[0082] Plasma activation utilizes plasma to act on the bonding surfaces of a wafer, thereby enhancing the reactivity of the surfaces to be bonded. The gases used in plasma activation include any one of Ar, N2, and O2, or a mixture of any two or three of these gases. Through plasma action, a highly reactive surface state is formed on the bonding surfaces, providing conditions for subsequent hydrophilic treatment and wafer contact bonding.

[0083] After plasma activation, the bonding side of the first substrate 300 and the bonding surface of the second substrate 200 are subjected to a hydrophilic treatment. This hydrophilic treatment enhances the adsorption or formation ability of the bonding surfaces for hydrophilic groups such as hydroxyl groups, enabling the formation of corresponding interfacial interactions when the bonding sides and surfaces come into contact. The combination of plasma activation and hydrophilic treatment creates an activated state rich in dangling bonds and hydroxyl groups on the bonding surfaces, allowing the first substrate 300 and the second substrate 200 to form an initial bond through van der Waals forces and hydrogen bonds upon contact.

[0084] After the hydrophilic treatment is completed, the first substrate 300 and the second substrate 200 are sent into the vacuum bonding chamber 500 for wafer bonding. The vacuum bonding chamber 500 is a processing chamber that provides a predetermined pressure environment for the first substrate 300 and the second substrate 200 and completes the contact bonding of the two wafers. Specifically, the pressure inside the vacuum bonding chamber 500 is 0.001 mbar to 1000 mbar.

[0085] Within the vacuum bonding cavity 500, the bonding side of the first substrate 300 is positioned facing the bonding surface of the second substrate 200, and the two are brought into contact. The dielectric film 301 of the bonding side of the first substrate 300 is located between the first substrate 300 and the second substrate 200. After surface activation and hydrophilic treatment, the bonding side forms an initial bond upon contact with the bonding surface, thereby forming a bonded wafer 400.

[0086] Figure 8The lower part shows the formed bonding wafer 400. The bonding wafer 400 includes a first substrate 300, a second substrate 200, and a dielectric thin film 301 located between the first substrate 300 and the second substrate 200. The first substrate 300 and the second substrate 200 are formed into a single bonding wafer 400 after wafer bonding, and then a post-bonding annealing process is performed according to the aforementioned embodiment.

[0087] use Figure 8 The surface treatment and bonding method shown include plasma activation to enhance the surface reactivity of the bonding sides and surfaces, hydrophilic treatment to further create a surface state suitable for wafer contact bonding, and a vacuum bonding cavity 500 to provide a predetermined pressure environment for the contact and bonding of the two wafers. Thus, a stable initial bond is formed based on the pre-annealing treatment, providing conditions for further strong interfacial bonding during subsequent post-bonding annealing. After room temperature contact, the wafers can form an initial bond through van der Waals forces and hydrogen bonds, followed by heat treatment to form a stronger covalent bond.

[0088] like Figure 9 As shown, Figure 9 The layer structure and relative positions of the first substrate 300 and the second substrate 200 in a specific application are shown. Figure 9 In the embodiment shown, the first substrate 300 is a support substrate and the second substrate 200 is a donor substrate.

[0089] A support substrate is a substrate that provides mechanical support for the other wafer and related film layers in a bonded wafer. A donor substrate is a substrate that is bonded to the support substrate during the bonding wafer fabrication process and can provide the basis for the corresponding wafer materials or functional layers for subsequent device structures. Figure 9 By using the parallel labeling of "first substrate / supporting substrate" and "second substrate / donor substrate", the correspondence between the first substrate 300, the second substrate 200 and the two specific substrates is established.

[0090] An oxide layer 201 is formed on the side of the second substrate 200 facing the first substrate 300. The oxide layer 201 covers the side of the second substrate 200 facing the first substrate 300 and serves as a surface film layer for the second substrate 200 to participate in subsequent wafer bonding. For example, the thickness of the oxide layer 201 can be 100 nm to 3000 nm, and it serves as a bonding layer for hydrophilic wafer bonding.

[0091] A dielectric film 301 is formed on the bonding side of the first substrate 300. The dielectric film 301 is located on the side of the first substrate 300 facing the second substrate 200. The specific film formation method and material of the dielectric film 301 adopt the embodiments provided in this application, such as forming a SiO2 film, a SiN film, or a SiCN film by PECVD. For SiO2 films and SiN films, the film thickness can be 30 nm to 3000 nm.

[0092] When the first substrate 300 is a support substrate, another oxide layer may be formed on the bonding side of the support substrate. The thickness of the other oxide layer may be, for example, 1 nm to 3000 nm, and it includes the natural oxide layer on the surface of the support substrate. A dielectric thin film 301 is further formed on the side of the oxide layer opposite to the support substrate. The oxide layer may be formed by furnace tube thermal oxidation or chemical vapor deposition; when furnace tube thermal oxidation is used to form the oxide layer, the thermal oxidation temperature is set to be higher than 800°C, for example, 900°C to 1100°C.

[0093] along Figure 9 The two arrows indicate the direction in which the oxide layer 201 faces the dielectric film 301, and the second substrate 200 is brought close to the first substrate 300. The oxide layer 201 and the dielectric film 301 thus form two opposing bonding layers. Figure 8 The corresponding surface treatment and vacuum bonding processes bring the oxide layer 201 and the dielectric film 301 into contact and form a bonding interface. Wafer bonding is then performed after surface treatment of the donor substrate-side oxide layer 201 and the support substrate-side dielectric film 301.

[0094] After wafer bonding is completed, the bonded wafer formed in this embodiment has, along the thickness direction, the following components in sequence: donor substrate, oxide layer, bonding interface, dielectric thin film 301, and support substrate.

[0095] The oxide layer 201 is located between the donor substrate and the dielectric film 301, the dielectric film 301 is located between the oxide layer 201 and the support substrate, and the bonding interface is formed at the contact position between the oxide layer 201 and the dielectric film 301.

[0096] This hierarchical relationship allows the oxide layer 201 on the donor substrate side and the dielectric film 301 on the support substrate side to directly participate in wafer bonding, thereby applying the aforementioned pre-annealing treatment of the dielectric film 301 to a specific bonding wafer structure with a donor substrate and a support substrate.

[0097] In embodiments where residual gas exists inside the dielectric film 301, the aforementioned pre-annealing treatment can be performed before the oxide layer 201 and the dielectric film 301 form a bonding interface, allowing at least a portion of the residual gas to be released before the interface is formed. After completing the corresponding surface treatment, the oxide layer 201 and the dielectric film 301 are then bonded together, thereby integrating the residual gas pretreatment process with... Figure 9 The specific layer structure combination is shown.

[0098] like Figure 10 As shown, Figure 10 The diagram shows a cross-sectional structure of a bonding wafer 400 formed after wafer bonding is completed. The bonding wafer 400 includes, along its thickness direction, a second substrate 200, an oxide layer 201, a bonding interface 401, a dielectric thin film 301, and a first substrate 300.

[0099] In this embodiment, the second substrate 200 is a donor substrate, and the first substrate 300 is a support substrate. An oxide layer 201 is formed on the side of the second substrate 200 facing the first substrate 300, and a dielectric film 301 is formed on the side of the first substrate 300 facing the second substrate 200. After the aforementioned surface treatment and wafer bonding, the oxide layer 201 and the dielectric film 301 are bonded together, forming a bonding interface 401 between them.

[0100] Among them, the bonding interface 401 is the bonding region formed after the oxide layer 201 and the dielectric film 301 are bonded together on a wafer. Figure 10 In the corresponding embodiment, the bonding interface 401 is located between the oxide layer 201 and the dielectric film 301 and extends along the lateral direction of the wafer, thereby connecting the oxide layer 201 on the side of the second substrate 200 and the dielectric film 301 on the side of the first substrate 300 into a whole.

[0101] An oxide layer is formed on the donor substrate side, and a dielectric thin film is formed on the support substrate side. After plasma activation and hydrophilic treatment, wafer bonding is performed to form a composite wafer. Thus, Figure 10 The aforementioned wafer bonding process is further implemented as a specific hierarchical structure after bonding is completed.

[0102] exist Figure 10 In the illustrated embodiment, the dielectric film 301 is located between the first substrate 300 and the bonding interface 401. The dielectric film 301 adopts the aforementioned PECVD-formed film layer embodiment, such as a SiO2 film, SiN film, or SiCN film; the specific material and film formation conditions of the dielectric film 301 can be found in [reference needed]. Figure 7 Corresponding implementation method. For SiO2 thin films and SiN thin films, the film thickness can be in the range of 30 nm to 3000 nm.

[0103] The oxide layer 201 is located between the second substrate 200 and the bonding interface 401. Figure 9 In the corresponding embodiment, the oxide layer 201 serves as a donor substrate-side film layer participating in the hydrophilic wafer bonding. Thus, a bonding interface 401 is formed between the two treated layers to be bonded, so that the oxide layer 201 and the dielectric film 301 together constitute the interface structure inside the bonded wafer 400.

[0104] In conjunction with the aforementioned pre-annealing process, the dielectric film 301 has undergone pre-annealing before the bonding interface 401 is formed, allowing at least some residual gas to be released before the interface forms. Subsequently, the oxide layer 201 and the dielectric film 301 bond together to form the bonding interface 401, and form... Figure 10 The bonded wafer 400 is shown. Residual gas inside the dielectric film may desorb and diffuse under subsequent high-temperature conditions, and may converge towards the closed bonding interface. Therefore, the aforementioned residual gas treatment process is applied... Figure 10 The layered structure shown helps to reduce the accumulation of gas near the bonding interface 401 during subsequent heat treatment.

[0105] like Figure 11 and Figure 12 As shown, the two images are ultrasonic scanning microscope images of the bonding interface obtained after the bonding wafer has undergone subsequent heat treatment, used to compare the bonding interface bubble situation corresponding to different pre-bonding treatment paths.

[0106] Ultrasonic scanning microscopy images the bonding interface state inside a wafer by detecting the differences in sound wave propagation and reflection at the material's internal interface. Figure 11 and Figure 12 In the embodiment shown, this detection method can be used to observe the local defect area formed by gas accumulation at the bonding interface, and to evaluate the bubble formation at the bonding interface accordingly.

[0107] Figure 11 This corresponds to a control sample. This sample enters the subsequent wafer bonding process after the formation of the dielectric thin film, and undergoes subsequent heat treatment after the formation of the bonded wafer. Figure 11 The circular area corresponds to the main inspection area of ​​the wafer, containing multiple bright-colored regions. Based on the sample's process conditions and ultrasonic scanning results, these bright-colored regions correspond to bubble defects at the bonding interface. The distribution of multiple bubble defects at different locations within the wafer indicates that gas components in the dielectric film can migrate to the already formed bonding interface and accumulate in localized areas during subsequent heat treatment.

[0108] Based on the aforementioned bubble formation mechanism, some of the gas introduced or generated during the dielectric film formation process may remain inside the film. When the wafer undergoes high-temperature heat treatment after bonding, the residual gas gains thermal energy and desorbs and diffuses from the interior of the dielectric film, subsequently migrating towards the bonding interface. Once the bonding interface has formed, the external migration path of the gas is restricted by the interface structure, and local accumulation to a certain extent can lead to… Figure 11 The bubble defect shown in the image.

[0109] Figure 12 The samples that underwent pre-annealing were treated accordingly. After the dielectric film was formed and before wafer bonding, the first substrate on which the dielectric film was formed was pre-annealed, followed by wafer bonding and post-bonding annealing. Figure 12 The circular detection area in the image shows a relatively uniform imaging state, indicating that the bonding interface has fewer bubble defect features.

[0110] exist Figure 12 In the corresponding process, pre-annealing occurs before the bonding interface forms. During this pre-annealing, gaseous components in the dielectric film can desorb and diffuse under heat treatment, migrating to the outside of the film. The bonding interface forms after pre-annealing, reducing the amount of residual gas that can be released during subsequent post-bonding annealing stages. Pre-annealing allows relevant gaseous components in the film to be released before wafer bonding and reduces the amount of gas that can be released in subsequent high-temperature steps.

[0111] The two sets of test results indicate that setting the pre-annealing treatment after the formation of the dielectric film and before wafer bonding allows the dielectric film to complete the corresponding heat treatment before the bonding interface is formed. This helps to release residual gas in the film in advance, thereby reducing the accumulation of residual gas at the bonding interface and the formation of bubbles during the subsequent post-bonding annealing process.

[0112] Furthermore, Figure 11 and Figure 12 It can also provide a basis for detection images for the area ratio of bubble defects at the bonding interface of bonded wafers.

[0113] After determining the detection area and bubble defect identification rules, image analysis can be performed on the ultrasonic scanning microscope image to obtain the area of ​​the bubble defect region, and the proportion of the bond interface bubble defect area can be calculated based on the detection area area. For example, this parameter is expressed as follows: .

[0114] in, This represents the total area within the evaluation region that is identified as a bubble defect. This represents the area of ​​the corresponding bonding interface evaluation region. This indicates the percentage of the area with bubble defects at the bonding interface.

[0115] This application also provides a bonding wafer 400. The bonding wafer 400 includes a first substrate 300, a second substrate 200, and a dielectric film 301, the dielectric film 301 being located between the first substrate 300 and the second substrate 200. After the first substrate 300 and the second substrate 200 are bonded together, a bonding interface 401 is formed between them.

[0116] The bonding wafer 400 is obtained by the bonding wafer fabrication method provided in this application. Specifically, the dielectric thin film 301 is deposited on the bonding side of the first substrate 300 at a thin film deposition temperature. Formation; after the dielectric thin film 301 is formed and before the first substrate 300 and the second substrate 200 are wafer bonded, the first substrate 300 on which the dielectric thin film 301 is formed is subjected to a pre-annealing temperature. Pre-annealing is performed; after the first substrate 300 and the second substrate 200 are wafer bonded, the bonded wafer 400 is annealed at the temperature after bonding. Bonding followed by annealing. The pre-annealing temperature is specified. Above the thin film deposition temperature And the temperature of the post-bonding annealing treatment Temperatures below the pre-annealing treatment .

[0117] In the above preparation process, the dielectric film 301 undergoes a pre-annealing treatment before the bonding interface 401 is formed, and the temperature of the pre-annealing treatment is... Above the thin film deposition temperature And higher than the temperature of subsequent bonding annealing. This allows at least a portion of the residual gas in the dielectric film 301 to be released before wafer bonding, thereby reducing the migration and accumulation of residual gas to the bonding interface 401 during the post-bonding annealing process.

[0118] Therefore, the area ratio of bubble defects at the bonding interface of bonding wafer 400 is less than or equal to 0.1%. The area ratio of bubble defects at the bonding interface is used to characterize the proportion of the bubble defect area within the evaluation region of bonding interface 401. Combined with... Figure 11 and Figure 12 An ultrasonic scanning microscope can be used to inspect the bonding interface 401, and the bubble defect status of the bonding interface can be determined based on the inspection results.

[0119] Furthermore, the bonding interface 401 possesses a corresponding bonding energy. The bonding energy characterizes the interfacial bonding performance of the bonding interface 401; it is the energy per unit area required for the bonding interface 401 to separate. Specifically, the bonding energy of the bonding interface 401 is greater than or equal to 2 J / m². The bonding energy is measured after the bonding wafer 400 has undergone annealing following bonding, and is obtained using the Maszara test.

[0120] It is understood that in some embodiments, the first substrate 300 is a support substrate and the second substrate 200 is a donor substrate. An oxide layer 201 is formed on the side of the donor substrate facing the first substrate, and the oxide layer 201 is located between the donor substrate and the dielectric film 301. After the first substrate 300 and the second substrate 200 are wafer bonded, a bonding interface 401 is formed between the oxide layer 201 and the dielectric film 301. Thus, the bonded wafer 400 sequentially includes the donor substrate, the oxide layer 201, the bonding interface 401, the dielectric film 301, and the support substrate along the thickness direction.

[0121] It is understood that in some embodiments, the dielectric film 301 is a SiO2 film, SiN film, or SiCN film formed by plasma-enhanced chemical vapor deposition. Regarding the dielectric film 301 described above, in conjunction with the pre-annealing treatment embodiment provided in this application, the dielectric film 301 is heat-treated before the bonding interface 401 is formed, causing at least some of the residual gas in the dielectric film 301 to be released in advance, thereby obtaining a bonded wafer 400 with a lower level of bonding interface bubble defects.

[0122] The following specific embodiments and comparative examples verify the bonding interface bubble situation corresponding to the bonding wafer preparation method provided in this application.

[0123] Comparative Example 1 In Comparative Example 1, a dielectric thin film 301 was formed on the bonding side of the first substrate 300 by plasma-enhanced chemical vapor deposition. The material of the dielectric thin film 301 was SiO2, and the film deposition temperature was... The temperature is 300℃, and the thickness of the dielectric thin film 301 is 500nm.

[0124] After the dielectric thin film 301 is formed, it is subjected to chemical mechanical polishing to reduce the profile arithmetic mean deviation of the surface roughness of the dielectric thin film 301. The thickness is 0.2 nm. Subsequently, the bonding side of the first substrate 300 and the bonding surface of the second substrate 200 are subjected to plasma activation and hydrophilic treatment, and wafer bonding is performed in a vacuum bonding cavity 500. The pressure in the vacuum bonding cavity 500 is 0.2 mbar. After the first substrate 300 and the second substrate 200 are wafer bonded, a bonded wafer 400 is formed.

[0125] Comparative Example 1 follows the existing process flow from the formation of the dielectric thin film 301 to wafer bonding. Subsequently, a post-bonding annealing treatment is performed at 500°C. Bonded wafer 400 was subjected to a 3-hour post-bonding annealing process.

[0126] The wafer specifications, dielectric film 301 material and thickness, CMP conditions, surface treatment conditions, wafer bonding conditions and post-bonding annealing conditions of Comparative Example 1 are consistent with those of Example 1.

[0127] Example 1 In Example 1, a first substrate 300 and a second substrate 200 with the same specifications as Comparative Example 1 were used. A dielectric thin film 301 was formed on the bonding side of the first substrate 300 by plasma-enhanced chemical vapor deposition. The material of the dielectric thin film 301 was SiO2, and the film deposition temperature was... The temperature is 300℃, and the thickness of the dielectric thin film 301 is 500nm.

[0128] After the dielectric thin film 301 is formed and before the first substrate 300 and the second substrate 200 are wafer bonded, a pre-annealing treatment is performed at a temperature of 600°C. The first substrate 300 on which the dielectric thin film 301 is formed is subjected to a pre-annealing treatment for 2 hours in a low-pressure environment.

[0129] After the pre-annealing treatment is completed, CMP is performed on the dielectric film 301 to reduce the profile arithmetic mean deviation of the surface roughness of the dielectric film 301. The thickness is 0.2 nm. Subsequently, the bonding side of the first substrate 300 and the bonding surface of the second substrate 200 are subjected to plasma activation and hydrophilic treatment, and wafer bonding is performed in the vacuum bonding cavity 500 to form a bonded wafer 400. The pressure in the vacuum bonding cavity 500 is 0.2 mbar.

[0130] Then, the bonding post-annealing treatment is carried out at a temperature of 500°C. Bonded wafer 400 was subjected to a 3-hour post-bonding annealing process.

[0131] In Example 1, the temperatures satisfy:

[0132] in: =600℃, =500℃, =300℃ Other process conditions in Example 1 were kept the same as in Comparative Example 1.

[0133] Example 2 To further verify the implementation effect when the post-bonding annealing temperature is higher than 500°C, Example 2 was set up.

[0134] Example 2 uses the same basic process flow as Example 1, the difference being that the process temperatures are set as follows: =700℃, =600℃, =350℃ And satisfy:

[0135] The pre-annealing process takes 2 hours, and the post-bonding annealing process takes 3 hours. The dielectric film 301 is made of SiO2 and has a thickness of 500 nm; the pre-annealing process is carried out in a low-pressure environment.

[0136] The other process conditions in Example 2 are the same as those in Example 1.

[0137] Example 3 To further verify the implementation effect when there is a predetermined temperature difference between adjacent process temperatures, Example 3 was set up.

[0138] Example 3 adopts the same basic process flow as Example 1, wherein: =600℃, =500℃, =300℃ And simultaneously satisfy: 100℃≥50℃ as well as: 200℃≥50℃.

[0139] The pre-annealing treatment takes 2 hours, and the post-bonding annealing treatment takes 3 hours. The dielectric film 301 is made of SiO2 and has a thickness of 500 nm.

[0140] The other process conditions in Example 3 are the same as those in Example 1.

[0141] To illustrate the rationality of the 50℃ temperature difference boundary, the following reference example is further provided.

[0142] Reference Example 1 Reference Example 1 uses the same process flow as Example 3, wherein: 30℃ < 50℃ and: 200℃≥50℃.

[0143] The remaining process conditions are the same as in Example 3.

[0144] See Example 2 Reference Example 2 uses the same process flow as Example 3, wherein: 100℃≥50℃ and: 30℃ < 50℃.

[0145] See Example 3 Reference Example 3 uses the same basic process flow as Example 3 to verify the implementation effect when the temperature difference between the pre-annealing treatment temperature and the post-bonding annealing treatment temperature is less than 50°C. The film deposition temperature is 300°C, the post-bonding annealing treatment temperature is 500°C, and the pre-annealing treatment temperature is 540°C. Therefore, the temperature difference between the pre-annealing treatment temperature and the post-bonding annealing treatment temperature is 40°C, and the temperature difference between the post-bonding annealing treatment temperature and the film deposition temperature is 200°C.

[0146] Other process conditions in Reference Example 3 are consistent with those in Example 3.

[0147] Example 4 Example 4 uses the same basic process flow as Example 3, wherein the film deposition temperature is 300°C, the post-bonding annealing temperature is 500°C, and the pre-annealing temperature is 550°C. Thus, the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature is 50°C, and the temperature difference between the post-bonding annealing temperature and the film deposition temperature is 200°C.

[0148] The other process conditions in Example 4 are the same as those in Example 3.

[0149] Example 5 Example 5 uses the same basic process flow as Example 3, wherein the film deposition temperature is 300°C, the post-bonding annealing temperature is 500°C, and the pre-annealing temperature is 560°C. Thus, the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature is 60°C, and the temperature difference between the post-bonding annealing temperature and the film deposition temperature is 200°C.

[0150] The other process conditions in Example 5 are the same as those in Example 3.

[0151] See Example 4 Reference Example 4 uses the same basic process flow as Example 3 to verify the implementation effect when the temperature difference between the post-bonding annealing treatment temperature and the thin film deposition temperature is less than 50°C. The thin film deposition temperature is 450°C, the post-bonding annealing treatment temperature is 490°C, and the pre-annealing treatment temperature is 590°C. Therefore, the temperature difference between the pre-annealing treatment temperature and the post-bonding annealing treatment temperature is 100°C, and the temperature difference between the post-bonding annealing treatment temperature and the thin film deposition temperature is 40°C.

[0152] Other process conditions in Example 4 are consistent with those in Example 3.

[0153] Example 6 Example 6 uses the same basic process flow as Example 3, wherein the film deposition temperature is 450°C, the post-bonding annealing temperature is 500°C, and the pre-annealing temperature is 600°C. Thus, the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature is 100°C, and the temperature difference between the post-bonding annealing temperature and the film deposition temperature is 50°C.

[0154] The other process conditions in Example 6 are the same as those in Example 3.

[0155] Example 7 Example 7 uses the same basic process flow as Example 3, wherein the film deposition temperature is 450°C, the post-bonding annealing temperature is 510°C, and the pre-annealing temperature is 610°C. Thus, the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature is 100°C, and the temperature difference between the post-bonding annealing temperature and the film deposition temperature is 60°C.

[0156] The other process conditions in Example 7 are the same as those in Example 3.

[0157] Test method description: The bonding wafers formed by Comparative Example 1, Examples 1-3, and Reference Examples 1 and 2 were subjected to the following tests.

[0158] In addition, the bonding wafers formed in Reference Examples 3 and 4 and Examples 4 to 7 were tested using the same equipment, parameters and judgment criteria as the samples described above, to verify the boundary effect of two adjacent process temperature differences at 40°C, 50°C and 60°C.

[0159] Test 1: Bubble Detection at Bonding Interface After the bonding and annealing process is completed, the bonding interface 401 of each bonded wafer is inspected using an ultrasonic scanning microscope.

[0160] The ultrasonic scanning microscope is model AW300, with a detection frequency of 230MHz, a scanning resolution of 30μm, and a scanning area covering the entire wafer.

[0161] For each bonded wafer, ultrasonic scanning microscope images of the bonding interface 401 were obtained using the same equipment parameters and image acquisition conditions.

[0162] Test 2: Percentage of area of ​​bubble defects at bonding interface The proportion of bubble defects at the bonding interface was determined based on the detection images obtained by ultrasonic scanning microscopy.

[0163] Among them, the bubble defect area is identified according to the defect identification program built into the detection equipment; the bubble defect identification threshold is 5μm; the area statistics are completed using the analysis software built into the equipment.

[0164] Test 3: Number of bubble defects Furthermore, the number of independent bubble defects identified within the evaluation area can be counted and recorded as follows: .

[0165] For adjacent defect regions that meet the criterion of a spacing of <5μm, they are counted as a single bubble defect; for defect regions that are separate from each other, they are counted separately.

[0166] This test is mainly used to help illustrate the distribution of bubbles at the bonding interface of different samples.

[0167] Test 4: Bonding Energy After post-bonding annealing, the bonding energy of each bonded wafer was tested at the bonding interface. The Maszara test was used to determine the energy per unit area corresponding to the separation of the bonding interface. For each bonded wafer, three test results were obtained at the wafer edge, and the average value was taken as the bonding energy of the corresponding bonded wafer, in J / m².

[0168] Test Results The test results of Comparative Examples 1, Examples 1-3 and Reference Examples 1 and 2 are summarized in Table 1; the process conditions and test results of the 50℃ temperature difference and temperature boundary verification group near 500℃ are summarized in Table 2.

[0169] Table 1. Bonding interface detection results for comparative examples, embodiments, and reference examples.

[0170] Table 2. Process conditions and test results of the verification group with a temperature difference of 50℃ and a temperature boundary near 500℃.

[0171] From Table 1 and Figure 11 , Figure 12The test results show that the area of ​​bond interface bubble defects in Comparative Example 1 is 9.53%, while the area of ​​bond interface bubble defects in Example 1 is 0.02%. Example 1 is 9.51 percentage points lower than Comparative Example 1.

[0172] Combination Figure 11 In Comparative Example 1, multiple large bubble defect regions can be observed in the bonding interface 401, with bubble defects mainly distributed throughout the entire sheet. Figure 12 In Example 1, the bonding interface 401 showed a detection state with almost no bubbles, and the corresponding bubble defect area ratio was 0.02%.

[0173] Comparative Example 1 and Example 1 use the same or corresponding dielectric film 301, CMP, surface treatment, wafer bonding, and post-bonding annealing conditions. The main process difference is that in Example 1, a pre-annealing treatment is performed after the dielectric film 301 is formed and before wafer bonding, and the temperature of the pre-annealing treatment is set higher. Temperature higher than the post-bonding annealing treatment And the temperature of the post-bonding annealing treatment Above the thin film deposition temperature .

[0174] In Example 1, the dielectric film 301 undergoes a pre-annealing treatment before the bonding interface 401 is formed. At least a portion of the residual gas in the dielectric film 301 desorbs and diffuses under the corresponding thermal conditions and is able to migrate outward before the bonding interface 401 is formed. Subsequently, when the bonding interface 401 is formed and a post-bonding annealing treatment is performed, the amount of residual gas that can continue to be released from the dielectric film 301 and migrate to the bonding interface 401 is correspondingly reduced, thereby achieving a lower bonding interface bubble defect area ratio in Example 1.

[0175] For Example 2, when:

[0176] In Example 2, the area of ​​bubble defects at the bonding interface was 0%. This test result indicates that when the bonding wafer needs to undergo post-bonding annealing at a temperature higher than 500°C, more gas can be removed by subjecting the dielectric film 301 to a higher pre-annealing temperature before wafer bonding.

[0177] For Example 3, when: 100℃≥50℃ and: 200℃≥50℃ At that time, the area ratio of bonding interface bubble defects in Example 3 was 0.02%. Therefore, the bonding interface bubble situation corresponding to the two minimum temperature difference conditions can be explained based on the actual test results.

[0178] Furthermore, to investigate the effect of the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature on the bonding interface state, the temperature difference was set to 40℃, 50℃, and 60℃ in Examples 3, 4, and 5, respectively, and the temperature difference between the post-bonding annealing temperature and the film deposition temperature was maintained at 200℃. The percentage of bubble defect area at the bonding interface was 0.11%, 0%, and 0%, respectively; the number of bubble defects was 1, 0, and 0, respectively; and the bonding energies were 2.36 J / m², 2.41 J / m², and 2.45 J / m², respectively.

[0179] To investigate the effect of the temperature difference between the post-bonding annealing temperature and the thin film deposition temperature on the bonding interface state, the temperature difference was set to 40℃, 50℃, and 60℃ in Examples 4, 6, and 7, respectively, and the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature was maintained at 100℃. The percentage of bubble defect area at the bonding interface was 0.07%, 0%, and 0%, respectively; the number of bubble defects was 1, 0, and 0, respectively; and the bonding energy was 2.38 J / m², 2.42 J / m², and 2.48 J / m², respectively.

[0180] Furthermore, Examples 4, 6, and 7 can also be used to verify the effectiveness of post-bonding annealing at temperatures around 500°C. The film deposition temperature for all three groups of samples was 450°C, the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature was 100°C, and the post-bonding annealing temperatures were 490°C, 500°C, and 510°C, respectively. The percentage of bubble defect area at the bonding interface for the three groups of samples was 0.07%, 0%, and 0%, respectively; the number of bubble defects was 1, 0, and 0, respectively; and the bonding energies were 2.38 J / m², 2.42 J / m², and 2.48 J / m², respectively. Through these settings, the bonding interface state can be compared when the post-bonding annealing temperature is below 500°C, 500°C, and above 500°C, thus providing experimental data for the specific temperature limit of post-bonding annealing above 500°C.

[0181] The test results under the above-mentioned different temperature difference conditions show that, for the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature, under the test conditions adopted in this application, when the temperature difference is 40℃, the proportion of bond interface bubble defect area in Reference Example 3 is 0.11%; when the temperature difference increases to 50℃ and 60℃, the proportion of bond interface bubble defect area in Examples 4 and 5 is 0%, and the bonding energy is greater than or equal to 2 J / m². Therefore, under the corresponding process conditions, setting the temperature difference between the pre-annealing temperature and the post-bonding annealing temperature to be greater than or equal to 50℃ is beneficial to obtaining a lower level of bond interface bubble defects.

[0182] Regarding the temperature difference between the post-bonding annealing temperature and the thin film deposition temperature, under the test conditions adopted in this application, when the temperature difference is 40℃, 50℃, and 60℃, the proportion of bubble defect area at the bonding interface in Reference Examples 4, 6, and 7 is less than or equal to 0.1%, and the bonding energy is greater than or equal to 2 J / m². These results indicate that, under the corresponding process conditions, setting the temperature difference within the test range of 40℃ to 60℃ can obtain a bonding interface state that meets the above evaluation indicators. This application further sets the temperature difference to greater than or equal to 50℃ as a preferred process parameter setting.

[0183] It should be noted that the aforementioned 50°C temperature difference is a preferred parameter determined in conjunction with the process conditions used in the embodiments of this application, and does not imply that the corresponding technical effect cannot be achieved at temperatures below 50°C. The appropriate temperature difference can be determined according to actual process requirements under different dielectric film materials, film thicknesses, and heat treatment conditions.

[0184] Based on the measured results of Examples 1 to 3, in the examples that meet the aforementioned preparation conditions, the area ratio of bubble defects at the bonding interface is 0.02%, 0%, and 0.02%, respectively.

[0185] Based on the above test data, the area ratio of bubble defects at the bonding interface of bonding wafer 400 is limited to: ≤0.1% Of this, 0.1% is determined based on the measured results of each embodiment and the allowable level of bonding interface defects in the product.

[0186] Furthermore, the bonding energy test results in Table 1 show that the bonding energies of Comparative Example 1, Examples 1-3, Reference Example 1, and Reference Example 2 are 1.29 J / m², 2.25 J / m², 2.42 J / m², 2.31 J / m², 1.83 J / m², and 2.15 J / m², respectively. Among them, the bonding energies of Examples 1-3 are all greater than or equal to 2 J / m².

[0187] Based on the measured results of Examples 1-3, the bonding energy of the bonding interface 401 of the bonding wafer 400 can be limited to greater than or equal to 2 J / m². Combined with the above data on the proportion of bubble defects at the bonding interface, Examples 1-3 all simultaneously satisfy the conditions that the proportion of bubble defects at the bonding interface is less than or equal to 0.1% and the bonding energy is greater than or equal to 2 J / m².

[0188] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0189] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for preparing a bonding wafer, characterized in that, include: Provide a first substrate and a second substrate; A dielectric thin film is formed on the bonding side of the first substrate at the thin film deposition temperature; The bonding surface of the second substrate is bonded to the dielectric film of the first substrate to form a bonding wafer; in, After the dielectric film is formed and before the first substrate and the second substrate are bonded, the first substrate on which the dielectric film is formed is subjected to a pre-annealing treatment at a temperature higher than the film deposition temperature, so that at least a portion of the residual gas in the dielectric film escapes from the dielectric film before bonding. After the bonding wafer is formed, the bonding wafer is subjected to post-bonding annealing, the temperature of which is lower than the temperature of the pre-annealing.

2. The method for preparing a bonding wafer according to claim 1, characterized in that, The bonding annealing temperature is higher than 500°C, and the film deposition temperature is lower than 500°C.

3. The method for preparing a bonding wafer according to claim 1, characterized in that, The difference between the temperature of the post-bonding annealing treatment and the temperature of the thin film deposition is greater than or equal to 50°C, and the difference between the temperature of the pre-annealing treatment and the temperature of the post-bonding annealing treatment is greater than or equal to 50°C.

4. The method for preparing a bonding wafer according to claim 1, characterized in that, The dielectric thin film is formed by plasma-enhanced chemical vapor deposition.

5. The method for preparing a bonding wafer according to claim 1, characterized in that, The pre-annealing process takes more than 1 hour.

6. The method for preparing a bonding wafer according to claim 1, characterized in that, The pre-annealing process is carried out in one of the following environments: nitrogen atmosphere, argon atmosphere, vacuum environment, or low-pressure environment.

7. The method for preparing a bonding wafer according to claim 4, characterized in that, The dielectric film is a SiO2 film, and the pre-annealing treatment is carried out in an oxidizing atmosphere.

8. The method for preparing a bonding wafer according to claim 1, characterized in that, After the first substrate undergoes the pre-annealing treatment and before the first substrate is bonded to the second substrate, the bonding surface of the dielectric film is chemically and mechanically polished.

9. The method for preparing a bonding wafer according to claim 1, characterized in that, After the dielectric film is formed and before the first substrate is subjected to the pre-annealing process, the dielectric film is chemically and mechanically polished.

10. The method for preparing a bonding wafer according to any one of claims 8 or 9, characterized in that, The arithmetic mean deviation of the surface roughness of the dielectric film after the chemical mechanical polishing is less than 0.3 nm.

11. The method for preparing a bonding wafer according to claim 1, characterized in that, After the pre-annealing process is completed and before the first substrate and the second substrate are bonded, the bonding side of the first substrate and the bonding surface of the second substrate are subjected to plasma activation and hydrophilic treatment.

12. The method for preparing a bonding wafer according to claim 11, characterized in that, The plasma activation is performed using any one of the following gases: argon, nitrogen, and oxygen, or a mixture of any two or three of these gases.

13. The method for preparing a bonding wafer according to claim 1, characterized in that, The first substrate and the second substrate are bonded in a vacuum bonding chamber, the pressure of which is 0.001 mbar to 1000 mbar.

14. A bonding wafer, characterized in that, include: First substrate; Second substrate; as well as A dielectric thin film is located between the first substrate and the second substrate; The dielectric film is formed on the bonding side of the first substrate at a film deposition temperature. After the dielectric film is formed and before the first substrate and the second substrate are bonded, the first substrate with the dielectric film is pre-annealed. The bonding wafer formed after the first substrate and the second substrate are bonded is post-bonding annealed. The temperature of the pre-annealing treatment is higher than the film deposition temperature, and the temperature of the post-bonding annealing treatment is lower than the temperature of the pre-annealing treatment. The area ratio of bubble defects at the bonding interface of the bonded wafer is less than or equal to 0.1%, and the bonding energy at the bonding interface is greater than or equal to 2J / m².

15. The bonding wafer according to claim 14, characterized in that, The first substrate is a support substrate, and the second substrate is a donor substrate. An oxide layer is formed on the side of the donor substrate facing the first substrate. The oxide layer is located between the donor substrate and the dielectric film and forms the bonding interface with the dielectric film.

16. The bonding wafer according to claim 14, characterized in that, The dielectric thin film is a SiO2 thin film, SiN thin film, or SiCN thin film formed by plasma-enhanced chemical vapor deposition.

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