Method for processing silicon-on-insulator and wafer

Abstract

The present disclosure provides a method for processing silicon-on-insulator and a wafer. The method comprises providing a donor wafer with a first silicon oxide layer on the surface, implanting helium ions into the donor wafer from the first silicon oxide layer at a first dose, implanting hydrogen ions at a second dose, forming a target separation surface at the depth of the hydrogen ion implantation peak, the helium ion implantation peak being below the target separation surface, and the first dose being greater than the second dose; providing a substrate wafer with a second silicon oxide layer on the surface, bonding the first silicon oxide layer and the second silicon oxide layer to obtain a bonded structure; performing a separation heat treatment on the bonded structure, wherein the heating rate of the initial heating stage is determined according to the depth difference between the two ion implantation peaks, and the region corresponding to the hydrogen ion implantation peak forms a damage layer for separation, and the donor wafer is separated along the target separation surface to obtain an initial silicon-on-insulator structure; and removing the damage layer on the top silicon surface by thermal annealing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor substrate manufacturing technology, and more particularly to a method for processing silicon on insulator and a wafer. Background Technology

[0002] Silicon-on-insulator (Si-O-I) wafers can achieve silicon thin-layer transfer through ion implantation, wafer bonding, and thermal processing. Typically, a defect region for separation is formed inside the donor wafer. After bonding the donor wafer to the substrate, thermal processing is performed, and the donor wafer is separated along the defect region to transfer a portion of the silicon layer to the substrate side.

[0003] During the process of ions penetrating to a predetermined depth from the donor surface, they pass through the silicon layer to be transferred, causing penetration damage. The separation process may also generate process damage near the separation surface. Reducing the hydrogen ion implantation dose helps reduce penetration damage in the silicon layer to be transferred; however, the defect regions corresponding to hydrogen ions also play a role in subsequent separation. Reducing the hydrogen ion implantation dose may compromise the conditions for separation along the predetermined location.

[0004] Therefore, during the transfer of silicon-on-insulator thin films, it is necessary to solve the problem of maintaining reliable and complete separation of the bonded structure along the predetermined position while reducing ion implantation damage in the silicon layer to be transferred. Summary of the Invention

[0005] This disclosure provides a method for processing silicon on insulators and a wafer; it can solve the problem of maintaining reliable and complete separation of the bonding structure along a predetermined position while reducing ion implantation damage in the silicon layer to be transferred during the transfer of silicon on insulator thin layers.

[0006] This disclosure provides a method for processing silicon-on-insulator. A donor wafer is provided, the surface of which has a first silicon oxide layer; helium ion implantation is performed from the first silicon oxide layer into the donor wafer at a first dose, forming a helium ion implantation peak within the donor wafer; hydrogen ion implantation is performed from the first silicon oxide layer into the donor wafer at a second dose, forming a hydrogen ion implantation peak within the donor wafer, the depth at which the hydrogen ion implantation peak is located constitutes a target release surface; the helium ion implantation peak is located below the target release surface, and the first dose is greater than the second dose.

[0007] A substrate is provided, the surface of which has a second silicon oxide layer; the first silicon oxide layer and the second silicon oxide layer are bonded to obtain a bonded structure; the bonded structure is subjected to a peeling heat treatment, causing the donor sheet to peel off along the target peeling surface to obtain an initial silicon-on-insulator structure, the initial silicon-on-insulator structure including a supporting substrate, an insulating buried layer, and a top silicon layer; a damaged layer on the surface of the top silicon layer is removed by a thermal annealing process. The peeling heat treatment includes an initial heating stage, the heating rate of which is determined based on the depth difference between the helium ion implantation peak and the hydrogen ion implantation peak, and a damaged layer for peeling is formed in the region of the donor sheet corresponding to the hydrogen ion implantation peak.

[0008] This disclosure also provides a wafer fabricated using the above-described silicon-on-insulator (SIO) fabrication method. The wafer includes a substrate, a buried insulating layer disposed on the substrate, and a top silicon layer disposed on the buried insulating layer. The thickness of the top silicon layer is 216.5 nm to 223.5 nm, and the pit density of the top silicon layer is not higher than 500 cm⁻¹. -2 .

[0009] In the above processing method, the helium ion implantation peak is located below the target stripping surface, ensuring that the main damage area near the helium ion implantation peak is on the side of the subsequent damaged layer away from the insulating buried layer. The first dose is greater than the second dose, which helps to reduce hydrogen ion penetration damage while maintaining the auxiliary effect of helium ions on the stripping process. The initial heating rate of the stripping heat treatment is determined based on the depth difference between the two ion implantation peaks, so that the heat treatment conditions are matched with the spatial configuration of the two ions. The region corresponding to the hydrogen ion implantation peak forms a damaged layer for stripping. After the donor sheet is stripped along the target stripping surface, the initial silicon-on-insulator structure is obtained, and the damaged layer on the top silicon surface is removed by thermal annealing. Therefore, it is beneficial to reduce ion implantation damage in the silicon layer to be transferred while ensuring the reliability of the separation process. Attached Figure Description

[0010] Figure 1 This is a schematic diagram illustrating an implementation scenario of silicon-on-insulator wafer fabrication according to one embodiment of this disclosure.

[0011] Figure 2 This is a schematic flowchart of a silicon-on-insulator processing method according to one embodiment of the present disclosure.

[0012] Figure 3 This is a schematic diagram showing the positional relationship between the helium ion implantation peak and the hydrogen ion implantation peak according to one embodiment of this disclosure.

[0013] Figure 4 This is a schematic diagram of the structure of the donor sheet and the substrate sheet after bonding, according to one embodiment of the present disclosure.

[0014] Figure 5 This is a schematic diagram illustrating the relationship between the injection peak depth difference and the initial heating rate, provided in one embodiment of this disclosure.

[0015] Figure 6 This is a schematic diagram illustrating the separation and transfer of a silicon layer along a damaged layer, according to one embodiment of this disclosure.

[0016] Figure 7 This is a schematic diagram of the post-processing of the silicon layer stripping surface provided in one embodiment of this disclosure.

[0017] Figure 8 This is a schematic diagram of a cross-section of a wafer obtained through processing according to one embodiment of this disclosure. Detailed Implementation

[0018] The embodiments of this disclosure will now be described with reference to the accompanying drawings. Each embodiment is used to illustrate the technical solution and parameter relationships of this disclosure; where technically compatible and with clear basis, lower-level parameters in different embodiments can be combined.

[0019] Existing silicon-on-insulator (STI) transfer processes typically begin by implanting hydrogen ions, or a combination of hydrogen and helium ions, into a donor wafer. This creates a damaged structure within the donor wafer that can develop into a separation region during subsequent heat treatment. The donor wafer is then bonded to a substrate, and heat treatment is used to propagate cracks to a predetermined depth, thereby transferring a layer of silicon to the substrate. Because the implanted ions need to travel from the wafer surface through the silicon layer to be transferred to reach the target implantation depth, through-path damage is formed along the implantation path. Bubble propagation, crack propagation, and the actual separation process can also create process damage of approximately 30 nm to 80 nm near the separation surface, with more concentrated separation surface damage regions reaching depths of approximately 30 nm to 60 nm.

[0020] For silicon photonics applications, the top silicon layer is typically on the order of approximately 220 nm in thickness, and a typical silicon optical waveguide can have a width of approximately 450 nm and a height of approximately 220 nm. Crystal defects such as dislocations and vacancy clusters can form light scattering centers, increasing waveguide transmission loss. Simultaneously, carrier transport in electro-optical devices such as modulators and detectors can be affected by the trapped state density. Therefore, in a class of silicon-on-insulator products, the top silicon pit density can be controlled to be below 500 cm⁻¹. -2 For products with higher requirements, the control can be further reduced to 100cm. -2 Magnitude.

[0021] In processes where a higher dose of hydrogen ions is used for separation alone, the hydrogen ion flux can reach approximately 5.0 × 10¹. 6 cm - ². In conventional hydrogen / helium co-implantation processes, the hydrogen ion flux can still be around 1.0 × 10¹.6 cm - ²~2.0×10¹ 6 cm - ². One type of near-field co-implantation method places the helium and hydrogen ion implantation peaks at similar positions, with a depth difference of approximately 10 nm to 20 nm, and utilizes the synergistic effect of the two ions to reduce the total flux required for separation. Even if this method can achieve separation, the main damage region of helium ions is still close to the subsequently retained top silicon layer. The displacement damage cross-section of helium ions can be approximately 1.6 times that of hydrogen ions; therefore, simply reducing the total flux as an optimization objective cannot necessarily guarantee a lower final top silicon defect level.

[0022] On the other hand, reducing the hydrogen ion implantation dose helps reduce hydrogen ion penetration damage in the silicon layer to be transferred, but the plate-like defects and associated bubbles formed by hydrogen ions during annealing also play a role in subsequent separation. As the hydrogen ion implantation dose decreases, the separation driving force provided by hydrogen-related defects may decrease. Therefore, the thin-layer transfer process needs to address two mutually restrictive aspects simultaneously: on the one hand, reducing ion implantation damage in the final transferred silicon layer, and on the other hand, ensuring that the bonded structure can still reliably separate along the predetermined position.

[0023] To address the aforementioned technical constraints, this disclosure establishes a coordination relationship between the helium ion implantation location, the hydrogen ion implantation location, and the subsequent lift-off heat treatment. The helium ion implantation peak is located deep to the hydrogen ion implantation peak, causing the region corresponding to the hydrogen ions to form a damaged layer during the lift-off heat treatment that defines the separation location. The initial heating conditions for the lift-off heat treatment are then configured based on the depth difference between the two implantation peaks. Thus, the main damaged region near the helium ion implantation peak can be located deep to the damaged layer, while the silicon material between the damaged layer and the insulating buried layer constitutes the silicon layer to be transferred.

[0024] In this disclosure, "implantation side" refers to the side of the donor sheet used to receive helium and hydrogen ions, the implantation side including an implantation surface; "implantation peak" refers to the position of the peak position of the concentration distribution of the corresponding ions along the depth direction of the donor sheet; "depth difference" refers to the distance between the helium ion implantation peak and the hydrogen ion implantation peak along the direction from the implantation side toward the interior of the donor sheet; "target peeling surface" refers to a predetermined peeling position at the depth where the hydrogen ion implantation peak is located; and "damaged layer" refers to a region corresponding to the hydrogen ion implantation region and developed into a region for silicon layer separation during the peeling heat treatment.

[0025] like Figure 1 As shown, Figure 1This is a schematic diagram illustrating an embodiment of silicon-on-insulator (SiI) wafer fabrication according to one embodiment of the present disclosure. The embodiment includes a donor wafer 100 and a substrate wafer 200. The donor wafer 100 undergoes surface treatment and ion implantation along a donor wafer processing path, while the substrate wafer 200 undergoes surface treatment for forming an insulating material along a substrate wafer processing path. The two processing paths converge during the wafer bonding stage. After bonding is completed, a bonding structure 400 is formed. After a peeling heat treatment, the silicon layer 130 remains on one side of the substrate wafer 200, and the silicon layer 130 can continue to be surface-trimmed and its thickness adjusted to form a wafer 500.

[0026] Figure 1 This describes the overall object flow between donor wafer 100, substrate wafer 200, bonding structure 400, and wafer 500, without requiring specific oxidation furnaces, ion implantation equipment, bonding equipment, or heat treatment equipment to be part of the wafer structure. The following is in conjunction with... Figure 2 First, the basic processing flow used to form the silicon-on-insulator structure will be explained.

[0027] like Figure 2 As shown, the basic processing flow of this disclosure includes steps S210 to S290. Steps S210 to S290 correspond sequentially to donor wafer preparation, helium ion implantation, hydrogen ion implantation, substrate preparation, bonding, initial heating rate determination, peeling heat treatment, peeling along the target peeling surface, and post-heat annealing treatment. The basic process will be described first below.

[0028] In step S210, a donor sheet having a first silicon oxide layer on its surface is provided.

[0029] The first silicon oxide layer is formed on the implantation side of the donor sheet, and subsequently helium ions and hydrogen ions are implanted into the donor sheet from the first silicon oxide layer. After bonding is completed, the first silicon oxide layer and the second silicon oxide layer together form an insulating layer.

[0030] In step S220, helium ions are implanted from the first silicon oxide layer into the donor wafer at a first dose, forming a helium ion implantation peak within the donor wafer.

[0031] The helium ion implantation peak is positioned deep on the target stripping surface, which is subsequently determined by the depth of the hydrogen ion implantation peak. This causes the main damaged area in the vicinity to tend to be removed along with the donor sheet after stripping. The first dose is used to maintain the deep helium-related damage and to provide auxiliary support in subsequent heat treatment.

[0032] In step S230, hydrogen ion implantation is performed from the first silicon oxide layer to the donor sheet at a second dose, forming a hydrogen ion implantation peak within the donor sheet; the depth at which the hydrogen ion implantation peak is located constitutes the target stripping surface.

[0033] Within the donor wafer 100, helium and hydrogen ion distributions are formed, staggered along the depth direction. The depth at which the hydrogen ion implantation peak is located constitutes the target stripping surface, and the helium ion implantation peak is located below the target stripping surface; the first dose is greater than the second dose. This spatial and dose relationship allows the hydrogen ion-corresponding region to define the stripping location and staggers the main helium ion damage area from the subsequently retained top silicon layer in the depth direction.

[0034] In step S240, a substrate having a second silicon oxide layer on its surface is provided.

[0035] The second silicon oxide layer is disposed on the bonding side of the substrate and is used to form an insulating layer after subsequent bonding with the first silicon oxide layer; after the thin layer transfer is completed, the substrate serves as a supporting substrate for the initial silicon-on-insulator structure.

[0036] In step S250, the first silicon oxide layer and the second silicon oxide layer are bonded to obtain a bonded structure.

[0037] A first silicon oxide layer on the surface of donor wafer 100 is bonded to a second silicon oxide layer on the surface of substrate wafer 200 to form a bonding structure 400. The two silicon oxide layers together constitute an insulating layer. The insulating layer separates the silicon material to be transferred on one side of donor wafer 100 from substrate wafer 200. After subsequent separation along the target peel surface, the silicon material remaining on the side of substrate wafer 200, together with the insulating layer and substrate wafer 200, constitutes the initial silicon-on-insulator structure.

[0038] In step S260, the heating rate of the initial heating stage of the stripping heat treatment is determined based on the depth difference between the helium ion implantation peak and the hydrogen ion implantation peak.

[0039] As the depth difference increases, the distance required for helium atoms to migrate from the deeper injection region to the shallower hydrogen-related defect region increases. Therefore, the upper limit of the initial heating rate can be reduced or maintained accordingly to provide a corresponding thermal history for a larger spatial distance.

[0040] In step S270, the bonded structure is subjected to a peeling heat treatment according to the determined initial heating rate, so that a damage layer for peeling is formed in the region of the donor sheet corresponding to the hydrogen ion implantation peak.

[0041] The exfoliation heat treatment includes an initial heating stage. The heating rate of the initial heating stage is determined based on the depth difference between the helium ion implantation peak and the hydrogen ion implantation peak, and a damage layer for exfoliation is formed in the region within the donor sheet corresponding to the hydrogen ion implantation peak.

[0042] The spatial relationship between the two ion implantation peaks formed in steps S220 and S230 is further used to determine the heat treatment conditions. The heating rate in the initial heating stage is matched with the depth difference between the two implantation peaks, so that the region corresponding to hydrogen ions gradually develops into a damaged layer during the heating and holding process, and establishes the heat treatment conditions for the donor sheet to be peeled off along the target peeling surface.

[0043] In step S280, the donor sheet is peeled off along the target peeling surface, leaving the silicon layer between the damaged layer and the insulating layer on one side of the substrate, resulting in an initial silicon-on-insulator structure including a supporting substrate, an insulating buried layer, and a top silicon layer.

[0044] The bonding structure 400 separates from the damaged layer formed near the target release surface. The silicon layer 130 between the damaged layer and the insulating layer remains on one side of the substrate 200, while the main body of the donor wafer 100 is located on the other side. Since the helium ion implantation peak is located below the target release surface, the main damaged area near the helium ion implantation peak also tends to be located on the side where the main body of the donor wafer 100 is located after separation. The insulating layer constitutes an insulating buried layer, and the silicon layer 130 constitutes the top silicon layer.

[0045] In step S290, the damaged layer on the top silicon surface is removed by thermal annealing.

[0046] The thermal annealing can be rapid thermal annealing, which promotes the migration of surface atoms near the separation surface, thereby repairing and reducing surface damage and improving surface morphology, and thus removing the damaged layer on the top silicon surface.

[0047] Through the above steps, the helium ion implantation peak, hydrogen ion implantation peak, dosage relationship, and the coordination of the location and process of the lift-off heat treatment are achieved. The deeper helium ion implantation peak offsets the main damage area from the silicon layer to be transferred. The heating rate in the initial heating stage is determined based on the depth difference between the two implantation peaks, and thermal annealing after lift-off reduces surface damage to the top silicon layer. Thus, the reliability of separation along the target lift-off surface can be maintained while reducing implantation damage to the transferred silicon layer.

[0048] Based on the above basic process, the specific settings of each process condition, as well as the intermediate and final structures, will be further explained below according to the actual processing sequence. The specific parameters are used to illustrate the subordinate methods that can implement the above basic process, and it is not required that all implementation methods use the same combination of parameters simultaneously.

[0049] Before ion implantation, donor wafer 100 and substrate wafer 200 can be prepared. Donor wafer 100 can be a single-crystal silicon wafer. In a complete set of processing conditions, donor wafer 100 is a Czochralski P-type (CZP) single-crystal silicon wafer with a diameter of 300 mm, a resistivity of 10 Ω·cm to 20 Ω·cm, and a crystal orientation of (100). This wafer material and electrical parameters are used to describe a processing condition for silicon substrates on silicon photoinsulators. Other single-crystal silicon wafers that can meet the requirements of ion implantation, bonding, and subsequent heat treatment can also be selected according to the target product.

[0050] A first silicon oxide layer can be formed on the implantation side of the donor wafer 100, and a second silicon oxide layer can be formed on the bonding side of the substrate 200. The first and second silicon oxide layers can be obtained through thermal oxidation, respectively. Under specific conditions, the donor wafer 100 forms approximately 200 nm of SiO2 in a dry oxygen environment at 1000°C, with a thickness ranging from 198 nm to 202 nm; the substrate 200 is formed approximately 2300 nm of SiO2 using a dry / wet oxygen composite oxidation process, with a thickness ranging from 2285 nm to 2315 nm. After bonding, the two oxide layers together form an insulating layer of approximately 2500 nm.

[0051] Combination Figure 3 The ion implantation conditions are explained in detail below. The implantation dose of helium ions is greater than that of hydrogen ions. The implantation dose of helium ions can be 1.0 × 10⁻⁶. 16 cm -2 ~3.0×10 16 cm -2 One representative dose is 2.0 × 10⁻⁶. 16 cm -2 The hydrogen ion injection dose can be 0.5 × 10⁻⁶. 16 cm -2 ~0.8×10 16 cm -2 One representative dose is 0.5 × 10¹ 6 cm - ². A lower hydrogen ion dose is used to reduce hydrogen ion penetration damage in the silicon layer to be transferred; a relatively higher helium ion dose is used to maintain helium-related damage on the deeper side of the damaged layer and the participation of subsequent heat treatment.

[0052] The target implantation peak of helium ions can be located approximately 280 nm to 350 nm below the interface between the first silicon oxide layer 120 and the donor wafer 100, while the target implantation peak of hydrogen ions can be located approximately 240 nm to 260 nm below this interface, thus placing the helium ion implantation peak on the side opposite to the hydrogen ion implantation peak. The depth difference between the two ion implantation peaks can be 30 nm to 100 nm, with 50 nm to 70 nm considered as a more concentrated implementation range.

[0053] The implantation energy for helium ions can be 60 keV to 75 keV, and the implantation energy for hydrogen ions can be 45 keV to 50 keV. For a set of conditions with a first silicon oxide layer 120 of approximately 200 nm, the helium ion implantation energy can be 66 keV or approximately 69 keV, and the hydrogen ion implantation energy can be 48 keV. Ion implantation can be performed at room temperature. By matching the implantation energy and dose, the two types of ions can form predetermined depth distributions after passing through the first silicon oxide layer 120.

[0054] like Figure 3 As shown, the first depth can represent the depth of the helium ion implantation peak (He implantation peak) relative to the interface between the first silicon oxide layer 120 and the donor wafer 100, and the second depth can represent the depth of the hydrogen ion implantation peak (H implantation peak) relative to the same interface. The difference between the two forms the depth difference. At a representative parameter point, the helium ion implantation peak is located approximately 310 nm below the interface, and the hydrogen ion implantation peak is located approximately 250 nm below the interface, with a depth difference of approximately 60 nm.

[0055] The lower limit of the depth difference is related to whether the main helium ion damage region can be sufficiently offset from the subsequently retained top silicon layer. When the depth difference is less than 30 nm, the overlap between the main helium ion damage region and the hydrogen ion-related defect region increases, and the residual helium-related damage in the top silicon layer tends to increase after separation. When the depth difference reaches more than 30 nm, the main helium ion damage peak begins to be located more fully in the deeper side of the damage layer. The upper limit of the depth difference is related to the effective migration distance of helium atoms during the heating process and the degree of assistance of the deep-side damage region to the separation conditions. When the depth difference further exceeds 100 nm, the separation success rate under low hydrogen flux conditions will decrease.

[0056] During the process of helium ions reaching the implantation peak from the surface, shallow silicon still suffers some penetration damage. However, the nuclear blocking effect of helium ions in the shallow region before reaching the implantation peak is lower than that near the implantation peak. Estimates have described shallow penetration damage as being on the order of 1% to 5% of the damage at the implantation peak. This relationship indicates that the main helium damage is concentrated near the deeper implantation peak, but it does not mean that helium ion penetration damage is completely absent in the silicon layer to be transferred.

[0057] like Figure 4 As shown, the implantation side of the donor wafer 100 is bonded to the substrate wafer 200 at low temperature using hydrophilic bonding, so that the first silicon oxide layer 120 and the second silicon oxide layer 220 are located between the two wafers. After bonding, a bonding structure 400 is formed. The first silicon oxide layer 120 and the second silicon oxide layer 220 together constitute the insulating layer 300; the silicon layer 130 is located between the insulating layer 300 and the subsequent damage layer 150; the main damage region of helium ions is located on the side of the damage layer 150 further away from the insulating layer 300.

[0058] The first silicon oxide layer 120 and the second silicon oxide layer 220 are in Figure 4 The figures are shown separately to indicate their formation origin. Two layers of SiO2 form a continuous insulating material structure at the bonding interface. When using a first silicon oxide layer 120 of approximately 200 nm and a second silicon oxide layer 220 of approximately 2300 nm, the final total thickness of the buried insulating layer is approximately 2.5 μm. Surface cleaning or activation can be performed according to wafer bonding process requirements before bonding to obtain bonding strength that meets the requirements of subsequent heat treatment.

[0059] Combination Figure 5 Within a depth difference range of 30 nm to 100 nm, the heating rate in the initial heating stage can be configured according to the depth difference, and the upper limit of the allowable heating rate can decrease or remain unchanged as the depth difference increases. This relationship indicates that as the injection peak distance increases, the heat treatment formulation does not use a higher upper limit of the allowable heating rate than that for smaller depth differences, thus providing a corresponding thermal history for larger spatial distances.

[0060] As Figure 5 For the specific implementation of the relationship shown, when the depth difference is 30nm~50nm, the initial heating rate can be 2°C / min~5°C / min; when the depth difference is greater than or equal to 60nm and less than 80nm, the initial heating rate can be 2°C / min~3°C / min; when the depth difference is 80nm~100nm, the initial heating rate can be set to no higher than 3°C / min. Figure 5 The above-mentioned matching relationship is represented by a parameter region, without requiring the depth difference and heating rate to satisfy a strictly continuous mathematical function.

[0061] Determining the initial heating rate based on the depth difference can be done either in advance during the process design phase based on the target implantation depth, or after ion implantation, by selecting the corresponding heat treatment formulation based on the actual implantation peak position. It does not require the heat treatment equipment to monitor the implantation peak position in real time during the heating process. Therefore, the depth difference, as a spatial parameter for front-end ion implantation, can be used for the process configuration of subsequent stripping heat treatment.

[0062] In a specific set of heat treatment conditions, the bonded structure 400 is heated from room temperature to 350°C at a rate of 3°C / min and held at 350°C for 20 min. The temperature is then increased to 500°C at a rate of 5°C / min and held at 500°C for 30 min. The heat treatment can be performed under a nitrogen atmosphere. For a wider implementation range, the initial heating rate from room temperature to 350°C can be 2°C / min to 5°C / min, with a holding time of 10 min to 30 min at 350°C; followed by further heating to 500°C and a holding time of 10 min to 30 min at 500°C.

[0063] The relationship between the aforementioned depth difference and the initial heating rate can be understood by considering the thermal behavior of helium and hydrogen in silicon. The diffusion activation energy of helium in silicon is approximately 0.5 eV to 0.8 eV, and significant migration occurs within a temperature window of approximately 150°C to 300°C; large-scale hydrogen diffusion, on the other hand, primarily occurs in the temperature range of approximately 300°C to 450°C. The greater the depth difference, the longer the distance helium atoms need to traverse from the deeper implanted region to the shallower hydrogen-related defect region. By limiting the allowable upper limit of the initial heating rate, the usable time of the wafer within the lower temperature migration window can be increased.

[0064] Before the exfoliation heat treatment begins and during the initial heating phase, the high-density vacancies and damage regions formed by deeper helium ion implantation are located deep within the damage layer. The lattice integrity of this region is lower than that of intact single-crystal silicon, and the local elastic modulus and critical fracture toughness can also be correspondingly reduced, thus altering the material resistance that crack propagation near the damage layer needs to overcome. Since the main damage peak of helium ions maintains a certain interval with the corresponding region of hydrogen ions, this auxiliary effect does not require the main damage regions of the two ions to overlap at the same depth.

[0065] As temperature increases, hydrogen ions can accumulate near the {001} crystal plane and form plate-like defects. These plate-like defects can further develop into microcavities, bubbles, and crack initiation regions. Helium atoms migrating from deeper helium ion implantation regions to the vicinity of these plate-like defects can be trapped by the defect regions and contribute to the internal pressure of the bubbles along with the hydrogen gas. Therefore, the total bubble pressure can be understood as a combined contribution of the hydrogen partial pressure and the helium partial pressure, with the helium partial pressure replenishing the bubble pressure after the hydrogen ion dosage decreases.

[0066] This process differs from the near-field co-implantation method, which directly provides nucleation sites through highly overlapping hydrogen / helium damage regions. When the helium ion implantation peak and the hydrogen ion implantation peak are spaced 30 nm to 100 nm apart, the effect of helium ions can be divided into two continuous stages: before heating and in the early stage of heating, the deep-side damage region changes the separation resistance conditions; during heating, some helium migrates from the deeper region to the vicinity of the hydrogen plate-like defects and participates in bubble pressure formation.

[0067] Within the scope of this disclosure, reducing the hydrogen ion dose is beneficial in minimizing penetration damage, but requires corresponding helium-assisted conditions. A hydrogen ion dose of approximately 0.5 × 10¹ is used. 6 cm - For example, a depth difference of not less than approximately 40 nm and a helium ion dose of not less than approximately 1.5 × 10¹ can be achieved. 6 cm - ², to maintain reliable separation.

[0068] Hydrogen ion dose: 0.3 × 10¹ 6 cm -² As a low-dose contrast condition. At a depth difference of approximately 60 nm and a helium ion dose of approximately 2.0 × 10¹ 6 cm - Under the condition of 2, the separation success rate under this comparative condition is less than 50%. Therefore, the following positive example uses 0.5 × 10¹ 6 cm - ² This serves as a representative implementation point for lower doses.

[0069] In a preferred parameter combination, the depth difference between the helium ion implantation peak and the hydrogen ion implantation peak is approximately 60 nm, and the hydrogen ion implantation dose is approximately 0.5 × 10¹. 6 cm - ², the helium ion injection dose is approximately 2.0 × 10¹ 6 cm - ², the initial heating rate was 2°C / min to 3°C / min. In the corresponding experiments, the separation success rate was greater than 99%, and the density of silicon etched pits in the post-processed top layer was less than 200 cm². - ². At a depth difference of approximately 45 nm to 75 nm and a hydrogen ion dose of approximately 0.4 × 10¹ 6 cm - ²~0.6×10¹ 6 cm - Within the fluctuation range of ², relevant experiments show that the process results have a certain margin.

[0070] like Figure 6 As shown, the bonding structure 400 separates along the damaged layer 150, while the silicon layer 130, insulating layer 300, and substrate 200 remain bonded, and the main body of the donor sheet 100 separates from the silicon layer 130. Since the position of the damaged layer 150 corresponds to the hydrogen ion implantation peak, the initial transfer thickness of the silicon layer 130 is mainly determined by the hydrogen ion implantation depth. Subsequently, the thickness of the top silicon layer is measured, and the decision to continue the sacrificial oxidation cycle is determined based on the thickness measurement results. The substrate 200 forms the supporting substrate, the insulating layer 300 forms the insulating buried layer, and the silicon layer 130 forms the top silicon layer, thus obtaining the initial silicon-on-insulator structure.

[0071] The separation path is jointly determined by the active bubble-driving force provided by the hydrogen ion-associated damage layer and the material fracture conditions at various depths. Near the hydrogen ion implantation peak at approximately 250 nm, hydrogen plate-like defects provide the active driving force for bubble and crack propagation, and helium atoms migrating to this region can further participate in the bubble pressure. Although the material damage is relatively high in the helium ion-dominant damage region located at approximately 295 nm–310 nm, some helium migrates to shallower regions during heating, and this deeper region lacks an active bubble-driving force comparable to that of hydrogen plate-like defects. Therefore, the final separation path can be locked near the hydrogen ion-associated damage layer.

[0072] The primary damage region caused by helium ions is located on the side of the damaged layer 150 away from the insulating layer 300. Therefore, after separation, this primary damage region is located on the other side along with the donor sheet 100. The final silicon layer 130 may still contain low-dose hydrogen ion penetration damage, minor penetration damage caused by helium ions passing through shallow silicon, and process damage near the separation surface, but does not include all the primary damage near the helium ion implantation peak.

[0073] like Figure 7 As shown, the separated silicon layer 130 is located on the insulating layer 300 and the substrate 200. Rapid Thermal Annealing (RTA) is a type of thermal annealing process used to promote the migration of surface atoms near the separated surface, repair lattice defects in the damaged layer on the top silicon surface, thereby removing at least some surface damage and initially smoothing the separated surface. RTA can be performed at 1100°C to 1300°C for 10 to 60 seconds in an Ar atmosphere; under one specific condition, the RTA temperature is 1250°C and the processing time is 45 seconds.

[0074] After RTA is completed, the silicon layer 130 is subjected to sacrificial oxidation in the form of rapid thermal oxidation (RTO) to form a sacrificial oxide layer 160 on a portion of the surface silicon of the silicon layer 130. RTO can be performed in an O2 atmosphere at 900°C~1100°C for 30s~90s, forming approximately 10nm~20nm of SiO2 each time. Subsequently, the sacrificial oxide layer 160 is removed using a dilute hydrofluoric acid (HF) solution, with an HF concentration of 1%~20%, consuming approximately 5nm~10nm of silicon per cycle.

[0075] For example, sacrificial oxidation is performed at 1000°C for 60 seconds, forming approximately 15 nm of SiO2 and consuming approximately 7 nm of silicon. This is followed by treatment with a 1%–5% HF solution at room temperature for approximately 60 seconds to remove the sacrificial oxide layer 160. The thickness of the current silicon layer 130 is measured using an ellipsometry, and the decision to continue to the next cycle is based on the measurement results. Sacrificial oxidation and oxide layer removal can be repeated 2–4 times, with a specific processing step involving 2–3 cycles, resulting in a total silicon removal of approximately 20 nm–30 nm.

[0076] Rapid thermal annealing and sacrificial oxidation serve different purposes. Rapid thermal annealing primarily improves the surface morphology of the separation surface, while sacrificial oxidation and oxide layer removal further remove damage and adjust the thickness of the top silicon layer by actually consuming silicon material near the separation surface. Therefore, the total material removal of approximately 20nm~30nm mainly corresponds to the sacrificial oxidation cycle, and should not be understood as rapid thermal annealing directly removing silicon material of the same thickness.

[0077] To illustrate a complete processing method for the above process, the following parameter combination can be used. Donor wafer 100 is a 300mm diameter CZP type single-crystal silicon wafer with a resistivity of 10Ω·cm~20Ω·cm and a crystal orientation of (100), and approximately 200nm of SiO2 is formed in a dry oxygen environment at 1000°C. Subsequently, a 2.0×10¹ 6 cm - Helium ion implantation was performed at a dose of 2 and an implantation energy of 66 keV, so that the main damage peak of helium ions was located approximately 310 nm below the SiO2 / Si interface; then, at a dose of 0.5 × 10¹ 6 cm - Hydrogen ion implantation was performed at a dose of 2, with an implantation energy of 48 keV, resulting in a hydrogen ion implantation peak located approximately 250 nm below the interface. The difference in implantation peak depth between the two ions was approximately 60 nm.

[0078] The substrate 200 is formed into SiO2 of approximately 2300 nm using a dry / wet oxygen composite oxidation process. Then, the donor wafer 100 is bonded to the substrate 200 at a low temperature using hydrophilic bonding, with the oxide layers on both sides forming an insulating buried layer of approximately 2500 nm. The bonded wafer is then heated from room temperature to 350°C at a rate of 3°C / min and held for 20 min, followed by a further heating to 500°C at a rate of 5°C / min and held for 30 min. Separation is then completed under N2 protection to obtain the initial silicon-on-insulator wafer.

[0079] The separated wafers were subjected to RTA at 1250 °C for 45 s in an Ar atmosphere. Subsequently, they were subjected to RTO sacrificial oxidation at 1000 °C for 60 s in an O2 atmosphere, forming approximately 15 nm of SiO2 and consuming approximately 5 nm to 10 nm of silicon each time, for example, 7 nm, 9 nm, etc., which will not be elaborated here.

[0080] The sacrificial SiO2 was removed by treating with a 1%–5% HF solution at room temperature for approximately 60 s. The thickness of the top silicon layer was monitored using an ellipsometry, and the sacrificial oxidation cycle was repeated 2–3 times based on the actual measurement results to achieve a top silicon layer thickness of 216.5 nm–223.5 nm. In the experimental results with this parameter combination, the surface roughness Ra after RTA was less than 0.5 nm, and the final top silicon pit density was less than 200 cm⁻¹. - ².

[0081] The parameters described above are used to illustrate a set of specific processing conditions for silicon photonics platforms. They do not require all implementations to use the same wafer diameter, resistivity, crystal orientation, oxide layer thickness, or number of post-processing steps. Provided that the helium ion implantation peak is located deep to the hydrogen ion implantation peak, the initial heating conditions are configured according to the depth difference, and silicon layer transfer is completed along the hydrogen ion-related damage layer, the appropriate wafer specifications and insulating layer thickness can be selected based on the target silicon-on-insulator (SOI) specifications.

[0082] The residual damage remaining in the top silicon layer mainly includes penetration damage from low-dose hydrogen ions, minor penetration damage from helium ions passing through the shallow silicon layer, and process damage near the separation surface. Front-end implantation places the main helium ion damage peak deep within the damaged layer, ensuring that the highly damaged area largely leaves with the donor wafer after separation. The stripping heat treatment maintains separation under low hydrogen dosage conditions through a combination of depth difference and initial heating rate. Post-treatment is used to refine the separation surface and further remove surface damage.

[0083] Based on the processing results, multiple parameter points within a depth difference range of 30nm to 100nm can achieve a depth of no more than 500cm. - The density of top-layer silicon etch pits is approximately 200 cm². Under representative conditions with a depth difference of approximately 60 nm, a depth of less than 200 cm² can be achieved. - The pit density was controlled at 216.5 nm to 223.5 nm, and the top silicon thickness was controlled within this range. Compared to conditions outside the range of 15 nm or 130 nm, the above results demonstrate the combined influence of implantation peak spatial relationship, stripping heat treatment, and post-processing on the final wafer defect level.

[0084] Waveguides are typically formed directly within the top silicon layer. Dislocations, vacancies, and other lattice defects within this layer can scatter the propagating light field. For devices such as modulators and detectors, defect-related traps can also affect carrier lifetime, response speed, and conversion efficiency. Therefore, the defect level in the top silicon layer is not only a material indicator during wafer fabrication but also influences the performance of subsequent optical and electrical devices. For products with a top silicon layer thickness of approximately 220 nm, a lower pit density provides a material basis for lower defects in subsequent device fabrication.

[0085] Ion implantation damage needs to be considered in conjunction with the implantation location, implantation dose, and separation process. Both hydrogen and helium ions create traversing damage along the path from the implantation surface to their respective implantation peaks, while a higher density damage region forms near the implantation peaks; subsequently, bubble propagation and crack propagation also create process damage near the separation surface. This disclosure controls damage from these different sources by controlling the implantation location, implantation dose, exfoliation heat treatment, and post-separation material removal.

[0086] The asymmetric implantation relationship, where helium ion dosage is greater than hydrogen ion dosage, is used in conjunction with the implantation peak position relationship. A lower hydrogen dosage is used to reduce hydrogen penetration damage in the silicon layer to be transferred; a higher helium dosage is used to maintain separation assistance. Simultaneously, the helium ion implantation peak is located on the deeper side, ensuring that the main damage area is primarily located on the donor wafer side after separation. Therefore, the dosage relationship and spatial position relationship should be understood together.

[0087] The lower limit of the depth difference corresponds to the spatial condition under which the main damage area caused by helium ions can be moved away from the vicinity of the ultimately preserved silicon layer. When the depth difference is 0 nm, the main distribution areas of the two ions highly overlap, and the density of top-layer silicon etch pits in existing experiments is greater than 5000 cm⁻¹. - ²; When the depth difference is about 15nm, although the separation success rate is relatively high, the density of silicon etch pits in the top layer is still greater than 1000cm². - ²; When the depth difference increases to 30 nm, the pit density decreases to 200 cm². - 2~500cm - ². Thus, a transition boundary is formed around 30 nm, from the near-field overlapping state to the main helium damage region penetrating deep into the damage layer.

[0088] The upper limit of the depth difference corresponds to whether the assistance of helium ions in the separation process can be effectively transferred to the hydrogen ion-related damage layer within a limited thermal history. When the depth difference increases from 60 nm to 80 nm and 100 nm, the main damage area caused by helium ions can continue to move away from the final top silicon layer, but the distance that helium atoms need to cross during the heating process also increases. The separation success rate in related experiments gradually decreased from greater than 99% to greater than 95% and greater than 90%; when the depth difference reaches about 130 nm, the separation success rate drops below 70%. This result indicates that simply continuing to increase the depth difference does not continuously improve the overall process results.

[0089] The initial heating stage is used to convert the spatial distance formed in the front-end process into the time conditions for subsequent heat treatment. Using 150°C to 300°C as the temperature window where helium atoms migrate more easily, a lower heating rate results in a longer residence time for the wafer within that temperature window. For shorter migration distances of 30nm to 50nm, a heating rate of 2°C / min to 5°C / min can be used; when the depth difference increases to greater than or equal to 60nm but less than 80nm, the allowable upper limit can be reduced to 3°C / min; when the depth difference further reaches 80nm to 100nm, the allowable upper limit is still controlled within 3°C / min.

[0090] Within a depth difference range of 50nm to 70nm, the spatial separation of the main helium-damaged region and the final top silicon layer can be balanced, as well as the migration distance during annealing. At a representative parameter point of approximately 60nm, the helium ion implantation peak is located at approximately 310nm, and the hydrogen ion implantation peak is located at approximately 250nm, coupled with an initial heating rate of 2°C / min to 3°C / min. The separation success rate at this parameter point is greater than 99%, the surface roughness Ra after furnace tube separation can be less than 0.3nm, and the pit density of the post-processed top silicon layer can be less than 200cm². - ².

[0091] For 300mm wafers, controlling the top silicon thickness involves not only the average thickness but also the thickness consistency across different locations on the wafer. By first determining the initial transfer silicon layer position using the hydrogen ion implantation peak, and then gradually consuming the surface silicon through multiple sacrificial oxidation processes, the final thickness can be corrected while avoiding large-scale material removal at once. Under existing complete processing conditions, the final top silicon thickness can be controlled within the range of 216.5nm to 223.5nm. This is achieved with a depth difference of approximately 60nm and a hydrogen ion dose of approximately 0.5 × 10⁻⁶. 16 cm -2 The representative combination still has process margin under certain parameter fluctuations, which is conducive to forming repeatable process windows in wafer manufacturing.

[0092] The post-separation surface treatment is sequential with the aforementioned ion implantation and stripping steps. RTA primarily utilizes surface atomic migration at high temperatures to improve the morphology of the separated surface and does not perform the main material removal function. RTO sacrificial oxidation converts some of the silicon near the separation surface into SiO2, and then removes the resulting oxides by HF, thereby gradually consuming the surface silicon containing more damage from the separation process. Each cycle can consume approximately 5nm~10nm of silicon, and 2~4 cycles correspond to a total removal amount on the order of approximately 20nm~30nm.

[0093] The final wafer is assessed using two parameters that directly correspond to the product state: top silicon thickness and top silicon etch pit density. Top silicon thickness primarily reflects the initial separation position determined by ion implantation and the end point of post-processing, while etch pit density comprehensively reflects ion penetration damage, the location of the main helium ion damage area, separation surface process damage, and remaining crystal defects after post-processing. Therefore, when comparing the examples and comparative examples, even if the two sets of wafers have the same final thickness, the difference in final crystal quality caused by the front-end implantation position and dosage relationship can be observed through etch pit density.

[0094] The representative condition of a depth difference of approximately 60 nm does not employ a lower total hydrogen / helium injection rate compared to conventional near-field co-injection. Its total injection rate is approximately 1.75 × 10¹ 6 cm - ² Increased to approximately 2.5 × 10¹ 6 cm- ², an increase of approximately 43%; the increase mainly comes from helium ions located deep within the damaged layer, while the hydrogen ion dose increased from approximately 1.0 × 10¹. 6 cm - ² decreased to approximately 0.5 × 10¹ 6 cm - ². Correspondingly, the density of top-layer silicon etch pits under conventional near-field conditions is greater than 1000 cm⁻¹. - ², the aforementioned representative condition can then be reduced to 200cm. - Below 2. This result reflects the engineering trade-offs in optimizing the final top-layer silicon quality through flux allocation and spatial positioning.

[0095] The depths of the two ion implantation peaks can be determined relative to the same reference position to avoid inconsistent expression of positional relationships caused by different surface oxide layer thicknesses. In the case of forming the first silicon oxide layer 120, the SiO2 / Si interface between the first silicon oxide layer 120 and the donor wafer 100 can be used as a depth reference; the hydrogen ion implantation peak is located approximately 240 nm to 260 nm below this interface, and the helium ion implantation peak is located approximately 280 nm to 350 nm below this interface.

[0096] When helium ion implantation is performed first, followed by hydrogen ion implantation, a deeper helium ion distribution forms initially within the donor sheet. Subsequently, hydrogen ions form a distribution closer to the implantation side, which is relevant to subsequent separation. This sequence allows the initial implantation stage to establish a deep helium-related damage region before utilizing hydrogen ions to form defect precursors at the target separation depth. For subsequent heat treatment, the two ions have already formed a clear spatial misalignment before heating begins. Therefore, a heating formula matching the depth difference can be directly selected after determining the implantation formula, without needing to alter the spatial relationship between the two ions after bonding.

[0097] The insulating layer 300 is not only used to form the insulating buried layer of the final silicon-on-insulator structure, but also serves as an important structure for determining the lower boundary of the silicon layer 130 to be transferred during the fabrication process. The damaged layer 150 is located on the side of the silicon layer 130 away from the insulating layer 300, so after separating the donor wafer 100 along the damaged layer 150, the silicon layer 130 still maintains its bond with the insulating layer 300 and the substrate 200. By first forming oxide layers on the donor wafer 100 and the substrate 200 respectively and then performing bonding, the stacking relationship of the top silicon, the insulating buried layer, and the substrate can be obtained directly after separation, avoiding the need to insert insulating material separately after the thin-layer transfer is completed.

[0098] The working window of this disclosure is not simply to pursue the deeper the helium ion implantation peak. When approaching the lower boundary of 30 nm, the main goal is to ensure that the high-damage region of helium ions is sufficiently offset from the final retained silicon layer; when approaching the upper boundary of 100 nm, it is necessary to pay attention to whether helium atoms can cross a relatively long distance within the initial heating window, and whether the influence of the deep damage region on the fracture conditions near the damaged layer is still sufficient.

[0099] Once the top silicon thickness reaches 216.5nm~223.5nm, sacrificial oxidation can be stopped to avoid the top silicon thickness falling below the target thickness due to excessive cycle counts. Since the silicon consumption per cycle is approximately 5nm~10nm, the thickness range after the next cycle can be estimated based on the previous thickness measurement results, and a decision can be made whether to continue processing accordingly. This thickness closed-loop process is integrated with the process of determining the initial transfer layer thickness through ion implantation depth, ensuring that the final thickness is controlled by the hydrogen ion implantation peak position and can be further adjusted through post-processing.

[0100] In the above processing chain, the result of the previous process serves as the direct input for the next process. The depth difference formed by ion implantation is used to select the initial heating conditions; the insulating layer formed by bonding is used to define the hierarchical relationship between the transferred silicon layer and the substrate; the damage layer formed by the peeling heat treatment is used to determine the actual separation path; and the initial silicon layer thickness and surface condition obtained by separation are used to determine the number of post-processing cycles.

[0101] To compare different spatial configurations and dosage conditions within the same observation framework, Table 1 lists 12 examples and 6 comparative examples. When the top silicon thickness and top silicon etch pit density in Table 1 are expressed as ranges, they represent the measured results intervals at different measurement or sampling locations on the same wafer, rather than single values ​​at a single measurement point. The top silicon thickness in Table 1 is the measured result after post-processing; during post-processing, the measured top silicon thickness is used to determine whether to continue the next sacrificial oxidation cycle.

[0102] Table 1. Input parameters and wafer output parameters for the examples and comparative examples.

[0103] Comparative Examples 1 and 2, as well as Examples 1-3, show that when the implantation doses of helium ions and hydrogen ions are maintained at 2.0 × 10⁻⁶, the optimal results are achieved. 16 cm -2 and 0.5×10 16 cm -2 When the initial heating rate is 3°C / min and the post-processing conditions are basically the same, when the depth difference between the two ion implantation peaks increases from 0 nm and 15 nm to 30 nm, 50 nm and 60 nm, the density of top-layer silicon etch pits increases from greater than 5000 cm⁻¹.-2 and greater than 1000cm -2 Enter 200cm in sequence -2 ~500cm -2 100cm -2 ~300cm -2 and less than 200cm -2 The range of depth differences can be observed. Therefore, while maintaining other key process conditions, shifting the helium ion implantation peak from near the hydrogen ion implantation peak towards deeper layers can reduce the retention of the primary helium ion damage area on the final top silicon side. When the depth difference exceeds 30 nm, the top silicon etch pit density can be reduced to 500 cm⁻¹. -2 the following.

[0104] From Examples 3 to 5 and Comparative Example 3, it can be seen that when the helium ion dose is maintained at 2.0 × 10⁻⁶, 16 cm -2 The hydrogen ion dose is maintained at 0.5 × 10⁻⁶. 16 cm -2 With an initial heating rate maintained at 3°C / min, the top-layer silicon etch pit densities were less than 200 cm⁻¹ when the depth differences were 60 nm, 80 nm, and 100 nm, respectively. -2 100cm -2 ~300cm -2 and 200cm -2 ~500cm -2 When the depth difference further increases to 130nm, the top silicon etch pit density of Comparative Example 3 is greater than 1000cm². -2 Therefore, it can be concluded that further increasing the distance between the two injection peaks will not continuously improve the final wafer state. The depth difference range of 30nm~100nm can form an feasible parameter window between the main helium ion damage region being far away from the top silicon and the subsequent stripping heat treatment.

[0105] As can be seen from Comparative Example 4 and Example 3, the final top silicon thickness of both can reach 216.5nm~223.5nm, but the top silicon etch pit density of Comparative Example 4 is greater than 1000cm². -2 In Example 3, the density of silicon etch pits in the top layer is less than 200 cm³. -2 Comparative Example 4 employed a smaller implantation peak depth difference and different helium and hydrogen ion dosage relationships, while Example 3 placed the helium ion implantation peak deep to the hydrogen ion implantation peak and used stripping heat treatment conditions that matched this depth difference. This demonstrates that, with the same final top silicon thickness, the spatial relationship and dosage configuration of ion implantation still affect the crystal defect level of the final top silicon. Therefore, the final thickness alone cannot evaluate the impact of the front-end implantation and stripping processes on wafer quality.

[0106] From Examples 1 to 5, it can be seen that within a depth difference range of 30nm to 100nm, the parameter points for which pit density records have been obtained are all within a depth of no more than 500cm. -2 The range, where a 60nm depth difference corresponds to less than 200cm in Example 3. -2 Examples 6 to 12 are used to further cover the endpoints or intermediate values ​​of injection dose, injection energy, depth difference, heating rate, holding time, and post-processing parameters.

[0107] Comparative Example 6 illustrates the effect of insufficient post-processing cycles. The pre-processing ion implantation and stripping heat treatment conditions for Comparative Example 6 were the same as in Example 3, except that the number of sacrificial oxidation and sacrificial oxide layer removal processes was reduced to one. Table 1 shows the measured top silicon thickness range of this comparative wafer after one post-processing cycle (215nm~225nm), with a top silicon pit density greater than 1000 cm⁻¹. - ². Compared with the post-processing results of Example 3, this result shows that under the above process conditions, when only one sacrificial oxidation and oxide layer removal treatment is performed, the removal effect on residual damage near the separation surface is weak.

[0108] like Figure 8 As shown, wafer 500 is formed after the above-described thin-layer transfer and post-processing. Wafer 500 includes a substrate 200, an insulating layer 300 disposed on the substrate 200, and a silicon layer 130 disposed on the insulating layer 300, wherein the silicon layer 130 constitutes the top silicon layer, and the insulating layer 300 constitutes an insulating buried layer. In one product embodiment, the thickness of the top silicon layer is 216.5 nm to 223.5 nm, and the top silicon etch pit density is not higher than 500 cm⁻¹. -2 In further product conditions, the density of top-layer silicon etch pits can be less than 200 cm⁻¹. -2 .

[0109] For the thickness of the top silicon layer, an ellipsometry can be used to measure at multiple radial and circumferential positions on the wafer to evaluate the thickness level and uniformity within a 300mm range. For the pit density, it can be statistically analyzed based on the number of pits per unit area after the crystal defects have been appropriately revealed. The etching solution system, etching time, inspection area, and wafer sampling location can all affect the statistical results; therefore, uniform testing conditions should be used during product testing.

[0110] Based on the above processing flow and the comparison results in Table 1, it can be seen that positioning the helium ion implantation peak deep to the hydrogen ion implantation peak, and configuring the initial heating conditions for the stripping heat treatment according to the depth difference between the two implantation peaks, is beneficial for reducing crystal defects in the final top silicon layer while completing the silicon layer transfer. Under representative parameter conditions, the top silicon thickness can reach 216.5 nm to 223.5 nm, and the top silicon etch pit density can be controlled at 500 cm⁻¹.-2 The following parameters may be less than 200cm. -2 .

[0111] When helium ion implantation is performed first, followed by hydrogen ion implantation, a deeper helium ion distribution forms initially within the donor sheet. Subsequently, hydrogen ions form a distribution closer to the implantation side, which is relevant to subsequent separation. This sequence allows the initial implantation stage to establish a deep helium-related damage region before utilizing hydrogen ions to form defect precursors at the target separation depth. For subsequent heat treatment, the two ions have already formed a clear spatial misalignment before heating begins. Therefore, a heating formula matching the depth difference can be directly selected after determining the implantation formula, without needing to alter the spatial relationship between the two ions after bonding.

[0112] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0113] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for processing silicon on an insulator, characterized in that, include: A donor sheet is provided, the surface of which has a first silicon oxide layer; Helium ion implantation is performed from the first silicon oxide layer into the donor sheet at a first dose, forming a helium ion implantation peak within the donor sheet; Hydrogen ion implantation is performed from the first silicon oxide layer into the donor sheet at a second dose, forming a hydrogen ion implantation peak within the donor sheet, and the depth at which the hydrogen ion implantation peak is located constitutes the target stripping surface. The helium ion implantation peak is located below the target stripping surface, and the first dose is greater than the second dose; A substrate is provided, the surface of which has a second silicon oxide layer; The first silicon oxide layer and the second silicon oxide layer are bonded together to obtain a bonded structure; The bonding structure is subjected to a peeling heat treatment to peel the donor sheet along the target peeling surface to obtain an initial silicon-on-insulator structure, which includes a supporting substrate, an insulating buried layer, and a top silicon layer. The damaged layer on the surface of the top silicon layer is removed by rapid thermal annealing. The exfoliation heat treatment includes an initial heating stage, the heating rate of which is determined based on the depth difference between the helium ion implantation peak and the hydrogen ion implantation peak, and a damage layer for exfoliation is formed in the region of the donor sheet corresponding to the hydrogen ion implantation peak.

2. The method for processing silicon on an insulator according to claim 1, characterized in that, The first dose is 1.0 × 10¹ 6 cm - ²~3.0×10¹ 6 cm - ²; The second dose is 0.5 × 10¹ 6 cm - ²~0.8×10¹ 6 cm - ².

3. The method for processing silicon on an insulator according to claim 1, characterized in that, The depth difference between the helium ion implantation peak and the hydrogen ion implantation peak is 30 nm to 100 nm.

4. The method for processing silicon on an insulator according to claim 1, characterized in that, The heating rate in the initial heating stage is determined based on the depth difference according to the following relationship: When the depth difference is 30nm~50nm, the heating rate is 2°C / min~5°C / min; When the depth difference is greater than or equal to 60 nm and less than 80 nm, the heating rate is 2°C / min to 3°C / min; When the depth difference is 80nm~100nm, the heating rate is no greater than 3°C / min.

5. The method for processing silicon on an insulator according to claim 1, characterized in that, The donor sheet has a first silicon oxide layer on its implantation side, and the substrate has a second silicon oxide layer; The first silicon oxide layer and the second silicon oxide layer are bonded together to form the insulating buried layer, wherein the thickness of the first silicon oxide layer is 200 nm and the thickness of the second silicon oxide layer is 2300 nm.

6. The method for processing silicon on an insulator according to claim 5, characterized in that, The helium ion implantation energy is 60 keV~75 keV, and the hydrogen ion implantation energy is 45 keV~50 keV.

7. The method for processing silicon on an insulator according to claim 1, characterized in that, The stripping heat treatment includes: The bonding structure is heated to 350°C and held at 350°C for 10 min to 30 min. After holding at 350°C, continue heating to 500°C and hold at 500°C for 10 to 30 minutes.

8. The method for processing silicon on an insulator according to claim 1, characterized in that, After the donor wafer is peeled off along the target peeling surface, the top silicon layer remaining on one side of the substrate wafer is subjected to rapid thermal annealing and sacrificial oxidation treatment in sequence, and the sacrificial oxide layer formed by the sacrificial oxidation treatment is removed. The rapid thermal annealing temperature is 1100°C~1300°C, and the processing time is 10s~60s; the sacrificial oxidation treatment temperature is 900°C~1100°C, and the processing time is 30s~90s.

9. The method for processing silicon on an insulator according to claim 8, characterized in that, The sacrificial oxide layer is removed using an HF solution with a concentration of 1% to 20%, and the sacrificial oxide treatment and the removal of the sacrificial oxide layer are repeated 2 to 4 times to achieve a thickness of 216.5 nm to 223.5 nm for the top silicon layer.

10. A wafer, characterized in that, The wafer is fabricated using the silicon-on-insulator (SOI) processing method according to any one of claims 1 to 9. The wafer includes a substrate, an insulating buried layer disposed on the substrate, and a top silicon layer disposed on the insulating buried layer. The thickness of the top silicon layer is 216.5 nm to 223.5 nm, and the pit density of the top silicon layer is not greater than 500 cm⁻¹. -2 .

11. The wafer according to claim 10, characterized in that, The pit density of the top silicon layer is less than 200 cm⁻¹ -2 .

Images