A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof, including: providing a semiconductor structure, the semiconductor structure including a first region and a second region, the first region and the second region both including a substrate, a hard mask layer, an isolation structure and a trench, the hard mask layer being located on the substrate, the trench extending through the hard mask layer and extending into the substrate by a partial depth, and the isolation structure being filled in the trench, wherein the width of the trench in the first region is greater than the width of the trench in the second region, and the top surface of the isolation structure in the first region has a dish-shaped recess; etching to remove part of the isolation structure in the first region and the second region, so that the lowest point of the etched dish-shaped recess is not higher than the top surface of the isolation structure in the second region, and part of the substrate in the first region is exposed; oxidizing the exposed substrate into a protective layer through a thermal oxidation process; forming a doped region in the substrate and performing an annealing treatment, wherein the protective layer is used to block the annealing gas in the annealing treatment from contacting the substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for fabricating the same. Background Technology

[0002] With the increasing integration and performance requirements of semiconductor devices, electrical isolation between devices has become a key factor affecting device reliability and yield. Shallow Trench Isolation (STI) technology is widely used. Its process includes: sequentially forming a pad oxide layer and a silicon nitride layer on the substrate surface; etching the silicon nitride layer, pad oxide layer, and substrate to form an isolation trench; filling the isolation trench with an isolation medium such as silicon oxide; and removing excess isolation medium through chemical mechanical polishing (CMP) to achieve surface planarization. In this process, the chemical mechanical polishing process has a significant impact on the morphology of the shallow trench isolation, the remaining thickness of the silicon nitride layer, and the subsequent process window.

[0003] In existing shallow trench isolation (STI) processes, chemical mechanical polishing (CMP) typically employs a cerium oxide-containing polishing slurry. Due to the properties of this slurry, larger areas of silicon oxide (the material typically used in STIs) tend to form larger disc-shaped depressions compared to smaller areas. This significantly reduces the height of the STI and the thickness of the hard mask layer in these disc-shaped depression areas. Consequently, when adjusting the STI height using wet etching, over-etching of these areas can easily lead to exposure of the substrate beneath the hard mask layer. The exposed substrate reacts during subsequent ion implantation and annealing processes, such as reacting with gases in the furnace tube, resulting in damage defects that negatively impact device performance and yield.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for fabricating a semiconductor device, comprising: providing a semiconductor structure including a first region and a second region, both the first and second regions including a substrate, a hard mask layer, an isolation structure, and a trench, the hard mask layer being located on the substrate, the trench penetrating the hard mask layer and extending a certain depth into the substrate, the isolation structure filling the trench, wherein the width of the trench in the first region is greater than the width of the trench in the second region, and the top surface of the isolation structure in the first region has a dish-shaped recess; etching away portions of the isolation structure in the first and second regions such that the lowest point of the etched dish-shaped recess is not higher than the top surface of the isolation structure in the second region, and exposing a portion of the substrate in the first region; oxidizing the exposed substrate into a protective layer using a thermal oxidation process; forming a doped region in the substrate and performing an annealing treatment, wherein the protective layer serves to prevent annealing gases during the annealing treatment from contacting the substrate.

[0007] For example, the material of the protective layer includes silicon oxide.

[0008] For example, the thermal oxidation process is an in-situ water vapor generation oxidation process.

[0009] For example, the hard mask layer includes a first hard mask layer and a second hard mask layer located on the first hard mask layer, and before forming the doped region, the process further includes: removing the second hard mask layer.

[0010] For example, the step of forming a doped region in the substrate and performing an annealing process includes: forming a patterned mask layer on the isolation structure, the patterned mask layer exposing at least a portion of the first hard mask layer between adjacent isolation structures; forming a doped region in the substrate by an ion implantation process using the patterned mask layer as a mask, wherein the doped region is located in the substrate between adjacent isolation structures; removing the patterned mask layer and performing the annealing process.

[0011] For example, the material of the first hard mask layer includes silicon oxide, and the material of the second hard mask layer includes silicon nitride.

[0012] For example, the method of forming the isolation structure includes: forming an isolation layer covering the hard mask layer and filling the trenches in the first region and the second region; performing a planarization process on the isolation layer until the hard mask layer is exposed to form the isolation structure in the trenches in the first region and the second region, wherein the top surface of the first region after the planarization process has the dish-shaped recess.

[0013] For example, a wet etching process is used to etch away portions of the isolation structure in the first region and the second region.

[0014] For example, the substrate is made of silicon, and the isolation structure is made of silicon oxide.

[0015] This application also provides a semiconductor device, which is fabricated using the aforementioned method. The semiconductor device includes: a semiconductor structure comprising a first region and a second region, both the first and second regions including a substrate, a hard mask layer, an isolation structure, and a trench; the hard mask layer being located on the substrate; the trench penetrating the hard mask layer and extending a certain depth into the substrate; the isolation structure filling the trench; wherein the width of the trench in the first region is greater than the width of the trench in the second region; and the top surface of the isolation structure in the first region having a dish-shaped recess; a protective layer located on the substrate surface between adjacent isolation structures in the first region; and a doped region located in the substrate.

[0016] The semiconductor device and its fabrication method provided in this application, after etching away part of the isolation structure and exposing part of the substrate in the first region, utilize a thermal oxidation process to oxidize the exposed substrate into a protective layer. This protective layer effectively blocks annealing gases from contacting the substrate during subsequent annealing processes, preventing annealing gases from eroding and damaging the substrate, thereby suppressing the generation of damage defects and improving device reliability and yield. Furthermore, this application eliminates the need for excessive adjustment of the chemical mechanical planarization process window, avoiding residual defects in the isolation material, and features a simple process with good compatibility. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0018] In the attached image: Figures 1A to 1D A schematic diagram of the semiconductor device obtained by sequentially implementing the semiconductor device fabrication method of the related technology of this application is shown; Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown; Figures 3A to 3E The diagram illustrates a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0019] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0021] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] See attached document Figures 1A-1D The fabrication methods of semiconductor devices in related technologies are explained.

[0025] First, such as Figure 1A As shown, the semiconductor structure includes a first region 101 and a second region 102. Both the first region 101 and the second region 102 include a substrate 10, a hard mask layer (including a silicon dioxide layer 11 and a silicon nitride layer 12 thereon), and an insulating dielectric. The hard mask layer is located on the substrate 10, and a trench 13 penetrates the hard mask layer and extends a certain depth into the substrate. The insulating dielectric is located on the hard mask layer and fills the trench 13. The size of the trench 13 in the first region 101 is larger than the size of the trench 13 in the second region 102. Therefore, the trench 13 in the first region 101 is filled with more insulating dielectric than the trench 13 in the second region 102.

[0026] Then, as Figure 1A As shown, the insulating medium is polished to expose the hard mask layer, thereby forming a shallow trench isolation 14 in the trench 13. Since the trench 13 in the first region 101 is filled with more insulating medium than that in the second region 102, after polishing the insulating medium to form the shallow trench isolation 14, a dish-shaped depression is typically formed on the upper surface of the first region 101. This results in a thinner hard mask layer in the first region 101 compared to the hard mask layer in the second region 102, and a lower height of the shallow trench isolation 14 in the first region 101 (in the thickness direction of the substrate 10, i.e., ...). Figure 1A The height of the trench isolation 14 in the middle and upper directions is lower than that of the shallow trench isolation 14 located in the second region 102.

[0027] Then, as Figure 1BAs shown, shallow trench isolation 14 located in the first region 101 and the second region 102 is etched to adjust the height of the shallow trench isolation 14. During this process, the height of the shallow trench isolation 14 removed by etching (i.e.,...) Figure 1B H1 in the first region 101 is likely greater than the height of the remaining hard mask layer (i.e., Figure 1B H2 in the first region 101 causes the substrate 10 to be exposed after etching ( Figure 1B (As shown in the dashed box).

[0028] Finally, as Figure 1C and Figure 1D As shown, the silicon nitride layer 12 is removed, and the substrate 10 is subjected to ion implantation (the ion implantation area is not shown in the figure) and annealing. In the annealing process after ion implantation, the exposed substrate 10 is prone to react with the ambient gas, forming defects 15.

[0029] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps: Step S1, providing a semiconductor structure, the semiconductor structure including a first region and a second region, both the first region and the second region including a substrate, a hard mask layer, an isolation structure and a trench, the hard mask layer being located on the substrate, the trench penetrating the hard mask layer and extending into the substrate to a certain depth, the isolation structure filling the trench, wherein the width of the trench in the first region is greater than the width of the trench in the second region, and the top surface of the isolation structure in the first region has a dish-shaped recess; Step S2: Etch away part of the isolation structure in the first region and the second region so that the lowest point of the etched dish-shaped recess is not higher than the top surface of the isolation structure in the second region, and expose part of the substrate in the first region. Step S3: The exposed substrate is oxidized into a protective layer through a thermal oxidation process; Step S4: A doped region is formed in the substrate and annealing is performed, wherein a protective layer is used to prevent the annealing gas from contacting the substrate during the annealing process.

[0030] The semiconductor device and its fabrication method according to embodiments of this application involve etching away a portion of the isolation structure and exposing a portion of the substrate in the first region, followed by thermal oxidation to oxidize the exposed substrate into a protective layer. This protective layer effectively blocks annealing gases from contacting the substrate during subsequent annealing processes, preventing annealing gases from eroding and damaging the substrate, thereby suppressing the generation of damage defects and improving device reliability and yield. Furthermore, this application eliminates the need for excessive adjustment of the chemical mechanical planarization process window, avoiding residual defects in the isolation material, and features a simple process with good compatibility.

[0031] Example 1 Below, for reference Figure 2 as well as Figures 3A to 3E The method for fabricating the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for fabricating a semiconductor device according to a specific embodiment of this application is shown. Figures 3A to 3E The diagram illustrates a semiconductor device obtained by sequentially implementing a method for fabricating a semiconductor device according to a specific embodiment of this application.

[0032] For example, such as Figure 2 As shown, the method for fabricating the semiconductor device of this application includes the following steps: First, step S1 is performed to provide a semiconductor structure, which includes a first region and a second region. Both the first and second regions include a substrate, a hard mask layer, an isolation structure, and a trench. The hard mask layer is located on the substrate, and the trench penetrates the hard mask layer and extends into the substrate to a certain depth. The isolation structure fills the trench. The width of the trench in the first region is greater than the width of the trench in the second region. The top surface of the isolation structure in the first region has a dish-shaped recess.

[0033] In one example, the semiconductor structure includes a first region 201 and a second region 202, which are regions located at different positions within the semiconductor structure. Exemplarily, the first region 201 can be a region with a large isolation structure size and high isolation structure density, such as a region for forming power devices, high-voltage devices, or device termination areas, where a large isolation spacing is required. The second region 202 can be a region with a small isolation structure size and low isolation structure density, such as a region for forming logic devices, memory devices, or low-voltage devices, where a small isolation spacing is required. The isolation structure density can refer to the area ratio occupied by the isolation structure within the corresponding region. The first region 201 and the second region 202 can be different device regions within the same semiconductor device, without specific limitations. It should be understood that the specific number, location, and area of ​​the regions can be set according to the actual device layout. The above is only an exemplary division, and the technical solution of this application is also applicable to other semiconductor structures with differences in trench size or pattern density.

[0034] In one example, such as Figure 3AAs shown, both the first region 201 and the second region 202 include a substrate 20. The material of the substrate 20 includes, but is not limited to, at least one of the following: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate. Although several examples of materials that can form a substrate have been described herein, any material that can serve as a substrate falls within the spirit and scope of the invention. In this embodiment, the substrate 20 is a silicon substrate.

[0035] In one example, both the first region 201 and the second region 202 include a hard mask layer 21. The hard mask layer 21 is formed on the substrate 20. The hard mask layer 21 includes a first hard mask layer 22 and a second hard mask layer 23 located on the first hard mask layer 22. That is, the first hard mask layer 22 is first formed on the substrate, and then the second hard mask layer 23 is formed to cover the first hard mask layer 22. Exemplarily, the first hard mask layer 22 can be formed on the substrate 20 using processes including but not limited to low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), or atomic layer deposition (ALD). The material of the first hard mask layer 22 includes, but is not limited to, silicon oxide. Exemplarily, a second hard mask layer 23 can be formed on the first hard mask layer 22 using processes including but not limited to low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), or atomic layer deposition (ALD). The material of the second hard mask layer 23 includes, but is not limited to, silicon nitride. The first hard mask layer can serve as a buffer layer to buffer the stress between the second hard mask layer and the substrate, and as a transition layer between the second hard mask layer and the substrate to facilitate the subsequent removal of the second hard mask layer. It can also protect the substrate during processes such as ion implantation. The second hard mask layer can serve as an etching mask when etching trenches, as a stop layer in the chemical mechanical planarization process to control the planarization endpoint and the top height of the isolation structure, and as a barrier layer to prevent the oxidizing atmosphere from oxidizing the unexposed substrate in subsequent thermal oxidation processes.

[0036] In one example, such as Figure 3AAs shown, both the first region 201 and the second region 202 have trenches 24. The trenches 24 penetrate the hard mask layer 21 and extend into the substrate 20 to a certain depth. That is, the trenches 24 penetrate the first hard mask layer 22 and the second hard mask layer 23 and extend into the substrate 20 to a certain depth. Specifically, the steps for forming the trench 24 include: First, forming a patterned photoresist layer on the hard mask layer 21, with the patterned photoresist layer exposing a portion of the hard mask layer 21. The exposed portion of the hard mask layer corresponds to the location of the trench to be formed in the first region 201 and the second region 202. The patterned photoresist layer can be formed by processes such as photoresist coating, exposure, and development. Next, using the patterned photoresist layer as a mask, etching the second hard mask layer 23 and the first hard mask layer 22 to form an opening penetrating the second hard mask layer 23 and the first hard mask layer 22. Subsequently, removing the photoresist layer, using the etched hard mask layer 21 as a mask, continuing to etch the exposed substrate 20 to form a groove in the substrate 20. The opening and the groove below together constitute the trench 24, that is, the trench 24 penetrates the hard mask layer 21 and extends a certain depth into the substrate 20. Dry etching can be used to etch the hard mask layer and the substrate. Dry etching can be conventional etching processes such as reactive ion etching (RIE), ion beam etching, or plasma etching.

[0037] In other examples, the trench 24 can also be formed as follows: a patterned photoresist layer is formed on the hard mask layer 21; using the patterned photoresist layer as a mask, a one-step etching process is used to continuously etch the second hard mask layer 23, the first hard mask layer 22, and the substrate 20, directly forming a trench 24 that penetrates the hard mask layer 21 and extends to a certain depth within the substrate 20; subsequently, the patterned photoresist layer is removed. Exemplarily, the one-step etching process can be performed within the same etching chamber, and the etching gas and etching conditions can be switched according to the different materials being etched, for example, etching gases suitable for silicon nitride, silicon oxide, and silicon can be used sequentially to achieve continuous etching. Using the above method eliminates the steps of separately etching the hard mask layer, removing the photoresist, and then etching the substrate, simplifying the process and improving production efficiency.

[0038] It is worth mentioning that after the trench 24 is formed, it can be cleaned to remove etching byproducts and damaged layers on the sidewalls and bottom of the trench. Optionally, an oxide layer can also be formed on the sidewalls and bottom of the trench 24 to repair etching damage and improve the interface quality between the subsequent filling isolation medium and the substrate.

[0039] In one example, the size of the groove 24 in the first region 201 is larger than the size of the groove 24 in the second region 202. Exemplarily, the size of the groove 24 is the width of the groove 24, i.e., the groove 24 in the first direction (i.e.,...) Figure 3AThe dimensions in the horizontal direction (i.e., left-right direction) are parallel to the surface of the substrate 20. Specifically, the width of the trench 24 in the first region 201 is greater than the width of the trench 24 in the second region 202. It can be understood that the larger the width of the trench 24, the larger the area ratio occupied by the isolation structure 25 within the trench 24, the higher the density of the isolation structure 25 in the first region 201, and correspondingly, the smaller the area ratio occupied by the hard mask layer 21. During chemical mechanical planarization, wide trench regions are more prone to dish-shaped depressions, which makes the hard mask layer 21 in the first region 201 more susceptible to wear, thus exposing part of the substrate 20 after subsequent etching to adjust the step height. It should be understood that the dimensions of the trench 24 can also be at least one of the depth, length, or opening area of ​​the trench 24; this embodiment only uses the width of the trench 24 as an example for explanation.

[0040] In one example, both the first region 201 and the second region 202 include an isolation structure 25, which fills the trench 24. The specific steps for forming the isolation structure 25 include: first, forming an isolation layer that covers the hard mask layer 21 and fills the trench 24 of the first region 201 and the second region 202. The isolation layer can be formed using processes including but not limited to chemical vapor deposition (CVD) or atomic layer deposition (ALD). After forming the isolation layer, the isolation layer can be densified to improve the density and stability of the isolation structure 25. Subsequently, a planarization process is performed on the isolation layer until the hard mask layer 21 is exposed, so as to form the isolation structure 25 in the trench 24 of the first region 201 and the second region 202. The planarization process can be a chemical mechanical polishing (CMP) process, which can use a polishing slurry containing cerium dioxide, and remove the excess isolation layer above the hard mask layer 21, for example, using the second hard mask layer 23 as the stop layer, thereby forming the isolation structure 25. For example, the material of the isolation structure 25 includes, but is not limited to, silicon oxide.

[0041] Because the width of the groove 24 in the first region 201 is greater than the width of the groove 24 in the second region 202, the area occupied by the isolation structure 25 in the first region 201 is larger. Therefore, during the planarization process, the first region 201 is more prone to over-grinding. Consequently, the top surface of the isolation structure in the first region 201 after the planarization process has a dish-shaped recess 26 (e.g., ...). Figure 3A(As shown in the dashed box), the top surface of the isolation structure 25 in the first region 201 is lower than the top surface of the isolation structure 25 in the second region 202, and also lower than the top surface of the hard mask layer 21. This dish-shaped recess provides the conditions for exposing the substrate 20 of the first region 201 after subsequent etching to adjust the step height. The existence of the dish-shaped recess 26 makes the thickness of the hard mask layer 21 in the first region 201 smaller than the thickness of the hard mask layer 21 in the second region 202. The height of the isolation structure 25 in the first region 201 (in the substrate thickness direction, i.e., Figure 3A The height of the structure in the vertical direction is lower than the height of the isolation structure 25 located in the second region 202. For example, the structure can be cleaned after the planarization process to remove grinding slurry residue and grinding byproducts.

[0042] Next, step S2 is performed to etch away part of the isolation structure in the first region and the second region, so that the lowest point of the etched dish-shaped recess is not higher than the top surface of the isolation structure in the second region, and part of the substrate in the first region is exposed.

[0043] In one example, such as Figure 3B As shown, etching removes a portion of the isolation structure 25 in the first region 201 and the second region 202. Exemplarily, a wet etching process can be used to etch away the portion of the isolation structure 25 in the first region 201 and the second region 202. The wet etching process can use an etchant containing hydrofluoric acid, such as a dilute hydrofluoric acid solution or a buffered hydrofluoric acid solution, to etch the isolation structure 25. Since the material of the isolation structure 25 is silicon oxide, the etchant has a high etching rate for silicon oxide but a lower etching rate for the hard mask layer 21 and the substrate 20. Therefore, the amount of isolation structure 25 removed can be precisely controlled by controlling the concentration, temperature, and etching time of the etchant, thereby adjusting the height of the isolation structure 25.

[0044] Because the first region 201 has a dish-shaped recess 26 after planarization, and the remaining thickness of the isolation structure 25 in the first region 201 is small, and the hard mask layer 21 in the first region 201 is thinned due to wear during planarization (i.e., the thickness of the hard mask layer 21 in the first region 201 is less than the thickness of the hard mask layer 21 in the second region 202), under the same wet etching conditions, the isolation structure 25 in the first region 201 will be over-etched away. The height of the isolation structure 25 removed by the wet etching process ( Figure 3B H3 in the first region 201 is greater than the height of the remaining hard mask layer 21 in the first region 201, that is, the sum of the heights of the remaining first hard mask layer 22 and the second hard mask layer 23 in the first region 201. Figure 3B H1 and H2 in the first region 201 cause part of the substrate 20 to be exposed after the wet etching process. Figure 3BAs shown in the dashed box, the portion of the substrate 20 between adjacent isolation structures 25 in the first region 201 is exposed after the wet etching process. Under the same wet etching conditions, the isolation structure 25 in the second region 202 retains a certain thickness, the hard mask layer 21 in the second region 202 remains intact, and the substrate 20 is not exposed.

[0045] For example, after etching, the top surface of the isolation structure 25 located in the second region 202 is not lower than the lowest point of the dish-shaped recess 26 in the thickness direction of the substrate, that is, the lowest point of the etched dish-shaped recess 26 is not higher than the top surface of the isolation structure 25 in the second region 202. In other words, after etching, in the thickness direction of the substrate (i.e., Figure 3B (Up and down direction) The upper surface of the isolation structure 25 located in the second region 202 is flush with or higher than the lowest point of the dish-shaped recess 26.

[0046] In other examples, the etching removal of the isolation structure 25 can also be achieved using a dry etching process, such as plasma etching or reactive ion etching. A fluorine-containing etching gas, such as at least one of carbon tetrafluoride, trifluoromethane, sulfur hexafluoride, or octafluorocyclobutane, is used to etch the isolation structure 25. By controlling process parameters such as the flow rate of the etching gas, the chamber pressure, the radio frequency power, and the etching time, the amount of etched removal of the isolation structure 25 can be precisely controlled, thereby adjusting the height of the isolation structure 25.

[0047] Continue to step S3, and oxidize the exposed substrate into a protective layer through a thermal oxidation process.

[0048] In one example, such as Figure 3C As shown, the exposed substrate 20 is oxidized into a protective layer 27 through a thermal oxidation process. Exemplarily, the thermal oxidation process may include at least one of dry oxidation, wet oxidation, or in-situ steam generation oxidation. In this embodiment, the thermal oxidation process is an in-situ steam generation (ISSG) process, in which hydrogen and oxygen are introduced into the process chamber, causing the hydrogen and oxygen to generate steam in situ near the surface of the substrate 20. The steam is then used to oxidize the exposed substrate 20 in the first region 201 into a dense protective layer 27. Exemplarily, the material of the protective layer 27 includes, but is not limited to, silicon oxide. In this embodiment, the substrate 20 is a silicon substrate, and the exposed surface of the substrate 20 is oxidized into a silicon oxide protective layer using the in-situ steam generation oxidation process. After the protective layer 27 is formed by the above thermal oxidation process, the protective layer 27 covers the surface of the substrate 20 exposed in the first region 201. In the subsequent annealing process, the protective layer 27 can block the annealing gas from contacting the substrate 20, thereby avoiding oxidation damage to the substrate 20 caused by the annealing gas and suppressing the generation of silicon damage defects.

[0049] In the in-situ water vapor generation oxidation process, the thickness and density of the protective layer 27 can be controlled by adjusting process parameters such as temperature, pressure, hydrogen and oxygen flow ratio, and oxidation time within the process chamber, ensuring that the protective layer 27 completely covers the exposed substrate 20 surface. Compared to conventional thermal oxidation processes, the in-situ water vapor generation oxidation process has a lower oxidation temperature, produces a higher density and more uniform thickness of the generated silicon oxide protective layer, and exhibits better interface quality with the substrate 20, thus reducing additional damage to the substrate 20. During the thermal oxidation process, the portion of the second region 202 that is not exposed to the substrate remains covered by the hard mask layer 21, which blocks the oxidizing atmosphere. This allows the thermal oxidation process to primarily oxidize the exposed substrate 20 in the first region 201, while the unexposed substrate 20 remains largely unoxidized, achieving selective oxidation and avoiding additional consumption of unexposed active silicon.

[0050] Finally, step S4 is performed to form a doped region in the substrate and perform an annealing process, wherein a protective layer is used to prevent the annealing gas from contacting the substrate during the annealing process.

[0051] In one example, before forming the doped region, the process includes removing the second hard mask layer 23. Exemplarily, the second hard mask layer 23 can be removed using a wet etching process, such as etching the second hard mask layer 23 with a hot phosphoric acid solution. Since the material of the second hard mask layer 23 is silicon nitride, the hot phosphoric acid solution has a high etching rate for silicon nitride, but a low etching rate for silicon oxide (e.g., the first hard mask layer 22, the isolation structure 25, and the protective layer 27) and silicon (e.g., the substrate 20). Therefore, during the removal of the second hard mask layer 23, the isolation structure 25, the first hard mask layer 22, and the protective layer 27 are essentially not etched or are etched to a very small extent, and the substrate 20 exposed in the first region 201 remains covered and protected by the protective layer 27 and will not be re-exposed. Exemplarily, the removal of the second hard mask layer 23 can also be achieved using a dry etching process, such as a plasma etching process. After removing the second hard mask layer 23, the first hard mask layer 22 still covers the surface of the substrate 20, and the first hard mask layer 22 can protect the surface of the substrate 20 in subsequent ion implantation processes. After removing the second hard mask layer 23, the structure can also be cleaned to remove etching byproducts and residual etchant before proceeding with the subsequent steps of forming doped regions.

[0052] In one example, such as Figure 3D and Figure 3EAs shown, a doped region 28 is formed in the substrate 20. The specific steps for forming the doped region 28 include: first, forming a patterned mask layer 29, such as a photoresist layer, on the isolation structure 25, wherein the patterned mask layer 29 exposes at least a portion of the first hard mask layer 22 between adjacent isolation structures 25; next, using the patterned mask layer 29 as a mask, forming the doped region 28 in the substrate 20 through an ion implantation process to achieve threshold voltage adjustment, wherein the doped region 28 is located in the substrate 20 between adjacent isolation structures 25; finally, the patterned mask layer 29 may be removed using, but is not limited to, an ashing process or a wet cleaning process. Exemplarily, this ion implantation process may be a high-voltage (HV) ion implantation process.

[0053] For example, the dopant ions in the ion implantation process can be N-type dopant ions, such as phosphorus or arsenic ions, or P-type dopant ions, such as boron ions. The specific doping type, implantation energy, and implantation dose can be set according to the target doping concentration and target junction depth of the doped region 28. Before ion implantation, a first hard mask layer 22 covers the surface of the substrate 20. Dopant ions can pass through the first hard mask layer 22 and be implanted into the substrate 20. The first hard mask layer 22 can protect the surface of the substrate 20 during ion implantation, reducing damage to the substrate 20 surface.

[0054] In one example, after removing the patterned mask layer 29, an annealing process is performed. Exemplarily, the annealing process can be rapid thermal annealing (RTA) or furnace tube annealing. Annealing can effectively activate doped ions, repair implantation damage, and adjust the doping distribution. In this embodiment, since the surface of the substrate 20 in the first region 201 is covered with a protective layer 27, the annealing gas (e.g., the annealing atmosphere gas) cannot come into contact with the substrate 20 during the annealing process; therefore, the substrate 20 will not react with the annealing gas to form defects.

[0055] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0056] Thus, the process steps of the semiconductor device fabrication method according to the embodiments of this application are completed. It is understood that the semiconductor device fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0057] In summary, the semiconductor device fabrication method of this application, after etching away part of the isolation structure and exposing a portion of the substrate in the first region, utilizes a thermal oxidation process to oxidize the exposed substrate into a protective layer. This protective layer effectively blocks annealing gases from contacting the substrate during subsequent annealing processes, preventing annealing gases from eroding and damaging the substrate, thereby suppressing the generation of damage defects and improving device reliability and yield. Furthermore, this application eliminates the need for excessive adjustment of the chemical mechanical planarization process window, avoiding residual defects in the isolation material, and features a simple process with good compatibility.

[0058] Example 2 This application also provides a semiconductor device, which can be prepared by the method of the aforementioned embodiment one, or by other suitable preparation methods.

[0059] The following reference Figures 3A to 3E The semiconductor devices in the embodiments of this application will be explained and described, wherein structures that are the same as those in the aforementioned Embodiment 1 will not be described in detail here.

[0060] Specifically, such as Figures 3A to 3E As shown, the semiconductor device of this application includes: a semiconductor structure, the semiconductor structure including a first region 201 and a second region 202, both the first region 201 and the second region 202 including a substrate 20, a hard mask layer 21, an isolation structure 25 and a trench 24, the hard mask layer 21 being located on the substrate 20, the trench 24 penetrating the hard mask layer 21 and extending a certain depth into the substrate 20, the isolation structure 25 being filled in the trench 24, wherein the width of the trench 24 in the first region 201 is greater than the width of the trench 24 in the second region 202, and the top surface of the isolation structure in the first region 201 has a dish-shaped recess 26; a protective layer 27, the protective layer 27 being located on the surface of the substrate 20 between adjacent isolation structures 25 in the first region 201; and a doped region 28, the doped region 28 being located in the substrate 20.

[0061] The semiconductor device of this application, after etching away part of the isolation structure and exposing part of the substrate in the first region, uses a thermal oxidation process to oxidize the exposed substrate into a protective layer. This protective layer effectively blocks annealing gases from contacting the substrate during subsequent annealing processes, preventing annealing gases from eroding and damaging the substrate, thereby suppressing the generation of damage defects and improving device reliability and yield. Furthermore, this application does not require excessive adjustment of the chemical mechanical planarization process window, avoiding residual defects in the isolation material, and features a simple process and good compatibility.

[0062] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a first region and a second region, both the first region and the second region including a substrate, a hard mask layer, an isolation structure and a trench, the hard mask layer being located on the substrate, the trench penetrating the hard mask layer and extending into the substrate to a certain depth, the isolation structure filling the trench, wherein the width of the trench in the first region is greater than the width of the trench in the second region, and the top surface of the isolation structure in the first region has a dish-shaped recess; Etching removes portions of the isolation structures in the first and second regions, such that the lowest point of the etched dish-shaped recess is not higher than the top surface of the isolation structure in the second region, and exposes a portion of the substrate in the first region; The exposed substrate is oxidized into a protective layer using a thermal oxidation process; A doped region is formed in the substrate and then annealed, wherein the protective layer is used to prevent the annealing gas during the annealing process from contacting the substrate.

2. The preparation method according to claim 1, characterized in that, The material of the protective layer includes silicon oxide.

3. The preparation method according to claim 2, characterized in that, The thermal oxidation process is an in-situ water vapor generation oxidation process.

4. The preparation method according to claim 1, characterized in that, The hard mask layer includes a first hard mask layer and a second hard mask layer located on the first hard mask layer. Before forming the doped region, the method further includes removing the second hard mask layer.

5. The preparation method according to claim 4, characterized in that, The process of forming a doped region in the substrate and then performing an annealing treatment includes: A patterned mask layer is formed on the isolation structure, the patterned mask layer exposing at least a portion of the first hard mask layer between adjacent isolation structures; Using a patterned mask layer as a mask, doped regions are formed in the substrate by ion implantation, wherein the doped regions are located in the substrate between adjacent isolation structures; Remove the patterned mask layer and perform the annealing process.

6. The preparation method according to claim 4 or 5, characterized in that, The material of the first hard mask layer includes silicon oxide, and the material of the second hard mask layer includes silicon nitride.

7. The preparation method according to claim 1, characterized in that, The method of forming the isolation structure includes: An isolation layer is formed to cover the hard mask layer and fill the trenches in the first and second regions; A planarization process is performed on the isolation layer until the hard mask layer is exposed to form the isolation structure in the trenches of the first region and the second region, wherein the top surface of the first region after the planarization process has the dish-shaped recess.

8. The preparation method according to claim 1, characterized in that, A wet etching process is used to etch away portions of the isolation structure in the first and second regions.

9. The preparation method according to claim 1, characterized in that, The substrate is made of silicon, and the isolation structure is made of silicon oxide.

10. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor structure includes a first region and a second region. Both the first region and the second region include a substrate, a hard mask layer, an isolation structure, and a trench. The hard mask layer is located on the substrate. The trench penetrates the hard mask layer and extends into the substrate to a certain depth. The isolation structure fills the trench. The width of the trench in the first region is greater than the width of the trench in the second region. The top surface of the isolation structure in the first region has a dish-shaped recess. A protective layer is located on the substrate surface between adjacent isolation structures in the first region; A doped region located in the substrate.

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