Method of manufacturing a semiconductor structure and semiconductor structure
By introducing non-metallic doping and annealing into the etch barrier layer or oxide layer to form a sacrificial barrier layer, the problem of over-etching caused by gate height difference is solved, thereby improving the performance of semiconductor devices and maintaining process compatibility.
Patent Information
- Application Number
- CN202610950602.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-29
- Publication Date
- 2026-11-03
AI Technical Summary
In high-voltage, embedded flash memory, and bipolar transistor-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor processes, the over-etching of contact holes due to gate height differences causes self-aligned silicide abnormalities and unstable contact resistance.
Introducing non-metallic doping into the etch barrier layer or oxide layer and then annealing it forms a sacrificial barrier layer to control the etch endpoint and avoid over-etching caused by gate height difference.
By precisely controlling the etching endpoint, over-etching of the interlayer dielectric layer is avoided, improving the performance of semiconductor devices, avoiding voids and gaps, and eliminating the need to thicken the etch barrier layer, thus maintaining process compatibility.
Smart Images
Figure CN123035941A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology
[0002] In high-voltage (HV), embedded flash (e-Flash), and bipolar transistor-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor (BCD) processes, a contact hole etch stop layer (CESL) is typically deposited, followed by an oxide (SAOX) layer on its surface. However, due to the varying gate heights in these processes, a height difference is created between the thick gate, the thin gate, and the active area (AA). During contact hole etching, this height difference can easily lead to over-etching of the thick gate, resulting in abnormal self-aligned silicide and unstable contact resistance.
[0003] In existing technologies, although over-etching can be prevented by thickening the contact hole etching barrier layer, this also increases the aspect ratio of the interlayer dielectric (ILD) filling, which can easily cause voids and seams in the filling, resulting in a decrease in isolation performance. Summary of the Invention
[0004] The purpose of this invention is to provide a method for manufacturing a semiconductor structure and a semiconductor structure to solve the problem of over-etching when etching contact holes due to the height difference between different gate structures.
[0005] To address the aforementioned technical problems, the present invention provides a method for manufacturing a semiconductor structure, the method comprising the following steps:
[0006] A substrate is provided, on which at least two gate structures of different heights are formed, and active regions are formed in the substrate on both sides of each gate structure;
[0007] An etch barrier layer and an oxide layer are formed sequentially. The etch barrier layer conformally covers the active region and each of the gate structures, and the oxide layer conformally covers the etch barrier layer. In this case, one of the etch barrier layer and the oxide layer is formed as a sacrificial barrier layer by non-metallic doping and annealing.
[0008] A surface-planarized interlayer dielectric layer is formed, which covers the oxide layer;
[0009] A patterned photoresist layer is formed on the surface of the interlayer dielectric layer, and the interlayer dielectric layer, the oxide layer and the etch barrier layer are sequentially etched using the patterned photoresist layer as a mask to form contact holes that expose the surface of the gate structure portion.
[0010] The etching selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than that of the etching barrier layer or the oxide layer relative to the interlayer dielectric layer, and the etching selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than 1; the contact holes are formed by step etching, with the first etching stopping at the sacrificial barrier layer and the second etching stopping at the surface of each gate structure.
[0011] Optionally, the annealing process may include laser annealing.
[0012] Optionally, the laser annealing process uses an annealing temperature of 500℃~1100℃ and an annealing time of 0.1ms~20ms.
[0013] Optionally, the sacrificial barrier layer is formed within the etch barrier layer, and the step of forming the etch barrier layer and the oxide layer includes:
[0014] The etching barrier layer is formed, and the etching barrier layer conformally covers the active region and each of the gate structures;
[0015] The etching barrier layer is non-metallic doped and its surface is annealed to form the sacrificial barrier layer inside the etching barrier layer.
[0016] The oxide layer is formed, and the oxide layer conformally covers the etch barrier layer.
[0017] Optionally, the sacrificial barrier layer is formed within the oxide layer. The steps of forming the etch barrier layer and the oxide layer include:
[0018] The etching barrier layer is formed, and the etching barrier layer conformally covers the active region and each of the gate structures;
[0019] The oxide layer is formed, and the oxide layer conformally covers the etch barrier layer;
[0020] The oxide layer is non-metallic doped and its surface is annealed to form the sacrificial barrier layer inside the oxide layer.
[0021] Optionally, the material of the etch barrier layer includes silicon nitride.
[0022] Optionally, if the sacrificial barrier layer is formed within the etch barrier layer, the non-metallic doping is carbon doping with a doping concentration of 1×10⁻⁶. 13 / cm 3 ~1×10 16 / cm 3 The injection depth is 50 Å to 300 Å.
[0023] Optionally, the material of the oxide layer includes silicon dioxide.
[0024] Optionally, if the sacrificial barrier layer is formed within the oxide layer, the non-metallic doping is carbon doping or nitrogen doping, with a doping concentration of 1×10⁻⁶. 13 / cm 3 ~1×10 16 / cm 3 The injection depth is 50 Å to 300 Å.
[0025] Based on the same inventive concept, the present invention also provides a semiconductor structure, which is manufactured using the semiconductor structure manufacturing method described above.
[0026] In summary, the present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a substrate on which at least two gate structures of different heights are formed, and active regions are formed in the substrate on both sides of each gate structure; sequentially forming an etch stop layer and an oxide layer, wherein the etch stop layer conformally covers the active regions and each gate structure, and the oxide layer conformally covers the etch stop layer, wherein one of the etch stop layer and the oxide layer is internally formed as a sacrificial barrier layer by non-metallic doping and annealing; and forming a surface-planarized interlayer dielectric layer covering the oxide layer. A patterned photoresist layer is formed on the surface of the interlayer dielectric layer, and the interlayer dielectric layer, the oxide layer, and the etch stop layer are sequentially etched using the patterned photoresist layer as a mask to form contact holes that expose a portion of the gate structure surface; wherein, the etch selectivity of the sacrificial stop layer relative to the interlayer dielectric layer is greater than the etch selectivity of the etch stop layer or the oxide layer relative to the interlayer dielectric layer, and the etch selectivity of the sacrificial stop layer relative to the interlayer dielectric layer is greater than 1; the contact holes are formed by step-by-step etching, with the first etching stopping at the sacrificial stop layer and the second etching stopping at the surface of each of the gate structures.
[0027] The technical solution provided by this invention has the following advantages over the prior art:
[0028] To eliminate over-etching caused by gate height difference, this invention forms a sacrificial barrier layer by doping non-metals inside the etch barrier layer or oxide layer, precisely controlling the etch endpoint and avoiding over-etching caused by the interlayer dielectric layer covering the thick gate surface being too thin due to different gate heights during the formation of contact holes, thereby improving the performance of semiconductor devices.
[0029] This invention achieves improved semiconductor device performance without increasing the thickness of the etch barrier layer, avoiding problems such as the filling of voids / gaps in the interlayer dielectric layer caused by high aspect ratio.
[0030] The present invention only requires adding non-metallic doping and annealing steps to the etching barrier layer or oxide layer based on the existing technical steps. It has strong process compatibility and can be well integrated into existing processes. Attached Figure Description
[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention.
[0032] Figure 1 A schematic flowchart illustrating the manufacturing method of the semiconductor structure provided in an embodiment of the present invention;
[0033] Figures 2-6 for Figure 1 Schematic diagrams of the semiconductor structures corresponding to each step in the process;
[0034] The labels in the attached figures are explained as follows:
[0035] 100 - Substrate; 110 - Shallow trench isolation; 120 - First gate structure; 130 - Second gate structure; 140 - Etching barrier layer; 150 - Sacrificial barrier layer; 160 - Oxide layer; 170 - Interlayer dielectric layer; 180 - Hard mask layer; 190 - Dielectric anti-reflective coating; 200 - Adhesion layer; 210 - Bottom anti-reflective coating; 220 - Photoresist layer. Detailed Implementation
[0036] To make the objectives, advantages, and features of the present invention clearer, the manufacturing method and semiconductor structure provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly illustrating the embodiments of the present invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may have different emphases and sometimes use different scales. It should be understood that relative terms such as "above," "below," "top," and "bottom" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described as "above" another element will now be below that element. It should also be understood that, unless specifically stated or indicated, the terms "first," "second," "third," etc., in the specification are only used to distinguish the various components, elements, steps, etc., in the specification, and are not used to indicate logical or sequential relationships between the various components, elements, steps, etc.
[0037] Example 1
[0038] refer to Figure 1 As shown, this embodiment of the invention provides a method for manufacturing a semiconductor structure, the method comprising the following steps:
[0039] S1, a substrate is provided, on which at least two gate structures of different heights are formed, and active regions are formed in the substrate on both sides of each gate structure;
[0040] S2, an etch barrier layer and an oxide layer are formed sequentially. The etch barrier layer conformally covers the active region and each of the gate structures, and the oxide layer conformally covers the etch barrier layer. In this case, one of the etch barrier layer and the oxide layer is formed as a sacrificial barrier layer by non-metallic doping and annealing.
[0041] S3, forming a surface planarized interlayer dielectric layer, the interlayer dielectric layer covering the oxide layer;
[0042] S4, a patterned photoresist layer is formed on the surface of the interlayer dielectric layer, and the interlayer dielectric layer, the oxide layer and the etch barrier layer are sequentially etched using the patterned photoresist layer as a mask to form a contact hole that exposes the surface of the gate structure portion;
[0043] The etching selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than that of the etching barrier layer or the oxide layer relative to the interlayer dielectric layer, and the etching selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than 1; the contact holes are formed by step etching, with the first etching stopping at the sacrificial barrier layer and the second etching stopping at the surface of each gate structure.
[0044] By utilizing the technical solution provided in the embodiments of the present invention, a sacrificial barrier layer is formed by non-metallic doping and annealing of the etching barrier layer or oxide layer. This precisely controls the etching endpoint and avoids over-etching caused by the interlayer dielectric layer covering the thick gate surface being too thin due to different gate heights during the formation of contact holes. This improves the performance of semiconductor devices, and the method is simple, highly compatible, and easy to integrate into existing processes.
[0045] The following combination Figures 2-6 The manufacturing method and semiconductor structure provided in the embodiments of the present invention will be further described.
[0046] First refer to Figure 2As shown, in step S1, a substrate 100 is provided. As an example, a P-type silicon substrate is used in this embodiment of the invention. A shallow trench isolation 110 is formed on the substrate 100. A first gate structure 120 and a second gate structure 130 are formed on the substrate 100 on both sides of the shallow trench isolation 110, respectively. The height of the second gate structure 130 is greater than the height of the first gate structure 120. Active regions (not shown) are formed in the substrate 100 on both sides of the first gate 120 and the second gate structure 130, respectively.
[0047] Then refer to Figures 3-5 As shown, step S2 is performed to form an etch barrier layer 140 and an oxide layer 160, and a sacrificial barrier layer is formed by non-metallic doping.
[0048] In this embodiment, the sacrificial barrier layer is formed within the etch barrier layer 140. Specifically, the steps of forming the etch barrier layer 140 and the oxide layer 160 include:
[0049] S21a, as Figure 3 As shown, the etch barrier layer 140 is formed, and the etch barrier layer 140 conformally covers the active region, the shallow trench isolation 110, the first gate structure 120 and the second gate structure 130.
[0050] S22a, as Figure 4 As shown, the etching barrier layer 140 is non-metallic doped and the surface of the etching barrier layer 140 is annealed to form the sacrificial barrier layer 150 inside the etching barrier layer 140.
[0051] S23a, as Figure 5 As shown, the oxide layer 160 is formed, and the oxide layer 160 conformally covers the etch barrier layer 140.
[0052] Preferably, the etch barrier layer 140 is made of silicon nitride and is formed using plasma-enhanced chemical vapor deposition (PECVD) with silane as the silicon source and ammonia or nitrogen as the nitrogen source. In this embodiment, the etch barrier layer 140 is made of silicon nitride. When doping the etch barrier layer 140, carbon doping can be used for the non-metallic doping, and further, the carbon doping concentration can be 1 × 10⁻⁶. 13 / cm 3 ~1×10 16 / cm 3 During doping, the carbon doping depth can be 50 Å to 300 Å, such as 100 Å or 150 Å. Subsequently, the etch barrier layer 140 is annealed, which allows the doped atoms to react with the etch barrier layer 140 to form a sacrificial barrier layer 150.
[0053] Specifically, the etch barrier layer 140 is annealed. High temperature provides energy to the carbon atoms doped within the etch barrier layer, promoting the reaction of high-energy carbon atoms with surrounding silicon and nitrogen atoms to form stable chemical bonds. Ultimately, a sacrificial barrier layer 150 is formed within the etch barrier layer 140. In this embodiment, the sacrificial barrier layer is made of silicon, carbon, and nitrogen. Furthermore, the annealing process can also repair lattice damage caused by non-metallic doping to the etch barrier layer 140, protecting the film's performance.
[0054] Preferably, to prevent the diffusion of doped carbon atoms, this embodiment of the invention employs a laser annealing process. This laser annealing process can heat the surface of the etch barrier layer 140 to a high temperature in a very short time. For example, in this embodiment, the annealing temperature can be 500℃~1100℃, and the annealing time can be 0.1ms~20ms. Because the annealing time is extremely short, it effectively prevents the diffusion of doped atoms within the film layer. Consequently, the formed sacrificial barrier layer 150 is concentrated at the non-metallic dopant injection sites within the etch barrier layer 140, i.e., formed within the etch barrier layer 140 at a distance of 50Å~300Å from its upper surface, such as 100Å or 150Å. The etch barrier layers 140 above and below the sacrificial barrier layer 150 retain the undoped original material, thus avoiding stress effects on adjacent film layers.
[0055] Subsequently, using the physical morphology of the etch stop layer 140 and the first gate structure 120 and the second gate structure 130 below it as a mask, a self-aligned oxide layer 160 is formed on the surface of the etch stop layer. Preferably, the oxide layer 160 is made of silicon dioxide and is deposited using plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD), with tetraethoxysilane or silane as the silicon source and oxygen or nitrous oxide as the oxygen source. The oxide layer 160 is self-aligned with the etch stop layer 140 and the gate structures. The etch stop layer 140 serves as a stop layer during the etching of the interlayer dielectric layer 170, reducing the etching rate to protect the first gate structure 120 and the second gate structure 130 below it. The oxide layer 160 conformally covers the surface of the etch stop layer 140, protecting the etch stop layer from damage during subsequent processes (e.g., cleaning steps before depositing the interlayer dielectric layer and planarization after depositing the interlayer dielectric layer).
[0056] refer to Figure 6As shown, steps S3 and S4 are performed to form an interlayer dielectric layer 170 on the oxide layer 160. Then, the interlayer dielectric layer 170 is planarized by chemical mechanical polishing. Next, a hard mask layer 180, a dielectric antireflective coating 190, an adhesion layer 200, a bottom antireflective coating 210, and a photoresist layer 220 are sequentially formed on the surface of the interlayer dielectric layer 170.
[0057] Preferably, in this embodiment of the invention, the interlayer dielectric layer 170 is made of plasma-enhanced tetraethoxysilane (PETEOS) oxide and is formed using plasma-enhanced chemical vapor deposition; the hard mask layer 180 is made of amorphous carbon (APF) and is formed using chemical vapor deposition; the dielectric antireflective coating 190 is made of silicon oxynitride and is formed using plasma-enhanced chemical vapor deposition; and the adhesion layer 200 is made of silicon oxide and is formed using plasma-enhanced chemical vapor deposition or thermal oxidation.
[0058] Finally, the contact hole pattern is transferred to the photoresist layer 220 (not shown in the figure) through processes such as exposure and development. Then, using the patterned photoresist layer 220 as a mask, the contact hole is formed by step-by-step etching. Specifically, the first etching uses the patterned photoresist layer 220 as a mask to sequentially etch the bottom anti-reflective coating 210, the adhesion layer 200, the dielectric anti-reflective coating 190, the hard mask layer 180, and the interlayer dielectric layer 170, stopping at the sacrificial barrier layer 150. Since the etching selectivity of the sacrificial barrier layer 150 relative to the interlayer dielectric layer 170 is greater than that of the etching barrier layer 140 relative to the interlayer dielectric layer 170, and the etching selectivity of the sacrificial barrier layer 150 relative to the interlayer dielectric layer 170 is greater than 1, the etching rate is significantly slowed down when etching reaches the sacrificial barrier layer, allowing for precise control of the first etching endpoint to stop at the sacrificial barrier layer 150.
[0059] A second etching process is then performed to sequentially remove the exposed sacrificial barrier layer 150 and the etch barrier layer 140 below it, thereby exposing portions of the surfaces of the first gate structure 120 and the second gate structure 130 to form contact holes. During the second etching, since the sacrificial barrier layer 150 and the etch barrier layer 140 removed above the first gate structure 120 and the second gate structure 130 have the same thickness, the second etching can stop simultaneously on the surfaces of each gate structure, thus eliminating over-etching of the gate structure caused by differences in gate height.
[0060]
Example 2
[0061] Unlike Embodiment 1, in step S2, the sacrificial barrier layer is formed within the oxide layer 160. Specifically, the steps of forming the etch barrier layer 140 and the oxide layer 160 include:
[0062] S21b, forming the etch barrier layer, the etch barrier layer conformally covering the active region and each of the gate structures;
[0063] S22b, forming the oxide layer, the oxide layer conformally covering the etch barrier layer;
[0064] S23b, the oxide layer is non-metallic doped and the surface of the oxide layer is annealed to form the sacrificial barrier layer inside the oxide layer.
[0065] When performing non-metallic doping on the oxide layer, since the oxide layer material is silicon dioxide, the non-metallic doping can be carbon doping or nitrogen doping. Furthermore, the carbon or nitrogen doping concentration can be 1 × 10⁻⁶. 13 / cm 3 ~1×10 16 / cm 3 The doping depth can be 50 Å to 300 Å, for example, 100 Å, 150 Å, etc. Subsequently, the doped oxide layer is annealed using a laser annealing process, with an annealing temperature of 500℃ to 1100℃ and an annealing time of 0.1 ms to 20 ms. After annealing, the dopant reacts with the oxide layer to form the sacrificial barrier layer. When carbon is doped, the sacrificial barrier layer is silicon oxycarbide (SiOC); when nitrogen is doped, the sacrificial barrier layer is silicon oxynitride (SiON).
[0066] In this embodiment, the implementation of steps S3 and S4 can refer to the above embodiment one, so they will not be repeated here. It should be noted that, unlike embodiment one, in step S4, during the step-by-step etching, the first etching stops at the sacrificial barrier layer within the oxide layer, and the second etching removes the sacrificial barrier layer and the oxide layer and the etching barrier layer below it, and stops at the surface of each gate structure.
[0067] Based on the same inventive concept, this embodiment of the invention also provides a semiconductor structure, which is formed using the manufacturing method of the semiconductor structure provided in this embodiment of the invention. The semiconductor structure has the same technical effect as the manufacturing method of the above-mentioned semiconductor structure, and will not be described again here.
[0068] In summary, embodiments of the present invention provide a method for manufacturing a semiconductor structure and a semiconductor structure. The manufacturing method includes: providing a substrate on which at least two gate structures of different heights are formed, and active regions are formed in the substrate on both sides of each gate structure; sequentially forming an etch stop layer and an oxide layer, wherein the etch stop layer conformally covers the active regions and each gate structure, and the oxide layer conformally covers the etch stop layer, wherein one of the etch stop layer and the oxide layer is formed internally as a sacrificial barrier layer by non-metallic doping and annealing; and forming a surface-planarized interlayer dielectric layer, the interlayer dielectric layer covering the active regions and each gate structure. An oxide layer is formed; a patterned photoresist layer is formed on the surface of the interlayer dielectric layer, and the interlayer dielectric layer, the oxide layer, and the etch barrier layer are sequentially etched using the patterned photoresist layer as a mask to form contact holes exposing a portion of the gate structure surface; wherein, the etch selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than that of the etch barrier layer or the oxide layer relative to the interlayer dielectric layer, and the etch selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than 1; the contact holes are formed by step-by-step etching, with the first etching stopping at the sacrificial barrier layer and the second etching stopping at the surface of each gate structure. Using the technical solution provided by this embodiment of the invention, non-metallic doping and annealing are performed on the etch barrier layer or oxide layer to form a sacrificial barrier layer, precisely controlling the etching endpoint and avoiding over-etching of the gate due to different gate heights during the formation of contact holes, thereby improving device yield.
[0069] It should be noted that the above description is only a description of the preferred embodiment of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, on which at least two gate structures of different heights are formed, and active regions are formed in the substrate on both sides of each gate structure; An etch barrier layer and an oxide layer are formed sequentially. The etch barrier layer conformally covers the active region and each of the gate structures, and the oxide layer conformally covers the etch barrier layer. In this case, one of the etch barrier layer and the oxide layer is formed as a sacrificial barrier layer by non-metallic doping and annealing. A surface-planarized interlayer dielectric layer is formed, which covers the oxide layer; A patterned photoresist layer is formed on the surface of the interlayer dielectric layer, and the interlayer dielectric layer, the oxide layer and the etch barrier layer are sequentially etched using the patterned photoresist layer as a mask to form contact holes that expose the surface of the gate structure portion. The etching selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than that of the etching barrier layer or the oxide layer relative to the interlayer dielectric layer, and the etching selectivity of the sacrificial barrier layer relative to the interlayer dielectric layer is greater than 1; the contact holes are formed by step etching, with the first etching stopping at the sacrificial barrier layer and the second etching stopping at the surface of each gate structure.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The annealing process includes laser annealing.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The laser annealing process uses an annealing temperature of 500℃~1100℃ and an annealing time of 0.1ms~20ms.
4. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The step of forming the sacrificial barrier layer within the etch barrier layer, and forming the etch barrier layer and the oxide layer, includes: The etching barrier layer is formed, and the etching barrier layer conformally covers the active region and each of the gate structures; The etching barrier layer is non-metallic doped and its surface is annealed to form the sacrificial barrier layer inside the etching barrier layer. The oxide layer is formed, and the oxide layer conformally covers the etch barrier layer.
5. The method for manufacturing a semiconductor structure as described in claim 1, characterized in that, The steps of forming the sacrificial barrier layer within the oxide layer, and forming the etch barrier layer and the oxide layer, include: The etching barrier layer is formed, and the etching barrier layer conformally covers the active region and each of the gate structures; The oxide layer is formed, and the oxide layer conformally covers the etch barrier layer; The oxide layer is non-metallic doped and its surface is annealed to form the sacrificial barrier layer inside the oxide layer.
6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The material of the etching barrier layer includes silicon nitride.
7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, If the sacrificial barrier layer is formed within the etch barrier layer, then the non-metallic doping is carbon doping with a doping concentration of 1×10⁻⁶. 13 / cm 3 ~1×10 16 / cm 3 The injection depth is 50 Å to 300 Å.
8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The material of the oxide layer includes silicon dioxide.
9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that, If the sacrificial barrier layer is formed within the oxide layer, then the non-metallic doping is carbon doping or nitrogen doping, with a doping concentration of 1×10⁻⁶. 13 / cm 3 ~1×10 16 / cm 3 The injection depth is 50 Å to 300 Å.
10. A semiconductor structure, characterized in that, It is manufactured using the semiconductor structure manufacturing method as described in any one of claims 1 to 9.