Method of forming a contact in a conductive region, semiconductor structure, chip and electronic device
Patent Information
- Application Number
- CN202611268508.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-19
- Publication Date
- 2026-11-03
AI Technical Summary
With the development of semiconductor manufacturing technology, the reduction in wire width and the increase in the aspect ratio of contact features lead to an increase in interconnect resistance, an increase in the proportion of diffusion barrier thickness, an increase in contact resistivity, and a large edge resistance of metal silicides, making it difficult to form low-resistivity metal silicides.
A metal interface layer containing a high-melting-point metal is formed on the bottom surface of the through hole. A buffer layer and a contact body layer are formed through an annealing process to reduce the thickness of the adhesive material layer and optimize the resistivity and thermal stability of the contact.
By introducing a metal interface layer, the contact resistivity is reduced, the resistivity and thermal stability of the contact are improved, the thickness of the diffusion barrier is reduced, the filling process window is increased, and the interconnect resistance is reduced.
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Figure CN123035944A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a method for forming contacts in a conductive region, a semiconductor structure, a chip, and an electronic device. Background Technology
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. However, the continuous evolution of technology nodes leads to a reduction in wire width and a continuous increase in the aspect ratio of contact features, highlighting the growing demand for contacts with low resistivity, good thermal stability, and smooth interfaces with silicon. On the other hand, as wire width continues to decrease, the proportion of diffusion barrier thickness to the total wire cross-section increases dramatically. Since the resistivity of diffusion barriers is significantly greater than that of filler metals such as cobalt, this results in an increase in interconnect resistance. Summary of the Invention
[0003] In a first aspect, embodiments of this application provide a method for forming a contact in a conductive region, comprising: A substrate is provided, the substrate including an embedded silicon-containing conductive region, an interlayer dielectric layer covering the substrate, the interlayer dielectric layer having a via extending through the thickness direction and into the silicon-containing conductive region, the inner surface of the via including a bottom surface; A metal interface layer is formed on the bottom surface of the through hole, and the material of the metal interface layer includes a first metal; An adhesive material layer and a barrier material layer are formed sequentially on the inner surface of the through hole. The adhesive material layer contacts the metal interface layer at the bottom of the through hole. The material of the adhesive material layer includes a second metal. The metal interface layer is transformed into a buffer layer by an annealing process, and the adhesive material layer with at least a partial thickness is transformed into a contact body layer, thereby forming a contact portion including the buffer layer and the contact body layer. The material of the buffer layer includes a metal silicide comprising the first metal and the second metal, and the material of the contact body layer includes a silicide of the second metal. The first metal has a melting point higher than that of the second metal.
[0004] Secondly, embodiments of this application provide a method for fabricating a semiconductor structure, including: the method of forming a contact in a conductive region as described above; Forming a conductive part includes: A seed crystal material layer is formed inside the through hole and on the barrier material layer; A metallization layer is formed by filling the vias and covering the interlayer dielectric layer; The metallization layer is planarized so that the top surface of the planarized metallization layer is flush with the top surface of the interlayer dielectric layer.
[0005] Thirdly, embodiments of this application provide a semiconductor structure, including: Device layer, the device layer including silicon-containing conductive regions; An interlayer dielectric layer is applied over the device layer; The conductive portion extends along the thickness direction of the interlayer dielectric layer and is located above the silicon-containing conductive region; A diffusion barrier, at least covering the sidewall of the conductive portion; A contact portion is located between the silicon-containing conductive region and the conductive portion, and contacts the silicon-containing conductive region. The contact portion includes a buffer layer and a contact body layer stacked sequentially in a direction away from the device layer. The material of the buffer layer includes a metal silicide comprising a first metal and a second metal. The material of the contact body layer includes a silicide of the second metal. The first metal has a melting point higher than that of the second metal.
[0006] Fourthly, embodiments of this application provide a chip, including: the semiconductor structure as described above.
[0007] Fifthly, embodiments of this application provide an electronic device, including: the chip as described above. Attached Figure Description
[0008] Figures 1A to 1D The diagram illustrates the structures obtained at different stages of the method for forming contacts in the conductive region in the related technology, wherein, Figure 1A This is a schematic diagram of the structure corresponding to the formation of through holes in related technologies; Figure 1B This is a schematic diagram of the corresponding structure after the adhesion material layer is formed in the related technology; Figure 1C This is a schematic diagram of the corresponding structure after the formation of the barrier material layer in related technologies; Figure 1D This is a schematic diagram of the corresponding structure after the contact portion is formed in the related technology; Figure 2 The temperature phase diagram of the two rapid thermal annealing processes in the metal silicide process is shown.
[0009] Figure 3 A schematic flowchart of a method for forming a contact in a conductive region according to an embodiment of this application is shown.
[0010] Figures 4A to 4E The diagram shows the structures obtained at different stages of the method for forming contacts in a conductive region according to embodiments of this application, wherein... Figure 4A This is a schematic diagram of the structure corresponding to the through hole formed according to the embodiments of this application; Figure 4B This is a schematic diagram of the structure corresponding to the metal interface layer formed according to the embodiments of this application; Figure 4C This is a schematic diagram of the structure corresponding to the formation of the barrier material layer according to the embodiments of this application; Figure 4D This is a schematic diagram of the corresponding structure after the contact portion is formed according to the embodiments of this application; Figure 4E for Figure 4D A magnified view of a portion of structure A shown; Figures 5A to 5B The diagram shows schematic diagrams of the structures obtained at different stages of the method for forming conductive parts provided in the embodiments of this application, wherein, Figure 5A This is a schematic diagram of the corresponding structure after metal filling; Figure 5B This is a schematic diagram of the structure after the metal filling is planarized.
[0011] Explanation of reference numerals in the attached figures: 200 - Interlayer dielectric layer; 110 - Silicon-containing conductive region; 210 - Through-hole; 114 - Adhesive material layer; 116 - Barrier material layer; 120 - Contact portion; 212 - Metal interface layer; 214 - Adhesive material layer; 216 - Barrier material layer; 220 - Contact portion; 220a - Buffer layer; 220b - Contact body layer; 314 - Adhesive material layer; 316 - Barrier material layer; 314r - Adhesive layer; 316r - Barrier layer; 317 - Seed crystal material layer; 317r - Seed crystal layer; 318 - Metallization layer; 318f - Metal filler; 320 - Contact portion; 320a - Buffer layer; 320b - Contact body layer; 326 - Diffusion barrier; 328 - Conductive portion. Detailed Implementation
[0012] As described in the background art, with the continuous shrinking of device feature size, the linewidth of the conductors is decreasing and the aspect ratio of the contact features is continuously increasing, the demand for contacts with low resistivity, good thermal stability and smooth interface with silicon is becoming increasingly prominent.
[0013] Figures 1A to 1D The diagram illustrates the structures obtained at different stages of a method for forming contacts in a conductive region in related technologies. Methods for forming contacts in a conductive region generally include: like Figure 1A As shown, in step S02, a substrate (not shown) is provided. The substrate includes an embedded silicon conductive region 110. An interlayer dielectric layer 200 is covered on the substrate. The interlayer dielectric layer 200 has a via 210 that extends through the thickness direction and reaches the silicon conductive region 110.
[0014] like Figure 1B and Figure 1C As shown, in step S04, an adhesive material layer 114 and a barrier material layer 116 are sequentially formed on the inner surface of the through-hole 210. The adhesive material layer 114 can be made of titanium, and its thickness can be 90 Å-110 Å. The barrier material layer 116 can be made of titanium nitride (TiN), and its thickness can be 10 Å-20 Å.
[0015] like Figure 1D As shown, in step S06, the silicon material in the silicon-containing conductive region 110 reacts with the adhesion material layer 114 of a certain thickness to form a contact portion 120 through an annealing process. The contact portion 120 is located at the bottom of the through hole 210 and contacts the silicon-containing conductive region 110.
[0016] The above-mentioned method for forming contacts in conductive regions has some problems: Figure 2 The temperature phase diagram of the two rapid thermal annealing processes in metal silicide processing technology is shown. For example... Figure 2 As shown, metals such as titanium and silicon materials originating from the adhesion material layer, after low-temperature annealing, form high-resistivity C49 phase titanium silicide. When the annealing temperature is higher than the critical temperature T1, the high-resistivity C49 phase titanium silicide transforms into low-resistivity C54 phase titanium silicide. However, if the thickness of the contact portion 120, which is made of materials such as titanium silicide, is reduced, the critical temperature T1 for the transformation of the aforementioned titanium silicide into the low-resistivity C54 phase will increase, and the critical temperature T2 for the agglomeration of the low-resistivity C54 phase will decrease. This reduces the width of the via to a certain extent, and proportionally reduces the thickness of the metal silicide, causing the critical temperature T2 to be lower than the critical temperature T1. This results in the direct formation of C49 phase agglomeration after annealing, without the formation of the low-resistivity C54 phase, thereby increasing the contact resistance. Based on this, as the width of the via decreases, the thickness of the adhesive material layer is appropriately increased to facilitate the formation of low-resistivity metal silicides. However, this results in a larger thickness of the diffusion barrier formed based on the adhesive material layer 114 and the barrier material layer 116. This causes the formation of a metal filler in the via to form a connecting wire, and the proportion of the thickness of the diffusion barrier to the entire cross-section of the connecting wire increases sharply, leading to an increase in interconnect resistance.
[0017] Furthermore, during the annealing process, silicon and metal undergo interdiffusion. Silicon, as the main diffusing species, jumps through the lattice via vacancies and interstitial mechanisms, "passing through" the formed metal silicides, causing the metal silicides to continuously thicken. At the edges, the amount of silicon participating in the reaction is relatively small, so the thickness of the metal silicides formed at the edges will be correspondingly thinner. Consequently, the resistance of the thin film at the edges will increase, resulting in a higher resistance at the edges of the metal silicides.
[0018] Based on the above analysis, embodiments of this application provide a method for forming contacts in a conductive region, a semiconductor structure, a chip, and an electronic device. The method includes forming a metal interface layer on the bottom surface of the via after forming a via through an interlayer dielectric layer and before forming an adhesive material layer. The metal interface layer contains a high-melting-point metal. By introducing the metal interface layer, the high-melting-point metal from the metal interface layer reacts with the silicon material during the annealing process to form a buffer layer. The buffer layer provides a stable interface for the contact host layer, which is beneficial for preparing a contact host layer with low resistivity and optimized thermal stability, thereby improving the specific contact resistivity of the contact portion. In addition, by introducing the metal interface layer, the thickness of the adhesive material layer can be reduced by applying the above method for forming contacts in a conductive region, thereby improving the filling process window of the via.
[0019] The following will provide a more detailed description of a method for forming contacts in a conductive region, a semiconductor structure, a chip, and an electronic device according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.
[0020] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.
[0021] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.
[0022] Figures 4A-4E This is a schematic diagram of the steps involved in forming a contact in a conductive region according to an embodiment of this application. Next, we will combine... Figures 4A-4E The method for forming a contact in a conductive region provided in the embodiments of this application will be described in detail.
[0023] like Figure 3 As shown, firstly, step S12 is performed to provide a substrate (not shown), the substrate including an embedded silicon conductive region 110, an interlayer dielectric layer 200 covering the substrate, and a via 210 extending through the thickness direction and into the silicon conductive region 110 in the interlayer dielectric layer 200.
[0024] Please see Figure 4A , Figure 4A This is a schematic diagram of the structure corresponding to the via formed according to an embodiment of this application. The substrate may include a substrate and a device layer located above the substrate. The device layer includes a silicon-containing conductive region 110, which can be used as a source region and a drain region. The material of the substrate may include, but is not limited to, silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon-germanium-on-insulator (SGOI); or may be other materials, such as gallium arsenide or other III-V compounds.
[0025] An interlayer dielectric layer 200 is deposited on the device layer. The interlayer dielectric layer 200 can be formed using any suitable process known to those skilled in the art, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The material of the interlayer dielectric layer 200 is, for example, silicon dioxide.
[0026] As shown in Figure 4A, after forming the interlayer dielectric layer 200, a via 210 is formed in the interlayer dielectric layer 200 using a patterning process. The via 210 exposes at least a portion of the silicon-containing conductive region 110. The patterning process includes: first forming a patterned mask layer on the interlayer dielectric layer 200; then etching the interlayer dielectric layer 200 using the patterned mask layer as a mask until a portion of the silicon-containing conductive region 110 is exposed. In some embodiments, the patterned mask layer may include a patterned photoresist layer. The step of forming the patterned photoresist layer includes: forming a photoresist layer on the interlayer dielectric layer 200; performing exposure and development processes on the photoresist layer to form a patterned photoresist layer; then etching the interlayer dielectric layer 200 using the patterned photoresist layer as a mask until a portion of the silicon-containing conductive region 110 is exposed; and finally removing the patterned photoresist layer, thereby forming the via 210. In another embodiment, the patterned mask layer may include a patterned hard mask layer. In this case, forming a via 210 in the interlayer dielectric layer 200 by a patterning process includes: forming a patterned hard mask layer on the interlayer dielectric layer 200; using the patterned hard mask layer as a mask, etching the interlayer dielectric layer 200 to form the via 210. The patterned hard mask layer may be etched based on a patterned photoresist layer.
[0027] Referring again to Figure 4A, via 210 is located above silicon-containing conductive region 110 to expose silicon-containing conductive region 110. The inner surface of via 210 includes a bottom surface and sidewalls. The silicon-containing conductive region 110 is made of an element selected from at least one of Group IV compounds, or a compound composed of two or more of them.
[0028] In some embodiments, the silicon-containing conductive region 110 is used as a source region and a drain region, for example, a source region and a drain region formed by an ion implantation process, an epitaxial process or other processes, and the material of the silicon-containing conductive region 110 includes doped crystalline or amorphous silicon or silicon germanium.
[0029] like Figure 3 As shown, next, step S14 is performed to form a metal interface layer 212 on the bottom surface of the through hole 210.
[0030] Please see Figure 4B , Figure 4BThis is a schematic diagram of the structure corresponding to the metal interface layer formed according to an embodiment of this application. As shown in FIG4B, the metal interface layer 212 is selectively formed on the bottom surface of the via 210, but not on the sidewalls of the via 210 and the surface of the interlayer dielectric layer 200, which is made of a dielectric material. The material of the metal interface layer 212 includes a first metal, which is selected as a high-melting-point metal. It should be understood that the term "high-melting-point metal" as used herein refers to a transition metal with a melting point higher than that of iron (>1535°C). For example, the first metal included in the metal interface layer 212 is selected from at least one of molybdenum (Mo), tungsten (W), tantalum (Ta), and niobium (Nb).
[0031] In some embodiments, at step S14, an atomic layer deposition process is used to deposit a metal interface layer 212 using a halide of a first metal as a metal precursor. By selecting a high-melting-point metal as the first metal, and taking advantage of the metal affinity of high-melting-point metal halides, the high-melting-point metal halides will preferentially adsorb onto the silicon-containing conductive region 110. The surface of the interlayer dielectric layer 200, which is made of a material such as silicon oxide, is mainly composed of hydroxyl groups (-OH) or bridging oxygen bonds (-O-), exhibiting strong polarity but weak reducing ability. The high-melting-point metal halides are easily swept away from the surface of the interlayer dielectric layer.
[0032] The material and thickness of the metal interface layer 212 can be appropriately determined based on the width of the via and the required electrical properties. For example, the deposited metal interface layer 212 may be made of molybdenum (Mo) and have a thickness of less than or equal to 10 Å. For instance, a molybdenum-based metal interface layer 212 with a thickness of less than or equal to 3 Å, 5 Å, or 7 Å provides sufficient molybdenum to interdiffused with silicon to participate in the formation of low-resistivity metal silicides, while also reducing or avoiding the residue of non-low-resistivity molybdenum-containing materials, thereby preventing an undesirable increase in the overall contact resistivity.
[0033] Step S14 further includes pretreating the substrate surface exposed by the via 210 with hydrogen-containing plasma before forming the metal interface layer 212 on the bottom surface of the via 210. In one example, the material of the silicon conductive region 110 includes crystalline or amorphous silicon or silicon-germanium. The above pretreatment can be performed using a remote plasma source. The specific process includes: by configuring the radio frequency output power of the remote plasma source to 3500W-4000W, hydrogen-containing gas such as H2 is excited, and the excited state hydrogen-containing neutral particles obtained after filtering out charged particles are introduced into the reaction chamber. The excited state hydrogen-containing neutral particles are mainly hydrogen free radicals. Under the conditions of deposition temperature of 300℃-350℃ and chamber pressure of 50mTorr-80mTorr, hydrogen free radicals are used to enrich the surface of the exposed silicon or silicon-germanium material with Si-H bonds or Ge-H bonds. By performing pretreatment before forming the metal interface layer 212 on the bottom surface of the via 210, the reducibility and metal affinity of the silicon or silicon-germanium material surface can be enhanced, further improving the selectivity of thin film deposition. It can also promote the reduction / ligand exchange reaction of the metal precursor, thereby promoting the nucleation of high-melting-point metals.
[0034] Furthermore, after pretreatment of the substrate surface exposed by the via 210, a metal interface layer 212 is deposited on the bottom surface of the via 210 by atomic layer deposition. The specific process includes: introducing a halide of a first metal as a metal precursor under the conditions of deposition temperature of 300℃-500℃ and chamber pressure of less than 10 Torr, and performing atomic layer deposition. The halide of the first metal includes at least one of MoCl5, MoCl4, MoCl6, and MoF6.
[0035] like Figure 3 As shown, next, step S16 is performed, in which an adhesive material layer 214 and a barrier material layer 216 are sequentially formed on the inner surface of the through hole 210, and the adhesive material layer 214 contacts the metal interface layer 212 at the bottom of the through hole 210.
[0036] Please see Figure 4C , Figure 4C This is a schematic diagram of the structure corresponding to the formation of the barrier material layer according to an embodiment of this application. As shown in FIG4C, the adhesion material layer 214 is formed on the inner surface of the through hole 210 and also covers the interlayer dielectric layer 200.
[0037] In some embodiments, the adhesion material layer 214 is conformally deposited using chemical vapor deposition or atomic layer deposition. The adhesion material layer 214 is made of a second metal, the second metal having a melting point lower than that of the first metal, and includes at least one of cobalt (Co), titanium (Ti), nickel (Ni), and platinum (Pt). For example, titanium is selected as the material for the adhesion material layer 214, and the thickness of the adhesion material layer 214 is less than or equal to 80 Å.
[0038] In step S16, after forming the adhesion material layer 214, a barrier material layer 216 is formed on the adhesion material layer 214. Similarly, the barrier material layer 216 is formed on the adhesion material layer 214 using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The material of the barrier material layer 216 includes, but is not limited to, at least one of TiN, TaN, W₂N, and TiSiN. For example, the barrier material layer 216 can be made of TiN, TaN, W₂N, TiSiN, or a combination of TiN, TaN, W₂N, and TiSiN, and the thickness of the barrier material layer 216 is 10 Å-20 Å. Figure 4C As shown, the barrier material layer 216 covers the interlayer dielectric layer 200.
[0039] The steps of forming the adhesive material layer 214 and the barrier material layer 216 can be performed sequentially using similar metal precursors, with the metal elements contained in the adhesive material layer being the same as those in the barrier material layer. In this case, the method for forming the barrier material layer 216 can include forming the barrier material layer 216 on the adhesive material layer 214 using the same machine used to form the adhesive material layer 214. By making reasonable use of the machine, the preparation of two thin films can be completed in one machine, improving preparation efficiency and reducing the introduction of impurities.
[0040] like Figure 3 As shown, next, step S18 is performed, in which the metal interface layer 212 is transformed into a buffer layer 220a by an annealing process, and the adhesive material layer 214 with at least a partial thickness is transformed into a contact body layer 220b, thereby forming a contact portion 220 including the buffer layer 220a and the contact body layer 220b.
[0041] Please see Figure 4D and Figure 4E , Figure 4D This is a schematic diagram of the corresponding structure after the contact portion is formed according to the embodiments of this application. Figure 4E for Figure 4D A magnified view of a portion of the structure at position A. (See attached image.) Figure 4D and Figure 4E As shown, the contact portion 220 includes a buffer layer 220a and a contact body layer 220b sequentially stacked in a direction away from the substrate. The material of the buffer layer 220a includes a metal silicide comprising a first metal and a second metal, wherein the first metal is derived from the metal interface layer 212 and the second metal is derived from the adhesive material layer 214.
[0042] In step S18, through an annealing process, the metal interface layer 212 reacts with the silicon-containing conductive region 110 (e.g., source and drain regions) at the bottom of the via 210. At the interface between the metal interface layer 212 and the silicon-containing conductive region 110, the high-melting-point first metal undergoes a silicide reaction with the silicon material. Interdiffusion also occurs between the silicon and the metal. The resulting metal silicide hinders the diffusion of the metal to the substrate, while silicon atoms diffuse towards the adhesion material layer 214, transforming the metal interface layer 212 into a buffer layer 220a. The buffer layer 220a can serve as a growth substrate for subsequent metal silicides, thereby optimizing the nucleation sites of the contact host layer 220b containing the second metal silicide. Figure 4D and Figure 4E As shown, after the annealing process, a buffer layer 220a is formed, transforming a portion of the adhesive material layer 214 into a contact substrate layer 220b. The buffer layer 220a has a thickness close to that of the original metal interface layer 212. For example, the thickness of the resulting buffer layer 220a is less than or equal to 10 nm, particularly less than or equal to 5 nm.
[0043] In some embodiments, the annealing process includes a rapid thermal annealing (RTP) process to form a buffer layer 220a and a contact substrate layer 220b. The buffer layer 220a is made of a metal silicide comprising a first metal and a second metal, wherein the first metal is derived from the metal interface layer 212 and the second metal is derived from the adhesion material layer 214. For example, the buffer layer 220a may be made of at least one of molybdenum titanium silicide, molybdenum cobalt silicide, and molybdenum nickel silicide. Compared to not introducing the metal interface layer 212, by pre-forming the metal interface layer 212, the metal interface layer 212 transforms into the buffer layer 220a during the annealing process, providing a growth substrate with improved surface smoothness. This allows for the growth of a low-resistivity C54 phase titanium silicide with a clear interface, and also significantly improves the problem of high edge resistance in metal silicides.
[0044] For example, the metal interface layer 212 is made of molybdenum (Mo), the adhesive material layer 214 is made of titanium (Ti), the annealing process temperature can be from 500°C to 750°C, and the resulting contact body layer 220b is made of C54 phase titanium silicide. Compared to not introducing the metal interface layer 212, the annealing process for transforming native titanium silicide into low-resistivity C54 phase titanium silicide needs to be performed at temperatures above 750°C, or even as high as 950°C. By pre-forming an ultrathin metal interface layer 212 containing a high-melting-point metal, the nucleation of native titanium silicide can be guided, significantly reducing the process temperature used to transform into low-resistivity titanium silicide, and also improving the thermal stability of low-resistivity titanium silicide. Moreover, the resulting buffer layer 220a is also formed as a low-resistivity metal silicide, such as C40 phase molybdenum titanium silicide (Mo,Ti)Si2.
[0045] This application also provides a method for fabricating a semiconductor structure, including the method for forming a contact in a conductive region as described in previous embodiments, thereby forming a contact portion that contacts a silicon-containing conductive region; and, Step S20: Forming a conductive part.
[0046] After step S18, step S20 is performed to form a conductive portion 328, including: forming a seed crystal material layer 317 in the through hole 210 and on the barrier material layer; A metallization layer 318 is formed by filling the via 210 and covering it with an interlayer dielectric layer 200; The planarization process is applied to the metallization layer 318 so that the top surface of the planarized metallization layer is flush with the top surface of the interlayer dielectric layer 200.
[0047] Figures 5A to 5B Schematic diagrams of the structures obtained at different stages of the method for forming conductive parts provided in embodiments of this application are shown. Figure 5A As shown, a seed material layer 317 is formed on a barrier material layer 316, and a metallization layer 318 fills the via 210 and covers the interlayer dielectric layer 200.
[0048] In some embodiments, a metallization layer 318 is formed by depositing a metal filler material using an electrochemical plating (ECP) process. The metal filler material used to form the metallization layer 318 includes at least one of cobalt (Co), molybdenum (Mo), and ruthenium (Ru).
[0049] Step S20 further includes: after forming the metallization layer 318, performing a planarization process on the metallization layer 318, removing the portion of the metallization layer 318 covering the interlayer dielectric layer 200, and forming a metal filler 318f within the via 210, such that the top surface of the formed metal filler 318f is flush with the top surface of the interlayer dielectric layer 200. After performing the planarization process, as shown... Figure 5BAs shown, a conductive portion 328 is formed, comprising a seed crystal layer 317r and a metal filler 318f, wherein the seed crystal layer 317r is located between the metal filler 318f and the diffusion barrier 326.
[0050] In some embodiments, step S20, planarization of the metallization layer 318 is performed using, for example, a chemical mechanical polishing (CMP) process. This also includes removing portions of the adhesive material layer 314 and the barrier material layer 316 that are overlying the interlayer dielectric layer 200. The portions of the adhesive material layer 314 and the barrier material layer 316 located in the via 210 together constitute a diffusion barrier 326 to block the diffusion of the metal filler material. Figure 5A As shown, after planarization, the portions of the adhesive material layer 314 and the barrier material layer 316 on the interlayer dielectric layer 200 are removed. The portion of the adhesive material layer 314 located in the through hole 210 is formed as the adhesive layer 314r, and the portion of the barrier material layer 316 located in the through hole 210 is formed as the barrier layer 316r. The adhesive layer 314r and the barrier layer 316r together constitute the diffusion barrier 326. The diffusion barrier 326 extends along the thickness direction of the interlayer dielectric layer 200 and at least covers the sidewall of the through hole 210.
[0051] By pre-forming an ultrathin metal interface layer 312, the transformed buffer layer 320a contains silicides of high-melting-point metals derived from the metal interface layer. The buffer layer 320a serves as the growth substrate for the subsequent contact host layer, allowing the low-resistivity metal silicides with clear growth interfaces to serve as the contact host layer 320b. This promotes the formation of low-resistivity metal silicides without increasing the overall thickness of the contact portion 320, further reducing contact resistance and improving the filling process window.
[0052] This application also provides a semiconductor structure that can be fabricated using the methods described above. For example... Figure 5B As shown, the semiconductor structure 500 provided in this application embodiment includes: a device layer, an interlayer dielectric layer 200, a conductive portion 328, a diffusion barrier 326, and a contact portion 320. The device layer includes a silicon-containing conductive region 110. The interlayer dielectric layer 200 covers the device layer. The conductive portion 328 is provided through the thickness direction of the interlayer dielectric layer 200 and is located above the silicon-containing conductive region 110. The diffusion barrier 326 at least covers the sidewall of the conductive portion 328. The contact portion 320 is located between the silicon-containing conductive region 110 and the conductive portion 328 and is in contact with the silicon-containing conductive region 110. The contact portion 320 includes a buffer layer 320a and a contact body layer 320b that are sequentially stacked in a direction away from the device layer.
[0053] The buffer layer 320a is made of a metal silicide comprising a first metal and a second metal. The first metal is selected as a high-melting-point metal, including, for example, molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb), or similar high-melting-point metals. The first metal has a higher melting point than the second metal. The second metal includes at least one of cobalt (Co), titanium (Ti), nickel (Ni), and platinum (Pt). The contact body layer 320b is made of a metal silicide of the second metal. In some embodiments, such as... Figure 5B As shown, the buffer layer 320a is in contact with the silicon-containing conductive region 110, and the material of the contact body layer 320b includes at least one of molybdenum titanium silicide, molybdenum cobalt silicide, and molybdenum nickel silicide.
[0054] In some embodiments, such as Figure 5B As shown, the diffusion barrier 326 also covers the end face of the conductive portion 328 adjacent to the contact portion 320. The diffusion barrier 326 includes an adhesion layer 314r and a barrier layer 316r sequentially stacked in a direction away from the contact portion 320. The sum of the thicknesses of the contact portion 320 and the adhesion layer 314r in the stacking direction is less than or equal to 90 Å. By pre-forming an ultra-thin metal interface layer, the contact portion 320 includes a buffer layer 320a and a contact body layer 320b, promoting the formation of low-resistivity metal silicides without increasing the overall thickness of the contact portion 320. The specific contact resistance of the contact portion 320 is significantly reduced, and in some cases, the resistivity of the contact portion is reduced by more than 30%. It also reduces the thickness of the diffusion barrier as a proportion of the cross-section of the entire connecting wire, thereby significantly reducing interconnect delay.
[0055] The beneficial effects of the semiconductor structure provided in this application embodiment can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here.
[0056] This application also provides a chip, which may include the semiconductor structure described in this application. For a detailed description of the semiconductor structure, please refer to the preceding section on the construction and fabrication methods of the semiconductor structure; further details will not be repeated here.
[0057] The chip includes at least one semiconductor structure, which is the semiconductor structure described in the embodiments of this application. Optionally, the semiconductor structure may include a field-effect semiconductor structure. Based on the channel doping type, field-effect semiconductor structures can be divided into P-type channel semiconductor structures and N-type channel semiconductor structures. Spatially, field-effect semiconductor structures may include planar field-effect semiconductor structures, such as Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET), FinField Effect Transistor (FINFET), Gate-All-Around Field-Effect Transistor (GAAFET), etc.
[0058] This application also provides an electronic device that may include the semiconductor structure described in this application. The electronic device includes a chip and a circuit board. The chip includes the semiconductor structure, is disposed on the circuit board, and is electrically connected to the circuit board.
[0059] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device. In other embodiments of this application, the electronic device may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.
[0060] For example, the electronic devices in this application embodiment may include various devices with computing functions, such as mobile phones, tablets, televisions, desktop computers, laptops, handheld computers, laptops, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, smart wearable devices (e.g., smartwatches, smart bracelets), in-vehicle devices, smart home devices, and / or smart city devices. This application embodiment does not impose any special limitations on the specific types of the electronic devices.
[0061] In summary, this application provides a method for forming a contact in a conductive region, a semiconductor structure, a chip, and an electronic device. The method for forming a contact in a conductive region includes: providing a substrate, the substrate including an embedded silicon-containing conductive region, an interlayer dielectric layer covering the substrate, and a via extending through the thickness direction to the silicon-containing conductive region in the interlayer dielectric layer; forming a metal interface layer on the bottom surface of the via, the metal interface layer being made of a first metal; sequentially forming an adhesive material layer and a barrier material layer on the inner surface of the via, the adhesive material layer contacting the metal interface layer at the bottom of the via, the adhesive material layer being made of a second metal; transforming the metal interface layer into a buffer layer through an annealing process, and transforming at least a portion of the thickness of the adhesive material layer into a contact body layer, thereby forming a contact portion including the buffer layer and the contact body layer, the buffer layer being made of a metal silicide comprising the first metal and the second metal, the contact body layer being made of a silicide of the second metal, and the first metal having a melting point higher than that of the second metal. This application forms a metal interface layer on the bottom surface of the through-hole after forming a through-hole in the interlayer dielectric layer and before forming the adhesive material layer. The metal interface layer contains a high-melting-point metal. By introducing the metal interface layer, the first metal with a high melting point reacts with the silicon material during the annealing process to form a buffer layer. The buffer layer provides a stable interface for the contact host layer, which is beneficial for preparing a contact host layer with low resistivity and optimized thermal stability, thereby improving the specific contact resistivity of the contact portion.
[0062] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and not to indicate the logical or sequential relationships between the various components, elements, steps, etc.
[0063] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.
Claims
1. A method for forming a contact in a conductive region, characterized in that, include: A substrate is provided, the substrate including an embedded silicon-containing conductive region, an interlayer dielectric layer covering the substrate, the interlayer dielectric layer having a via extending through the thickness direction and into the silicon-containing conductive region, the inner surface of the via including a bottom surface; A metal interface layer is formed on the bottom surface of the through hole, and the material of the metal interface layer includes a first metal; An adhesive material layer and a barrier material layer are sequentially formed on the inner surface of the through hole. The adhesive material layer contacts the metal interface layer at the bottom of the through hole. The material of the adhesive material layer includes a second metal. The metal interface layer is transformed into a buffer layer by an annealing process, and the adhesive material layer with at least a partial thickness is transformed into a contact body layer, thereby forming a contact portion including the buffer layer and the contact body layer. The material of the buffer layer includes a metal silicide comprising the first metal and the second metal, and the material of the contact body layer includes a silicide of the second metal. The first metal has a melting point higher than that of the second metal.
2. The method according to claim 1, characterized in that, The formation of a metal interface layer on the bottom surface of the via includes: forming the metal interface layer on the bottom surface of the via using an atomic layer deposition process, wherein the thickness of the metal interface layer is less than or equal to 10 Å.
3. The method according to claim 2, characterized in that, The formation of a metal interface layer on the bottom surface of the through hole includes: the metal precursor used in the atomic layer deposition process includes a halide of a first metal, wherein the first metal includes at least one of molybdenum, tantalum, tungsten, and niobium.
4. The method according to claim 1, characterized in that, The step of sequentially forming an adhesive material layer and a barrier material layer on the inner surface of the through hole includes: conformally depositing the adhesive material layer by chemical vapor deposition or atomic layer deposition, wherein the adhesive material layer is formed on the inner surface of the through hole and covers the interlayer dielectric layer, wherein the second metal includes at least one of titanium, cobalt, and nickel, and the thickness of the adhesive material layer is less than or equal to 80 Å.
5. The method according to claim 1, characterized in that, The contact portion satisfies at least one of the following: The material of the buffer layer includes at least one of molybdenum titanium silicide, molybdenum cobalt silicide, and molybdenum tantalum silicide; The material of the contact body layer includes at least one of titanium silicide, cobalt silicide, and nickel silicide.
6. The method according to claim 1, characterized in that, The process of transforming the metal interface layer into a buffer layer and transforming at least a portion of the thickness of the adhesive material layer into a contact substrate layer by annealing includes: the annealing temperature is 500°C to 750°C, the material of the buffer layer includes molybdenum titanium silicide, and the material of the contact substrate layer includes C54 phase titanium silicide.
7. The method according to claim 1, characterized in that, Before forming a metal interface layer on the bottom surface of the through hole, the method further includes: pretreating the substrate surface exposed by the through hole with hydrogen-containing plasma.
8. A method for fabricating a semiconductor structure, characterized in that, include: The method for forming a contact in a conductive region as described in claim 1; Forming a conductive part includes: A seed crystal material layer is formed inside the through hole and on the barrier material layer; A metallization layer is formed by filling the vias and covering the interlayer dielectric layer; The metallization layer is planarized so that the top surface of the planarized metallization layer is flush with the top surface of the interlayer dielectric layer.
9. A semiconductor structure, characterized in that, include: Device layer, the device layer including silicon-containing conductive regions; An interlayer dielectric layer is applied over the device layer; The conductive portion extends along the thickness direction of the interlayer dielectric layer and is located above the silicon-containing conductive region; A diffusion barrier, at least covering the sidewall of the conductive portion; A contact portion is located between the silicon-containing conductive region and the conductive portion, and contacts the silicon-containing conductive region. The contact portion includes a buffer layer and a contact body layer stacked sequentially in a direction away from the device layer. The material of the buffer layer includes a metal silicide comprising a first metal and a second metal. The material of the contact body layer includes a silicide of the second metal. The first metal has a melting point higher than that of the second metal.
10. The semiconductor structure according to claim 9, characterized in that, The first metal includes at least one of molybdenum, tantalum, tungsten, and niobium, and the second metal includes at least one of titanium, cobalt, and nickel.
11. The semiconductor structure according to claim 10, characterized in that, The thickness of the buffer layer is less than or equal to 10 Å, and the material of the buffer layer includes at least one of molybdenum titanium silicide, molybdenum cobalt silicide, and molybdenum nickel silicide.
12. The semiconductor structure according to claim 9, characterized in that, The diffusion barrier also covers the end face of the conductive portion adjacent to the contact portion. The diffusion barrier includes an adhesive layer and a barrier layer stacked sequentially in a direction away from the contact portion. The sum of the thicknesses of the contact portion and the adhesive layer in the stacking direction is less than or equal to 90 Å.
13. A chip, characterized in that, include: The semiconductor structure as described in claim 9.
14. An electronic device, characterized in that, include: The chip as described in claim 13.