Through-silicon via (TSV) silicon wafer processing technology

Abstract

TSV silicon wafer through-hole process technology; The technical field to which the present invention belongs is: integrated circuits and semiconductor field; Silicon wafer through-hole process in wafer-to-wafer (W2W), chip-to-wafer (C2W) or chip-to-chip (C2C) stacking process; Wafer stacking; Wafer interposer stacking; Production and foundry of space computing chip, optical chip, quantum chip, computing data chip and high-end AI chip; Stacking (HBM) packaging technical field, relating to the process technology of silicon wafer through-hole. The advantages and effects of the present invention are: the present invention can realize vertical interconnection of multi-layer wafers or chips, and realize etching with higher aspect ratio; in addition, it is faster, can meet the requirements of cost and efficiency of the industry, and can reach the chip vertical interconnection design requirements of international leading chip enterprises. Purpose: to realize effective breakthrough in silicon wafer through-hole process in wafer-to-wafer (W2W), chip-to-chip (C2W) or chip-to-chip (C2C) stacking process, wafer stacking, wafer interposer stacking; to realize effective breakthrough in the process technology of silicon wafer through-hole in the production and foundry of quantum chip, computing data chip and high-end AI chip, stacking (HBM) packaging technical field, and to provide high-end process technology on the basis of the original, improve the production and yield of wafers and HBM chips. Use: high-precision wafer and chip manufacturing.

Description

[0001] Technical fields: integrated circuits and semiconductors; silicon wafer through-hole (TBH) technology in wafer-to-wafer (W2W), chip-to-wafer (C2W), or chip-to-chip (C2C) stacking processes; wafer stacking and interconnection; wafer interposer stacking interconnection; production and foundry of space computing chips, optical chips, quantum chips, computing data chips, and high-end AI chips; stacking (HBM) packaging technology, involving silicon wafer through-hole process technology.

[0002] Background technology: Currently, the related silicon wafer through-hole (TSV) technology in China has problems such as outdated process technology, low yield, and low production capacity. Moreover, it is difficult to achieve higher aspect ratio etching and the efficiency is limited in deep reactive ion etching (DRIE) for TSV holes. The number of wafer and chip stacking / interconnect layers is also limited.

[0004] This invention is mature and can be used for large-scale mass production.

[0005] Summary of the Invention: The technical solution of this invention is the four-step process technology of Guobiao Semiconductor's TSV silicon wafer through-hole process, namely, drilling, deposition coating, electroplating, and CMP polishing. The specific process steps are as follows: 1. Drilling to form blind holes. The method adopted in this invention is: laser drilling and Bosch process of deep reactive ion etching (DRIE). Key features: 1. The invention employs a unique 3-step "etch-deposition-re-etch" multi-cycle technique. This technique gradually deepens the trenches or holes until they meet the design requirements of leading international chip companies. For silicon-based TSV holes with large aspect ratios, a dry etching method using fluorine-based gases is primarily used to ensure hole smoothness, vertical sidewalls, and correct depth. 2. Deposition of dielectric and seed layers: Dielectric layer: A solid film or coating is formed on the silicon wafer surface using chemical vapor deposition (CVD) as an insulating layer. Seed layer: A layer of titanium is sputtered first (to improve adhesion and prevent copper diffusion with silicon), followed by a layer of copper (to provide conductivity for subsequent copper electroplating). The coating thickness of this invention is generally controlled within 50nm, reaching an internationally leading level. 3. Copper electroplating: The role of copper is to achieve electrical interconnection of TSVs. Advantages: Good conductivity and thermal conductivity, strong heterogeneous integration capabilities. The copper-plated pillars of this invention have a hole diameter of 3µm and a hole depth of 26µm. 4. CMP (Chemical Mechanical Polishing): Purpose: To remove the surface copper layer, thin the back of the silicon wafer, and expose the copper plating in the through-holes, preparing for subsequent multi-layer copper interconnects. Process: A combination of chemical reaction and mechanical polishing removes the surface layer of the silicon wafer. End-point monitoring determines the degree of polishing, and finally, cleaning removes particulate contaminants. Note: A tempering process is performed before CMP after electroplating to reduce the internal stress of the electroplated copper. The surface roughness Ra after CMP polishing in this invention is <1nm, reaching a wafer-level, internationally leading level, with test results showing Ra = 0.6665nm-0.7774nm.

[0006] The purpose of this invention is to achieve effective breakthroughs in silicon wafer through-hole (TBH) technology, wafer stacking / interconnection, and wafer interposer stacking / interconnection in wafer-to-wafer (W2W), chip-to-wafer (C2W), or chip-to-chip (C2C) stacking processes; to enable the production and foundry of space computing chips, optical chips, quantum chips, computing data chips, and high-end AI chips; to achieve effective breakthroughs in silicon wafer through-hole (HBM) process technology in the field of stacked packaging technology; and to provide advanced process technology on the existing basis to improve the production and yield of wafers and HBM chips.

[0007] The advantages and effects of this invention are as follows: This invention can realize multi-layer wafer or chip stacking / vertical interconnection and achieve higher aspect ratio etching; in addition, it has a faster speed, which can meet the industry's requirements for cost and efficiency, and even reach the chip vertical interconnection design requirements of leading international chip companies. It achieves effective breakthroughs in silicon wafer through-hole technology, wafer stacking / interconnection, and wafer interposer stacking / interconnection in wafer-to-wafer (W2W), chip-to-wafer (C2W), or chip-to-chip (C2C) stacking processes; it achieves effective breakthroughs in silicon wafer through-hole process technology in the production and foundry of space computing chips, optical chips, quantum chips, computing data chips, and high-end AI chips, as well as in the stacking (HBM) packaging technology field, while providing high-end process technology on the existing basis, improving the production and yield of wafers and HBM chips.

[0008] Detailed Implementation: The present invention will be further described below with reference to the embodiments: First, prepare a small piece of silicon wafer material, 15 mm * 7.5 mm in size and 500 mm in thickness. Then, implement the process steps of this invention as follows: 1. Drill holes to form blind vias. This invention adopts a 4-step method: laser drilling, deep reactive ion etching (DRIE) Bosch process. Key features: Guobiao Semiconductor's TSV silicon wafer through-hole process technology includes a unique 3-step "etch-deposition-re-etch" multi-cycle etching technique. This 3-step multi-cycle technique gradually deepens the trench or hole depth until it meets the design requirements of leading international chip companies. For silicon-based TSV holes with larger aspect ratios, a dry etching method using fluorine-based gases is primarily employed to ensure hole smoothness, vertical sidewalls, and correct depth. 2. Deposition of dielectric and seed layers: Dielectric layer: A solid thin film or coating is formed on the silicon wafer surface using chemical vapor deposition (CVD) as an insulating layer. Seed layer: A layer of titanium is sputtered first (to improve adhesion and prevent copper diffusion with silicon), followed by a layer of copper (to provide conductivity for subsequent copper electroplating). The coating thickness of this invention is basically controlled within 50nm, reaching an internationally leading level. 3. Copper electroplating: The role of copper is to achieve electrical interconnection of TSVs. Advantages: Good electrical and thermal conductivity, strong heterogeneous integration capabilities. The copper pillars of this invention have a hole diameter of 3µm and a hole depth of 26µm. 4. CMP (Chemical Mechanical Polishing): Function: Removes the surface copper layer, thins the back side of the silicon wafer, exposes the copper plating in the through-holes, and prepares for subsequent multi-layer copper interconnects. Process: Through a combination of chemical reaction and mechanical polishing, the surface layer of the silicon wafer is removed. The degree of polishing is determined by endpoint monitoring. Finally, particulate contaminants are removed by cleaning. Note: A tempering process is performed before CMP after electroplating to reduce the internal stress of the electroplated copper. The surface roughness Ra after CMP polishing of this invention is <1nm, reaching a wafer-level, internationally leading level, with test results showing Ra = 0.6665nm-0.7774nm.

[0009] Brief Description of the Drawings of the Invention: Figure 1 : Schematic diagram of the overall process flow of the third Guobiao TSV silicon wafer through-hole process technology in four steps; Figure 2 The prepared 8-inch silicon wafer is 200mm thick and 500um. Figure 3 The third process technology of Guobiao TSV silicon wafer through-hole process technology is a unique three-step "etching-deposition-re-etching" multiple cycle technology in the four-step etching process. Figure 4 : SEM image of the blind hole drilling process performed using the method unique to this invention; Figure 5 The thickness of the deposited film was measured by SEM using a unique method of this invention; the film thickness was 47 nm. Figure 6 : Photographs showing the effect of electroplating on silicon wafers according to the present invention; Figure 7 : SEM image of the electroplated copper pillar; Figure 8 This is a 3D imaging image showing the surface roughness after the unique CMP polishing process of this invention. Figure 9 Screenshot of the surface roughness test results after CMP polishing of the product processed according to this invention. CMP polishing: wafer-level CMP polishing, surface roughness Ra=0.6665nm-0.7774nm.

Claims

1. The technical solution of the present invention is: TSV silicon wafer through-hole process technology in 4 steps, namely drilling, deposition coating, electroplating, and CMP polishing.

2. The specific process steps are as follows:

1. Drilling to form blind vias. The method adopted in this invention is: laser drilling and Bosch process of deep reactive ion etching (DRIE). Key: The invention's unique 3-step "etch-deposition-re-etch" multiple-cycle technology gradually deepens the depth of trenches or holes until the design requirements of leading international chip companies are met. For silicon-based TSV vias with a large aspect ratio, a dry etching method using fluorine-based gas is mainly used to ensure the smoothness, vertical sidewalls, and correct depth of the vias.

2. Deposition of dielectric and seed layers: Dielectric layer: A solid thin film or coating is formed on the silicon wafer surface using chemical vapor deposition (CVD) as an insulating layer; Seed layer: A layer of titanium is first sputtered using physical vapor deposition (PVD) (to improve adhesion and prevent copper-silicon diffusion), followed by a layer of copper (to provide conductivity for subsequent copper electroplating). The coating thickness of this invention is basically controlled within 50nm, reaching an internationally leading level.

3. Copper electroplating: The role of copper is to achieve electrical interconnection of TSVs. Advantages: good electrical and thermal conductivity, strong heterogeneous integration capabilities. The electroplated copper pillars of this invention have a hole diameter of 3µm and a hole depth of 26µm.

4. CMP (Chemical Mechanical Polishing): Purpose: To remove the surface copper layer, thin the back of the silicon wafer, and expose the copper plating in the through-holes, preparing for subsequent multi-layer copper interconnects. Process: A combination of chemical reaction and mechanical polishing removes the surface layer of the silicon wafer. End-point monitoring determines the degree of polishing, and finally, cleaning removes particulate contaminants. Note: A tempering process is performed before CMP after electroplating to reduce the internal stress of the electroplated copper. The surface roughness Ra after CMP polishing in this invention is <1nm, reaching a wafer-level, internationally leading level, with test results showing Ra = 0.6665nm-0.7774nm.

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