A shielding structure, a boundary structure for multi-section silicon interposer and a design method thereof

Abstract

The present disclosure relates to a shielding structure, a boundary structure and a design method thereof for multi-section silicon interposers, according to the characteristic information of each sub-interposer and the process design rules, the wiring density threshold at the splicing boundary between adjacent sub-interposers is set; based on the characteristic information, the splicing distance between adjacent sub-interposers and the wiring density threshold, the initial boundary structure for each splicing boundary is determined, the initial boundary structure includes a shielding corridor and a shielding structure and a cross-boundary signal trace located in the shielding corridor; based on the target impedance, the initial boundary structure is iteratively optimized to obtain the target boundary structure set at each splicing boundary that meets the preset conditions, the density control, the shielding structure design and the impedance tuning are organically integrated, and the signal integrity and reliability problems at the splicing boundary are systematically solved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a shielding structure, boundary structure and design method for multi-segment silicon interposers. Background Technology

[0002] With the ever-increasing demands for computing power from applications such as high-performance computing, artificial intelligence, and graphics processing units (GPUs), semiconductor packaging based on large-area interposers is gaining increasing attention. Chip-on-Wafer-on-Substrate (CoWoS-L), as a representative of advanced packaging, achieves ultra-short-distance, ultra-high-density interconnects between logic chips (such as GPUs or ASICs) and high-bandwidth memory (HBM) by introducing high-density interposers. However, when the package size exceeds the limit of the photomask size, multiple sub-interposers need to be stitched together to form a large multi-segment silicon interposer. This multi-segment silicon interposer, formed by stitching together multiple sub-interposers, suffers from physical gaps at the stitch interface between adjacent sub-interposers, leading to discontinuities in wiring, increased electromagnetic interference, and enhanced coupling, resulting in decreased signal integrity—a technical problem that urgently needs to be solved. Summary of the Invention

[0003] In view of this, this disclosure proposes a shielding structure, boundary structure and design method for multi-segment silicon interposers.

[0004] According to one aspect of this disclosure, a design method for a boundary structure of a multi-segment silicon interposer is provided, wherein the multi-segment silicon interposer is formed by splicing together multiple sub-interposers, the method comprising:

[0005] Based on the characteristic information and process design rules of each sub-intermediate layer, set the wiring density threshold at the splicing boundary between adjacent sub-intermediate layers;

[0006] Based on the feature information, the splicing distance between adjacent sub-intermediate layers and the wiring density threshold, an initial boundary structure is determined for each splicing boundary. The initial boundary structure includes a shielding corridor and a shielding structure and cross-boundary signal traces located within the shielding corridor.

[0007] The initial boundary structure is optimized and iterated based on the target impedance to obtain a target boundary structure that meets the preset conditions and is set at each of the splicing boundaries, so that the signal integrity and reliability of the multi-segment silicon interposer are optimal at each of the splicing boundaries.

[0008] The target impedance refers to the characteristic impedance value that the cross-boundary signal trace is expected to achieve to avoid signal reflection during signal transmission.

[0009] In one possible implementation, the shielding corridor is located at the corresponding splicing boundary and extends along the splicing boundary;

[0010] The cross-boundary signal trace extends from one sub-intermediate layer through the interior of the shielded corridor, across the splicing boundary, to another adjacent sub-intermediate layer.

[0011] The shielding structure includes a TSV shielding column array and / or grounding shielding traces;

[0012] The TSV shielding pillar array includes multiple conductive pillars that penetrate the sub-intermediate layer and are arranged around the cross-boundary signal trace.

[0013] The grounding shielding trace is located in the redistribution layer within the shielding corridor of the sub-intermediate layer, and is disposed on at least one side of the cross-boundary signal trace and extends along the extension direction of the cross-boundary signal trace.

[0014] In one possible implementation, the initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that satisfies preset conditions, including:

[0015] Based on the target impedance, an optimization adjustment operation is performed on the initial boundary structure to obtain the optimized boundary structure;

[0016] If the optimized boundary structure satisfies the preset conditions, the optimized boundary structure is determined as the target boundary structure.

[0017] The preset conditions include at least one of the following:

[0018] First condition: The deviation between the characteristic impedance and the target impedance of the cross-boundary signal trace is within a preset range;

[0019] Second condition: The crosstalk between the cross-boundary signal trace and the adjacent signal trace is lower than a preset threshold;

[0020] Third condition: The geometric parameters of each structure in the optimized boundary structure all satisfy the process design rules.

[0021] In one possible implementation, the initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that satisfies preset conditions, and the implementation further includes:

[0022] If the optimized boundary structure does not meet the first condition in the preset conditions, the optimization adjustment operation and subsequent steps are re-executed.

[0023] In one possible implementation, the initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that satisfies preset conditions, and the implementation further includes:

[0024] If the optimized boundary structure does not satisfy the second condition in the preset conditions, the steps of determining the initial boundary structure and subsequent steps are re-executed.

[0025] In one possible implementation, the initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that satisfies preset conditions, and the implementation further includes:

[0026] If the optimized boundary structure does not meet the third condition in the preset conditions, the steps of setting the wiring density threshold and subsequent steps are re-executed.

[0027] In one possible implementation, based on the characteristic information of each sub-intermediate layer and process design rules, a wiring density threshold is set at the splicing boundary between adjacent sub-intermediate layers, including:

[0028] Based on the highest signal frequency of the cross-boundary signal in the feature information, and according to the inverse relationship between frequency and wiring density, the first candidate wiring density corresponding to each splicing boundary is determined, and the cross-boundary signal is a signal transmitted through the cross-boundary signal trace.

[0029] Based on the minimum line spacing and minimum line width indicated by the process design rules, the second candidate wiring density corresponding to each of the splicing boundaries is determined.

[0030] Based on the larger of the first candidate wiring density and the second candidate wiring density corresponding to each of the splicing boundaries, a wiring density threshold corresponding to each of the splicing boundaries is set.

[0031] In one possible implementation, the feature information includes at least one of the following: the planar geometry and size of each of the sub-intermediate layers, the number of stacked redistribution layers in each of the sub-intermediate layers, the material type and thickness of each dielectric layer in each of the sub-intermediate layers, the thickness of each metal layer in each of the sub-intermediate layers, and the frequency of the cross-boundary signal transmitted by the cross-boundary signal traces in each of the sub-intermediate layers.

[0032] In one possible implementation, based on the feature information, the splicing distance between adjacent sub-intermediary layers, and the wiring density threshold, an initial boundary structure is determined for each of the splicing boundaries, including:

[0033] Based on the splicing distance between adjacent sub-intermediate layers, the width of the shielding corridor between adjacent sub-intermediate layers along the direction perpendicular to the splicing boundary is determined;

[0034] Based on the wiring density threshold, the frequency of the cross-boundary signal transmitted by the cross-boundary signal trace, and the process design rules, the arrangement position and diameter of the conductive pillars within the corridor width of the shielded corridor, the spacing between the conductive pillars, and the grounding plane electrically connected to each conductive pillar are determined to obtain a TSV shielding pillar array; and / or, based on the wiring density threshold and the position of the cross-boundary signal trace in the sub-intermediate layer, the grounding shielding trace is provided on at least one side of the cross-boundary signal trace in the redistribution layer within the corridor width of the shielded corridor.

[0035] In one possible implementation, the optimization adjustment operation includes at least one of the following operations:

[0036] Adjust the line width of the cross-boundary signal trace based on the comparison result between the current characteristic impedance of the cross-boundary signal trace and the target impedance.

[0037] Based on the comparison between the current characteristic impedance of the cross-boundary signal trace and the target impedance, the thickness of the medium at the splicing boundary in the shielding corridor is adjusted.

[0038] Based on the lithographic overlay deviation in the splicing sub-intermediate layer, the spacing between differential signal pairs in the cross-boundary signal trace is adjusted.

[0039] In one possible implementation, the method further includes:

[0040] Boundary proximity analysis is performed on the multiple sub-intermediary layers to obtain the physical characteristics of each sub-intermediary layer and determine the splicing distance between adjacent sub-intermediary layers; the splicing distance is the physical interval width of adjacent sub-intermediary layers at the splicing boundary.

[0041] According to another aspect of this disclosure, a shielding structure for multi-segment silicon interposers is provided, wherein the multi-segment silicon interposers are formed by splicing together multiple sub-interposers. The shielding structure is located within a shielding corridor, which is located at the splicing boundary between adjacent sub-interposers. The shielding structure includes a TSV shielding pillar array and / or grounding shielding traces.

[0042] The TSV shielding pillar array includes multiple conductive pillars that penetrate the sub-intermediate layer and are arranged around the cross-boundary signal trace;

[0043] The grounding shielding trace is located in the redistribution layer within the shielding corridor of the sub-intermediate layer, and is disposed on at least one side of the cross-boundary signal trace and extends along the extension direction of the cross-boundary signal trace;

[0044] The shielding corridor is located at the splicing boundary between corresponding adjacent sub-intermediate layers and extends along the splicing boundary; the cross-boundary signal trace is located within the shielding corridor and extends from one sub-intermediate layer through the interior of the shielding corridor, through the splicing boundary, to another adjacent sub-intermediate layer.

[0045] According to another aspect of this disclosure, a boundary structure for a multi-segment silicon interposer is provided, wherein the multi-segment silicon interposer is a plurality of sub-interposers, the boundary structure comprising:

[0046] The shielded corridor is located at the splicing boundary between the corresponding adjacent sub-intermediary layers and extends along the splicing boundary;

[0047] Cross-boundary signal traces are located within the shielded corridor and extend from one sub-intermediate layer through the interior of the shielded corridor, across the splicing boundary, to another adjacent sub-intermediate layer.

[0048] The shielding structure, located within the shielding corridor, includes a TSV shielding column array and / or grounding shielding traces;

[0049] The TSV shielding pillar array includes multiple conductive pillars that penetrate the sub-intermediate layer and are arranged around the cross-boundary signal trace.

[0050] The grounding shielding trace is located in the redistribution layer within the shielding corridor of the sub-intermediate layer, and is disposed on at least one side of the cross-boundary signal trace and extends along the extension direction of the cross-boundary signal trace.

[0051] According to another aspect of this disclosure, a design apparatus for a boundary structure of a multi-segment silicon interposer is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0052] According to another aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the above-described method.

[0053] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0054] The shielding structure, boundary structure, and design method for multi-segment silicon interposers provided in this disclosure, based on the characteristic information and process design rules of each sub-interposer, sets a wiring density threshold at the splicing boundary between adjacent sub-interposers. Based on the characteristic information, the splicing distance between adjacent sub-interposers, and the wiring density threshold, an initial boundary structure is determined for each splicing boundary. This initial boundary structure includes a shielding corridor, a shielding structure within the shielding corridor, and cross-boundary signal traces. The initial boundary structure is iteratively optimized based on the target impedance to obtain a target boundary structure that meets preset conditions at each splicing boundary, thereby optimizing the signal integrity and reliability of the multi-segment silicon interposers at each splicing boundary. By setting the wiring density threshold, the congestion of traces at the splicing boundary is pre-controlled from the wiring resource allocation level, reserving space for the subsequent insertion of shielding structures. By constructing an initial boundary structure including a shielding corridor and shielding structures, an electromagnetic shielding barrier is actively formed at the splicing boundary. Through iterative optimization constrained by the target impedance, the impedance continuity of cross-boundary signal traces is ensured. This method organically integrates density control, shielding structure design, and impedance tuning, systematically solving the signal integrity and reliability issues at the splicing boundary.

[0055] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0056] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0057] Figure 1 A schematic diagram of a semiconductor packaging structure according to an embodiment of the present disclosure is shown.

[0058] Figures 2-3 A schematic diagram of the boundary structure in a multi-segment silicon interposer according to an embodiment of the present disclosure is shown.

[0059] Figure 4 A flowchart illustrating a design method for a boundary structure of a multi-segment silicon interposer according to an embodiment of the present disclosure is shown.

[0060] Figure 5 A schematic diagram of the structure of a TSV shielding column array with different conductive column density distributions is shown in an example according to an embodiment of the present disclosure.

[0061] Figure 6 This diagram illustrates the electromagnetic field distribution of a TSV shielding column array under different conductive column density distributions according to an embodiment of the present disclosure.

[0062] Figure 7This diagram illustrates the shielding effectiveness curves of a TSV shielding column array under different conductive column density distributions in an example according to an embodiment of the present disclosure.

[0063] Figure 8 This is a block diagram illustrating an apparatus 1900 for a boundary structure design method for a multi-segment silicon interposer, according to an exemplary embodiment. Detailed Implementation

[0064] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0065] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0066] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0067] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0068] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0069] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0070] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0071] In multi-segment silicon interposer packages, the bonding region between adjacent sub-interposers forms a splice boundary. Cross-boundary signal traces need to extend from one sub-interposer across the splice boundary to another adjacent sub-interposer to achieve cross-segment signal transmission. Due to the physical gaps at the splice boundary, cross-boundary signal traces face multiple technical challenges in this area:

[0072] First, there is the issue of discontinuity in the wiring. Physical breaks at the splicing boundary mean that cross-boundary signal traces need to be connected when crossing the boundary, which disrupts the geometric continuity of the traces and affects the smooth transmission of signals.

[0073] Second, impedance mismatch. Differences between the dielectric material and trace geometry at the splicing boundary and the interior of the sub-intermediate layer cause abrupt changes in the characteristic impedance of the cross-boundary signal trace at the splicing boundary, resulting in signal reflection, increased insertion loss, and decreased transmission quality.

[0074] Third, electromagnetic interference and crosstalk are aggravated. The lack of a complete reference plane and shielding structure at the splicing boundary makes cross-boundary signal traces susceptible to external electromagnetic interference (EMI) in this area. At the same time, the electromagnetic coupling (crosstalk) between adjacent cross-boundary signal traces is significantly enhanced, affecting the signal integrity and timing consistency of high-speed links.

[0075] Fourth, irregular current density. Geometric variations in the traces at the splicing boundary may cause abnormal local current density, affecting the reliability and lifespan of the package.

[0076] Current splicing boundary handling methods typically treat splicing boundaries as passive physical connection nodes, focusing primarily on mechanical alignment and electrical connectivity, without specifically addressing shielding and impedance continuity. Traditional shielding methods often involve encasing sensitive signal lines in metal, but this approach is ineffective at handling electromagnetic leakage at splicing boundaries and fails to resolve impedance discontinuities in cross-boundary signal traces. Furthermore, existing methods lack adaptive control over wiring density at splicing boundaries, leading to a conflict between the insertion of shielding structures and the demands of high-density wiring.

[0077] Therefore, there is an urgent need for a technical solution that can systematically design shielding structures and optimize impedance for the splicing boundaries of multi-segment silicon interposers, in order to enhance the electromagnetic shielding effect of cross-boundary signal transmission, maintain impedance continuity, and thus improve the signal integrity and reliability of large-area advanced packaging systems.

[0078] To address the aforementioned technical problems, this disclosure provides a shielding structure, boundary structure, and design method for multi-segment silicon interposers. Based on the characteristic information and process design rules of each sub-interposer, a wiring density threshold is set at the splicing boundary between adjacent sub-interposers. Based on the characteristic information, the splicing distance between adjacent sub-interposers, and the wiring density threshold, an initial boundary structure is determined for each splicing boundary. The initial boundary structure includes a shielding corridor, a shielding structure within the shielding corridor, and cross-boundary signal traces. The initial boundary structure is iteratively optimized based on a target impedance to obtain a target boundary structure that meets preset conditions at each splicing boundary, thereby optimizing the signal integrity and reliability of the multi-segment silicon interposer at each splicing boundary. By setting a wiring density threshold, the congestion of traces at the splicing boundary is pre-controlled from the wiring resource allocation level, reserving space for the subsequent insertion of shielding structures. By constructing an initial boundary structure including a shielding corridor and shielding structures, an electromagnetic shielding barrier is actively formed at the splicing boundary. Through iterative optimization constrained by the target impedance, the impedance continuity of cross-boundary signal traces is ensured. This method organically integrates density control, shielding structure design, and impedance tuning, systematically solving the signal integrity and reliability issues at the splicing boundary.

[0079] like Figures 1-3 As shown, in Figure 1 The semiconductor package structure shown (such as the CoWoS-L package structure) 1 includes a multi-segment silicon interposer 10, a wafer layer 20 above the multi-segment silicon interposer 10, a substrate layer 30 below the multi-segment silicon interposer 10, and a ground plane 40 below the substrate layer 30. The shielding structure for the multi-segment silicon interposer 10 provided in this embodiment is disposed within the multi-segment silicon interposer 10. The multi-segment silicon interposer 10 is formed by splicing multiple sub-interposer layers 101, and adjacent sub-interposer layers 101 are joined by a splicing process; the joining area is called the splicing boundary 102. A boundary structure is provided at the splicing boundary 102. The boundary structure for the multi-segment silicon interposer 10 provided in this embodiment includes: a shielding corridor 103 extending along the splicing boundary 102, and a shielding structure and a cross-boundary signal trace 401 located within the shielding corridor 103. The shielding structure includes a TSV shielding pillar array 105 and / or a ground shielding trace 402.

[0080] The shielding corridor 103 is located at the splicing boundary 102 between the corresponding adjacent sub-intermediate layers 101 and extends along the splicing boundary 102. That is, the longitudinal extension direction of the shielding corridor 103 is consistent with the direction of the splicing boundary 102. The width of the shielding corridor 103 in the direction perpendicular to the splicing boundary 102 is the corridor width W, which is determined according to the splicing distance D between adjacent sub-intermediate layers 101. A larger splicing distance results in greater impedance disturbance when the cross-boundary signal trace 401 crosses the physical gap at the splicing boundary 102, requiring a wider shielding corridor 103 to accommodate more shielding structures and a more gentle impedance transition area. In one embodiment, the corridor width W is set to 2 to 5 times the splicing distance D to ensure sufficient arrangement space for the shielding structures.

[0081] The cross-boundary signal trace 401 is a metal conductor transmitting high-speed signals. It extends from one sub-intermediate layer 101 through the interior of the shielded corridor 103, across the splicing boundary 102, to another adjacent sub-intermediate layer 101. That is, the cross-boundary signal trace 401 crosses the splicing boundary 102 along the signal transmission direction and is completely within the coverage of the shielded corridor 103 at the splicing boundary 102, ensuring that it is shielded and protected by the shielding structure throughout its entire length across the physical gap at the splicing boundary 102. The cross-boundary signal trace 401 can be a single signal line, multiple parallel signal line groups, or differential signal line pairs. In one embodiment, the cross-boundary signal trace 401 extends in a straight line at the splicing boundary 102 to reduce impedance abrupt changes; in another embodiment, depending on wiring space constraints, the cross-boundary signal trace 401 can extend in a slightly curved path within the shielded corridor 103.

[0082] The TSV shielding pillar array 105 includes multiple conductive pillars 501 that penetrate the sub-intermediate layer 101 and are arranged around the cross-boundary signal trace 401. Each conductive pillar 501 is a conductive via structure that vertically penetrates the silicon substrate of the sub-intermediate layer 101 and is filled with a conductive material (such as copper). The conductive pillars 501 extend from the top surface to the bottom surface of the sub-intermediate layer 101 and are electrically connected to the ground plane 40 below the substrate layer 30 through the substrate layer 30, thereby forming a grounded vertical conductive path. The multiple conductive pillars 501 are arranged around the cross-boundary signal trace 401 in the following manner: they are arranged in rows along the length direction of the splicing boundary 102, and in columns in the direction perpendicular to the splicing boundary 102, forming a fence-like vertical shielding structure surrounding the cross-boundary signal trace 401. In some embodiments, the TSV shielding column array 105 is disposed on opposite sides of the splicing boundary 102, and arranged in a single column or multiple columns on each side along the extension direction of the cross-boundary signal trace 401, so that the cross-boundary signal trace 401 is shielded and protected in both the horizontal and vertical directions.

[0083] The grounding shielding trace 402 is located in the redistribution layer 104 within the shielding corridor 103 of the sub-intermediate layer 101, and is disposed on at least one side of the cross-boundary signal trace 401 and extends along the extension direction of the cross-boundary signal trace 401. The grounding shielding trace 402 is a grounding metal wire (such as a copper wire) formed in the redistribution layer 104, which is electrically connected to the grounding plane 40 or the grounding network. In some embodiments, the grounding shielding trace 402 may be disposed on one side of the cross-boundary signal trace 401 (i.e., only one accompanying grounding wire is disposed on one side), or it may be disposed on both sides of the cross-boundary signal trace 401 (i.e., one accompanying grounding wire is disposed on each of the left and right sides, forming a "signal line-ground line-signal line" arrangement structure). In some embodiments, the grounding shielding trace 402 is disposed on both sides of the cross-boundary signal trace 401 to form accompanying shielding for differential or single-ended signals in the horizontal direction, reducing electromagnetic coupling between adjacent signal lines.

[0084] The TSV shielding pillar array 105 (vertical direction) and the grounding shielding trace 402 (horizontal direction) together constitute a shielding structure surrounding the cross-boundary signal trace 401. This shielding structure forms a grounded vertical shielding fence in the vertical direction through conductive pillars 501, and a grounded horizontal accompanying shielding line in the horizontal direction through the grounding shielding trace 402. Together, they form a essentially enclosed cage-like shielding space within the shielding corridor 103. The cross-boundary signal trace 401 is located inside this shielding space, thus effectively isolating external electromagnetic interference in three-dimensional space. By combining the TSV shielding pillar array 105 and the grounding shielding trace 402, shielding can be formed simultaneously in both vertical and horizontal directions, resulting in a better shielding effect than a single-direction shielding structure. The TSV shielding pillar array 105 effectively blocks the vertical and horizontal propagation of cross-segment noise in the silicon substrate, while the grounding shielding trace 402 reduces crosstalk between adjacent signal lines in the redistribution layer 104. Their synergistic effect significantly reduces electromagnetic interference at the splicing boundary 102, improving the quality of high-speed signal transmission.

[0085] In this embodiment, the sub-intermediate layer 101 refers to a semiconductor intermediate layer unit composed of a silicon substrate and one or more redistribution layers (RDLs, also known as redistribution layers) 104 formed thereon. Multiple sub-intermediate layers 101 are joined along the splicing boundary 102 through a splicing process to form a large-area multi-segment silicon intermediate layer 10. The splicing boundary 102 is the bonding interface between adjacent sub-intermediate layers 101. The direction extending along this boundary is the splicing direction, and the direction perpendicular to the splicing boundary 102 is the splicing width direction (hereinafter referred to as "the extension direction perpendicular to the splicing boundary"). The shielding corridor 103 is a strip-shaped physical space area located at the splicing boundary 102, used to accommodate the cross-boundary signal trace 401 and the shielding structure. It extends longitudinally along the splicing boundary 102 and has a preset corridor width in the direction perpendicular to the splicing boundary 102. The corridor width is determined according to the splicing distance between adjacent sub-intermediate layers 101. The redistribution layer 104 is a metal wiring layer formed in the sub-intermediate layer 101, used to realize the electrical interconnection between the chip in the chip layer 10 and the multi-segment silicon intermediate layer 10.

[0086] like Figure 4 As shown in the embodiments of this disclosure, a design method for the boundary structure of a multi-segment silicon interposer 10 is also provided, the method including steps S601 to S603.

[0087] In step S601, a wiring density threshold is set at the splicing boundary 102 between adjacent sub-intermediate layers 101 based on the feature information of each sub-intermediate layer 101 and the process design rule. This wiring density threshold is used to constrain the wiring density in the area near the splicing boundary 102, avoiding increased crosstalk and decreased process yield due to excessively dense wiring.

[0088] In some embodiments, the feature information may include at least one of the following: the planar geometry and size of each of the sub-intermediate layers 101, the number of stacked redistribution layers 104 in each of the sub-intermediate layers 101, the material type and thickness of each dielectric layer in each of the sub-intermediate layers 101, the thickness of each metal layer in each of the sub-intermediate layers 101, and the frequency of the cross-boundary signal transmitted by the cross-boundary signal traces 401 in each of the sub-intermediate layers 101.

[0089] The planar geometry refers to the outline shape of the sub-intermediate layer 101 on a horizontal plane, such as a rectangle, square, L-shape, or other polygon. Dimensional specifications include the length and width of the sub-intermediate layer 101. The planar geometry and dimensions of each sub-intermediate layer 101 are used to determine the position, orientation, and length of the splicing boundary 102, as well as the start and end positions of the shielding corridor 103. The number of redistribution layers 104 (e.g., 2, 4, or 6 layers) determines the metal layers that can be laid across the boundary signal trace 401 and the layer positions that can be set for the grounding shield trace 402, and also affects the number of layers that the TSV shielding pillar array 105 needs to penetrate. The material type and thickness of each dielectric layer (e.g., silicon dioxide, polyimide, etc.) in each sub-intermediate layer 101 are also important parameters. The material type determines the dielectric constant Dk and loss factor Df, while the thickness affects the capacitance between the signal line and the reference plane; both together determine the characteristic impedance, which is a crucial input parameter for impedance calculation and tuning. The thickness of each metal layer (conductive material in the redistribution layer 104) in each sub-intermediate layer 101. The metal thickness affects the resistance and characteristic impedance of the signal line and is an important input parameter for impedance calculation. The frequency of the cross-boundary signal transmitted by the cross-boundary signal trace 401 in each sub-intermediate layer 101. This frequency includes the fundamental frequency and major harmonic frequencies of the signal, used to determine the wiring density threshold and the arrangement of the TSV shielding pillar array 105 (high-frequency signals require denser shielding).

[0090] In one possible implementation, the method may further include: before step S601, performing boundary proximity analysis on multiple sub-intermediate layers 101 to obtain the physical characteristics of each sub-intermediate layer 101 and determine the splicing distance D between adjacent sub-intermediate layers 101; the splicing distance D is the physical spacing width of adjacent sub-intermediate layers 101 at the splicing boundary 102, i.e., the straight-line distance between the relative edges of two sub-intermediate layers 101. This analysis obtains the physical characteristics (including but not limited to shape, size, number of layers, material, etc.) of each sub-intermediate layer 101 by reading the design database (GDSII, LEF / DEF, or other formats) and splicing process parameters of each sub-intermediate layer 101, and determines the splicing distance between adjacent sub-intermediate layers 101. The splicing distance is the physical spacing width of adjacent sub-intermediate layers 101 at the splicing boundary 102. The boundary proximity analysis can be performed automatically by EDA tools (Electronic Design Automation tools) or manually by the designer. This analysis step provides the necessary foundational data for subsequent wiring density setting, determination of the width of shielded corridor 103, and construction of the initial boundary structure.

[0091] In one possible implementation, step S601 may include: a first candidate wiring density calculation step, a second candidate wiring density calculation step, and a threshold setting step.

[0092] First candidate wiring density calculation step: according to the highest signal frequency of the cross-boundary signal in the feature information , according to the inverse relationship between frequency and wiring density, determine the first candidate wiring density corresponding to each stitching boundary 102 . The cross-boundary signal is a signal transmitted through the cross-boundary signal trace 401. Since a higher signal frequency is more sensitive to crosstalk and requires a looser trace spacing, the allowable wiring density should be lower. Therefore, the inverse relationship between frequency and wiring density can be expressed as: = , where is the reference density (for example, the allowable wiring density at 1 GHz), is the reference frequency (for example, 1 GHz), is the highest fundamental frequency or highest harmonic frequency of the cross-boundary signal, and α is the empirical attenuation coefficient (with a value range of 0.5 to 1, for example, 0.7 may be selected). For example, when the highest frequency of the cross-boundary signal is 10 GHz, the reference frequency is 1 GHz, the reference density is 10 traces per millimeter, and the attenuation coefficient is 0.7, the first candidate wiring density is approximately 10×(1 / 10)^0.7≈10×0.199≈1.99 traces per millimeter.

[0093] Second candidate wiring density calculation step: based on the minimum line width Wmin and minimum line spacing Smin specified by the process design rule, determine the second candidate wiring density Drule corresponding to each stitching boundary 102. The maximum number of traces allowed to be arranged in a unit width can be calculated according to the minimum line width and minimum line spacing: Drule=1 / (Wmin+Smin). Drule is the physical upper limit allowed by the process capability, and no actual wiring density shall exceed this value.

[0094] Threshold setting step: based on the larger one of the first candidate wiring density corresponding to each stitching boundary 102 and the second candidate wiring density Drule, set the wiring density threshold Dthreshold corresponding to each stitching boundary 102 as max( , Drule). In other words, the finally adopted wiring density threshold takes the stricter one (i.e., the constraint corresponding to the smaller value) between the signal integrity requirement (determined by frequency) and the process capability requirement (determined by the minimum line width / spacing). If <Drule, it indicates that the restriction of frequency on density is stricter than that of the process rule, and is taken as the threshold; if Drule < , it indicates that the restriction of the process rule is stricter, and Drule is taken as the threshold.

[0095] The above-mentioned wiring density threshold Dthreshold setting method takes into account the constraints of both signal integrity and manufacturability, ensuring that the set wiring density threshold can effectively control crosstalk between high-frequency signals and meet process design rules, avoiding setting it too aggressively, which would lead to manufacturing failure, or too conservatively, which would waste wiring resources.

[0096] In step S602, based on the feature information of each sub-intermediary layer 101, the splicing distance between adjacent sub-intermediary layers 101 and the aforementioned wiring density threshold, the initial boundary structure at each splicing boundary 102 is determined.

[0097] The initial boundary structure includes a shielded corridor 103, a shielding structure located within the shielded corridor 103, and a cross-boundary signal line 401. The shielded corridor 103 is a physical space area defined at the splicing boundary 102. The shielding structure is deployed within the shielded corridor 103 to provide electromagnetic shielding, and the cross-boundary signal line 401 passes through the splicing boundary 102 from inside the shielded corridor 103 to achieve cross-segment signal transmission.

[0098] In one possible implementation, step S602 may include the following steps: determining the corridor width of the shielded corridor 103; determining the layout parameters of the TSV shielded column array 105; and determining the layout position of the grounding shielded wiring 402.

[0099] Determining the width of the shielded corridor 103 may include: determining the corridor width W of the shielded corridor 103 along the direction perpendicular to the splicing boundary 102 based on the splicing distance D between adjacent sub-intermediate layers 101. The corridor width W is positively correlated with the splicing distance D. In one embodiment, W = D + 2 × Δ, where Δ is the width extending on both sides (e.g., 5 μm to 20 μm) for providing at least one row of TSV shielding posts and one grounding shielding trace on each side of the gap. In another embodiment, W = k × D, where k is a scaling factor (2 to 5, such as 3), and the larger the splicing distance, the wider the required shielded corridor. Determining the corridor width W ensures that the shielded corridor 103 has sufficient physical space to accommodate the shielding structure and the cross-boundary signal trace 401.

[0100] Determining the layout parameters of the TSV shielding pillar array 105 may include: determining the layout position and diameter d of the conductive pillars 501 within the corridor width of the shielding corridor 103, the spacing P between the conductive pillars 501, and the grounding plane of each conductive pillar 501 electrically connected, based on the wiring density threshold Dthreshold, the frequency F of the cross-boundary signal transmitted by the cross-boundary signal trace 401, and the process design rules.

[0101] The diameter d of the conductive post 501 can be determined according to the process design rules, which is determined by the TSV process capability of the processing technology (e.g., aspect ratio 10:1, diameter 5μm or 10μm).

[0102] The spacing P between the conductive posts 501 is determined based on the signal frequency F and the wiring density threshold Dthreshold, while meeting the process design rules (minimum post spacing). In one embodiment, P = min(Prule, Pshield), where Prule is the minimum post spacing allowed by the process, and Pshield is the maximum allowable post spacing required for shielding based on the frequency F (the higher the frequency, the smaller Pshield, i.e., the denser the posts). The smaller of the two values ​​is ultimately used to ensure maximum shielding effectiveness.

[0103] The conductive posts 501 are arranged around the cross-boundary signal trace 401. In one embodiment, for a single cross-boundary signal trace 401, one or more columns of conductive posts 501 are arranged on each side; for multiple parallel cross-boundary signal traces 401, the conductive posts 501 are arranged around the signal line group as a whole, and additional conductive posts 501 can also be added between the signal lines to enhance isolation.

[0104] Determining the placement of the grounding shield trace 402 may include: based on the wiring density threshold Dthreshold and the position of the cross-boundary signal trace 401 in the sub-intermediate layer 101, placing the grounding shield trace 402 on at least one side of the cross-boundary signal trace 401 in the redistribution layer 104 within the corridor width of the shielded corridor 103. The linewidth of the grounding shield trace 402 is determined according to impedance requirements and process design rules (e.g., the linewidth is the same as or slightly wider than the linewidth of the cross-boundary signal trace 401). The spacing between the grounding shield trace 402 and the cross-boundary signal trace 401 is set according to the wiring density threshold Dthreshold; the lower the wiring density threshold (the sparser the traces), the larger the spacing can be; the higher the wiring density threshold, the smaller the spacing should be to ensure that wiring is completed within a limited space.

[0105] In step S603, the initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that meets the preset conditions and is set at each of the splicing boundaries, so that the signal integrity and reliability of the multi-segment silicon interposer are optimal at each of the splicing boundaries.

[0106] Specifically, the initial boundary structure is optimized iteratively using the target impedance as a constraint to obtain a target boundary structure that meets the preset conditions. This optimization iterative process continuously adjusts the parameters affecting the impedance in the initial boundary structure, making the characteristic impedance of the cross-boundary signal trace 401 approach the target impedance, while simultaneously satisfying electromagnetic shielding effects and process design rules, ultimately outputting a target boundary structure that meets the requirements.

[0107] In a possible implementation, step S603 may include: an optimization step and a result evaluation step, wherein in step S603, the optimization step is executed first, and then the result evaluation step is executed.

[0108] Optimization step: Perform an optimization adjustment operation on the initial boundary structure based on the target impedance to obtain an optimized boundary structure.

[0109] Result evaluation step: When it is determined that the optimized boundary structure satisfies the preset condition, the optimized boundary structure is determined as the target boundary structure.

[0110] In some embodiments, the optimization adjustment operation may include at least one of the following operations: optimization adjustment operations A, B, and C.

[0111] Optimization adjustment operation A: Adjust the line width of the cross-boundary signal trace 401.

[0112] The line width Wtrace of the cross-boundary signal trace 401 may be adjusted according to the comparison result between the current characteristic impedance Zcurrent of the cross-boundary signal trace 401 and the target impedance Ztarget. When Zcurrent > Ztarget (the current impedance is on the high side), the line width Wtrace is increased; when Zcurrent < Ztarget (the current impedance is on the low side), the line width Wtrace is decreased. The specific adjustment amount of the line width may be calculated by an analytical formula, or may be scanned and optimized by electromagnetic field simulation, which is not limited in the present disclosure. In an embodiment, a series of line width values may be set (for example, scanning within a range of ±50% of the initial line width with a step size of 0.1 μm), impedance simulation is performed respectively, and the line width value closest to the target impedance is selected as the adjustment result. The larger the line width, the smaller the resistance per unit length and the smaller the characteristic impedance; the smaller the line width, the larger the characteristic impedance. By adjusting the line width, the characteristic impedance of the cross-boundary signal trace 401 can be directly and effectively adjusted to be close to the target value.

[0113] Optimization adjustment operation B: Adjust the thickness of the medium at the splicing boundary 102 in the shielding corridor 103.

[0114] The thickness Hdielectric of the dielectric layer 107 at the splicing boundary 102 in the shielding corridor 103 can be adjusted according to the comparison result between the current characteristic impedance Zcurrent of the cross-boundary signal trace 401 and the target impedance Ztarget. When Zcurrent>Ztarget (the current impedance is on the high side), the dielectric thickness Hdielectric is reduced; when Zcurrent < Ztarget (the current impedance is on the low side), the dielectric thickness Hdielectric is increased. The adjustment of the dielectric thickness can be achieved by additionally depositing or thinning the dielectric material at the splicing boundary 102. The determination of the adjustment amount can also be optimized by using a transmission line theoretical formula or electromagnetic field simulation, which is not limited in the present disclosure. The thinner the dielectric, the larger the capacitance between the signal line and the reference plane, and the smaller the characteristic impedance; the thicker the dielectric, the larger the characteristic impedance. This optimization adjustment is aimed at the non-uniform dielectric thickness at the splicing boundary 102 caused by the splicing process, and compensates for impedance offset by locally adjusting the dielectric thickness.

[0115] Optimization adjustment operation C: adjusting the spacing between the differential signal line pairs in the cross-boundary signal trace 401.

[0116] The spacing Sdiff between the differential signal line pairs in the cross-boundary signal trace 401 can be adjusted based on the photolithography overlay deviation Δoverlay when splicing the sub-interposers 101. In the actual splicing process, there is an overlay deviation in the photolithography alignment between the two sub-interposers 101, which causes the spacing of the differential signal line pairs at the splicing boundary 102 to deviate from the design value, thereby causing the offset of the differential impedance. The preset spacing of the differential line pairs is adjusted according to the measured value or statistical value of the overlay deviation. Wherein, if the overlay deviation causes the actual spacing to decrease, the preset spacing is correspondingly increased in the design stage for compensation; and vice versa. The smaller the spacing of the differential signal lines, the stronger the coupling, and the smaller the differential impedance; the larger the spacing, the larger the differential impedance. By compensating for the geometric change caused by the overlay deviation, the actual differential impedance of the differential signal line pair at the splicing boundary 102 is ensured to be consistent with the target value.

[0117] The above three optimization adjustment operations A, B, and C can be used independently or in combination. In some embodiments, the above three optimization adjustment operations are simultaneously adopted for comprehensive optimization: first, the line width is roughly adjusted (optimization adjustment operation A) to make the impedance enter the range near the target value, then the dielectric thickness is finely adjusted (optimization adjustment operation B) to compensate for the local impedance deviation at the splicing gap, and finally the differential spacing is finely adjusted according to the overlay deviation (optimization adjustment operation C) for fine correction, so as to achieve the optimal impedance matching effect.

[0118] In some implementations, the preset condition may include at least one of the following: a first condition, a second condition, and a third condition.

[0119] The first condition can be that the deviation between the characteristic impedance and the target impedance of the cross-boundary signal trace is within a preset range. The target impedance is determined according to the signal type; for example, for single-ended signals, the target impedance is typically set to 50Ω; for differential signals, the target impedance is typically set to 100Ω or 85Ω. The preset range is, for example, ±5% or ±10% of the target impedance value. If the deviation between the characteristic impedance and the target impedance is within this range, the first condition is deemed satisfied. This first condition ensures the impedance continuity of the cross-boundary signal trace 401 when it crosses the splicing boundary 102, reducing signal reflection and insertion loss.

[0120] The second condition is that the crosstalk between the cross-boundary signal trace 401 and adjacent signal traces is lower than a preset threshold. Adjacent signal traces can be adjacent cross-boundary signal traces and / or adjacent ordinary signal traces. Crosstalk can be obtained by calculating the near-end crosstalk (NEXT) and far-end crosstalk (FEXT) in the S-parameters using electromagnetic simulation (such as the finite element method or the method of moments). The preset threshold is, for example, -30dB or -35dB (i.e., the crosstalk energy does not exceed 0.1% or 0.03% of the signal energy). If it is lower than the threshold, the second condition is deemed met. This condition ensures that the shielding effect of the shielding structure within the shielded corridor 103 is sufficient, and that adjacent signal lines will not interfere with each other.

[0121] The third condition can be that the geometric parameters of each structure in the optimized boundary structure meet the process design rules. These process design rules may include minimum linewidth, minimum line spacing, minimum TSV aperture, minimum TSV spacing, minimum dielectric thickness, etc., and this disclosure does not impose any limitations on them. If all geometric parameters meet the process design rules, then the third condition is deemed satisfied. The setting of the third condition ensures that the optimized boundary structure can be directly fabricated, exhibiting good manufacturability and yield.

[0122] In some implementations, the "result evaluation step" in step S603 may further include: if the optimized boundary structure does not meet the first condition in the preset conditions, re-execute the optimization adjustment operation and subsequent steps.

[0123] If the optimized boundary structure does not meet the first condition, it indicates that the deviation between the characteristic impedance and the target impedance of the cross-boundary signal trace 401 exceeds the allowable range. In this case, the optimized boundary structure needs to be re-optimized based on the target impedance. That is, the step of adjusting the geometric dimensions of the cross-boundary signal trace 401 is repeated, and the line width, dielectric thickness, or differential line spacing is readjusted to obtain a new optimized boundary structure. The condition is then checked again. This process can be repeated multiple times until the first condition is met.

[0124] In some implementations, the "result evaluation step" in step S603 may further include: if the optimized boundary structure does not meet the second condition in the preset conditions, re-execute the steps of determining the initial boundary structure and thereafter, that is, re-execute steps S602 and S603.

[0125] When the optimized boundary structure fails to meet the second condition, it indicates that the shielding effect of the shielding structure is insufficient and the electromagnetic coupling between adjacent signal lines is too strong. In this case, simple impedance tuning cannot solve the problem of insufficient shielding, and it is necessary to start from the layout of the shielding structure itself, that is, to re-execute steps S602 and S603. When redetermining the initial boundary structure, the density of the TSV shielding column array 105 can be increased (by reducing the column spacing P or increasing the number of rows), grounding shielding lines 402 can be set on more sides of the cross-boundary signal line 401, and the corridor width W of the shielding corridor 103 can be increased to increase the accommodation space of the shielding structure.

[0126] In some implementations, the "result evaluation step" in step S603 may also include: if the optimized boundary structure does not meet the third condition in the preset conditions, re-execute the steps of setting the wiring density threshold and subsequent steps, that is, re-execute steps S601 to S603.

[0127] When the optimized boundary structure fails to meet the third condition (design rule check condition) among the preset conditions, it indicates that certain geometric parameters violate the process design rules, such as the line width being less than the minimum line width or the conductive post spacing being less than the minimum spacing. In this case, adjustments need to be made at a more fundamental level, i.e., steps S601-S603 need to be re-executed. When resetting the wiring density threshold, the wiring density threshold is lowered (i.e., the wiring density is further restricted), thereby allowing a larger margin for the geometric parameters to meet the process design rules.

[0128] By setting the aforementioned preset conditions, different fallback paths are established for different types of failure causes, avoiding repeated trial and error in a single direction and improving optimization efficiency. Impedance problems (first condition) only require local adjustment of geometric dimensions; shielding problems (second condition) require reconstruction of the shielding layout; and process problems (third condition) require adjustment of density constraints from scratch. Each of these three issues has its own specific target, forming an efficient and precise closed-loop optimization.

[0129] To verify the effectiveness of the method provided in the embodiments of this disclosure, such as Figures 5-7 As shown, different wiring density thresholds are set for the same CoWoS-L package structure to design different shielding structures. For example, Figure 5As shown, the density distribution of conductive pillars 501 in the multi-segment silicon interposer 10 of the TSV shielding pillar array is divided into 10%, 20%, 40%, 60%, and 80% according to the area ratio. Simulation tests were conducted to obtain the desired results for different shielding structures. Figure 6 The electromagnetic field distribution diagram and shielding effectiveness (SE) shown are referenced. Figure 6 , Figure 7 It is evident that as the density of conductive pillars in the TSV shielding pillar array increases, the shielding effectiveness of the CoWoS-L packaging structure significantly improves across the entire frequency band, especially at higher frequencies (>10GHz). When the conductive pillar density in the TSV shielding pillar array reaches 40%-60%, the improvement in shielding effectiveness tends to saturate, balancing signal integrity and manufacturing feasibility, making this the recommended optimization range. Therefore, the TSV shielding pillar array effectively suppresses electromagnetic leakage, reduces crosstalk and radiated interference, and significantly enhances the system's EMI suppression capability by forming a high-density grounding channel.

[0130] It should be noted that although the above embodiments have been used as examples to illustrate the shielding structure, boundary structure, and design method for multi-segment silicon interposers, those skilled in the art will understand that this disclosure is not limited thereto. In fact, users can flexibly set each step and structural composition according to their personal preferences and / or actual application scenarios, as long as it conforms to the technical solution of this disclosure.

[0131] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0132] This disclosure also provides a design apparatus for a boundary structure of a multi-segment silicon interposer, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0133] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0134] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described method.

[0135] Figure 8 This is a block diagram illustrating an apparatus 1900 for a boundary structure design method for multi-segment silicon interposers, according to an exemplary embodiment. For example, apparatus 1900 can be provided as a server or terminal device. (Refer to...) Figure 8 The apparatus 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions executable by the processing component 1922, such as application programs. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0136] Device 1900 may also include a power supply component 1926 configured to perform power management of device 1900, a wired or wireless network interface 1950 configured to connect device 1900 to a network, and an input / output interface 1958 (I / O interface). Device 1900 can operate on an operating system, such as Windows Server, stored in memory 1932. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0137] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of the device 1900 to perform the above-described method.

[0138] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0139] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0140] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0141] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0142] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0143] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0144] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0145] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A design method for boundary structures of multi-segment silicon interposers, characterized in that, The multi-segment silicon interposer is formed by splicing together multiple sub-interposers, and the method includes: Based on the characteristic information and process design rules of each sub-intermediate layer, set the wiring density threshold at the splicing boundary between adjacent sub-intermediate layers; Based on the feature information, the splicing distance between adjacent sub-intermediate layers and the wiring density threshold, an initial boundary structure is determined for each splicing boundary. The initial boundary structure includes a shielding corridor and a shielding structure and cross-boundary signal traces located within the shielding corridor. The initial boundary structure is optimized and iterated based on the target impedance to obtain a target boundary structure that meets the preset conditions and is set at each of the splicing boundaries, so that the signal integrity and reliability of the multi-segment silicon interposer are optimal at each of the splicing boundaries. The target impedance refers to the characteristic impedance value that the cross-boundary signal trace is expected to achieve to avoid signal reflection during signal transmission.

2. The method according to claim 1, characterized in that, The shielding corridor is located at the corresponding splicing boundary and extends along the splicing boundary; The cross-boundary signal trace extends from one sub-intermediate layer through the interior of the shielded corridor, across the splicing boundary, to another adjacent sub-intermediate layer. The shielding structure includes a TSV shielding column array and / or grounding shielding traces; The TSV shielding pillar array includes multiple conductive pillars that penetrate the sub-intermediate layer and are arranged around the cross-boundary signal trace. The grounding shielding trace is located in the redistribution layer within the shielding corridor of the sub-intermediate layer, and is disposed on at least one side of the cross-boundary signal trace and extends along the extension direction of the cross-boundary signal trace.

3. The method according to claim 1 or 2, characterized in that, The initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that meets preset conditions, including: Based on the target impedance, an optimization adjustment operation is performed on the initial boundary structure to obtain the optimized boundary structure; If the optimized boundary structure satisfies the preset conditions, the optimized boundary structure is determined as the target boundary structure. The preset conditions include at least one of the following: First condition: The deviation between the characteristic impedance and the target impedance of the cross-boundary signal trace is within a preset range; Second condition: The crosstalk between the cross-boundary signal trace and the adjacent signal trace is lower than a preset threshold; Third condition: The geometric parameters of each structure in the optimized boundary structure all satisfy the process design rules.

4. The method according to claim 3, characterized in that, The initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that meets preset conditions, and the process further includes: If the optimized boundary structure does not meet the first condition in the preset conditions, the optimization adjustment operation and subsequent steps are re-executed.

5. The method according to claim 3, characterized in that, The initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that meets preset conditions, and the process further includes: If the optimized boundary structure does not satisfy the second condition in the preset conditions, the steps of determining the initial boundary structure and subsequent steps are re-executed.

6. The method according to claim 3, characterized in that, The initial boundary structure is optimized iteratively based on the target impedance to obtain a target boundary structure that meets preset conditions, and the process further includes: If the optimized boundary structure does not meet the third condition in the preset conditions, the steps of setting the wiring density threshold and subsequent steps are re-executed.

7. The method according to claim 1, characterized in that, Based on the characteristic information and process design rules of each sub-intermediate layer, the wiring density threshold at the splicing boundary between adjacent sub-intermediate layers is set, including: Based on the highest signal frequency of the cross-boundary signal in the feature information, and according to the inverse relationship between frequency and wiring density, the first candidate wiring density corresponding to each splicing boundary is determined, and the cross-boundary signal is a signal transmitted through the cross-boundary signal trace. Based on the minimum line spacing and minimum line width indicated by the process design rules, the second candidate wiring density corresponding to each of the splicing boundaries is determined. Based on the larger of the first candidate wiring density and the second candidate wiring density corresponding to each of the splicing boundaries, a wiring density threshold corresponding to each of the splicing boundaries is set.

8. The method according to claim 1, characterized in that, The feature information includes at least one of the following: the planar geometry and size of each sub-intermediate layer, the number of stacked redistribution layers in each sub-intermediate layer, the material type and thickness of each dielectric layer in each sub-intermediate layer, the thickness of each metal layer in each sub-intermediate layer, and the frequency of the cross-boundary signal transmitted by the cross-boundary signal traces in each sub-intermediate layer.

9. The method according to claim 2, characterized in that, Based on the feature information, the splicing distance between adjacent sub-intermediary layers, and the wiring density threshold, an initial boundary structure is determined for each splicing boundary, including: Based on the splicing distance between adjacent sub-intermediate layers, the width of the shielding corridor between adjacent sub-intermediate layers along the direction perpendicular to the splicing boundary is determined; Based on the wiring density threshold, the frequency of the cross-boundary signal transmitted by the cross-boundary signal trace, and the process design rules, the arrangement position and diameter of the conductive pillars within the corridor width of the shielded corridor, the spacing between the conductive pillars, and the grounding plane electrically connected to each conductive pillar are determined to obtain a TSV shielding pillar array; and / or, based on the wiring density threshold and the position of the cross-boundary signal trace in the sub-intermediate layer, the grounding shielding trace is provided on at least one side of the cross-boundary signal trace in the redistribution layer within the corridor width of the shielded corridor.

10. The method according to claim 3, characterized in that, The optimization and adjustment operation includes at least one of the following operations: Adjust the line width of the cross-boundary signal trace based on the comparison result between the current characteristic impedance of the cross-boundary signal trace and the target impedance. Based on the comparison between the current characteristic impedance of the cross-boundary signal trace and the target impedance, the thickness of the medium at the splicing boundary in the shielding corridor is adjusted. Based on the lithographic overlay deviation in the splicing sub-intermediate layer, the spacing between differential signal pairs in the cross-boundary signal trace is adjusted.

11. The method according to claim 1, characterized in that, The method further includes: Boundary proximity analysis is performed on the multiple sub-intermediary layers to obtain the physical characteristics of each sub-intermediary layer and determine the splicing distance between adjacent sub-intermediary layers; the splicing distance is the physical interval width of adjacent sub-intermediary layers at the splicing boundary.

12. A shielding structure for multi-segment silicon interposers, characterized in that, The multi-segment silicon interposer is formed by splicing together multiple sub-interposers. The shielding structure is located within a shielding corridor, which is located at the splicing boundary between adjacent sub-interposers. The shielding structure includes a TSV shielding pillar array and / or grounding shielding traces. The TSV shielding pillar array includes multiple conductive pillars that penetrate the sub-intermediate layer and are arranged around the cross-boundary signal trace; The grounding shielding trace is located in the redistribution layer within the shielding corridor of the sub-intermediate layer, and is disposed on at least one side of the cross-boundary signal trace and extends along the extension direction of the cross-boundary signal trace; The shielding corridor is located at the splicing boundary between corresponding adjacent sub-intermediate layers and extends along the splicing boundary; the cross-boundary signal trace is located within the shielding corridor and extends from one sub-intermediate layer through the interior of the shielding corridor, through the splicing boundary, to another adjacent sub-intermediate layer.

13. A boundary structure for a multi-segment silicon interposer, characterized in that, The multi-segment silicon interposer is a plurality of sub-interposer layers, and the boundary structure includes: The shielded corridor is located at the splicing boundary between the corresponding adjacent sub-intermediary layers and extends along the splicing boundary; Cross-boundary signal traces are located within the shielded corridor and extend from one sub-intermediate layer through the interior of the shielded corridor, across the splicing boundary, to another adjacent sub-intermediate layer. The shielding structure, located within the shielding corridor, includes a TSV shielding column array and / or grounding shielding traces; The TSV shielding pillar array includes multiple conductive pillars that penetrate the sub-intermediate layer and are arranged around the cross-boundary signal trace. The grounding shielding trace is located in the redistribution layer within the shielding corridor of the sub-intermediate layer, and is disposed on at least one side of the cross-boundary signal trace and extends along the extension direction of the cross-boundary signal trace.

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