Shift register unit and driving method thereof, display driving circuit, display device

Abstract

A shift register unit, a driving method thereof, a display driving circuit and a display device. The shift register unit comprises a first input control circuit (01), a second input control circuit (02) and an output circuit (03). The first input control circuit (01) is connected with a first clock terminal (CK), an input terminal (IN), a second clock terminal (CB), a first power supply terminal (V1), a first node (N1) and a second node (N2) respectively. The first input control circuit (01) is configured to control a potential of the first node (N1) based on a first clock signal provided by the first clock terminal (CK), an input signal provided by the input terminal (IN), a second clock signal provided by the second clock terminal (CB), a first power supply signal provided by the first power supply terminal (V1) and a potential of the second node (N2). The second input control circuit (02) is connected with the first clock terminal (CK), the first node (N1) and the second node (N2) respectively. The second input control circuit (02) is configured to control a potential of the second node (N2) based on the first clock signal and the potential of the first node (N1). The output circuit (03) is connected with the first node (N1), the second node (N2), a second power supply terminal (V2), the second clock terminal (CB) and an output terminal (OUT) respectively. The output circuit (03) is configured to control on-off of the second power supply terminal (V2) and the output terminal (OUT) and on-off of the second clock terminal (CB) and the output terminal (OUT) based on the potential of the first node (N1) and the potential of the second node (N2), so as to output a display driving signal through the output terminal (OUT). The characteristics of the transistors in the shift register input control circuit are not easy to shift.

Description

Shift register unit and its driving method, display driver circuit, display device Technical Field

[0001] This application relates to the field of display technology, and in particular to a shift register unit and its driving method, a display driving circuit, and a display device. Background Technology

[0002] With the development of display technology, gate drive on array (GOA) technology is increasingly used to integrate the display driving circuitry onto the display panel, facilitating narrow bezel designs. Therefore, the display driving circuitry is also called a GOA circuit.

[0003] Currently, GOA circuits typically consist of multiple cascaded GOA units, also known as shift register units. Each GOA unit outputs a display drive signal to the pixels in the display panel based on the power signal provided by the connected power supply terminal and the clock signal provided by the clock terminal, thereby driving the pixels to emit light and enabling the display panel to display an image.

[0004] However, due to various factors, the characteristics of the transistors in the GOA unit are prone to deviation, which can easily lead to abnormal display drive signals output by the GOA unit, resulting in poor display effects of the display panel. Summary of the Invention

[0005] A shift register unit and its driving method, a display driving circuit, and a display device are provided. The technical solution is as follows:

[0006] On the one hand, a shift register unit is provided, the shift register unit comprising:

[0007] The first input control circuit is connected to the first clock terminal, the input terminal, the second clock terminal, the first power supply terminal, the first node, and the second node, respectively, and is used to control the potential of the first node based on the first clock signal provided by the first clock terminal, the input signal provided by the input terminal, the second clock signal provided by the second clock terminal, the first power supply signal provided by the first power supply terminal, and the potential of the second node.

[0008] The second input control circuit is connected to the first clock terminal, the first node, and the second node respectively, and is used to control the potential of the second node based on the first clock signal and the potential of the first node.

[0009] The output circuit is connected to the first node, the second node, the second power supply terminal, the second clock terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal based on the potential of the first node and the potential of the second node, and to control the on / off state of the second clock terminal and the output terminal, so as to output a display drive signal through the output terminal.

[0010] Optionally, the first input control circuit includes:

[0011] The first input control sub-circuit is connected to the first clock terminal, the input terminal, and the first node respectively, and is used to control the on / off state of the input terminal and the first node in response to the first clock signal, so as to control the potential of the first node;

[0012] The second input control sub-circuit is connected to the second clock terminal, the first power supply terminal, the second node, and the first node, respectively, and is used to control the on / off state of the first power supply terminal and the first node in response to the second clock signal and the potential of the second node, so as to control the potential of the first node.

[0013] Optionally, the first input control circuit includes a first transistor; the second input control sub-circuit includes a second transistor and a third transistor.

[0014] The gate of the first transistor is connected to the first clock terminal, the first electrode of the first transistor is connected to the input terminal, and the second electrode of the first transistor is connected to the first node.

[0015] The gate of the second transistor is connected to the second node, the first terminal of the second transistor is connected to the first power supply terminal, the second terminal of the second transistor is connected to the first terminal of the third transistor, the gate of the third transistor is connected to the second clock terminal, and the second terminal of the third transistor is connected to the first node.

[0016] Optionally, the first node includes: a first child node and a second child node; the shift register unit further includes:

[0017] The third input control circuit is connected to the input control terminal, the first sub-node, and the second sub-node respectively, and is used to control the on / off state of the first sub-node and the second sub-node in response to the control signal provided by the input control terminal.

[0018] And / or, a fourth input control circuit, connected to the first clock terminal, the input terminal and the second sub-node respectively, and used to control the on / off state of the input terminal and the second sub-node in response to the first clock signal;

[0019] Furthermore, both the first input control sub-circuit and the second input control circuit are connected to the first sub-node; the output circuit is connected to the second sub-node; when the third input control circuit is included, the second input control sub-circuit is connected to either the first sub-node or the second sub-node; when the third input control circuit is not included, the second input control sub-circuit is connected to the second sub-node.

[0020] Optionally, when the fourth input control circuit is included, the input control terminal is shared with the first clock terminal or the second clock terminal; when the fourth input control circuit is not included, the input control terminal is shared with the first clock terminal; or, the input control terminal is a third power supply terminal.

[0021] Optionally, the third input control circuit includes: a fourth transistor;

[0022] The gate of the fourth transistor is connected to the input control terminal, the first electrode of the fourth transistor is connected to the first sub-node, and the second electrode of the fourth transistor is connected to the second sub-node.

[0023] Optionally, the fourth input control circuit includes: a fifth transistor;

[0024] The gate of the fifth transistor is connected to the first clock terminal, the first terminal of the fifth transistor is connected to the input terminal, and the second terminal of the fifth transistor is connected to the second child node.

[0025] Optionally, the shift register unit further includes:

[0026] A potential adjustment circuit is connected to both the potential adjustment terminal and the first sub-node, and is used to adjust the potential of the first sub-node based on the adjustment signal provided by the potential adjustment terminal.

[0027] Optionally, the potential adjustment terminal is shared with the first power supply terminal or the first clock terminal, or the potential adjustment terminal is a third power supply terminal.

[0028] Optionally, the potential adjustment circuit includes: a first capacitor;

[0029] The first capacitor is connected between the potential adjustment terminal and the first sub-node.

[0030] Optionally, the second input control circuit includes:

[0031] The third input control sub-circuit is connected to the first clock terminal, the target signal terminal, and the second node respectively, and is used to control the on / off state of the target signal terminal and the second node in response to the first clock signal, so as to control the potential of the second node; wherein, the target signal terminal is shared with the first clock terminal or is a third power supply terminal;

[0032] The fourth input control sub-circuit is connected to the first node, the first clock terminal, and the second node respectively, and is used to control the on / off state of the first clock terminal and the second node in response to the potential of the first node, so as to control the potential of the second node.

[0033] Optionally, the third input control sub-circuit includes a sixth transistor; the fourth input control sub-circuit includes a seventh transistor.

[0034] The gate of the sixth transistor is connected to the first clock terminal, the first terminal of the sixth transistor is connected to the target signal terminal, and the second terminal of the sixth transistor is connected to the second node;

[0035] The gate of the seventh transistor is connected to the first node, the first terminal of the seventh transistor is connected to the first clock terminal, and the second terminal of the seventh transistor is connected to the second node.

[0036] Optionally, the second node includes: a third child node and a fourth child node; the shift register unit further includes:

[0037] The fifth input control circuit is connected to the first node, the third sub-node, and the fourth sub-node respectively, and is used to control the on / off state of the third sub-node and the fourth sub-node in response to the potential of the first node.

[0038] The sixth input control circuit is connected to the first clock terminal, the target signal terminal and the fourth sub-node respectively, and is used to control the on / off state of the target signal terminal and the fourth sub-node in response to the first clock signal;

[0039] Furthermore, both the third input control sub-circuit and the fourth input control sub-circuit are connected to the third sub-node, and both the output circuit and the first input control circuit are connected to the fourth sub-node.

[0040] Optionally, the fifth input control circuit includes: an eighth transistor;

[0041] The gate of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the third child node, and the second electrode of the eighth transistor is connected to the fourth child node.

[0042] Optionally, the sixth input control circuit includes: a ninth transistor;

[0043] The gate of the ninth transistor is connected to the first clock terminal, the first terminal of the ninth transistor is connected to the target signal terminal, and the second terminal of the ninth transistor is connected to the fourth child node.

[0044] Optionally, the output circuit includes:

[0045] The first output sub-circuit is connected to the first node, the second clock terminal and the output terminal respectively, and is used to control the on / off state of the second clock terminal and the output terminal in response to the potential of the first node, so as to output the second clock signal as a display driving signal through the output terminal, and is also used to adjust the potential of the first node based on the display driving signal output through the output terminal.

[0046] The second output sub-circuit is connected to the second node, the second power supply terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the second node, so as to output the second power supply signal provided by the second power supply terminal as a display driving signal through the output terminal, and is also used to adjust the potential of the second node based on the second power supply signal.

[0047] Optionally, the first output sub-circuit includes: a tenth transistor and a second capacitor; the second output sub-circuit includes: an eleventh transistor and a third capacitor;

[0048] The gate of the tenth transistor is connected to the first node, the first terminal of the tenth transistor is connected to the second clock terminal, and the second terminal of the tenth transistor is connected to the output terminal.

[0049] The second capacitor is connected between the output terminal and the first node;

[0050] The gate of the eleventh transistor is connected to the second node, the first terminal of the eleventh transistor is connected to the second power supply terminal, and the second terminal of the eleventh transistor is connected to the output terminal.

[0051] The third capacitor is connected between the second power supply terminal and the second node.

[0052] On the other hand, a method for driving a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method includes:

[0053] In the first stage, the potential of the first clock signal provided by the first clock terminal is the first potential, the potential of the second clock signal provided by the second clock terminal and the potential of the input signal provided by the input terminal are both the second potential. The first input control circuit controls the potential of the first node to be the first potential based on the received first clock signal, input signal, second clock signal, first power signal with the second potential provided by the first power terminal and the potential of the second node. The second input control circuit controls the potential of the second node to be the first potential based on the received first clock signal and the potential of the first node. The output circuit controls the second power terminal and the second clock terminal to be connected to the output terminal based on the potentials of the first node and the second node.

[0054] In the second stage, the potential of the second clock signal provided by the second clock terminal is the first potential, and the potential of the first clock signal provided by the first clock terminal and the potential of the input signal provided by the input terminal are both the second potential. The first input control circuit controls the potential of the first node to be the first potential based on the received first clock signal, input signal, second clock signal, first power signal and the potential of the second node. The second input control circuit controls the potential of the second node to be the second potential based on the received first clock signal and the potential of the first node. The output circuit controls the second clock terminal to be connected to the output terminal based on the potentials of the first node and the second node.

[0055] In another aspect, a display driving circuit is provided, the display driving circuit comprising: a plurality of cascaded shift register units as described in the above aspect.

[0056] In another aspect, a display device is provided, the display device comprising: a display panel, and a display driving circuit as described in yet another aspect above; the display panel comprising a plurality of pixels;

[0057] The display driving circuit is connected to the plurality of pixels via its output terminal and is used to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light. Attached Figure Description

[0058] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 is a schematic diagram of the structure of a shift register unit provided in an embodiment of this application;

[0060] Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0061] Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0062] Figure 4 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0063] Figure 5 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0064] Figure 6 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0065] Figure 7 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0066] Figure 8 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0067] Figure 9 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0068] Figure 10 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0069] Figure 11 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0070] Figure 12 is a schematic diagram of another shift register unit provided in an embodiment of this application;

[0071] Figure 13 is a schematic diagram of the circuit structure of a shift register unit provided in an embodiment of this application;

[0072] Figure 14 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0073] Figure 15 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0074] Figure 16 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0075] Figure 17 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0076] Figure 18 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0077] Figure 19 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0078] Figure 20 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0079] Figure 21 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0080] Figure 22 is a schematic diagram of the circuit structure of another shift register unit provided in an embodiment of this application;

[0081] Figure 23 is a flowchart illustrating a method for driving a shift register unit according to an embodiment of this application;

[0082] Figure 24 is a schematic diagram of the driving timing signals of a shift register unit provided in an embodiment of this application;

[0083] Figure 25 is a schematic diagram of the driving timing signals of another shift register unit provided in an embodiment of this application;

[0084] Figure 26 is a schematic diagram of the driving timing signals of another shift register unit provided in an embodiment of this application;

[0085] Figure 27 is a schematic diagram of the driving timing signals of another shift register unit provided in an embodiment of this application;

[0086] Figure 28 is a schematic diagram of the driving timing signals of another shift register unit provided in an embodiment of this application;

[0087] Figure 29 is a schematic diagram of a display driving circuit provided in an embodiment of this application;

[0088] Figure 30 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0089] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0090] It should be noted that the transistors used in the embodiments of this application can be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. An example of a FET is a metal-oxide-semiconductor (MOS) FET, also known as a MOS transistor. Furthermore, based on their function in the circuit, the transistors used in the embodiments of this application are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this application, the source can be referred to as the first electrode, and the drain as the second electrode. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the control electrode, also known as the gate; the signal input terminal is the source, and the signal output terminal is the drain. In addition, the switching transistors used in the embodiments of this application can include either P-type transistors or N-type transistors. A P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; an N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential. Furthermore, multiple signals in the various embodiments of this application correspond to a first potential and a second potential. Furthermore, the first potential and the second potential only represent that the potential of the signal has two state variables, and do not mean that the first potential or the second potential has a specific value in the whole text.

[0091] This application provides a shift register unit with improved transistor characteristic offset. Consequently, the display drive signal output by the shift register unit is more stable and reliable, resulting in better display performance of the display panel. The transistor characteristic is, for example, a threshold voltage, and the offset can include offsets under positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS).

[0092] Figure 1 is a schematic diagram of a shift register unit provided in an embodiment of this application. As shown in Figure 1, the shift register unit includes: a first input control circuit 01, a second input control circuit 02, and an output circuit 03.

[0093] The first input control circuit 01 is connected to the first clock terminal CK, the input terminal IN, the second clock terminal CB, the first power supply terminal V1, the first node N1, and the second node N2. Furthermore, the first input control circuit 01 controls the potential of the first node N1 based on the first clock signal provided by the first clock terminal CK, the input signal provided by the input terminal IN, the second clock signal provided by the second clock terminal CB, the first power supply signal provided by the first power supply terminal V1, and the potential of the second node N2.

[0094] For example, the first input control circuit 01 can control the input terminal IN to be connected to the first node N1 when the potential of the first clock signal provided by the first clock terminal CK is a first potential, so that the input signal provided by the input terminal IN is transmitted to the first node N1, that is, control the potential of the first node N1 to be the potential of the input signal. Furthermore, the first input control circuit 01 can control the input terminal IN to be disconnected from the first node N1 when the potential of the first clock signal provided by the first clock terminal CK is a second potential.

[0095] For example, the first input control circuit 01 can control the first power supply terminal V1 to conduct with the first node N1 when the potential of the second node N2 and the potential of the second clock signal provided by the second clock terminal CB are both the first potential, so that the first power signal provided by the first power supply terminal V1 is transmitted to the first node N1, that is, control the potential of the first node N1 to be the potential of the first power signal. Furthermore, the first input control circuit 01 can control the first power supply terminal V1 to disconnect from the first node N1 when the potential of the second node N2 and / or the potential of the second clock signal provided by the second clock terminal CB are the second potential.

[0096] Optionally, in the embodiments of this application, the first potential can refer to an effective potential, and the second potential can refer to an ineffective potential, and the first potential can be a low potential relative to the second potential. That is, the first potential can be a low potential, and the second potential can be a high potential. Of course, in some other embodiments, the first potential can also be a high potential relative to the second potential. This depends on the transistor in the circuit. As mentioned above, for a P-type transistor, the first potential can be a low potential relative to the second potential. For an N-type transistor, the first potential can be a high potential relative to the second potential.

[0097] Optionally, the potential of the first power supply signal provided by the first power supply terminal V1 can be a constant high potential. That is, the first power supply terminal V1 can be a DC power supply terminal, and can be a pull-up power supply terminal VGH1 capable of providing a high-potential power supply signal. The first clock signal provided by the first clock terminal CK and the second clock signal provided by the second clock terminal CB can both be periodic pulse signals, and not both at an effective potential at the same time. Of course, this is only an illustrative illustration. For example, in some other embodiments, the first power supply terminal V1 can also be a pull-down power supply terminal VGL, used to provide a low-potential first power supply signal.

[0098] Optionally, the input terminal IN of the nth stage shift register unit can be connected to the output terminal OUT of the cascaded nith stage shift register unit to receive the input signal provided by the output terminal of the nith stage shift register unit. Alternatively, the input terminal IN of the first stage shift register unit can be connected to a separate enable signal terminal STV to receive the input signal provided by the enable signal terminal STV. Here, n and i are both positive integers, and n is less than or equal to the total number of stages of the cascaded multi-stage shift register units, and i is less than n.

[0099] The second input control circuit 02 is connected to the first clock terminal CK, the first node N1, and the second node N2, respectively. Furthermore, the second input control circuit 02 is used to control the potential of the second node N2 based on the first clock signal and the potential of the first node N1.

[0100] For example, the second input control circuit 02 can control the first clock terminal CK to conduct with the second node N2 when the potential of the first clock signal is the first potential, so that the first clock signal provided by the first clock terminal CK is transmitted to the second node N2, that is, control the potential of the second node N2 to be the potential of the first clock signal. Furthermore, the second input control circuit 02 can control the first clock terminal CK to disconnect from the second node N2 when the potential of the first clock signal is the second potential.

[0101] For example, when the potential of the first node N1 is the first potential, the second input control circuit 02 can also control the first clock terminal CK to be connected to the second node N2, so that the first clock signal provided by the first clock terminal CK is transmitted to the second node N2, that is, control the potential of the second node N2 to be the potential of the first clock signal. Furthermore, when the potential of the first node N1 is the second potential, the second input control circuit 02 can also control the first clock terminal CK to be disconnected from the second node N2.

[0102] Output circuit 03 is connected to the first node N1, the second node N2, the second power supply terminal V2, the second clock terminal CB, and the output terminal OUT. Furthermore, output circuit 03 controls the switching between the second power supply terminal V2 and the output terminal OUT based on the potentials of the first node N1 and the second node N2, and also controls the switching between the second clock terminal CB and the output terminal OUT, so as to output a display drive signal via output terminal OUT.

[0103] For example, the output circuit 03 can control the second clock terminal CB to conduct with the output terminal OUT when the potential of the first node N1 is the first potential, so that the second clock signal provided by the second clock terminal CB is output through the output terminal OUT. Also, the output circuit 03 can control the second clock terminal CB to disconnect from the output terminal OUT when the potential of the first node N1 is the second potential.

[0104] For example, the output circuit 03 can control the second power supply terminal V2 to conduct with the output terminal OUT when the potential of the second node N2 is the first potential, so that the second power supply signal provided by the second power supply terminal V2 is output through the output terminal OUT. Also, the output circuit 03 can control the second power supply terminal V2 to disconnect from the output terminal OUT when the potential of the second node N2 is the second potential.

[0105] In other words, the display drive signal output via the OUT terminal can include a second clock signal and a second power supply signal. Furthermore, the OUT terminal can typically be connected to a pixel to transmit the display drive signal to the pixel, thereby driving the pixel to emit light. For example, the OUT terminal can be connected to the pixel via a gate line to transmit a gate drive signal to the pixel.

[0106] Optionally, like the first power supply terminal V1, the potential of the second power signal provided by the second power supply terminal V2 can also be a constant high potential. That is, the second power supply terminal V2 can also be a DC power supply terminal, and can be a pull-up power supply terminal VGH2 capable of providing a high-potential power signal. Of course, in some embodiments, the second power supply terminal V2 can also be a pull-down power supply terminal VGL, used to provide a low-potential second power signal. In addition, the potential of the second power signal can be the same as or different from the potential of the first power signal. Thus, in some embodiments, when the potential of the second power signal is the same as the potential of the first power signal, the second power supply terminal V2 and the first power supply terminal V1 can also be shared, that is, it can be simplified to a single power supply terminal (e.g., VGH1). This simplifies wiring, saves costs, and is beneficial for narrow bezel designs.

[0107] It is also understandable that, because the input control circuit (including the first input control circuit 01 and the second input control circuit 02) in this shift register unit is connected to fewer DC signal terminals, and controls the potential of the nodes (including the first node N1 and the second node N2) connected to the output circuit 03 under the control of the clock signal, it can be known that the transistors in the input control circuit will not be subjected to a constant high potential or a constant low potential for a long time. Therefore, the characteristic deviation of the transistors in the input control circuit is relatively small. Correspondingly, the input control circuit can reliably control the potential of the nodes, so that the output circuit 03 can reliably output the display drive signal through the output terminal OUT under the control of the node's potential, thereby reliably driving the pixels to emit light and improving the display effect.

[0108] In summary, this application provides a shift register unit. Since each input control circuit in this shift register unit controls the potential of the node connected to the output circuit under the control of multiple clock signals, it is known that the transistors in the input control circuit will not be subjected to high or low potentials for extended periods, and the characteristics of the transistors in the input control circuit are less prone to shift. Accordingly, the input control circuit can reliably control the node potential, thereby enabling the output circuit to reliably output display drive signals under the control of the node potential, reliably driving pixel illumination and ensuring a better display effect on the display panel.

[0109] Optionally, Figure 2 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 2, the first input control circuit 01 includes: a first input control sub-circuit 011 and a second input control sub-circuit 012.

[0110] The first input control sub-circuit 011 can be connected to the first clock terminal CK, the input terminal IN, and the first node N1, respectively. Furthermore, the first input control sub-circuit 011 can be used to control the on / off state of the input terminal IN and the first node N1 in response to the first clock signal, thereby controlling the potential of the first node N1.

[0111] For example, the first input control sub-circuit 011 can control the input terminal IN to be connected to the first node N1 when the potential of the first clock signal is the first potential, so that the input signal provided by the input terminal IN is transmitted to the first node N1, that is, control the potential of the first node N1 to be the potential of the input signal. Furthermore, the first input control circuit 01 can control the input terminal IN to be disconnected from the first node N1 when the potential of the first clock signal is the second potential.

[0112] The second input control sub-circuit 012 can be connected to the second clock terminal CB, the first power supply terminal V1, the second node N2, and the first node N1, respectively. Furthermore, the second input control sub-circuit 012 can be used to control the switching between the first power supply terminal V1 and the first node N1 in response to the second clock signal and the potential of the second node N2, thereby controlling the potential of the first node N1.

[0113] For example, the second input control sub-circuit 012 can control the first power supply terminal V1 to conduct with the first node N1 when the potential of the second node N2 and the potential of the second clock signal are both the first potential, so that the first power signal provided by the first power supply terminal V1 is transmitted to the first node N1, that is, control the potential of the first node N1 to be the potential of the first power signal. Furthermore, the second input control sub-circuit 012 can control the first power supply terminal V1 to disconnect from the first node N1 when the potential of the second node N2 and / or the potential of the second clock signal are the second potential.

[0114] Optionally, referring to Figure 2, the second input control circuit 02 may include a third input control sub-circuit 021 and a fourth input control sub-circuit 022.

[0115] The third input control sub-circuit 021 can be connected to the first clock terminal CK, the target signal terminal V01, and the second node N2, respectively. Furthermore, the third input control sub-circuit 021 can be used to control the on / off state of the target signal terminal V01 and the second node N2 in response to the first clock signal, thereby controlling the potential of the second node N2.

[0116] The target signal terminal V01 can be shared with the first clock terminal CK or can be the third power supply terminal V3. That is, the signal provided by the target signal terminal V01 can be the first clock signal or the third power supply signal provided by the third power supply terminal V3. Optionally, the potential of the third power supply signal can be a constant low potential. That is, the third power supply terminal V3 can also be a DC power supply terminal, and can be a pull-down power supply terminal VGL1 capable of providing a low-potential power supply signal. Of course, in some embodiments, the third power supply terminal V3 can also be a pull-up power supply terminal VGH, used to provide a high-potential third power supply signal.

[0117] Furthermore, it is understandable that by sharing the target signal terminal V01 with the first clock terminal CK, not only can wiring be simplified, costs saved, and narrow bezel design facilitated, but the characteristic shift of the transistors included in the third input control sub-circuit 021 due to prolonged exposure to high or low potentials can also be prevented. This improves the characteristic shift of the transistors in the third input control sub-circuit 021, thereby helping to maintain circuit stability and reliably control the potential of the second node N2. This allows the output circuit 03 to reliably control the switching between the first power supply terminal V1 and the output terminal OUT under the control of the potential of the second node N2. In other words, the output circuit 03 can reliably output the display drive signal via the output terminal OUT.

[0118] For example, taking the target signal terminal V01 as the first clock terminal CK, the third input control sub-circuit 021 can control the first clock terminal CK to conduct with the second node N2 when the potential of the first clock signal is the first potential, so that the first clock signal provided by the first clock terminal CK is transmitted to the second node N2, that is, control the potential of the second node N2 to be the potential of the first clock signal. Furthermore, the third input control sub-circuit 021 can also control the first clock terminal CK to disconnect from the second node N2 when the potential of the first clock signal is the second potential.

[0119] The fourth input control sub-circuit 022 can be connected to the first node N1, the first clock terminal CK, and the second node N2, respectively. Furthermore, the fourth input control sub-circuit 022 can be used to control the switching between the first clock terminal CK and the second node N2 in response to the potential of the first node N1, thereby controlling the potential of the second node N2.

[0120] For example, the fourth input control sub-circuit 022 can control the first clock terminal CK to conduct with the second node N2 when the potential of the first node N1 is the first potential, so that the first clock signal provided by the first clock terminal CK is transmitted to the second node N2, that is, control the potential of the second node N2 to be the potential of the first clock signal. Furthermore, the fourth input control sub-circuit 022 can control the first clock terminal CK to disconnect from the second node N2 when the potential of the first node N1 is the second potential.

[0121] Optionally, referring to Figure 2, the output circuit 03 may include: a first output sub-circuit 031 and a second output sub-circuit 032.

[0122] The first output sub-circuit 031 can be connected to the first node N1, the second clock terminal CB, and the output terminal OUT, respectively. Furthermore, the first output sub-circuit 031 can be used to control the switching between the second clock terminal CB and the output terminal OUT in response to the potential of the first node N1, so as to output a second clock signal via the output terminal OUT as a display driving signal. It can also be used to adjust the potential of the first node N1 based on the display driving signal output via the output terminal OUT.

[0123] For example, the first output sub-circuit 031 can control the second clock terminal CB to conduct with the output terminal OUT when the potential of the first node N1 is at the first potential, so that the second clock signal provided by the second clock terminal CB is output through the output terminal OUT. Furthermore, the first output sub-circuit 031 can control the second clock terminal CB to disconnect from the output terminal OUT when the potential of the first node N1 is at the second potential. In addition, the first output sub-circuit 031 can also adjust the potential of the first node N1 through coupling.

[0124] The second output sub-circuit 032 can be connected to the second node N2, the second power supply terminal V2, and the output terminal OUT, respectively. Furthermore, the second output sub-circuit 032 can be used to control the switching between the second power supply terminal V2 and the output terminal OUT in response to the potential of the second node N2, so as to output a second power signal via the output terminal OUT as a display drive signal. It can also be used to adjust the potential of the second node N2 based on the second power signal.

[0125] For example, the second output sub-circuit 032 can control the second power supply terminal V2 to conduct with the output terminal OUT when the potential of the second node N2 is the first potential, so that the second power signal provided by the second power supply terminal V2 is output through the output terminal OUT. Furthermore, the second output sub-circuit 032 can control the second power supply terminal V2 to disconnect from the output terminal OUT when the potential of the second node N2 is the second potential. In addition, the second output sub-circuit 032 can also adjust the potential of the second node N2 through coupling.

[0126] Optionally, Figure 3 is a schematic diagram of another shift register unit provided in an embodiment of this application. As shown in Figure 3, the first node N1 may include: a first child node N11 and a second child node N12. That is, the first node N1 can be divided into two child nodes. Based on this, the shift register unit may further include: a third input control circuit 04 and / or a fourth input control circuit 05.

[0127] The third input control circuit 04 can be connected to the input control terminal V02, the first sub-node N11, and the second sub-node N12, respectively. Furthermore, the third input control circuit 04 can be used to control the on / off state of the first sub-node N11 and the second sub-node N12 in response to the control signal provided by the input control terminal V02.

[0128] For example, the third input control circuit 04 can control the first sub-node N11 and the second sub-node N12 to conduct when the potential of the control signal provided by the input control terminal VO2 is a first potential, so that the signal transmitted to the first sub-node N11 can be further transmitted to the second sub-node N12, and the potential of the second sub-node N12 can be the same as the potential of the first sub-node N11. Furthermore, the third input control circuit 04 can control the first sub-node N11 and the second sub-node N12 to disconnect when the potential of the control signal provided by the input control terminal VO2 is a second potential.

[0129] The fourth input control circuit 05 can be connected to the first clock terminal CK, the input terminal IN, and the second sub-node N12, respectively. Furthermore, this fourth input control circuit 05 can be used to control the on / off state of the input terminal IN and the second sub-node N12 in response to the first clock signal.

[0130] For example, the fourth input control circuit 05 can control the input terminal IN to be connected to the second sub-node N12 when the potential of the first clock signal is the first potential, so that the input signal provided by the input terminal IN is transmitted to the second sub-node N12. Also, the fourth input control circuit 05 can control the input terminal IN to be disconnected from the second sub-node N12 when the potential of the first clock signal is the first potential.

[0131] As can be seen from the preceding description, the fourth input control circuit 05 and the first input control sub-circuit 011 can refer to two circuits that simultaneously write the input signal provided by the input terminal IN into the first sub-node N11 and the second sub-node N12 through different paths. These two circuits can be considered to be connected in parallel.

[0132] Furthermore, referring to Figure 3, it can be seen that when the first node N1 is divided into two sub-nodes, both the first input control sub-circuit 011 and the second input control circuit 02 can be connected to the first sub-node N11. The output circuit 03 can be connected to the second sub-node N12. That is, in conjunction with the above description, the first input control sub-circuit 011 can control the potential of the first sub-node N11; the second input control circuit 02 (referring to the fourth input control sub-circuit 022) can control the switching between the first clock terminal CK and the second node N2 under the control of the potential of the first sub-node N11; the output circuit 03 (referring to the first output sub-circuit 031) can control the switching between the second clock terminal CB and the output terminal OUT under the control of the potential of the second sub-node N12. Therefore, it can also be understood that the third input control circuit 04 is equivalent to an isolation circuit, used to isolate the first sub-node N11 and the second sub-node N12, to prevent leakage current, and to ensure better potential stability of the node.

[0133] For example, the shift register units shown in Figures 3 and 4 include a third input control circuit 04 and a fourth input control circuit 05; the shift register units shown in Figures 5 and 6 include a fourth input control circuit 05 but do not include a third input control circuit 04; the shift register units shown in Figures 7 to 12 include a third input control circuit 04 but do not include a fourth input control circuit 05.

[0134] Optionally, when the third input control circuit 04 is included, as can be seen from Figures 3 and 4, and Figures 7 to 12, the second input control sub-circuit 012 can be connected to either the first sub-node N11 or the second sub-node N12. For example, in Figures 3, 11, and 12, the second input control sub-circuit 012 is connected to the first sub-node N11; in Figure 4, and Figures 7 to 10, the second input control sub-circuit 012 is connected to the second sub-node N12. When the third input control circuit 04 is not included, as can be seen from Figures 5 and 6, the second input control sub-circuit 012 can be connected to the second sub-node N12. That is, as described above, when the third input control circuit 04 is included, the second input control sub-circuit 012 can control the on / off state of the first power supply terminal V1 and the first sub-node N11, or control the on / off state of the first power supply terminal V1 and the second sub-node N12. Without the third input control circuit 04, the second input control sub-circuit 012 can control the connection and disconnection between the first power supply terminal V1 and the second sub-node N12.

[0135] Optionally, when the fourth input control circuit 05 is included, referring to Figures 3 and 4, it can be seen that the input control terminal V02 connected to the third input control circuit 04 can be shared with either the first clock terminal CK or the second clock terminal CB. For example, the input control terminal V02 shown in Figures 3 and 4 is shared with the second clock terminal CB. However, when the fourth input control circuit 05 is not included, referring to Figures 7 to 11, it can be seen that the input control terminal V02 can be shared with the first clock terminal CK. That is, the control signal provided by the input control terminal V02 can be either the first clock signal or the second clock signal. This is mainly because it is generally necessary to simultaneously control the potentials of the first child node N11 and the second child node N12 to be the same. With the fourth input control circuit 05 included, as described above, the fourth input control circuit 05 and the first input control sub-circuit 011 can jointly write the input signal provided by the input terminal IN to the first child node N11 and the second child node N12 simultaneously via different paths. Therefore, whether the first clock signal or the second clock signal is used as the control signal for the third input control circuit 04, it does not affect the simultaneous control of the potentials of the first child node N11 and the second child node N12 to be the same. However, without the fourth input control circuit 05, the third input control circuit 04 needs to respond to the same first clock signal as the first input control sub-circuit 011, simultaneously controlling the potentials of the first child node N11 and the second child node N12 to be the same. Of course, in some embodiments, as can be seen from Figure 12, the input control terminal V02 can also be the third power supply terminal V3.

[0136] Understandably, by sharing the input control terminal V02 with either the first clock terminal CK or the second clock terminal CB, not only can wiring be simplified and costs saved, but narrow bezel designs are also facilitated. Furthermore, it prevents the transistors in the third input control circuit 04 from experiencing characteristic shifts due to prolonged exposure to high or low potentials. This improves the characteristic shift of the transistors in the third input control circuit 04, thereby helping to maintain circuit stability and reliably control the potential of the second sub-node N12. This allows the first output sub-circuit 031 to reliably control the switching between the second clock terminal CB and the output terminal OUT under the control of the potential of the second sub-node N12. In other words, this ensures that the output circuit 03 reliably outputs the display drive signal via the output terminal OUT.

[0137] Optionally, referring to Figure 6 and Figures 8 to 10, it can be seen that the shift register unit may also include: a potential adjustment circuit 06.

[0138] The potential adjustment circuit 06 can be connected to the potential adjustment terminal V03 and the first sub-node N11 respectively. Furthermore, the potential adjustment circuit 06 can be used to adjust the potential of the first sub-node N11 based on the adjustment signal provided by the potential adjustment terminal V03.

[0139] For example, the potential adjustment circuit 06 can adjust the potential of the first sub-node N11 based on the adjustment signal through coupling or bootstrapping to further ensure that the potential stability of the first sub-node N11 is good.

[0140] Optionally, referring to Figures 6 and 8 through 10, it can be seen that the potential adjustment terminal V03 can be shared with either the first power supply terminal V1 or the first clock terminal CK. That is, the adjustment signal provided by the potential adjustment terminal V03 can be the first power supply signal provided by the first power supply terminal V1 (e.g., VGH1) or the first clock signal provided by the first clock terminal CK. Of course, in some embodiments, the potential adjustment terminal V03 can also be a third power supply terminal V3. For example, the potential adjustment terminal V03 shown in Figure 6 is shared with the first power supply terminal V1. The potential adjustment terminal V03 shown in Figures 8 through 10 is shared with the first clock terminal CK.

[0141] Furthermore, it is understandable that by sharing the potential adjustment terminal V03 with either the first power supply terminal V1 or the first clock terminal CK, wiring can be simplified, costs saved, and narrow bezel designs facilitated. Additionally, when the potential adjustment terminal V03 is shared with the first power supply terminal V1 or is the third power supply terminal V3, the potential adjustment circuit 06 can control the potential of the first sub-node N11 to be low or high based on a constant potential power signal. For example, the potential adjustment circuit 06 can control the potential of the first sub-node N11 to be high based on a high-potential first power signal provided by the first power supply terminal V1, and control the potential of the first sub-node N11 to be low based on a low-potential third power signal provided by the third power supply terminal V3. When the potential adjustment terminal V03 is shared with the first clock terminal CK, on ​​the one hand, as shown in Figure 8, the potential adjustment terminal V03 can be connected to the same first clock terminal CK as the first input control sub-circuit 011; or, as shown in Figure 9, the potential adjustment terminal V03 can be connected to the same first clock terminal CK as the third input control sub-circuit 021; or, as shown in Figure 10, the potential adjustment terminal V03 can be connected to the same first clock terminal CK as the third input control circuit 04, so as to further raise or lower the potential of the first sub-node N11 based on the potential change of the first clock signal provided by the first clock terminal CK. For example, when the potential of the first clock signal switches from high to low, the potential of the first sub-node N11 is further lowered. When the potential of the first clock signal switches from low to high, the potential of the first sub-node N11 is further raised.

[0142] Optionally, referring to Figure 12, the second node N2 may include a third child node N21 and a fourth child node N22. That is, the second node N2 can also be divided into two child nodes. Based on this, the shift register unit may also include a fifth input control circuit 07 and a sixth input control circuit 08.

[0143] The fifth input control circuit 07 can be connected to the first node N1, the third child node N21, and the fourth child node N22, respectively. Furthermore, this fifth input control circuit 07 can be used to control the on / off state of the third child node N21 and the fourth child node N22 in response to the potential of the first node N1. It can be understood that, based on dividing the first node N1 into a first child node N11 and a second child node N12, as shown in Figure 12, the fifth input control circuit 07 can be connected to the first child node N11.

[0144] For example, the fifth input control circuit 07 can control the third child node N21 and the fourth child node N22 to conduct when the potential of the first node N1 (e.g., the first child node N11) is at a first potential, so that the signal transmitted to the third child node N21 can be further transmitted to the fourth child node N22, and the potential of the fourth child node N22 can be the same as the potential of the third child node N21. Furthermore, the fifth input control circuit 07 can control the third child node N21 and the fourth child node N22 to disconnect when the potential of the first node N1 is at a second potential.

[0145] The sixth input control circuit 08 can be connected to the first clock terminal CK, the target signal terminal V01, and the fourth sub-node N22, respectively. Furthermore, this sixth input control circuit 08 can be used to control the on / off state of the target signal terminal V01 and the fourth sub-node N22 in response to the first clock signal.

[0146] For example, still taking the target signal terminal V01 as the first clock terminal CK, the sixth input control circuit 08 can control the first clock terminal CK to conduct with the fourth child node N22 when the potential of the first clock signal is the first potential, so that the first clock signal provided by the first clock terminal CK is transmitted to the fourth child node N22, that is, control the potential of the fourth child node N22 to be the potential of the first clock signal. Furthermore, the sixth input control circuit 08 can control the first clock terminal CK to disconnect from the fourth child node N22 when the potential of the first clock signal is the second potential.

[0147] As can be seen from the preceding description, the sixth input control circuit 08 and the third input control sub-circuit 021 can refer to two circuits that simultaneously write the signal provided by the target signal terminal V01 into the third sub-node N21 and the fourth sub-node N22 through different paths. These two circuits can be considered to be connected in parallel.

[0148] Understandably, by simultaneously controlling the potential of the fourth sub-node N22 using the fifth input control circuit 07 and the sixth input control circuit 08, the problem of unreliable control of the fourth sub-node N22's potential due to transistor characteristic shifts in a single circuit can be reduced. That is, the potential stability of the fourth sub-node N22 can be improved, thereby enabling the second output sub-circuit 032 to reliably control the switching between the second power supply terminal V2 and the output terminal OUT in response to the potential of the fourth sub-node N22, and reliably output the display drive signal. This helps improve circuit stability.

[0149] Furthermore, referring to Figure 12, it can be seen that when the second node N2 is divided into two sub-nodes, the third input control sub-circuit 021 and the fourth input control sub-circuit 022 can both be connected to the third sub-node N21, and the output circuit 03 and the first input control circuit 01 can both be connected to the fourth sub-node N22. That is, in conjunction with the above description, the third input control sub-circuit 021 can control the on / off state of the target signal terminal V01 and the third sub-node N21 under the control of the first clock signal; the fourth input control sub-circuit 022 can control the on / off state of the first clock terminal CK and the third sub-node N21 based on the potential of the first node N1 (e.g., the first sub-node N11); the output circuit 03 (here referring to the second output sub-circuit 032) can control the on / off state of the second power supply terminal V2 and the output terminal OUT under the control of the fourth sub-node N22; the first input control circuit 01 (here referring to the second input control sub-circuit 012) can control the on / off state of the second power supply terminal V2 and the first node N1 (e.g., the first sub-node N11 or the second sub-node N12) under the control of the fourth sub-node N22 and the second clock signal.

[0150] Of course, the above structure is only illustrative. Any other combination design that can achieve the same function and effect can be applied to this application. For example, in some other embodiments, the shift register unit may include one of the fifth input control circuit 07 and the sixth input control circuit 08.

[0151] Optionally, taking the structures shown in Figures 3 to 12 as examples, Figures 13 to 22 respectively show the corresponding circuit structure schematics. Combining Figures 13 to 22, it can be seen that:

[0152] The first input control circuit 01 may include a first transistor T1. The second input control sub-circuit 012 may include a second transistor T2 and a third transistor T3. The third input control circuit 04 may include a fourth transistor T4. The fourth input control circuit 05 may include a fifth transistor T5. The potential adjustment circuit 06 may include a first capacitor C1. The third input control sub-circuit 021 may include a sixth transistor T6. The fourth input control sub-circuit 022 may include a seventh transistor T7. The fifth input control circuit 07 may include an eighth transistor T8. The sixth input control circuit 08 may include a ninth transistor T9. The first output sub-circuit 031 may include a tenth transistor T10 and a second capacitor C2. The second output sub-circuit 032 may include an eleventh transistor T11 and a third capacitor C3.

[0153] The gate of the first transistor T1 can be connected to the first clock terminal CK, the first terminal of the first transistor T1 can be connected to the input terminal IN (e.g., STV), and the second terminal of the first transistor T1 can be connected to the first node N1.

[0154] It is understandable that, as mentioned above, based on dividing the first node N1 into the first child node N11 and the second child node N12, as shown in Figures 13 to 22, the second pole of the first transistor T1 can be connected to the first child node N11.

[0155] The gate of the second transistor T2 can be connected to the second node N2, the first terminal of the second transistor T2 can be connected to the first power supply terminal V1, the second terminal of the second transistor T2 can be connected to the first terminal of the third transistor T3, the gate of the third transistor T3 can be connected to the second clock terminal CB, and the second terminal of the third transistor T3 can be connected to the first node N1.

[0156] As can be understood, as mentioned earlier, based on dividing the first node N1 into the first child node N11 and the second child node N12, the second terminal of the third transistor T3 can be connected to either the first child node N11 or the second child node N12. For example, in Figures 13, 21, and 22, the second terminal of the third transistor T3 is connected to the first child node N11; in Figures 14 to 20, the second terminal of the third transistor T3 is connected to the second child node N12. Based on dividing the second node N2 into the third child node N21 and the fourth child node N22, as shown in Figure 22, the gate of the second transistor T2 can be connected to the fourth child node N22. In Figures 13 to 22, the connection node between the second transistor T2 and the third transistor T3 is also labeled as the third node N3.

[0157] The gate of the fourth transistor T4 can be connected to the input control terminal V02, the first terminal of the fourth transistor T4 can be connected to the first child node N11, and the second terminal of the fourth transistor T4 can be connected to the second child node N12.

[0158] Optionally, as described above, the input control terminal V02 can be a first clock terminal CK, a second clock terminal CB, or a third power supply terminal V3. For example, referring to Figures 13 to 16, the input control terminal V02 shown is the second clock terminal CB; referring to Figures 17 to 21, the input control terminal V02 shown is the first clock terminal CK; referring to Figure 22, the input control terminal V02 shown is the third power supply terminal V3.

[0159] The gate of the fifth transistor T5 can be connected to the first clock terminal CK, the first terminal of the fifth transistor T5 can be connected to the input terminal IN, and the second terminal of the fifth transistor T5 can be connected to the second sub-node N12.

[0160] The first capacitor C1 can be connected between the potential adjustment terminal V03 and the first sub-node N11.

[0161] Optionally, as described above, the potential adjustment terminal V03 can be a first power supply terminal V1, a third power supply terminal V3, or a first clock terminal CK. For example, referring to Figure 16, the potential adjustment terminal V03 shown therein is the first power supply terminal V1. Referring to Figures 18 to 20, the potential adjustment terminal V03 shown therein is the first clock terminal CK.

[0162] The gate of the sixth transistor T6 can be connected to the first clock terminal CK, the first terminal of the sixth transistor T6 can be connected to the target signal terminal V01, and the second terminal of the sixth transistor T6 can be connected to the second node N2.

[0163] Optionally, as described above, the target signal terminal V01 can be either the first clock terminal CK or the third power supply terminal V3. For example, referring to Figures 13 to 21, the target signal terminal V01 shown is the first clock terminal CK; referring to Figure 22, the target signal terminal V01 shown is the third power supply terminal V3. Furthermore, it can be understood that, based on dividing the second node N2 into the third sub-node N21 and the fourth sub-node N22, as shown in Figure 22, the second terminal of the sixth transistor T6 can be connected to the third sub-node N21.

[0164] The gate of the seventh transistor T7 can be connected to the first node N1, the first terminal of the seventh transistor T7 can be connected to the first clock terminal CK, and the second terminal of the seventh transistor T7 can be connected to the second node N2.

[0165] Understandably, as mentioned earlier, based on dividing the first node N1 into the first child node N11 and the second child node N12, as shown in Figures 13 to 22, the gate of the seventh transistor T7 can be connected to the first child node N11. Similarly, based on dividing the second node N2 into the third child node N21 and the fourth child node N22, as shown in Figure 22, the second terminal of the seventh transistor T7 can be connected to the third child node N21.

[0166] The gate of the eighth transistor T8 can be connected to the first node N1, the first terminal of the eighth transistor T8 can be connected to the third child node N21, and the second terminal of the eighth transistor T8 can be connected to the fourth child node N22.

[0167] It is understandable that, as mentioned above, based on dividing the first node N1 into the first child node N11 and the second child node N12, as shown in Figure 22, the gate of the eighth transistor T8 can be connected to the first child node N11.

[0168] The gate of the ninth transistor T9 can be connected to the first clock terminal CK, the first terminal of the ninth transistor T9 can be connected to the target signal terminal V01 (e.g., the first clock terminal CK), and the second terminal of the ninth transistor T9 can be connected to the fourth child node N22.

[0169] The gate of the tenth transistor T10 can be connected to the first node N1, the first terminal of the tenth transistor T10 can be connected to the second clock terminal CB, and the second terminal of the tenth transistor T10 can be connected to the output terminal OUT.

[0170] The second capacitor C2 can be connected between the output terminal OUT and the first node N1.

[0171] Understandably, as mentioned earlier, based on dividing the first node N1 into the first child node N11 and the second child node N12, as shown in Figures 13 to 22, the gate of the tenth transistor T10 can be connected to the second child node N12. The second capacitor C2 can be connected between the output terminal OUT and the first child node N11.

[0172] The gate of the eleventh transistor T11 can be connected to the second node N2, the first terminal of the eleventh transistor T11 can be connected to the second power supply terminal V2, and the second terminal of the eleventh transistor T11 can be connected to the output terminal OUT.

[0173] The third capacitor C3 can be connected between the second power supply terminal V2 and the second node N2.

[0174] As can be understood, as mentioned earlier, based on dividing node N2 into a third sub-node N21 and a fourth sub-node N22, as shown in Figure 22, the gate of the eleventh transistor T11 can be connected to the fourth sub-node N22. The third capacitor C3 can be connected between the second power supply terminal V2 and the fourth sub-node N22.

[0175] Optionally, the capacitance of the first capacitor C1 can be between approximately 10 F and 30 F to ensure better control of the potential of the first sub-node N11. The capacitances of the second capacitor C2 and the third capacitor C3 are generally larger, between approximately 50 F and 150 F, to ensure better stability of the potentials of the first node N1 (referring to the second sub-node N12) and the second node N2 (referring to the fourth sub-node N22).

[0176] Optionally, in the circuits shown in Figures 13 to 12, the first power supply terminal V1 and the second power supply terminal V2 are shared, and are the same pull-up power supply terminal VGH1. The third power supply terminal V3 is a pull-down power supply terminal VGL1.

[0177] That is, embodiments of this application provide shift register units with at least ten embodiment circuit structures as shown in Figures 13 to 22:

[0178] Example 1: The 9T2C structure (i.e., including 9 transistors and 2 capacitors) is shown in Figure 13. The specific connection method can be referred to the previous description and Figure 13, and will not be repeated here.

[0179] Example 2: The 9T2C structure shown in Figure 14. The specific connection method can be found in the preceding description and Figure 14, and will not be repeated here. The difference from Example 1 is that the second terminal of the third transistor T3 in the second input control sub-circuit 012 is changed from being connected to the first sub-node N11 to being connected to the second sub-node N12.

[0180] Example 3: The 8T2C structure shown in Figure 15. The specific connection method can be found in the previous description and Figure 15, and will not be repeated here. The difference from Example 2 is that the fourth transistor T4 is omitted.

[0181] Example 4: The 8T3C structure shown in Figure 16. The specific connection method can be found in the preceding description and Figure 16, and will not be repeated here. The difference from Example 3 is the addition of a first capacitor C1, which is connected between the first power supply terminal V1 and the first sub-node N11. That is, in Example 4, the potential adjustment terminal V03 is shared with the first power supply terminal V1.

[0182] Example 5: The 8T2C structure shown in Figure 17. The specific connection method can be found in the previous description and Figure 17, and will not be repeated here. The difference from Example 2 is that the fifth transistor T5 is omitted, and the gate of the fourth transistor T4 is changed from being connected to the second clock terminal CB to being connected to the first clock terminal CK. That is, the input control terminal VO2 is changed from being shared with the second clock terminal CB to being shared with the first clock terminal CK.

[0183] Example 6: The 8T3C structure shown in Figure 18. The specific connection method can be found in the preceding description and Figure 18, and will not be repeated here. The difference from Example 5 is the addition of a first capacitor C1, which is connected between the first clock terminal CK and the first child node N11. That is, in this Example 4, the potential adjustment terminal V03 is shared with the first clock terminal CK, and the first clock terminal CK is the first clock terminal CK connected to the gate of the first transistor T1.

[0184] Example 7: The 8T3C structure shown in Figure 19. The specific connection method can be found in the preceding description and Figure 19, and will not be repeated here. The difference from Example 6 is that the first clock terminal CK, to which the first capacitor C1 is connected, is changed from the gate of the first transistor T1 to the gate of the sixth transistor T6.

[0185] Example 8: The 8T3C structure shown in Figure 20. The specific connection method can be found in the previous description and Figure 20, and will not be repeated here. The difference from Example 6 is that the first clock terminal CK connected to the first capacitor C1 is changed from the gate of the first transistor T1 to the gate of the fourth transistor.

[0186] Example 9: The 8T2C structure shown in Figure 21. The specific connection method can be found in the previous description and Figure 21, and will not be repeated here. The difference from Example 5 is that the second terminal of the third transistor T3 in the second input control sub-circuit 012 is changed from being connected to the second sub-node N12 to being connected to the first sub-node N11.

[0187] Example 10: The 10T2C structure shown in Figure 22. The specific connection method can be found in the previous description and Figure 22, and will not be repeated here. The difference from Example 9 is the addition of an eighth transistor T8 and a ninth transistor T9, and the gate of the fourth transistor T4 is changed from being connected to the first clock terminal CK to being connected to the third power supply terminal V3. In other words, the input control terminal V02 is changed from being shared with the second clock terminal CB to being connected to the third power supply terminal V3.

[0188] Optionally, referring to Figures 13 to 22, it can be seen that the transistors in the shift register units shown are all P-type transistors. Correspondingly, as described above, the first potential can be a low potential, and the second potential can be a high potential. Of course, in some other embodiments, the transistors in the shift register units can also be N-type transistors. Alternatively, the shift register unit can include both P-type and N-type transistors. Furthermore, as described above, it is not limited to the structures of embodiments 1 to 10. For example, in some other embodiments, based on embodiment 1 shown in Figure 13, the eighth transistor T8 and the ninth transistor T9 shown in embodiment 10 of Figure 22 can be added, that is, the shift register unit can also be a 11T2C structure (i.e., including 11 transistors and 2 capacitors). In some other embodiments, based on embodiment 10 shown in Figure 22, the first capacitor C1 can be added. That is, the shift register unit can also be a 10T3C structure (i.e., including 10 transistors and 3 capacitors).

[0189] As can be seen from the foregoing description, the embodiments of this application can improve the characteristic offset of the transistor and ensure better output stability by reducing the DC power supply terminal (e.g., VGH or VGL) as the gate voltage of the transistor.

[0190] In summary, this application provides a shift register unit. Since each input control circuit in this shift register unit controls the potential of the node connected to the output circuit under the control of multiple clock signals, it is known that the transistors in the input control circuit will not be subjected to high or low potentials for extended periods, and the characteristics of the transistors in the input control circuit are less prone to shift. Accordingly, the input control circuit can reliably control the node potential, thereby enabling the output circuit to reliably output display drive signals under the control of the node potential, reliably driving pixel illumination and ensuring a better display effect on the display panel.

[0191] This application also provides a method for driving a shift register unit, which can be used to drive any of the shift register units shown in Figures 1 to 22. As shown in Figure 23, the method includes:

[0192] Step 2301, First stage: The potential of the first clock signal provided by the first clock terminal is the first potential; the potential of the second clock signal provided by the second clock terminal and the potential of the input signal provided by the input terminal are both the second potential; the first input control circuit controls the potential of the first node to be the first potential based on the received first clock signal, input signal, second clock signal, first power signal with the second potential provided by the first power terminal, and the potential of the second node; the second input control circuit controls the potential of the second node to be the first potential based on the received first clock signal and the potential of the first node; the output circuit controls the second power terminal and the second clock terminal to be connected to the output terminal based on the potentials of the first node and the second node.

[0193] Step 2302, Second Stage: The potential of the second clock signal provided by the second clock terminal is the first potential, and the potential of the first clock signal provided by the first clock terminal and the potential of the input signal provided by the input terminal are both the second potential. The first input control circuit controls the potential of the first node to be the first potential based on the received first clock signal, input signal, second clock signal, first power signal and the potential of the second node. The second input control circuit controls the potential of the second node to be the second potential based on the received first clock signal and the potential of the first node. The output circuit controls the second clock terminal to be connected to the output terminal based on the potentials of the first node and the second node.

[0194] Optionally, based on Figure 21, taking the connection of the gate of the fourth transistor T4 to the pull-down power supply terminal VGL1 as an example, Figure 24 schematically shows a schematic diagram of the drive timing signals of the shift register unit in some embodiments. Referring to Figure 24, it can be seen that due to the influence of transistor characteristic offset (e.g., PBTS occurring in the seventh transistor T7), the display drive signal output through the output terminal OUT will be abnormal, forming a multi-pulse waveform. Moreover, from the output terminal OUT1 of the first-stage shift register unit to the output terminal OUT3 of the third-stage shift register unit, the abnormality of the output display drive signal will gradually worsen. This abnormality will cause display panel display abnormalities, resulting in abnormal display. In Figure 24, dvth = 0 indicates that the threshold voltage Vth of the seventh transistor T7 has not shifted; dvth = 4 indicates that the threshold voltage Vth of the seventh transistor T7 has shifted positively, and the shift amount is 4V. When dvth = 4, the display drive signal output through the output terminal OUT will be abnormal.

[0195] Analysis revealed that the characteristic deviation of the transistor was mainly due to the gate being subjected to positive or negative voltage for a long period of time. Based on this, as described above, the embodiments of this application can avoid the gate being subjected to positive or negative voltage for a long period of time by reducing the DC power supply terminal (e.g., VGH or VGL) as the gate voltage of the transistor, thereby solving the above-mentioned abnormal problem.

[0196] For example, taking the structure shown in Figure 13 as an example, i.e., with the first potential being low and the second potential being high, and both the first power supply terminal V1 and the second power supply terminal V2 being pull-up power supply terminals VGH1 capable of providing high-potential power signals, and referring to the schematic diagram of the driving timing signal of a shift register unit shown in Figure 25, the working process of the shift register unit is explained as follows:

[0197] After the input signal provided at the input terminal IN (e.g., STV) changes from a high level to a low level:

[0198] In stage t01, the potential of the first clock signal provided by the first clock terminal CK is low, and the potential of the second clock signal provided by the second clock terminal CB is high. Correspondingly, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 can all be turned on, while the third transistor T3 and the fourth transistor T4 can all be turned off. This allows the low-potential input signal provided by the input terminal IN to be simultaneously transmitted to the first sub-node N11 and the second sub-node N12 via the turned-on first transistor T1 and fifth transistor T5, controlling the potentials of both sub-node N11 and N12 to be low. Furthermore, the low-potential first clock signal provided by the first clock terminal CK can be transmitted to the second node N2 via the turned-on sixth transistor T6, controlling the potential of the second node N2 to be low. Correspondingly, the second transistor T2, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 can all be turned on. This allows the low-potential first clock signal to also be transmitted to the second node N2 via the turned-on seventh transistor T7, ensuring that the second transistor T2 and the eleventh transistor T11 are reliably turned on. Furthermore, the high-potential first power signal provided by the first power supply terminal V1 can be transmitted to the third node N3 via the activated second transistor T2, controlling the potential of the third node N3 to be high. This allows the high-potential second clock signal to be transmitted to the output terminal OUT via the activated tenth transistor T10, and the high-potential second power signal provided by the second power supply terminal V2 to be transmitted to the output terminal OUT via the activated eleventh transistor T11. That is, in this stage t01, a high-potential display drive signal can be output via the output terminal OUT.

[0199] In stage t02, the potential of the first clock signal provided by the first clock terminal CK changes from low to high, and the potential of the second clock signal provided by the second clock terminal CB changes from high to low. Correspondingly, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 can all be turned off, and the third transistor T3 and the fourth transistor T4 can both be turned on. Furthermore, in this stage t02, the potential of the first child node N11 can be maintained at the low potential of the previous stage. Correspondingly, the seventh transistor T7 can be turned on. Thus, the high-potential first clock signal provided by the first clock terminal CK can be transmitted to the second node N2 via the turned-on seventh transistor T7, controlling the potential of the second node N2 to be high. Correspondingly, the second transistor T2 and the eleventh transistor T11 can both be turned off. And, the low potential of the first child node N11 can be further written to the third node N3 and the second child node N12, controlling the potential of the third node N3 and the second child node N12 to be low. Furthermore, because the second clock signal changes from a high potential to a low potential, the coupling effect of the second capacitor C2 can further pull down the potential of the second sub-node N12, controlling the potential of the second sub-node N12 to a lower low potential. Correspondingly, the tenth transistor T10 can be fully turned on. Thus, the low-potential second clock signal can be transmitted to the output terminal OUT via the turned-on tenth transistor T10. That is, in this stage t02, a low-potential display drive signal can be output through the output terminal OUT.

[0200] In stage t03, the potential of the first clock signal provided by the first clock terminal CK changes from high to low, and the potential of the second clock signal provided by the second clock terminal CB changes from low to high. Correspondingly, as in stage t01, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 can all be turned on, and the third transistor T3 and the fourth transistor T4 can all be turned off. This allows the low-potential input signal provided by the input terminal IN to be simultaneously transmitted to the first sub-node N11 and the second sub-node N12 via the turned-on first transistor T1 and fifth transistor T5, controlling the potentials of the first sub-node N11 and the second sub-node N12 to remain low. Furthermore, the low-potential first clock signal provided by the first clock terminal CK can be transmitted to the second node N2 via the turned-on sixth transistor T6, controlling the potential of the second node N2 to be low. And because the fourth transistor T4 is turned off, the potential of the second sub-node N12 can be maintained at the low potential of the previous stage. Correspondingly, the second transistor T2, the seventh transistor T7, the tenth transistor T10, and the eleventh transistor T11 can all be turned on. This allows the low-level first clock signal to be transmitted to the second node N2 via the turned-on seventh transistor T7, ensuring the reliable turn-on of the second transistor T2 and the eleventh transistor T11. Furthermore, the high-level first power signal provided by the first power supply terminal V1 can be transmitted to the third node N3 via the turned-on second transistor T2, controlling the potential of the third node N3 to be high. This allows the high-level second clock signal to be transmitted to the output terminal OUT via the turned-on tenth transistor T10, and the high-level second power signal provided by the second power supply terminal V2 to be transmitted to the output terminal OUT via the turned-on eleventh transistor T11. That is, in this stage t03, a high-level display drive signal can be output via the output terminal OUT.

[0201] It is understandable that when the input signal provided by the input terminal IN (e.g., STV) is continuously at a low potential, the above-mentioned t01 to t03 stages can occur periodically with the potential changes of the first clock signal and the second clock signal.

[0202] After the input signal provided at the input terminal IN (e.g., STV) changes from a low potential to a high potential:

[0203] In stage t04, the potential of the first clock signal provided by the first clock terminal CK is high, and the potential of the second clock signal provided by the second clock terminal CB is low. Accordingly, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 can all be turned off, and the third transistor T3 and the fourth transistor T4 can both be turned on. Furthermore, in stage t05, the potentials of the first sub-node N11 and the second sub-node N12 can be maintained at the high potential of the previous stage. Accordingly, the seventh transistor T7 can be turned off. And, under the action of the third capacitor C3, the potential of the second node N2 can be maintained at a low potential. Accordingly, the second transistor T2 and the eleventh transistor T11 can both be turned on, and the tenth transistor T10 can be turned off. In this way, the high-potential first power supply signal can be transmitted to the third node N3 via the turned-on second transistor T2, then to the first child node N11 via the turned-on third transistor T3, and finally to the second child node N12 via the turned-on fourth transistor T4. This reliably controls the potential of the first child node N11 and the potential of the second child node N12 to remain high, ensuring that the tenth transistor T10 is reliably turned off. Furthermore, the high-potential second power supply signal provided by the second power supply terminal V2 can be transmitted to the output terminal OUT via the turned-on eleventh transistor T11. That is, in this stage t04, a high-potential display drive signal can continue to be output via the output terminal OUT.

[0204] In stage t05, the potential of the first clock signal provided by the first clock terminal CK changes from high to low, and the potential of the second clock signal provided by the second clock terminal CB changes from low to high. Correspondingly, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 can all be turned on, while the third transistor T3 and the fourth transistor T4 can both be turned off. This allows the high-potential input signal provided by the input terminal IN to be simultaneously transmitted to the first sub-node N11 and the second sub-node N12 via the turned-on first transistor T1 and fifth transistor T5, controlling the potentials of both sub-node N11 and N12 to be high. Furthermore, the low-potential first clock signal provided by the first clock terminal CK can be transmitted to the second node N2 via the turned-on sixth transistor T6, controlling the potential of the second node N2 to be low. Correspondingly, the second transistor T2 and the eleventh transistor T11 can both be turned on, while the seventh transistor T7 and the tenth transistor T10 can both be turned off. In this way, the high-potential first power signal provided by the first power supply terminal V1 can be transmitted to the third node N3 via the activated second transistor T2, controlling the potential of the third node N3 to be high, and the high-potential second clock signal can be transmitted to the output terminal OUT via the activated tenth transistor T10. That is, in this stage t05, a high-potential display drive signal can be output through the output terminal OUT.

[0205] It is understandable that when the input signal provided by the input terminal IN (e.g., STV) is continuously at a high potential, the above-mentioned t04 to t05 stages can occur periodically with the potential changes of the first clock signal and the second clock signal.

[0206] Optionally, Figure 25 not only shows the display drive signal output by the first-stage shift register unit through the output terminal OUT (marked as OUT1 in the figure), but also schematically shows the display drive signal output by the second-stage shift register unit through the output terminal OUT2 and the display drive signal output by the third-stage shift register unit through the output terminal OUT3.

[0207] Furthermore, referring to Figure 25, it can be seen that the first clock signal provided by the first clock terminal CK and the second clock signal provided by the second clock terminal CB differ by 1H, which is half a clock cycle. Additionally, each output terminal (e.g., OUT1) can output two low-level display drive signals, with a difference of 2H between the two low-level display drive signals, which is one clock cycle. It is understood that the phase intervals here are measured by the time interval between adjacent falling edges (i.e., the transition edge from high to low level) between signals. Also, the number of times the display drive signal output from each output terminal is at a low level is equal to the number of times the first clock signal is at a low level within the duration of the input signal provided by the input terminal IN (e.g., STV).

[0208] Furthermore, as shown in Figure 25, by using the first clock signal as the gate voltage of the fourth transistor T4, the characteristic offset of the fourth transistor T4 can be effectively improved, thereby ensuring reliable control of the potential of the second sub-node N12. This allows the tenth transistor T10 to reliably control the switching of the second clock terminal CB and the output terminal OUT in response to the potential of the second sub-node N12, and reliably output the display drive signal through the output terminal OUT, which is beneficial for maintaining circuit stability. In other words, the display drive signal output by the shift register unit provided in this embodiment does not have multipulse waveforms, i.e., there are no abnormal conditions, thus ensuring that the display panel can display a better effect.

[0209] Optionally, taking the structure shown in Figure 15 as an example, Figure 26 schematically shows a driving timing signal diagram of another shift register unit. The operation process of the shift register unit of this structure can be referred to the relevant description in Figure 25, and will not be repeated here. Furthermore, referring to Figure 26, it can also be seen that since the structure shown in Figure 15 uses the first clock signal as the gate voltage of the first transistor T1 and the fifth transistor T5, it can help improve the BTS of the first transistor T1 and the fifth transistor T5, reduce the characteristic offset of the first transistor T1 and the fifth transistor T5, and thus ensure reliable control of the potential of the second sub-node N12. This allows the tenth transistor T10 to reliably control the switching of the second clock terminal CB and the output terminal OUT in response to the potential of the second sub-node N12, and reliably output the display driving signal through the output terminal OUT, which is beneficial to maintaining circuit stability.

[0210] Optionally, taking the structure shown in Figure 17 as an example, Figure 27 schematically illustrates the driving timing signal diagram of another shift register unit. The operation process of the shift register unit of this structure can be referred to the relevant description in Figure 25, and will not be repeated here. Furthermore, referring to Figure 27, it can be seen that even if the characteristics of the seventh transistor T7 are offset, because other transistors can reliably control the node potential, the display driving signal output through any output terminal OUT (e.g., OUT1) will not exhibit multipulse waveforms, regardless of whether dvth = 0 or dvth = 4. That is, there is no abnormal situation, and thus the display effect of the display panel can still be ensured to be good. It can also be seen that the transistor characteristic offset margin provided by the embodiment of this application is larger, and the working reliability is higher.

[0211] Optionally, taking the structure shown in Figure 22 as an example, Figure 28 schematically illustrates the driving timing signal diagram of another shift register unit. The operation process of the shift register unit of this structure can be referred to the relevant description in Figure 25, and will not be repeated here. Furthermore, referring to Figure 28, it can also be seen that because two transistors, the seventh transistor T7 and the eighth transistor T8, are set to simultaneously control the potential of the fourth sub-node N22, the problem of potential instability of the fourth sub-node N22 caused by the characteristic offset of a single transistor can be solved. That is, the potential of the fourth sub-node N22 can be reliably controlled, so that the eleventh transistor T11 responds to the potential of the fourth sub-node N22 to reliably control the on / off state of the second power supply terminal V2 and the output terminal OUT, and the display driving signal is reliably output through the output terminal OUT, which is beneficial to maintaining circuit stability.

[0212] It is understood that the operation of other shift register units is similar and will not be described in detail here. Furthermore, since the driving method of this shift register unit can have essentially the same technical effect as the shift register unit described in the previous embodiments, for the sake of brevity, the technical effect of the driving method of the shift register unit will not be described again here.

[0213] This application also provides a display driving circuit. As shown in FIG29, the display driving circuit includes: a plurality of cascaded shift register units (i.e., GOA units) as shown in any of FIG1 to FIG22.

[0214] For example, referring to Figure 29, in the display driver circuit shown therein, every two adjacent GOA units are cascaded together through the output terminal OUT and the input terminal IN.

[0215] It is understood that since the display driving circuit can have essentially the same technical effect as the shift register unit described in the previous embodiment, the technical effect of the gate driving circuit will not be repeated here for the sake of brevity.

[0216] This application also provides a display device. As shown in FIG30, the display device includes a display panel 10 and a display driving circuit 00 as shown in FIG29. The display panel 10 includes a plurality of pixels (not shown in the figure).

[0217] The display driver circuit 00 is connected to multiple pixels via its output terminal and is used to transmit display driver signals to the multiple pixels to drive them to emit light.

[0218] Optionally, referring to FIG29, the display driving circuit 00 can be, for example, a gate driving circuit. Each GOA unit in the display driving circuit 00 can be connected to the pixel via the gate line through the output terminal OUT to transmit the required gate driving signal to the pixel.

[0219] Optionally, the display device described in this application embodiment can be any product or component with display function, such as an organic light-emitting diode (OLED) display device or an active matrix organic light-emitting diode (AMOLED) display device. Furthermore, the display device can be any suitable display device, including but not limited to mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and e-books, etc., any product or component with display function.

[0220] Furthermore, it is understood that since the display device can have essentially the same technical effect as the gate drive circuit described in the previous embodiments, the technical effect of the display device will not be repeated here for the sake of brevity.

[0221] It should be noted that the terminology used in the embodiments of this application is for illustrative purposes only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in the implementation of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains.

[0222] For example, the terms "first," "second," or "third," and similar words used in the patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "an" or "a," and similar words do not indicate a quantity limitation, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the element or object preceding "comprising" covers the element or object listed after "comprising" or "including," and does not exclude other elements or objects. "Above," "below," "left," or "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0223] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A shift register unit, the shift register unit comprising: The first input control circuit is connected to the first clock terminal, the input terminal, the second clock terminal, the first power supply terminal, the first node, and the second node, respectively, and is used to control the potential of the first node based on the first clock signal provided by the first clock terminal, the input signal provided by the input terminal, the second clock signal provided by the second clock terminal, the first power supply signal provided by the first power supply terminal, and the potential of the second node. The second input control circuit is connected to the first clock terminal, the first node, and the second node respectively, and is used to control the potential of the second node based on the first clock signal and the potential of the first node. The output circuit is connected to the first node, the second node, the second power supply terminal, the second clock terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal based on the potential of the first node and the potential of the second node, and to control the on / off state of the second clock terminal and the output terminal, so as to output a display drive signal through the output terminal.

2. The shift register unit according to claim 1, wherein, The first input control circuit includes: The first input control sub-circuit is connected to the first clock terminal, the input terminal, and the first node respectively, and is used to control the on / off state of the input terminal and the first node in response to the first clock signal, so as to control the potential of the first node; The second input control sub-circuit is connected to the second clock terminal, the first power supply terminal, the second node, and the first node, respectively, and is used to control the on / off state of the first power supply terminal and the first node in response to the second clock signal and the potential of the second node, so as to control the potential of the first node.

3. The shift register unit according to claim 2, wherein, The first input control circuit includes a first transistor; the second input control sub-circuit includes a second transistor and a third transistor. The gate of the first transistor is connected to the first clock terminal, the first electrode of the first transistor is connected to the input terminal, and the second electrode of the first transistor is connected to the first node. The gate of the second transistor is connected to the second node, the first terminal of the second transistor is connected to the first power supply terminal, the second terminal of the second transistor is connected to the first terminal of the third transistor, the gate of the third transistor is connected to the second clock terminal, and the second terminal of the third transistor is connected to the first node.

4. The shift register unit according to claim 2 or 3, wherein, The first node includes: a first child node and a second child node; the shift register unit further includes: The third input control circuit is connected to the input control terminal, the first sub-node, and the second sub-node respectively, and is used to control the on / off state of the first sub-node and the second sub-node in response to the control signal provided by the input control terminal. And / or, a fourth input control circuit, connected to the first clock terminal, the input terminal and the second sub-node respectively, and used to control the on / off state of the input terminal and the second sub-node in response to the first clock signal; Furthermore, both the first input control sub-circuit and the second input control circuit are connected to the first sub-node; the output circuit is connected to the second sub-node; when the third input control circuit is included, the second input control sub-circuit is connected to either the first sub-node or the second sub-node; when the third input control circuit is not included, the second input control sub-circuit is connected to the second sub-node.

5. The shift register unit according to claim 4, wherein, When the fourth input control circuit is included, the input control terminal is shared with the first clock terminal or the second clock terminal; when the fourth input control circuit is not included, the input control terminal is shared with the first clock terminal; or, the input control terminal is a third power supply terminal.

6. The shift register unit according to claim 4 or 5, wherein, The third input control circuit includes: a fourth transistor; The gate of the fourth transistor is connected to the input control terminal, the first electrode of the fourth transistor is connected to the first sub-node, and the second electrode of the fourth transistor is connected to the second sub-node.

7. The shift register unit according to any one of claims 4 to 6, wherein, The fourth input control circuit includes: a fifth transistor; The gate of the fifth transistor is connected to the first clock terminal, the first terminal of the fifth transistor is connected to the input terminal, and the second terminal of the fifth transistor is connected to the second child node.

8. The shift register unit according to any one of claims 4 to 7, wherein, The shift register unit further includes: A potential adjustment circuit is connected to both the potential adjustment terminal and the first sub-node, and is used to adjust the potential of the first sub-node based on the adjustment signal provided by the potential adjustment terminal.

9. The shift register unit according to claim 8, wherein, The potential adjustment terminal is shared with the first power supply terminal or the first clock terminal, or the potential adjustment terminal is a third power supply terminal.

10. The shift register unit according to claim 8 or 9, wherein, The potential adjustment circuit includes: a first capacitor; The first capacitor is connected between the potential adjustment terminal and the first sub-node.

11. The shift register unit according to any one of claims 1 to 10, wherein, The second input control circuit includes: The third input control sub-circuit is connected to the first clock terminal, the target signal terminal, and the second node respectively, and is used to control the on / off state of the target signal terminal and the second node in response to the first clock signal, so as to control the potential of the second node; wherein, the target signal terminal is shared with the first clock terminal or is a third power supply terminal; The fourth input control sub-circuit is connected to the first node, the first clock terminal, and the second node respectively, and is used to control the on / off state of the first clock terminal and the second node in response to the potential of the first node, so as to control the potential of the second node.

12. The shift register unit according to claim 11, wherein, The third input control sub-circuit includes a sixth transistor; the fourth input control sub-circuit includes a seventh transistor. The gate of the sixth transistor is connected to the first clock terminal, the first terminal of the sixth transistor is connected to the target signal terminal, and the second terminal of the sixth transistor is connected to the second node; The gate of the seventh transistor is connected to the first node, the first terminal of the seventh transistor is connected to the first clock terminal, and the second terminal of the seventh transistor is connected to the second node.

13. The shift register unit according to claim 11 or 12, wherein, The second node includes: a third child node and a fourth child node; the shift register unit further includes: The fifth input control circuit is connected to the first node, the third sub-node, and the fourth sub-node respectively, and is used to control the on / off state of the third sub-node and the fourth sub-node in response to the potential of the first node. The sixth input control circuit is connected to the first clock terminal, the target signal terminal and the fourth sub-node respectively, and is used to control the on / off state of the target signal terminal and the fourth sub-node in response to the first clock signal; Furthermore, both the third input control sub-circuit and the fourth input control sub-circuit are connected to the third sub-node, and both the output circuit and the first input control circuit are connected to the fourth sub-node.

14. The shift register unit according to claim 13, wherein, The fifth input control circuit includes: an eighth transistor; The gate of the eighth transistor is connected to the first node, the first electrode of the eighth transistor is connected to the third child node, and the second electrode of the eighth transistor is connected to the fourth child node.

15. The shift register unit according to claim 13 or 14, wherein, The sixth input control circuit includes: a ninth transistor; The gate of the ninth transistor is connected to the first clock terminal, the first terminal of the ninth transistor is connected to the target signal terminal, and the second terminal of the ninth transistor is connected to the fourth child node.

16. The shift register unit according to any one of claims 1 to 15, wherein, The output circuit includes: The first output sub-circuit is connected to the first node, the second clock terminal and the output terminal respectively, and is used to control the on / off state of the second clock terminal and the output terminal in response to the potential of the first node, so as to output the second clock signal as a display driving signal through the output terminal, and is also used to adjust the potential of the first node based on the display driving signal output through the output terminal. The second output sub-circuit is connected to the second node, the second power supply terminal, and the output terminal respectively, and is used to control the on / off state of the second power supply terminal and the output terminal in response to the potential of the second node, so as to output the second power supply signal provided by the second power supply terminal as a display driving signal through the output terminal, and is also used to adjust the potential of the second node based on the second power supply signal.

17. The shift register unit according to claim 16, wherein, The first output sub-circuit includes: a tenth transistor and a second capacitor; the second output sub-circuit includes: an eleventh transistor and a third capacitor; The gate of the tenth transistor is connected to the first node, the first terminal of the tenth transistor is connected to the second clock terminal, and the second terminal of the tenth transistor is connected to the output terminal. The second capacitor is connected between the output terminal and the first node; The gate of the eleventh transistor is connected to the second node, the first terminal of the eleventh transistor is connected to the second power supply terminal, and the second terminal of the eleventh transistor is connected to the output terminal. The third capacitor is connected between the second power supply terminal and the second node.

18. A method for driving a shift register unit, used to drive a shift register unit as described in any one of claims 1 to 17; the method comprising: In the first stage, the potential of the first clock signal provided by the first clock terminal is the first potential, the potential of the second clock signal provided by the second clock terminal and the potential of the input signal provided by the input terminal are both the second potential. The first input control circuit controls the potential of the first node to be the first potential based on the received first clock signal, input signal, second clock signal, first power signal with the second potential provided by the first power terminal and the potential of the second node. The second input control circuit controls the potential of the second node to be the first potential based on the received first clock signal and the potential of the first node. The output circuit controls the second power terminal and the second clock terminal to be connected to the output terminal based on the potentials of the first node and the second node. In the second stage, the potential of the second clock signal provided by the second clock terminal is the first potential, and the potential of the first clock signal provided by the first clock terminal and the potential of the input signal provided by the input terminal are both the second potential. The first input control circuit controls the potential of the first node to be the first potential based on the received first clock signal, input signal, second clock signal, first power signal and the potential of the second node. The second input control circuit controls the potential of the second node to be the second potential based on the received first clock signal and the potential of the first node. The output circuit controls the second clock terminal to be connected to the output terminal based on the potentials of the first node and the second node.

19. A display driving circuit, the display driving circuit comprising: A cascaded plurality of shift register units as described in any one of claims 1 to 17.

20. A display device, the display device comprising: The display panel, and the display driving circuit as described in claim 19; The display panel includes multiple pixels; The display driving circuit is connected to the plurality of pixels via its output terminal and is used to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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