Display substrate and display device

Abstract

A display substrate and a display device, in the display substrate, a gate of a first output control transistor (T8) is coupled with a first level signal line (VGL), a first electrode of the first output control transistor (T8) is coupled with a first input node (N1), and a second electrode of the first output control transistor (T8) is coupled with a first output node (N4); a gate of a second output control transistor (T10) is coupled with a gate driving signal output end (Gout(n+1)) of a next stage shift register unit adjacent to the shift register unit, a first electrode of the second output control transistor (T10) is coupled with the first level signal line (VGL), and a second electrode of the second output control transistor (T10) is coupled with a second output node (N2); a projection of the first output control transistor (T8) on a substrate and a projection of the second output control transistor (T10) on the substrate are both located on the same side of a projection of the first level signal line (VGL) on the substrate.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] Currently, the development of display products is characterized by high integration and low cost. A crucial technology employed in display products is the mass production of GOA (Gate Driver on Array) technology. GOA technology integrates the gate driver circuit onto the array substrate of the display panel, thus eliminating the need for the gate driver integrated circuit itself, thereby reducing product costs in terms of both materials and manufacturing processes. This gate driver circuit integrated onto the array substrate using GOA technology is also called a GOA circuit or shift register circuit, where each shift register circuit within the gate driver circuit is also called a shift register unit. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display substrate and a display device.

[0004] To achieve the above objectives, this disclosure provides the following technical solution:

[0005] A first aspect of this disclosure provides a display substrate, comprising: a substrate, and a first level signal line and a gate driving circuit disposed on the substrate; the gate driving circuit includes a plurality of cascaded shift register units, each shift register unit including: a first input node, a first output node, a second output node, a first output control transistor, and a second output control transistor;

[0006] The gate of the first output control transistor is coupled to the first level signal line, the first terminal of the first output control transistor is coupled to the first input node, and the second terminal of the first output control transistor is coupled to the first output node; the gate of the second output control transistor is coupled to the gate drive signal output terminal of the next-level shift register unit adjacent to its own shift register unit, the first terminal of the second output control transistor is coupled to the first level signal line, and the second terminal of the second output control transistor is coupled to the second output node.

[0007] The orthographic projections of the first output control transistor and the second output control transistor on the substrate are both located on the same side of the orthographic projection of the first level signal line on the substrate.

[0008] Optionally, the orthographic projection of the first output control transistor on the substrate and the orthographic projection of the second output control transistor on the substrate are arranged along the first direction.

[0009] Optionally, the active layer of the first output control transistor extends along the first direction; the gate of the first output control transistor extends along a second direction, which intersects with the first direction; one end of the gate of the first output control transistor near the first level signal line is coupled to the first level signal line; and the orthographic projection of the gate of the first output control transistor on the substrate overlaps with the orthographic projection of the active layer of the first output control transistor on the substrate.

[0010] Optionally, the active layer of the second output control transistor extends along a second direction, which intersects with the first direction; the end of the active layer of the second output control transistor near the first level signal line is coupled to the first level signal line.

[0011] The gate of the second output control transistor includes at least a portion extending along the first direction, and the orthographic projection of the gate of the second output control transistor on the substrate overlaps with the orthographic projection portion of the active layer included in the second output control transistor on the substrate.

[0012] Optionally, the display substrate further includes a first clock signal input terminal and a second level signal line; the shift register unit further includes a first output transistor and a second output transistor; the gate of the first output transistor is coupled to the first output node, the first terminal of the first output transistor is coupled to the first clock signal input terminal, and the second terminal of the first output transistor is coupled to the gate drive signal output terminal of its respective shift register unit; the gate of the second output transistor is coupled to the second output node, the first terminal of the second output transistor is coupled to the second level signal line, and the second terminal of the second output transistor is coupled to the gate drive signal output terminal of its respective shift register unit;

[0013] The orthographic projection of the active layer of the first output control transistor on the substrate is located between the orthographic projection of the active layer of the first output transistor on the substrate and the orthographic projection of the first level signal line on the substrate.

[0014] The orthographic projection of the active layer of the second output control transistor onto the substrate is located between the orthographic projection of the active layer of the second output transistor onto the substrate and the orthographic projection of the first level signal line onto the substrate.

[0015] Optionally, the shift register unit further includes a first capacitor, the first plate of the first capacitor being coupled to the gate of the first output transistor, and the second plate of the first capacitor being coupled to the second terminal of the first output transistor.

[0016] The orthographic projection of the second plate of the first capacitor onto the substrate is located between the orthographic projection of the active layer of the first output transistor onto the substrate and the orthographic projection of the first level signal line onto the substrate.

[0017] Optionally, the orthographic projection of the active layer of the first output control transistor on the substrate is located between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first level signal line on the substrate.

[0018] Optionally, the first electrode of the first capacitor includes a first electrode body portion and a first electrode protrusion portion coupled together. The first electrode body portion extends along the first direction, and the second electrode of the first capacitor extends along the first direction. The orthographic projection of the first electrode body portion on the substrate and the orthographic projection of the second electrode of the first capacitor on the substrate at least partially overlap.

[0019] The first electrode protrusion protrudes from the first electrode body in a second direction, and the first electrode protrusion is coupled to the second electrode of the first output control transistor.

[0020] Optionally, the shift register unit further includes a first capacitor, the first plate of the first capacitor being coupled to the gate of the first output transistor, and the second plate of the first capacitor being coupled to the second terminal of the first output transistor; the shift register unit further includes a first conductive connection portion, the first end of the first conductive connection portion being coupled to the gate of the second output control transistor, and the second end of the first conductive connection portion being coupled to the second plate of the first capacitor in the next-level shift register unit adjacent to its own shift register unit; at least a portion of the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate are arranged along the first direction.

[0021] Optionally, the shift register unit further includes a second capacitor, the first plate of the second capacitor being coupled to the gate of the second output transistor, and the second plate of the second capacitor being coupled to the second level signal line;

[0022] The shift register unit further includes a third capacitor and a second input transistor. The first plate of the third capacitor is coupled to the gate of the second input transistor, and the second plate of the third capacitor is coupled to the first clock signal input terminal. The first terminal of the second input transistor is coupled to the first clock signal input terminal, and the second terminal of the second input transistor is coupled to the second output node.

[0023] The second plate of the third capacitor is arranged along the first direction with the second plate of the second capacitor.

[0024] The orthographic projection of the active layer of the second input transistor onto the substrate is located between the orthographic projection of the second plate of the third capacitor onto the substrate and the orthographic projection of the second plate of the second capacitor onto the substrate.

[0025] Optionally, the first plate of the third capacitor and the gate of the second input transistor are formed as an integral structure.

[0026] Optionally, the second plate of the third capacitor includes a main body portion, the edge of which has a first notch;

[0027] The first plate of the third capacitor includes a first part and a second part, the second part being coupled to the second electrode of the fourth control transistor in the shift register unit; the orthographic projection of the first part on the substrate overlaps with the orthographic projection of the main body of the second plate of the third capacitor on the substrate, and the orthographic projection of the second part on the substrate at least partially overlaps with the orthographic projection of the first notch on the substrate.

[0028] Optionally, the second plate of the second capacitor includes a main body portion, the edge of which has a second notch;

[0029] The first electrode of the second capacitor includes a third part and a fourth part, the fourth part being coupled to the second electrode of the second input transistor; the orthographic projection of the third part on the substrate overlaps with the orthographic projection of the main body of the second electrode of the second capacitor on the substrate, and the orthographic projection of the fourth part on the substrate at least partially overlaps with the orthographic projection of the second notch on the substrate.

[0030] Optionally, the shift register unit further includes a third control transistor and a fourth control transistor; the gate of the third control transistor is coupled to the first input node, the first terminal of the third control transistor is coupled to the second level signal line, and the second terminal of the third control transistor is coupled to the second output node; the gate of the fourth control transistor is coupled to the first input node, the first terminal of the fourth control transistor is coupled to the second level signal line, and the second terminal of the fourth control transistor is coupled to the gate of the second input transistor.

[0031] The orthographic projection of the active layer of the third control transistor onto the substrate lies between the orthographic projection of the second plate of the third capacitor onto the substrate and the orthographic projection of the second plate of the second capacitor onto the substrate; and / or

[0032] The orthographic projection of the active layer of the fourth control transistor on the substrate is located between the orthographic projection of the second plate of the third capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate.

[0033] Optionally, the display substrate further includes a second clock signal input terminal; the shift register unit further includes a first input transistor, a first control transistor, and a second control transistor;

[0034] The gate of the first input transistor is coupled to the second clock signal input terminal, the first terminal of the first input transistor is coupled to the start signal input terminal, and the second terminal of the first input transistor is coupled to the first input node;

[0035] The gate of the first control transistor is coupled to the second output node, the first terminal of the first control transistor is coupled to the second level signal line, and the second terminal of the first control transistor is coupled to the first terminal of the second control transistor; the gate of the second control transistor is coupled to the first clock signal input terminal, and the second terminal of the second control transistor is coupled to the first input node.

[0036] The active layer of the first input transistor, the active layer of the second control transistor, and the active layer of the first control transistor are arranged along the first direction.

[0037] Optionally, the display substrate further includes a frame start signal line, a first clock signal line, and a second clock signal line; the frame start signal line, the first clock signal line, the second clock signal line, the second level signal line, and the first level signal line are arranged sequentially along a second direction;

[0038] In the cascaded multiple shift register units, the first terminal of the first input transistor in the first-stage shift register unit is coupled to the frame start signal line, and the first terminal of the first input transistor in the (n+1)th-stage shift register unit is coupled to the gate drive signal output terminal of the nth-stage shift register unit; n is an integer greater than or equal to 1.

[0039] In one of the odd-level shift register units and the even-level shift register units, the first clock signal input terminal is coupled to the first clock signal line, and the second clock signal input terminal is coupled to the second clock signal line.

[0040] In another shift register unit among the odd-level shift register units and the even-level shift register units, the first clock signal input terminal is coupled to the second clock signal line, and the second clock signal input terminal is coupled to the first clock signal line.

[0041] Optionally, the orthographic projections of all transistors in the shift register unit onto the substrate are located between the orthographic projections of the second level signal line onto the substrate and the orthographic projections of the first level signal line onto the substrate.

[0042] Optionally, the first clock signal line includes two stacked first signal transmission layers; the second clock signal line includes two stacked second signal transmission layers.

[0043] Optionally, the shift register unit further includes a first capacitor, the first plate of the first capacitor being coupled to the gate of the first output transistor, and the second plate of the first capacitor being coupled to the second terminal of the first output transistor.

[0044] The orthographic projection of the active layer of the first output transistor on the substrate is located between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first level signal line on the substrate.

[0045] Optionally, the shift register unit further includes a second capacitor, the first plate of the second capacitor being coupled to the gate of the second output transistor, and the second plate of the second capacitor being coupled to the second level signal line;

[0046] The second electrode of the second capacitor includes a second electrode body portion and a second electrode connecting portion coupled together. The orthographic projection of the second electrode body portion on the substrate overlaps at least partially with the orthographic projection of the first electrode of the second capacitor on the substrate. The second electrode connecting portion is coupled to the second level signal line.

[0047] At least a portion of the orthographic projection of the second electrode body onto the substrate is located between the orthographic projection of the active layer of the first output transistor onto the substrate and the orthographic projection of the first level signal line onto the substrate.

[0048] Optionally, the orthographic projection of the active layer of the first output control transistor on the substrate, the orthographic projection of the second plate body of the second capacitor on the substrate, and the orthographic projection of the active layer of the second output control transistor on the substrate are arranged sequentially along the first direction.

[0049] Optionally, the shift register unit further includes a first conductive connection portion, a first end of which is coupled to the gate of the second output control transistor, and a second end of which is coupled to the second terminal of the first output transistor in the next-level shift register unit adjacent to its own shift register unit; at least a portion of the orthographic projection of the first conductive connection portion on the substrate is aligned with the orthographic projection of the active layer of the second output transistor on the substrate along the first direction.

[0050] Based on the above-described display substrate technical solution, a second aspect of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0051] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0052] Figure 1 is a circuit schematic diagram of the shift register unit provided in an embodiment of this disclosure;

[0053] Figure 2 is a schematic cross-sectional view of the film layer of the display substrate provided in the embodiment of this disclosure;

[0054] Figure 3 is a timing diagram of the shift register unit provided in an embodiment of this disclosure;

[0055] Figure 4 is a schematic diagram of the layout of the active layer in two shift register units provided in an embodiment of this disclosure;

[0056] Figure 5 is a schematic diagram of the layout of the first gate metal layer in two shift register units provided in an embodiment of this disclosure;

[0057] Figure 6 is a schematic diagram of the layout of the second gate metal layer in two shift register units provided in an embodiment of this disclosure;

[0058] Figure 7 is a schematic diagram of the layout of the active layer, the first gate metal layer and the second gate metal layer in two shift register units provided in an embodiment of this disclosure;

[0059] Figure 8 is a schematic diagram of the layout of the first source-drain metal layer in two shift register units provided in the embodiments of this disclosure;

[0060] Figure 9 is a schematic diagram of the layout with the first source / drain metal layer added based on Figure 7;

[0061] Figure 10 is a schematic diagram of another layout of the active layer in the shift register unit provided in the embodiment of this disclosure;

[0062] Figure 11 is a schematic diagram of another layout of the first gate metal layer in the shift register unit provided in the embodiment of this disclosure;

[0063] Figure 12 is a schematic diagram of another layout of the second gate metal layer in the shift register unit provided in the embodiment of this disclosure;

[0064] Figure 13 is a schematic diagram of another layout of the first source-drain metal layer in the shift register unit provided in the embodiment of this disclosure;

[0065] Figure 14 is a schematic diagram of another layout of the shift register unit provided in this embodiment of the present disclosure, which includes a source layer, a first gate metal layer, a second gate metal layer and a first source-drain metal layer.

[0066] Figure 15 is a schematic diagram of another layout of the shift register unit provided in the embodiment of this disclosure, which includes a source layer, a first gate metal layer, a second gate metal layer, and a first source-drain metal layer.

[0067] Figure 16 is a simulation waveform of the gate drive signal output from the gate drive signal output terminal of the shift register unit in the related technology.

[0068] Figure 17 is a simulation waveform diagram of the gate drive signal output from the gate drive signal output terminal of the shift register unit provided in the embodiment of this disclosure. Detailed Implementation

[0069] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0070] Currently, when laying out gate drive circuits in display products, shift register units occupy a large layout space, affecting the bezel width of the display products; therefore, how to effectively narrow the bezel width of display products has become an urgent technical problem to be solved.

[0071] Please refer to Figures 1, 4 to 15. This disclosure provides a display substrate, including: a substrate, and a first level signal line VGL and a gate driving circuit disposed on the substrate; the gate driving circuit includes a plurality of cascaded shift register units 10, each shift register unit 10 including: a first input node N1, a first output node N4, a second output node N2, a first output control transistor T8, and a second output control transistor T10;

[0072] The gate 48 of the first output control transistor T8 is coupled to the first level signal line VGL, the first terminal of the first output control transistor T8 is coupled to the first input node N1, and the second terminal of the first output control transistor T8 is coupled to the first output node N4; the gate 410 of the second output control transistor T10 is coupled to the gate drive signal output terminal of the next-level shift register unit 10 adjacent to its own shift register unit 10, the first terminal of the second output control transistor T10 is coupled to the first level signal line VGL, and the second terminal of the second output control transistor T10 is coupled to the second output node N2;

[0073] The orthographic projection of the first output control transistor T8 on the substrate and the orthographic projection of the second output control transistor T10 on the substrate are both located on the same side of the orthographic projection of the first level signal line VGL on the substrate.

[0074] For example, the display substrate includes a display area and a peripheral area surrounding the display area. The display area includes a plurality of sub-pixels, and the peripheral area includes the gate driving circuit. The gate driving circuit includes a plurality of cascaded shift register units 10, and the shift register units 10 are used to provide gate driving signals to the corresponding sub-pixels.

[0075] For example, the display substrate further includes a first level signal line VGL located in the peripheral area. The first level signal line VGL is used to transmit a first level signal, which includes, but is not limited to, a low level signal.

[0076] For example, the specific structure of the shift register unit 10 can vary, such as using a 10T3C structure (i.e., including 10 transistors and 1 capacitor), but it is not limited to this. The following describes the specific structure of the shift register unit 10 in detail, taking the 10T3C structure as an example.

[0077] As shown in Figure 1, the shift register unit 10 includes a first output control transistor T8, a second output control transistor T10, a first output transistor T5, a second output transistor T4, a first input transistor T1, a second input transistor T3, a first control transistor T6, a second control transistor T9, a third control transistor T2, a fourth control transistor T7, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first input node N1, a second input node N3, a first output node N4, and a second output node N2.

[0078] The gate 48 of the first output control transistor T8 is coupled to the first level signal line VGL, the first terminal of the first output control transistor T8 is coupled to the first input node N1, and the second terminal of the first output control transistor T8 is coupled to the first output node N4.

[0079] The gate 410 of the second output control transistor T10 is coupled to the gate drive signal output terminal Gout(n+1) of the next-level shift register unit 10 adjacent to its corresponding shift register unit 10. The first terminal of the second output control transistor T10 is coupled to the first level signal line VGL. The second terminal of the second output control transistor T10 is coupled to the second output node N2.

[0080] The gate 45 of the first output transistor T5 is coupled to the first output node N4, the first terminal of the first output transistor T5 is coupled to the first clock signal input terminal CB, and the second terminal of the first output transistor T5 is coupled to the gate drive signal output terminal Gout(n) of the shift register unit 10 to which it belongs.

[0081] The gate 44 of the second output transistor T4 is coupled to the second output node N2, the first terminal of the second output transistor T4 is coupled to the second level signal line VGH, and the second terminal of the second output transistor T4 is coupled to the gate drive signal output terminal of its corresponding shift register unit 10.

[0082] The first plate C11 of the first capacitor C1 is coupled to the gate 45 of the first output transistor T5, and the second plate C12 of the first capacitor C1 is coupled to the second plate of the first output transistor T5.

[0083] The first plate C21 of the second capacitor C2 is coupled to the gate 44 of the second output transistor T4, and the second plate C22 of the second capacitor C2 is coupled to the second level signal line VGH.

[0084] The first plate C31 of the third capacitor C3 is coupled to the gate 43 (i.e., the second input node N3) of the second input transistor T3, and the second plate C32 of the third capacitor C3 is coupled to the first clock signal input terminal CB.

[0085] The gate 41 of the first input transistor T1 is coupled to the second clock signal input terminal CK. The first terminal of the first input transistor T1 is coupled to the frame start signal line STV, or coupled to the gate drive signal output terminal Gout(n-1) of the previous level shift register unit 10 adjacent to its own shift register unit 10. The second terminal of the first input transistor T1 is coupled to the first input node N1.

[0086] The first terminal of the second input transistor T3 is coupled to the first clock signal input terminal CB, and the second terminal of the second input transistor T3 is coupled to the second output node N2;

[0087] The gate 46 of the first control transistor T6 is coupled to the second output node N2, the first terminal of the first control transistor T6 is coupled to the second level signal line VGH, and the second terminal of the first control transistor T6 is coupled to the first terminal of the second control transistor T9.

[0088] The gate 49 of the second control transistor T9 is coupled to the first clock signal input terminal CB, and the second terminal of the second control transistor T9 is coupled to the first input node N1;

[0089] The gate 42 of the third control transistor T2 is coupled to the first input node N1, the first terminal of the third control transistor T2 is coupled to the second level signal line VGH, and the second terminal of the third control transistor T2 is coupled to the second output node N2.

[0090] The gate 47 of the fourth control transistor T7 is coupled to the first input node N1, the first terminal of the fourth control transistor T7 is coupled to the second level signal line VGH, and the second terminal of the fourth control transistor T7 is coupled to the gate 43 of the second input transistor T3.

[0091] In the aforementioned shift register unit 10, by adding a second output control transistor T10, when the next-stage shift register unit 10 outputs (i.e., during period P3), the potential of the second output node N2 is pulled down in a timely manner, making the potential of the second output node N2 low. This controls the second output transistor T4 to turn on, outputting the second-level signal transmitted by the second-level signal line VGH to the gate drive signal output terminal of the current-stage shift register unit 10. This control method can effectively improve the situation where the first output node N4 and the second output node N2 are simultaneously in a floating state, improve the floating problem of the gate drive signal output terminal of the current-stage shift register unit 10, and enhance the stability of the gate drive signal output terminal of the shift register unit 10.

[0092] For example, the first level signal line VGL extends along a first direction, and the orthographic projection of the first output control transistor T8 on the substrate and the orthographic projection of the second output control transistor T10 on the substrate are both located on the same side of the orthographic projection of the first level signal line VGL on the substrate along a second direction, and the second direction intersects with the first direction.

[0093] For example, the orthographic projections of the first output control transistor T8 and the second output control transistor T10 on the substrate are both adjacent to the orthographic projection of the first level signal line VGL on the substrate; that is, no other structure is provided between the orthographic projection of the first output control transistor T8 on the substrate and the orthographic projection of the first level signal line VGL on the substrate; no other structure is provided between the orthographic projection of the second output control transistor T10 on the substrate and the orthographic projection of the first level signal line VGL on the substrate.

[0094] As can be seen from the structure of the display substrate described above, in the display substrate provided in this embodiment, the gate 48 of the first output control transistor T8 and the first electrode of the second output control transistor T10 are both coupled to the first level signal line VGL. By setting the orthographic projection of the first output control transistor T8 on the substrate and the orthographic projection of the second output control transistor T10 on the substrate to be located on the same side of the orthographic projection of the first level signal line VGL on the substrate, it is possible not only to ensure the reliability of the connection between the first output control transistor T8 and the second output control transistor T10 and the first level signal line VGL, but also to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, thereby effectively narrowing the bezel width of the display substrate.

[0095] More specifically, in the display substrate provided in the embodiments of this disclosure, by optimizing the layout of the first level signal line VGL, the first output control transistor T8 and the second output control transistor T10, the layout space occupied by the shift register unit 10 can be narrowed by more than 15 micrometers along the second direction.

[0096] As shown in Figures 9 and 14, in some embodiments, the orthographic projection of the first output control transistor T8 on the substrate is arranged along the first direction with the orthographic projection of the second output control transistor T10 on the substrate.

[0097] For example, the orthographic projection of the gate 48 of the first output control transistor T8 on the substrate and the orthographic projection of the gate 410 of the second output control transistor T10 on the substrate are arranged along the first direction.

[0098] For example, the orthographic projection of the active layer 38 of the first output control transistor T8 on the substrate and the orthographic projection of the active layer 310 of the second output control transistor T10 on the substrate are arranged along the first direction.

[0099] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, thereby effectively narrowing the bezel width of the display substrate.

[0100] As shown in Figures 4 to 14, in some embodiments, the active layer 38 of the first output control transistor T8 extends along the first direction; the gate 48 of the first output control transistor T8 extends along a second direction, which intersects with the first direction; one end of the gate 48 of the first output control transistor T8 near the first level signal line VGL is coupled to the first level signal line VGL; the orthographic projection of the gate 48 of the first output control transistor T8 on the substrate overlaps with the orthographic projection portion of the active layer 38 of the first output control transistor T8 on the substrate.

[0101] The above configuration can minimize the overall layout space occupied by the first output control transistor T8 while ensuring that the gate 48 of the first output control transistor T8 is coupled to the first level signal line VGL.

[0102] As shown in Figures 4 to 14, in some embodiments, the active layer 310 of the second output control transistor T10 extends along a second direction, which intersects with the first direction; one end of the active layer of the second output control transistor T10 near the first level signal line VGL is coupled to the first level signal line VGL; the gate 410 of the second output control transistor T10 includes at least a portion extending along the first direction, and the orthographic projection of the gate 410 of the second output control transistor T10 on the substrate overlaps with the orthographic projection portion of the active layer 310 of the second output control transistor T10 on the substrate.

[0103] The above configuration can minimize the overall layout space occupied by the second output control transistor T10 while ensuring that the first terminal of the second output control transistor T10 is coupled to the first level signal line VGL.

[0104] As shown in Figures 4 to 14, in some embodiments, the display substrate further includes a first clock signal input terminal CB and a second level signal line VGH; the shift register unit 10 further includes a first output transistor T5 and a second output transistor T4; the gate 45 of the first output transistor T5 is coupled to the first output node N4, the first terminal of the first output transistor T5 is coupled to the first clock signal input terminal CB, and the second terminal of the first output transistor T5 is coupled to the gate drive signal output terminal of its corresponding shift register unit 10; the gate 44 of the second output transistor T4 is coupled to the second output node N2, the first terminal of the second output transistor T4 is coupled to the second level signal line VGH, and the second terminal of the second output transistor T4 is coupled to the gate drive signal output terminal of its corresponding shift register unit 10;

[0105] The orthographic projection of the active layer 38 of the first output control transistor T8 onto the substrate is located between the orthographic projection of the active layer 35 of the first output transistor T5 onto the substrate and the orthographic projection of the first level signal line VGL onto the substrate.

[0106] The orthographic projection of the active layer 310 of the second output control transistor T10 onto the substrate is located between the orthographic projection of the active layer 34 of the second output transistor T4 onto the substrate and the orthographic projection of the first level signal line VGL onto the substrate.

[0107] For example, the active layer 35 of the first output transistor T5 includes a plurality of first active patterns arranged sequentially along the second direction, and the orthographic projection of the active layer 38 of the first output control transistor T8 on the substrate is located between the orthographic projection of the plurality of first active patterns on the substrate and the orthographic projection of the first level signal line VGL on the substrate.

[0108] For example, the active layer 34 of the second output transistor T4 includes a plurality of second active patterns arranged sequentially along the second direction, and the orthographic projection of the active layer 310 of the second output control transistor T10 on the substrate is located between the orthographic projection of the plurality of second active patterns on the substrate and the orthographic projection of the first level signal line VGL on the substrate.

[0109] As shown in Figures 4 to 9, in some embodiments, the shift register unit 10 further includes a first capacitor C1. The first plate C11 of the first capacitor C1 is coupled to the gate 45 of the first output transistor T5, and the second plate C12 of the first capacitor C1 is coupled to the second terminal 54 of the first output transistor T5. The orthographic projection of the second plate C12 of the first capacitor C1 on the substrate is located between the orthographic projection of the active layer 35 of the first output transistor T5 on the substrate and the orthographic projection of the first level signal line VGL on the substrate.

[0110] For example, the first plate C11 of the first capacitor C1 is formed as an integral structure with the gate 45 of the first output transistor T5.

[0111] For example, the first plate C11 of the first capacitor C1 extends along the first direction, and the second plate C12 of the first capacitor C1 extends along the first direction. The orthographic projection of the second plate C12 of the first capacitor C1 on the substrate is located inside the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate.

[0112] Since the first plate C11 of the first capacitor C1, the second terminal of the first output control transistor T8, and the gate 45 of the first output transistor T5 are all connected together, the layout described above allows the first plate C11 of the first capacitor C1, the second terminal of the first output control transistor T8, and the gate 45 of the first output transistor T5 to be centrally located. This not only ensures the reliability of the connection and reduces the difficulty of connection, but also helps to further reduce the layout space occupied by the shift register unit 10.

[0113] As shown in Figures 4 to 9, in some embodiments, the orthographic projection of the active layer 38 of the first output control transistor T8 onto the substrate is located between the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate and the orthographic projection of the first level signal line VGL onto the substrate.

[0114] The above configuration helps to shorten the distance between the first output control transistor T8 and the first level signal line VGL. This not only ensures the reliability of the connection between the gate 48 of the first output control transistor T8 and the first level signal line VGL and reduces the difficulty of connection, but also helps to further reduce the layout space occupied by the shift register unit 10.

[0115] As shown in Figures 4 to 9, in some embodiments, the first electrode C11 of the first capacitor C1 includes a first electrode body C110 and a first electrode protrusion C111 coupled together. The first electrode body C110 extends along the first direction, and the second electrode C12 of the first capacitor C1 extends along the first direction. The orthographic projection of the first electrode body C110 on the substrate and the orthographic projection of the second electrode C12 of the first capacitor C1 on the substrate at least partially overlap. The first electrode protrusion C111 protrudes from the first electrode body C110 along the second direction and is coupled to the second electrode of the first output control transistor T8.

[0116] For example, the first electrode plate main body C110 and the first electrode plate protrusion C111 are formed as an integral structure.

[0117] For example, at least a portion of the orthographic projection of the first electrode protrusion C111 onto the substrate is aligned along a first direction with the orthographic projection of the active layer 38 of the first output control transistor T8 onto the substrate. For instance, the first electrode protrusion C111 is coupled to the second electrode of the first output control transistor T8 via a second conductive connection 22.

[0118] The above configuration not only ensures the reliability of the connection between the first plate C11 of the first capacitor C1 and the second electrode of the first output control transistor T8, but also further narrows the width of the layout space occupied by the shift register unit 10 while ensuring that the first plate C11 of the first capacitor C1 and the gate 48 of the first output control transistor T8 are kept at a suitable distance.

[0119] As shown in Figures 4 to 9, in some embodiments, the shift register unit further includes a first capacitor C1, the first plate C11 of the first capacitor C1 is coupled to the gate of the first output transistor T5, and the second plate C12 of the first capacitor C1 is coupled to the second plate of the first output transistor T5; the shift register unit 10 further includes a first conductive connection portion 21, the first end of the first conductive connection portion 21 is coupled to the gate 410 of the second output control transistor T10, and the second end of the first conductive connection portion 21 is coupled to the second plate C12 of the first capacitor C1 in the next-level shift register unit 10 adjacent to its own shift register unit 10; at least a portion of the orthographic projection of the first conductive connection portion 21 on the substrate and the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate are arranged along the first direction.

[0120] For example, the first conductive connection portion 21 is formed as an integral structure with the second pole 54 of the first output transistor T5 in the next-level shift register unit 10 adjacent to its corresponding shift register unit 10.

[0121] The above layout method is beneficial to shorten the distance between the gate 410 of the second output control transistor T10 and the second plate C12 of the first capacitor C1 in the next-level shift register unit 10 adjacent to its corresponding shift register unit 10, effectively shortening the length of the first conductive connection 21 and reducing the layout difficulty of the adjacent shift register units 10; at the same time, it is beneficial to reduce the width of the layout space occupied by the gate driving circuit along the first direction.

[0122] Furthermore, the above layout avoids overlap between the first conductive connection portion 21 and the functional structure 55 used to transmit the gate drive signal output by the current stage shift register unit. This prevents the gate drive signal output by the adjacent next-stage shift register unit from affecting the gate drive signal output by the current stage shift register unit, ensuring the stability of the gate drive signal output by the current stage shift register unit. Specifically, refer to Figures 16 and 17. In Figure 16, the waveform of the gate drive signal has glitches, while in Figure 17, the waveform of the gate drive signal is glitches-free and the signal waveform is stable.

[0123] As shown in Figures 4 to 9, in some embodiments, the shift register unit 10 further includes a second capacitor C2, the first plate C21 of the second capacitor C2 being coupled to the gate 44 of the second output transistor T4, and the second plate C22 of the second capacitor C2 being coupled to the second level signal line VGH; the shift register unit 10 further includes a third capacitor C3 and a second input transistor T3, the first plate C31 of the third capacitor C3 being coupled to the gate 43 of the second input transistor T3, and the second plate C32 of the third capacitor C3 being coupled to the first clock signal input terminal CB; the first terminal of the second input transistor T3 is coupled to the first clock signal input terminal CB, and the second terminal of the second input transistor T3 is coupled to the second output node N2; the second plates C32 of the third capacitor C3 and C22 of the second capacitor C2 are arranged along the first direction;

[0124] The orthographic projection of the active layer 33 of the second input transistor T3 onto the substrate is located between the orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate and the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate.

[0125] For example, the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate is located inside the orthographic projection of the first plate C21 of the second capacitor C2 onto the substrate. The orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate is located inside the orthographic projection of the first plate C31 of the third capacitor C3 onto the substrate.

[0126] The arrangement of the second plate C32 of the third capacitor C3 and the second plate C22 of the second capacitor C2 along the first direction helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, thereby effectively narrowing the bezel width of the display substrate.

[0127] As shown in Figures 5 to 7 and Figures 11 to 15, in some embodiments, the first plate C31 of the third capacitor C3 and the gate 43 of the second input transistor T3 are formed as an integral structure. This arrangement not only ensures the connection performance between the third capacitor C3 and the second input transistor T3, but also helps to reduce the layout difficulty of the shift register unit and reduce the layout space occupied by the shift register unit.

[0128] As shown in Figures 5 to 7 and Figures 11 to 15, in some embodiments, the second plate C32 of the third capacitor C3 includes a main body portion, the edge of which has a first notch O1;

[0129] The first electrode C31 of the third capacitor C3 includes a first part C31a and a second part C31b. The second part C31b is coupled to the second electrode of the fourth control transistor T7. The orthographic projection of the first part C31a on the substrate overlaps with the orthographic projection of the main body of the second electrode C32 of the third capacitor C3 on the substrate. The orthographic projection of the second part C31b on the substrate overlaps at least partially with the orthographic projection of the first notch O1 on the substrate.

[0130] It should be noted that the first notch O1 on the edge of the main body of the third capacitor C3 does not have a solid structure; it can be understood as a notch formed by the edge of the main body. The orthographic projection of the second part C31b on the substrate at least partially overlaps with the orthographic projection of the first notch O1 on the substrate. This means that the area where the first notch is located will not obstruct the second part C31b, thus enabling the second part C31b to be coupled to the corresponding conductive connection while preventing a short circuit between it and the main body.

[0131] For example, the second portion C31b is coupled to the second electrode of the fourth control transistor T7 via the fourth conductive connection portion 24.

[0132] The above arrangement can better increase the facing area of ​​the third capacitor C3, improve its capacitance, and better guarantee its performance. At the same time, this arrangement makes the overall shape of the third capacitor C3 regular, which helps reduce the difficulty of placing it within a limited layout space.

[0133] As shown in Figures 5 to 7, in some embodiments, the second plate C22 of the second capacitor C2 includes a main body portion, the edge of which has a second notch O2.

[0134] The first electrode C21 of the second capacitor C2 includes a third part C21a and a fourth part C21b. The fourth part C21b is coupled to the second electrode of the second input transistor T3. The orthographic projection of the third part C21a on the substrate overlaps with the orthographic projection of the main body of the second electrode C22 of the second capacitor C2 on the substrate. The orthographic projection of the fourth part C21b on the substrate overlaps at least partially with the orthographic projection of the second notch O2 on the substrate.

[0135] It should be noted that the second notch O2 on the edge of the main body of the second capacitor C2 does not have a solid structure; it can be understood as a notch formed by the edge of the main body. The orthographic projection of the fourth part C21b on the substrate at least partially overlaps with the orthographic projection of the second notch O2 on the substrate. This means that the area where the second notch O2 is located will not obstruct the fourth part C21b, thus enabling the fourth part C21b to be coupled to the corresponding conductive connection while preventing a short circuit between it and the main body.

[0136] For example, the fourth part C21b is coupled to the second terminal of the second input transistor T3 via the sixth conductive connection 26.

[0137] The above arrangement can better increase the facing area of ​​the second capacitor C2, improve its capacitance, and better guarantee its performance. At the same time, this arrangement makes the overall shape of the second capacitor C2 regular, which helps reduce the difficulty of placing it within a limited layout space.

[0138] As shown in Figures 4 to 9, in some embodiments, the shift register unit 10 further includes a third control transistor T2 and a fourth control transistor T7; the gate 42 of the third control transistor T2 is coupled to the first input node N1, the first terminal of the third control transistor T2 is coupled to the second level signal line VGH, and the second terminal of the third control transistor T2 is coupled to the second output node N2; the gate 47 of the fourth control transistor T7 is coupled to the first input node N1, the first terminal of the fourth control transistor T7 is coupled to the second level signal line VGH, and the second terminal of the fourth control transistor T7 is coupled to the gate 43 of the second input transistor T3;

[0139] The orthographic projection of the active layer 32 of the third control transistor T2 onto the substrate is located between the orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate and the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate; and / or

[0140] The orthographic projection of the active layer 37 of the fourth control transistor T7 onto the substrate is located between the orthographic projection of the second plate C32 of the third capacitor C3 onto the substrate and the orthographic projection of the second plate C22 of the second capacitor C2 onto the substrate.

[0141] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, thereby effectively narrowing the bezel width of the display substrate.

[0142] As shown in Figures 4 to 9, in some embodiments, the display substrate further includes a second clock signal input terminal CK; the shift register unit 10 further includes a first input transistor T1, a first control transistor T6, and a second control transistor T9; the gate 41 of the first input transistor T1 is coupled to the second clock signal input terminal CK, the first terminal of the first input transistor T1 is coupled to the start signal input terminal, and the second terminal of the first input transistor T1 is coupled to the first input node N1; the gate 46 of the first control transistor T6 is coupled to the second output node N2, the first terminal of the first control transistor T6 is coupled to the second level signal line VGH, and the second terminal of the first control transistor T6 is coupled to the first terminal of the second control transistor T9; the gate 49 of the second control transistor T9 is coupled to the first clock signal input terminal CB, and the second terminal of the second control transistor T9 is coupled to the first input node N1;

[0143] The active layer 31 of the first input transistor T1, the active layer 39 of the second control transistor T9, and the active layer 36 of the first control transistor T6 are arranged along the first direction.

[0144] For example, the active layer 31 of the first input transistor T1 extends along the first direction, the active layer 39 of the second control transistor T9 extends along the first direction, and the active layer 36 of the first control transistor T6 extends along the first direction. The active layer 31 of the first input transistor T1, the active layer 39 of the second control transistor T9, and the active layer 36 of the first control transistor T6 are formed into a single structure.

[0145] The above configuration helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, thereby effectively narrowing the bezel width of the display substrate.

[0146] As shown in Figures 4 to 9, in some embodiments, the display substrate further includes a frame start signal line STV, a first clock signal line GCB, and a second clock signal line GCK; the frame start signal line STV, the first clock signal line GCB, the second clock signal line GCK, the second level signal line VGH, and the first level signal line VGL are arranged sequentially along a second direction;

[0147] In the cascaded multiple shift register units 10, the first terminal of the first input transistor T1 in the first-stage shift register unit 10 is coupled to the frame start signal line STV, and the first terminal of the first input transistor T1 in the (n+1)th-stage shift register unit 10 is coupled to the gate drive signal output terminal of the nth-stage shift register unit 10; n is an integer greater than or equal to 1.

[0148] In one of the odd-level shift register units 10 and the even-level shift register units 10, the first clock signal input terminal CB is coupled to the first clock signal line GCB, and the second clock signal input terminal CK is coupled to the second clock signal line GCK.

[0149] In another shift register unit 10 among the odd-level shift register units 10 and the even-level shift register units 10, the first clock signal input terminal CB is coupled to the second clock signal line GCK, and the second clock signal input terminal CK is coupled to the first clock signal line GCB.

[0150] For example, the orthographic projections of all transistors in the shift register unit 10 onto the substrate are located between the orthographic projections of the second level signal line VGH and the first level signal line VGL onto the substrate. This arrangement concentrates all transistors in the shift register unit 10 between the first level signal line VGL and the second level signal line VGH, resulting in a uniform distribution density of CNT vias around each transistor. This avoids the increase in regional characteristic differences caused by hydrogen removal in the layout area due to uneven via distribution.

[0151] For example, the first clock signal line GCB includes two stacked first signal transmission layers; the second clock signal line GCK includes two stacked second signal transmission layers.

[0152] As shown in Figure 2, exemplarily, the display substrate includes, sequentially stacked along a direction away from the substrate 70, a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarization layer PLN1, a second source / drain metal layer SD2, a second planarization layer PLN2, an anode layer ANO, a pixel defining layer PDL, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, etc. The display substrate may also include a passivation layer PVX, but is not limited thereto.

[0153] For example, one of the dual-layer first signal transmission layers is disposed in the same layer and with the same material as the first source / drain metal layer, and the other of the dual-layer first signal transmission layers is disposed in the same layer and with the same material as the second source / drain metal layer.

[0154] As shown in Figures 4 to 9, the shift register unit 10 further includes a third conductive connection portion 23, which is coupled to the second terminal of the second output control transistor T10 and the gate 44 of the second output transistor T4.

[0155] The shift register unit 10 further includes a fourth conductive connection part 24, which is coupled to the first plate C31 of the third capacitor C3 and the second plate of the fourth control transistor T7, respectively.

[0156] The shift register unit 10 further includes a fifth conductive connection portion 25, which is coupled to the second terminal of the first input transistor T1 and the gate 47 of the fourth control transistor T7, respectively.

[0157] The shift register unit 10 further includes a sixth conductive connection part 26, which is coupled to the second electrode of the second input transistor T3 and the first plate C21 of the second capacitor C2.

[0158] The shift register unit 10 further includes a seventh conductive connection portion 27, which is coupled to the first terminal of the first output control transistor T8 and the gate 42 of the third control transistor T2, respectively.

[0159] It is worth noting that Figure 9 also illustrates the first terminal 53 of the first output transistor T5, the second terminal 54 of the first output transistor T5, the first terminal 51 of the second output transistor T4, and the second terminal 52 of the second output transistor T4.

[0160] As shown in Figures 10 to 15, in some embodiments, the shift register unit 10 further includes a first capacitor C1, the first plate C11 of the first capacitor C1 is coupled to the gate 45 of the first output transistor T5, and the second plate C12 of the first capacitor C1 is coupled to the second plate of the first output transistor T5; the orthographic projection of the active layer 35 of the first output transistor T5 on the substrate is located between the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate and the orthographic projection of the first level signal line VGL on the substrate.

[0161] For example, the shift register unit 10 further includes a second capacitor C2, the first plate C21 of the second capacitor C2 is coupled to the gate 44 of the second output transistor T4, and the second plate C22 of the second capacitor C2 is coupled to the second level signal line VGH; the second plate C22 of the second capacitor C2 includes a second plate body portion C220 and a second plate connection portion C221 coupled together, the orthographic projection of the second plate body portion C220 on the substrate at least partially overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate; the second plate connection portion C221 is coupled to the second level signal line VGH; at least a portion of the orthographic projection of the second plate body portion C220 on the substrate is located between the orthographic projection of the active layer 35 of the first output transistor T5 on the substrate and the orthographic projection of the first level signal line VGL on the substrate.

[0162] For example, the second electrode plate main body C220 and the second electrode plate connecting part C221 are formed as an integral structure.

[0163] For example, the orthographic projection of the second electrode body C220 on the substrate is located inside the orthographic projection of the first electrode C21 of the second capacitor C2 on the substrate.

[0164] For example, at least a portion of the orthographic projection of the second electrode body C220 onto the substrate is located between the orthographic projection of the active layer 34 of the second output transistor T4 onto the substrate and the orthographic projection of the first level signal line VGL onto the substrate.

[0165] For example, the orthographic projection of the active layer 38 of the first output control transistor T8 on the substrate, the orthographic projection of the second electrode body C220 of the second capacitor C2 on the substrate, and the orthographic projection of the active layer 310 of the second output control transistor T10 on the substrate are arranged sequentially along the first direction.

[0166] In the display substrate provided in the above embodiments, the first output control transistor T8, the second capacitor C2, and the second output control transistor T10 are arranged sequentially along the first direction and positioned between the first level signal line VGL and the two output transistors (i.e., the first output transistor T5 and the second output transistor T4). This allows the first output transistor T5, the second output transistor T4, the first output control transistor T8, the second output control transistor T10, the second capacitor C2, and the first level signal line VGL to be centrally located. This not only reduces the difficulty of circuit connection and ensures the reliability of the connection, but also helps to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, thereby effectively narrowing the bezel width of the display substrate. More specifically, in the display substrate provided in this disclosure embodiment, by optimizing the layout of the first level signal line VGL, the second capacitor C2, the first output control transistor T8, and the second output control transistor T10, the layout space occupied by the shift register unit 10 along the second direction can be narrowed by more than 15 micrometers.

[0167] As shown in Figures 10 to 15, in some embodiments, the shift register unit 10 further includes a first conductive connection portion 21. The first end of the first conductive connection portion 21 is coupled to the gate 410 of the second output control transistor T10, and the second end of the first conductive connection portion 21 is coupled to the second terminal of the first output transistor T5 in the next-level shift register unit 10 adjacent to its own shift register unit 10. At least a portion of the orthographic projection of the first conductive connection portion 21 on the substrate is aligned with the orthographic projection of the active layer 34 of the second output transistor T4 on the substrate along the first direction.

[0168] For example, the first conductive connection portion 21 is formed as an integral structure with the second pole of the first output transistor T5 in the next-level shift register unit 10 adjacent to its corresponding shift register unit 10.

[0169] The above layout method is beneficial to shorten the distance between the gate 410 of the second output control transistor T10 and the second pole of the first output transistor T5 in the next-level shift register unit 10 adjacent to its corresponding shift register unit 10, effectively shortening the length of the first conductive connection portion 21 and reducing the layout difficulty of adjacent shift register units 10; at the same time, it is beneficial to reduce the width of the layout space occupied by the gate driving circuit along the first direction.

[0170] As shown in Figures 10 to 15, in some embodiments, the display substrate includes four clock signal lines, namely the first clock signal line GCB1, the second clock signal line GCK1, the third clock signal line GCB2, and the fourth clock signal line GCK2.

[0171] For example, in the multiple shift register units 10 included in the gate drive circuit, in the 4m+1th stage shift register unit 10, the first clock signal input terminal CB is coupled to the first clock signal line GCB1, and the second clock signal input terminal CK is coupled to the second clock signal line GCK1.

[0172] In the gate drive circuit, among the multiple shift register units 10, in the 4m+2th level shift register unit 10, the first clock signal input terminal CB is coupled to the second clock signal line GCK1, and the second clock signal input terminal CK is coupled to the first clock signal line GCB1.

[0173] In the gate drive circuit, among the multiple shift register units 10, in the 4m+3 level shift register unit 10, the first clock signal input terminal CB is coupled to the third clock signal line GCB2, and the second clock signal input terminal CK is coupled to the fourth clock signal line GCK2.

[0174] In the gate drive circuit, among the multiple shift register units 10, in the 4m+4th shift register unit 10, the first clock signal input terminal CB is coupled to the fourth clock signal line GCK2, and the second clock signal input terminal CK is coupled to the third clock signal line GCB2.

[0175] As shown in Figure 14, in some embodiments, the frame start signal line STV, the first clock signal line GCB1, the second clock signal line GCK1, the third clock signal line GCB2, and the fourth clock signal line GCK2 can all adopt a double-layer structure, that is, they all include a double-layer signal transmission layer. One of the double-layer signal transmission layers is made of the same material as the first source-drain metal layer, and the other layer of the double-layer signal transmission layer is made of the same material as the first source-drain metal layer, but it is not limited to this.

[0176] It should be noted that, as shown in Figure 15, the shift register unit 10 further includes a ninth conductive connection portion 29, which is coupled to the second electrode of the second control transistor T9 and the gate of the fourth control transistor T7, respectively.

[0177] The shift register unit 10 further includes a tenth conductive connection part 210, which is coupled to the second plate C32 of the third capacitor C3, the first electrode of the second input transistor T3, and the gate of the second control transistor T9.

[0178] The shift register unit 10 further includes an eleventh conductive connection 211, which is coupled to the first pole of the first input transistor T1 in the adjacent next-level shift register unit, and is also coupled to the fifteenth conductive connection 215.

[0179] The shift register unit 10 further includes a twelfth conductive connection portion 212, which is coupled to the gate 45 of the second output transistor T5 and the second pole of the second output control transistor T8.

[0180] The shift register unit 10 further includes a thirteenth conductive connection portion 213, which is coupled to the second electrode of the second output control transistor T10 and the gate 44 of the second output transistor T4.

[0181] As shown in Figure 11, the shift register unit 10 further includes a fourteenth conductive connection portion 214, which is coupled to the first terminal and the tenth conductive connection portion 210 of the second output transistor T5, respectively. The shift register unit 10 also includes a fifteenth conductive connection portion 215, which is coupled to the second terminal 52 of the second output transistor T4.

[0182] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0183] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0184] In the display substrate provided in the above embodiments, the gate 48 of the first output control transistor T8 and the first electrode of the second output control transistor T10 are both coupled to the first level signal line VGL. By setting the orthographic projection of the first output control transistor T8 on the substrate and the orthographic projection of the second output control transistor T10 on the substrate to be located on the same side of the orthographic projection of the first level signal line VGL on the substrate, not only can the connection reliability between the first output control transistor T8 and the second output control transistor T10 and the first level signal line VGL be guaranteed, but it is also beneficial to narrow the width of the layout space occupied by the shift register unit 10 along the second direction, thereby effectively narrowing the bezel width of the display substrate.

[0185] The display device provided in this disclosure, when including the display substrate provided in the above embodiments, also has the above-mentioned beneficial effects, which will not be repeated here.

[0186] It should be noted that the signal line extending in a certain direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends in a certain direction, and the length of the main part extending in a certain direction is greater than the length of the secondary part extending in other directions.

[0187] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0188] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0189] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0190] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0191] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0192] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0193] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: A substrate, and a first level signal line and a gate driving circuit disposed on the substrate; The gate drive circuit includes multiple cascaded shift register units, each shift register unit including: a first input node, a first output node, a second output node, a first output control transistor, and a second output control transistor; The gate of the first output control transistor is coupled to the first level signal line, the first terminal of the first output control transistor is coupled to the first input node, and the second terminal of the first output control transistor is coupled to the first output node; the gate of the second output control transistor is coupled to the gate drive signal output terminal of the next-level shift register unit adjacent to its own shift register unit, the first terminal of the second output control transistor is coupled to the first level signal line, and the second terminal of the second output control transistor is coupled to the second output node. The orthographic projections of the first output control transistor and the second output control transistor on the substrate are both located on the same side of the orthographic projection of the first level signal line on the substrate.

2. The display substrate according to claim 1, wherein, The orthographic projection of the first output control transistor on the substrate and the orthographic projection of the second output control transistor on the substrate are arranged along a first direction.

3. The display substrate according to claim 2, wherein, The active layer of the first output control transistor extends along the first direction; the gate of the first output control transistor extends along the second direction, which intersects with the first direction; the end of the gate of the first output control transistor near the first level signal line is coupled to the first level signal line; the orthographic projection of the gate of the first output control transistor on the substrate overlaps with the orthographic projection of the active layer of the first output control transistor on the substrate.

4. The display substrate according to claim 2, wherein, The second output control transistor includes an active layer that extends along a second direction, which intersects with the first direction; The active layer of the second output control transistor is coupled to the first level signal line at one end near the first level signal line. The gate of the second output control transistor includes at least a portion extending along the first direction, and the orthographic projection of the gate of the second output control transistor on the substrate overlaps with the orthographic projection portion of the active layer included in the second output control transistor on the substrate.

5. The display substrate according to any one of claims 2 to 4, wherein, The display substrate further includes a first clock signal input terminal and a second level signal line; the shift register unit further includes a first output transistor and a second output transistor; the gate of the first output transistor is coupled to the first output node, the first terminal of the first output transistor is coupled to the first clock signal input terminal, and the second terminal of the first output transistor is coupled to the gate drive signal output terminal of its respective shift register unit; the gate of the second output transistor is coupled to the second output node, the first terminal of the second output transistor is coupled to the second level signal line, and the second terminal of the second output transistor is coupled to the gate drive signal output terminal of its respective shift register unit; The orthographic projection of the active layer of the first output control transistor on the substrate is located between the orthographic projection of the active layer of the first output transistor on the substrate and the orthographic projection of the first level signal line on the substrate. The orthographic projection of the active layer of the second output control transistor onto the substrate is located between the orthographic projection of the active layer of the second output transistor onto the substrate and the orthographic projection of the first level signal line onto the substrate.

6. The display substrate according to claim 5, wherein, The shift register unit further includes a first capacitor, the first plate of the first capacitor being coupled to the gate of the first output transistor, and the second plate of the first capacitor being coupled to the second terminal of the first output transistor. The orthographic projection of the second plate of the first capacitor onto the substrate is located between the orthographic projection of the active layer of the first output transistor onto the substrate and the orthographic projection of the first level signal line onto the substrate.

7. The display substrate according to claim 6, wherein, The orthographic projection of the active layer of the first output control transistor on the substrate is located between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first level signal line on the substrate.

8. The display substrate according to claim 7, wherein, The first electrode of the first capacitor includes a first electrode body portion and a first electrode protrusion portion coupled together. The first electrode body portion extends along the first direction. The second electrode of the first capacitor extends along the first direction. The orthographic projection of the first electrode body portion on the substrate and the orthographic projection of the second electrode of the first capacitor on the substrate at least partially overlap. The first electrode protrusion protrudes from the first electrode body in a second direction, and the first electrode protrusion is coupled to the second electrode of the first output control transistor.

9. The display substrate according to claim 5, wherein, The shift register unit further includes a first capacitor, the first plate of the first capacitor being coupled to the gate of the first output transistor, and the second plate of the first capacitor being coupled to the second terminal of the first output transistor. The shift register unit further includes a first conductive connection portion, a first end of which is coupled to the gate of the second output control transistor, and a second end of which is coupled to the second plate of the first capacitor in the next-level shift register unit adjacent to its own shift register unit; at least a portion of the orthographic projection of the first conductive connection portion on the substrate is arranged along the first direction with the orthographic projection of the second plate of the first capacitor on the substrate.

10. The display substrate according to claim 5, wherein, The shift register unit further includes a second capacitor, the first plate of which is coupled to the gate of the second output transistor, and the second plate of which is coupled to the second level signal line. The shift register unit further includes a third capacitor and a second input transistor. The first plate of the third capacitor is coupled to the gate of the second input transistor, and the second plate of the third capacitor is coupled to the first clock signal input terminal. The first terminal of the second input transistor is coupled to the first clock signal input terminal, and the second terminal of the second input transistor is coupled to the second output node. The second plate of the third capacitor is arranged along the first direction with the second plate of the second capacitor. The orthographic projection of the active layer of the second input transistor onto the substrate is located between the orthographic projection of the second plate of the third capacitor onto the substrate and the orthographic projection of the second plate of the second capacitor onto the substrate.

11. The display substrate according to claim 10, wherein, The first plate of the third capacitor and the gate of the second input transistor are formed as a single unit.

12. The display substrate according to claim 10, wherein, The second plate of the third capacitor includes a main body portion, the edge of which has a first notch. The first electrode of the third capacitor includes a first part and a second part, the second part being coupled to the second electrode of the fourth control transistor in the shift register unit; the orthographic projection of the first part on the substrate overlaps with the orthographic projection of the main body of the second electrode of the third capacitor on the substrate, and the orthographic projection of the second part on the substrate at least partially overlaps with the orthographic projection of the first notch on the substrate.

13. The display substrate according to claim 10, wherein, The second plate of the second capacitor includes a main body portion, the edge of which has a second notch; The first electrode of the second capacitor includes a third part and a fourth part, the fourth part being coupled to the second electrode of the second input transistor; the orthographic projection of the third part on the substrate overlaps with the orthographic projection of the main body of the second electrode of the second capacitor on the substrate, and the orthographic projection of the fourth part on the substrate at least partially overlaps with the orthographic projection of the second notch on the substrate.

14. The display substrate according to claim 10, wherein, The shift register unit further includes a third control transistor and a fourth control transistor; the gate of the third control transistor is coupled to the first input node, the first terminal of the third control transistor is coupled to the second level signal line, and the second terminal of the third control transistor is coupled to the second output node; the gate of the fourth control transistor is coupled to the first input node, the first terminal of the fourth control transistor is coupled to the second level signal line, and the second terminal of the fourth control transistor is coupled to the gate of the second input transistor. The orthographic projection of the active layer of the third control transistor on the substrate is located between the orthographic projection of the second plate of the third capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate. And / or, The orthographic projection of the active layer of the fourth control transistor on the substrate is located between the orthographic projection of the second plate of the third capacitor on the substrate and the orthographic projection of the second plate of the second capacitor on the substrate.

15. The display substrate according to claim 6, wherein, The display substrate further includes a second clock signal input terminal; the shift register unit further includes a first input transistor, a first control transistor, and a second control transistor; The gate of the first input transistor is coupled to the second clock signal input terminal, the first terminal of the first input transistor is coupled to the start signal input terminal, and the second terminal of the first input transistor is coupled to the first input node; The gate of the first control transistor is coupled to the second output node, the first terminal of the first control transistor is coupled to the second level signal line, and the second terminal of the first control transistor is coupled to the first terminal of the second control transistor; the gate of the second control transistor is coupled to the first clock signal input terminal, and the second terminal of the second control transistor is coupled to the first input node. The active layer of the first input transistor, the active layer of the second control transistor, and the active layer of the first control transistor are arranged along the first direction.

16. The display substrate according to claim 15, wherein, The display substrate further includes a frame start signal line, a first clock signal line, and a second clock signal line; the frame start signal line, the first clock signal line, the second clock signal line, the second level signal line, and the first level signal line are arranged sequentially along a second direction; In the cascaded multiple shift register units, the first terminal of the first input transistor in the first-stage shift register unit is coupled to the frame start signal line, and the first terminal of the first input transistor in the (n+1)th-stage shift register unit is coupled to the gate drive signal output terminal of the nth-stage shift register unit; n is an integer greater than or equal to 1. In one of the odd-level shift register units and the even-level shift register units, the first clock signal input terminal is coupled to the first clock signal line, and the second clock signal input terminal is coupled to the second clock signal line. In another shift register unit among the odd-level shift register units and the even-level shift register units, the first clock signal input terminal is coupled to the second clock signal line, and the second clock signal input terminal is coupled to the first clock signal line.

17. The display substrate according to claim 16, wherein, The orthographic projections of all transistors in the shift register unit onto the substrate are located between the orthographic projections of the second level signal line onto the substrate and the orthographic projections of the first level signal line onto the substrate.

18. The display substrate according to claim 16, wherein, The first clock signal line includes two stacked first signal transmission layers; the second clock signal line includes two stacked second signal transmission layers.

19. The display substrate according to claim 5, wherein, The shift register unit further includes a first capacitor, the first plate of the first capacitor being coupled to the gate of the first output transistor, and the second plate of the first capacitor being coupled to the second terminal of the first output transistor. The orthographic projection of the active layer of the first output transistor on the substrate is located between the orthographic projection of the second plate of the first capacitor on the substrate and the orthographic projection of the first level signal line on the substrate.

20. The display substrate according to claim 19, wherein, The shift register unit further includes a second capacitor, the first plate of which is coupled to the gate of the second output transistor, and the second plate of which is coupled to the second level signal line. The second electrode of the second capacitor includes a second electrode body portion and a second electrode connecting portion coupled together. The orthographic projection of the second electrode body portion on the substrate overlaps at least partially with the orthographic projection of the first electrode of the second capacitor on the substrate. The second electrode plate connection portion is coupled to the second level signal line; At least a portion of the orthographic projection of the second electrode body onto the substrate is located between the orthographic projection of the active layer of the first output transistor onto the substrate and the orthographic projection of the first level signal line onto the substrate.

21. The display substrate according to claim 20, wherein, The orthographic projection of the active layer of the first output control transistor on the substrate, the orthographic projection of the second plate body of the second capacitor on the substrate, and the orthographic projection of the active layer of the second output control transistor on the substrate are arranged sequentially along the first direction.

22. The display substrate according to claim 19, wherein, The shift register unit further includes a first conductive connection portion, a first end of which is coupled to the gate of the second output control transistor, and a second end of which is coupled to the second terminal of the first output transistor in the next-level shift register unit adjacent to its own shift register unit; at least a portion of the orthographic projection of the first conductive connection portion on the substrate and the orthographic projection of the active layer of the second output transistor on the substrate are arranged along the first direction.

23. A display device comprising a display substrate as claimed in any one of claims 1 to 22.

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