Overcurrent protection for load control devices

Abstract

A load control device can include a closed-loop gate drive circuit coupled to the semiconductor switch and configured to render the semiconductor switch conductive or non-conductive at a control time during a half-cycle of an AC mains voltage. The gate drive circuit can limit a magnitude of a load current conducted through the semiconductor switch to a maximum current limit. The load control device can include a control circuit configured to set the maximum current limit to a second magnitude for a period of time after the control time of the semiconductor switch during a conductive period of a half-cycle of an AC mains voltage and set the maximum current limit to a first magnitude after expiration of the period of time during the conductive period of the half-cycle of the AC mains voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Provisional U.S. Patent Application No. 63 / 560,212, filed March 1, 2024, the entire disclosure of which is hereby incorporated herein by reference. Background Technology

[0003] Existing load control devices, such as dimmer switches, can be connected in series between an alternating current (AC) power source and a lighting load to control the amount of power delivered from the AC power source to the lighting load. A standard dimmer switch typically includes a bidirectional semiconductor switch, such as a thyristor (e.g., a triac-controlled rectifier) ​​or two anti-parallel field-effect transistors (FETs) connected in series. This bidirectional semiconductor switch can be controlled to be on and off during a portion of a half-cycle of the AC power supply, thereby controlling the amount of power delivered to the electrical load.

[0004] Typically, dimmer switches can use forward phase control dimming technology or reverse phase control dimming technology to control when a bidirectional semiconductor switch is turned on and off, thereby controlling the power delivered to the load. The dimmer switch may include a toggle actuator for turning the lighting load on and off, and an intensity adjustment actuator for adjusting the intensity level of the lighting load. Examples of prior art dimmer switches are described in more detail in commonly assigned U.S. Patent No. 5,248,919, entitled "LIGHTING CONTROL DEVICE," published September 29, 1993, and U.S. Patent No. 6,969,959, entitled "ELECTRONIC CONTROL SYSTEMS ANDMETHODS," published November 29, 2005, the entire disclosure of which is hereby incorporated by reference. Summary of the Invention

[0005] As described herein, a load control device can be configured to control power delivered from an alternating current (AC) power source to an electrical load. The load control device can include a controllably conductive device adapted to be coupled in series between the AC power source and the electrical load. The AC power source can be configured to generate an AC mains voltage. The controllably conductive device can include a semiconductor switch configured to conduct a load current through the electrical load. The load control device can include a closed-loop gate drive circuit coupled to the semiconductor switch and configured to render the semiconductor switch conductive or non-conductive at a control time during a half-cycle of the AC mains voltage. The closed-loop gate drive circuit can be configured to limit a magnitude of the load current conducted through the semiconductor switch to within a maximum current limit. The load control device can include a control circuit configured to generate a drive signal to adjust the control time of the semiconductor switch during each half-cycle of the AC mains voltage to control an amount of power delivered to the electrical load. The control circuit can be configured to control the drive signal to render the semiconductor switch conductive at the control time during a half-cycle of the AC mains voltage to cause the semiconductor switch to remain conductive for a conduction period of the half-cycle of the AC mains voltage. The control circuit can set the maximum current limit of the closed-loop gate drive circuit to a first limit for a period of time after the control time during the conduction period of the half-cycle of the AC mains voltage. The control circuit can set the maximum current limit of the closed-loop gate drive circuit to a second limit after expiration of the period of time, where the second limit is less than the first limit.

[0006] The control circuit can be configured to set the maximum current limit to the first limit for a pulse period beginning at the control time during the half-cycle of the AC mains voltage and to set the maximum current limit to the second limit at an end of the pulse period and during a remaining portion of the conduction period of the half-cycle of the AC mains voltage. The pulse period can be approximately 500 microseconds. The control circuit can be configured to set the maximum current limit to the first limit for the pulse period to allow a capacitance of a capacitive load to charge during the half-cycle of the AC mains voltage.

[0007] The control circuit can be configured to set the maximum current limit of the closed-loop gate drive circuit to the first limit for a pulse period following the control time of the semiconductor switch during an amount of time (e.g., an initial number of half cycles of the AC mains voltage) following turning on the electrical load; and set the maximum current limit of the closed-loop gate drive circuit to the second limit at control times during subsequent half cycles of the AC mains voltage following the initial number of half cycles and while controlling power to the electrical load. The control circuit can be configured to shorten a duration of the pulse period for an initial number of half cycles of the AC mains voltage following turning on the electrical load.

[0008] The control circuit is configured to set a length of the pulse period to a second time period for a number of half cycles following turning on the electrical load; and set the length of the pulse period to a first time period following the number of half cycles and while controlling power to the electrical load. The first time period can be approximately 500 microseconds, the second time period can be approximately 2,000 microseconds, and / or the number of half cycles can be approximately 120 half cycles.

[0009] The control circuit can be configured to adjust the maximum current limit within a range of values from the first limit to the second limit for a number of half cycles of the AC mains voltage. The control circuit can be configured to linearly decrease the maximum current limit within the range of values from the first limit to the second limit for the number of half cycles of the AC mains voltage.

[0010] When operating in a forward phase control technique, the control circuit can be configured to set the maximum current limit of the closed-loop gate drive circuit to the first limit for the period of time following the control time of the semiconductor switch during a conduction period of each half cycle of the AC mains voltage while controlling power to the electrical load. The control circuit can be configured to set the maximum current limit of the closed-loop gate drive circuit to the second limit following expiration of the period of time during the conduction period of each half cycle of the AC mains voltage while controlling power to the electrical load. For example, when operating in a reverse phase control technique, the control circuit can be configured to set the maximum current limit of the closed-loop gate drive circuit to a third limit for an entire conduction period of each half cycle of the AC mains voltage while controlling power to the electrical load. The third limit can be equal to the first limit.

[0011] The closed-loop gate drive circuit can be configured to: generate a target signal in response to the control circuit, receive a feedback signal indicating the amplitude of the load current conducted through the semiconductor switch, and generate a gate control signal in response to the target signal and the feedback signal. The semiconductor switch of the controllable conductive device can be configured to be turned on and off in response to the gate control signal.

[0012] When using forward phase control technology, the control circuit can be configured to: control the drive signal to de-convert the semiconductor switch at the beginning of each half-cycle of the AC main line voltage while controlling the power to the electrical load, and control the drive signal to convert the semiconductor switch during a control time within each half-cycle of the AC main line voltage and for the remainder of each half-cycle. For example, when using reverse phase control technology, the control circuit can be configured to: control the drive signal to convert the semiconductor switch at the beginning of each half-cycle of the AC main line voltage, and control the drive signal to de-convert the semiconductor switch during a control time within each half-cycle of the AC main line voltage.

[0013] The control circuit can be configured to control the semiconductor switch to be non-conducting during non-conducting periods and conduct during conducting periods during one or more half-cycles of the AC main line voltage, so as to control the amount of power delivered to the electrical load.

[0014] Some examples may include a load control device configured to control power supplied from an alternating current (AC) power source to an electrical load, wherein the load control device includes a controllable conductor adapted to be coupled in series between the AC power source and the electrical load, wherein the AC power source is configured to generate an AC mainline voltage, and wherein the controllable conductor includes a semiconductor switch configured to conduct load current through the electrical load. The load control device may include a closed-loop gate drive circuit coupled to the semiconductor switch and configured to turn the semiconductor switch on or off during a control time within half a cycle of the AC mainline voltage. The closed-loop gate drive circuit may be configured to limit the amplitude of the load current conducted through the semiconductor switch to a maximum current limit, wherein the maximum current limit may be adjusted between a first limit and a second limit. The load control device may include control circuitry configured to generate a drive signal to adjust the control time of the semiconductor switch during each half-cycle of the AC mains voltage, thereby controlling the amount of power delivered to the electrical load; determine that the electrical load is an inductive load; and set the maximum current limit of the closed-loop gate drive circuitry to the second limit based on the fact that the electrical load is an inductive load.

[0015] The control circuit can be configured to determine that the electrical load is inductive based on the fact that the amplitude of the load current conducted through the semiconductor switch is out of phase with the AC main line voltage. The load control device may include: a zero-crossing detection signal configured to generate a zero-crossing signal indicating the zero-crossing point of the AC main line voltage; and a feedback resistor coupled in series to the semiconductor switch and configured to generate a feedback signal. The control circuit can be configured to determine the zero-crossing point of the AC main line voltage based on the zero-crossing signal generated by the zero-crossing detection signal, and to determine the zero-crossing point of the load current conducted through the semiconductor switch based on the feedback signal generated by the feedback resistor. When the zero-crossing point of the load current conducted through the semiconductor switch is not aligned with the zero-crossing point of the AC main line voltage, the control device can be configured to determine that the load current conducted through the semiconductor switch is out of phase with the AC main line voltage.

[0016] The control circuit can be configured to determine whether to operate using a forward phase control technique based on whether the electrical load is inductive. The control circuit can also be configured to detect whether to operate using a reverse phase control technique or a forward phase control technique based on the electrical load, and when operating using a reverse phase control technique, the control circuit can be configured to set the maximum current limit of the closed-loop gate drive circuit to a first limit. For example, when operating using a forward phase control technique and based on the electrical load not being inductive, the control circuit can be configured to set the maximum current limit of the closed-loop gate drive circuit to the first limit. When operating using a forward phase control technique and based on the electrical load not being inductive, the control circuit can be configured to set the maximum current limit of the closed-loop gate drive circuit to the first limit for a period of time after the control time during the on-time period of half a cycle of the AC main line voltage, and to set the maximum current limit to the second limit after the expiration of this period of time during the on-time period of half a cycle of the AC main line voltage.

[0017] Some examples may include a load control device configured to control power supplied from an alternating current (AC) power source to an electrical load, wherein the load control device includes a controllable conductor adapted to be coupled in series between the AC power source and the electrical load, wherein the AC power source is configured to generate an AC mainline voltage, and wherein the controllable conductor includes a semiconductor switch configured to conduct load current through the electrical load. The load control device may include a closed-loop gate drive circuit coupled to the semiconductor switch and configured to turn the semiconductor switch on or off during a control time within half a cycle of the AC mainline voltage, wherein the closed-loop gate drive circuit is configured to limit the amplitude of the load current conducted through the semiconductor switch to within a maximum current limit. The load control device may include a control circuit configured to: during the initial plurality of half-cycles of the AC main line voltage after the electrical load is turned on, for a period of time after the control time of the semiconductor switch during the on-time period of each half-cycle of the AC main line voltage in the initial plurality of half-cycles, set the maximum current limit of the closed-loop gate drive circuit to a first limit; and after the period of time during the on-time period of each half-cycle of the AC main line voltage in the initial plurality of half-cycles expires, set the maximum current limit of the closed-loop gate drive circuit to a second limit, wherein the second limit is less than the first limit. The control circuit may also be configured to: after the initial plurality of half-cycles of the AC main line voltage, while controlling the power of the electrical load, set the maximum current limit of the closed-loop gate drive circuit to the second limit at the control time during the subsequent half-cycles of the AC main line voltage after the initial plurality of half-cycles and throughout the on-time period.

[0018] Some examples may include a load control device configured to control power delivered from an alternating current (AC) power source to an electrical load, wherein the load control device includes a controllable conductor adapted to be coupled in series between the AC power source and the electrical load, wherein the AC power source is configured to generate an AC mainline voltage, and wherein the controllable conductor includes a semiconductor switch configured to conduct load current through the electrical load. The load control device may also include control circuitry configured to generate a drive signal to adjust the control time of the semiconductor switch during each half-cycle of the AC mainline voltage, thereby controlling the amount of power delivered to the electrical load. The load control device may include a closed-loop gate drive circuitry coupled to the semiconductor switch, wherein the closed-loop gate drive circuitry is configured to: receive the drive signal from the control circuitry, and in response to the drive signal, turn the semiconductor switch on or off at a control time during a half-cycle of the AC mainline voltage, and limit the amplitude of the load current conducted through the semiconductor switch to within a maximum current limit. The closed-loop gate drive circuit can be configured to adjust the maximum current limit from a first limit to a second limit during the on-time period of half a cycle of the AC main line voltage. In some examples, the second limit is smaller than the first limit. In some examples, the closed-loop gate drive circuit can be configured to: turn on the semiconductor switch at the control time when operating with a positive phase control technique; and turn off the semiconductor switch at the control time when operating with a reverse phase control technique.

[0019] A method can be performed by a load control device configured to control power supplied from an alternating current (AC) power source to an electrical load. The method may include generating a drive signal to adjust the control time of a semiconductor switch of the load control device during each half-cycle of the AC mains voltage, thereby controlling the amount of power supplied to the electrical load. The method may include controlling the drive signal to turn on the semiconductor switch during a control time within the half-cycle of the AC mains voltage, thereby maintaining the semiconductor switch on during an on-time period within the half-cycle of the AC mains voltage. The method may include setting a maximum current limit of a closed-loop gate drive circuit to a first limit for a period of time after the control time during the on-time period of the half-cycle of the AC mains voltage, wherein the closed-loop gate drive circuit is configured to limit the amplitude of the load current conducted through the semiconductor switch to the maximum current limit. The method may include setting the maximum current limit of the closed-loop gate drive circuit to a second limit after the expiration of the period of time during the on-time period of the half-cycle of the AC mains voltage, wherein the second limit is less than the first limit.

[0020] The method may include setting the maximum current limit to the first limit during a pulse period beginning at the control time during half a cycle of the AC main line voltage. The method may also include setting the maximum current limit to the second limit at the end of the pulse period and for the remainder of the conduction period of the half-cycle of the AC main line voltage. The pulse period may be approximately 500 microseconds. The method may include setting the maximum current limit to the first limit during the pulse period to allow the capacitance of a capacitive load to charge during half a cycle of the AC main line voltage.

[0021] The method may include: during an initial plurality of half-cycles of the AC main line voltage after the electrical load is turned on, within a pulse period following the control time of the semiconductor switch, setting the maximum current limit of the closed-loop gate drive circuit to the first limit. The method may also include: after the initial plurality of half-cycles of the AC main line voltage, while controlling the power of the electrical load, setting the maximum current limit of the closed-loop gate drive circuit to the second limit at the control time during a subsequent half-cycle of the AC main line voltage after the initial plurality of half-cycles.

[0022] This method may include shortening the duration of the pulse period during the initial half-cycles of the AC main line voltage after the electrical load is turned on.

[0023] The method may include setting the length of the pulse period to a second time period during a plurality of half-cycles after the electrical load is turned on. The method may also include setting the length of the pulse period to a first time period after the plurality of half-cycles and while controlling the power to the electrical load. In some examples, the first time period is approximately 500 microseconds, the second time period is approximately 2,000 microseconds, and the plurality of half-cycles is approximately 120 half-cycles.

[0024] The method may include: adjusting the maximum current limit within a range from the first limit to the second limit over multiple half-cycles of the AC main line voltage. The method may also include: linearly decreasing the maximum current limit within a range from the first limit to the second limit over multiple half-cycles of the AC main line voltage.

[0025] When operating with forward phase control technology, the method may include: setting the maximum current limit of the closed-loop gate drive circuit to the first limit during a period of time following the control time of the semiconductor switch, while controlling the power of the electrical load; and setting the maximum current limit of the closed-loop gate drive circuit to the second limit after the period of time following the conduction period of each half-cycle of the AC main line voltage, while controlling the power of the electrical load.

[0026] When operating with reverse phase control technology, the method may include setting a third limit on the maximum current of the closed-loop gate drive circuit during the entire on-time period of each half-cycle of the AC mains voltage, while controlling the power to the electrical load. In some examples, this third limit is equal to the first limit.

[0027] When using forward phase control technology, the method may include: controlling the drive signal to de-conduct the semiconductor switch at the beginning of each half-cycle of the AC main line voltage while controlling the power to the electrical load, and controlling the drive signal to conduct the semiconductor switch at a control time during each half-cycle of the AC main line voltage and for the remainder of each half-cycle of the AC main line voltage. When using reverse phase control technology, the method may include: controlling the drive signal to conduct the semiconductor switch at the beginning of each half-cycle of the AC main line voltage, and controlling the drive signal to de-conduct the semiconductor switch at a control time during each half-cycle of the AC main line voltage.

[0028] The method may include controlling the semiconductor switch to be non-conducting during a non-conducting period and on during a conducting period during one or more half-cycles of the AC main line voltage, so as to control the amount of power delivered to the electrical load. Attached Figure Description

[0029] Figure 1 This is a block diagram of an example load control device used to control the amount of power delivered to an electrical load.

[0030] Figure 2 This is a block diagram of an exemplary gate drive circuit configured to control the amount of power delivered to an electrical load.

[0031] Figure 3 A waveform example illustrating the operation of a load control device using positive phase control dimming technology is shown.

[0032] Figure 4 A waveform example illustrating the operation of a load control device using reverse phase control dimming technology is shown.

[0033] Figure 5 The diagram shows a waveform example illustrating the operation of a gate drive circuit using positive phase control dimming technology to turn on a semiconductor switch.

[0034] Figure 6 The diagram shows a waveform example illustrating the operation of a gate drive circuit using reverse phase control dimming technology to turn on a semiconductor switch.

[0035] Figure 7The diagram illustrates a waveform example of a gate drive circuit using positive phase control dimming technology and a limiting signal set to a first amplitude to turn on a semiconductor switch.

[0036] Figure 8 The diagram illustrates a waveform example of a gate drive circuit using positive phase control dimming technology and a limiting signal adjusted between a second amplitude and a first amplitude during the conduction period of half a cycle of the AC main line voltage to turn on a semiconductor switch.

[0037] Figure 9 A waveform example is shown illustrating another example operation of a gate drive circuit that uses positive phase control dimming technology and a limiting signal adjusted between a second amplitude and a first amplitude during the conduction period of half a cycle of the AC main line voltage to turn on a semiconductor switch.

[0038] Figure 10 The diagram illustrates a waveform example of a gate drive circuit using positive phase control dimming technology and a limiting signal that is linearly adjusted between a second amplitude and a first amplitude during the conduction period of half a cycle of the AC main line voltage to turn on a semiconductor switch.

[0039] Figure 11A This is a flowchart of an example process for setting the maximum current limit of a load control device based on the type of phase control technology configured for that load control device.

[0040] Figure 11B This is a flowchart of an example process for setting the maximum current limit of a load control device based on the type of phase control technology configured for that load control device.

[0041] Figure 11C This is a flowchart of an example process for adjusting the maximum current limit of a load control device during a pulse period in response to a command to start an electrical load.

[0042] Figure 12 This is a flowchart of an example process for controlling the maximum current limit of a load control device based on whether the electrical load coupled to the load control device is an inductive load. Detailed Implementation

[0043] Figure 1 This is a block diagram of an example load control device 100 (e.g., a dimmer switch) for controlling the amount of power supplied from an alternating current (AC) power source 104 to an electrical load such as a lighting load 102. The load control device 100 may include: a thermal terminal H coupled to the live wire side of the AC power source 104 for receiving the AC mains voltage V. AC; and a dimming hot terminal DH, which is coupled to the lighting load 102. The load control device 100 may also include a neutral terminal N, which can be adapted to be coupled to the neutral side of the AC power supply 104.

[0044] The load control device 100 may include a load conditioning circuit 110 (e.g., a dimming circuit). For example, the load conditioning circuit 110 may include a controllable conductive device having one or more semiconductor switches, such as two field-effect transistors (FETs) Q111 and Q112. The FETs Q111 and Q112 may be anti-coupled in series between a hot terminal H and a dimming hot terminal DH. The load conditioning circuit 110 may also include: a first feedback circuit, such as a first sensing resistor R113, which is coupled in series to the first FET Q111; and a second feedback circuit, such as a second sensing resistor R114, which is coupled in series to the second FET Q112. The nodes of the first sensing resistor R113 and the second sensing resistor R114 may be coupled to a common circuit terminal. In some examples, the controllable conductive device of the load conditioning circuit 110 may include a single FET in a full-wave bridge rectifier (e.g., coupled between the hot terminal H and the dimming hot terminal DH), and the load conditioning circuit 110 may include a single closed-loop gate drive circuit.

[0045] The load control device 100 may include, for example, a control circuit 120 of digital control circuitry, for controlling the load regulating circuit 110 to conduct load current I. LOAD The current intensity level L of the lighting load 102 is adjusted by means of this lighting load 102. PRES For example, the control circuit 120 can be configured to operate at high strength level L. HE (e.g., approximately 100%) and lower strength grade L LE Adjust the current intensity level L of the lighting load 102 between approximately 0.1-5% (for example). PRES The control circuit 120 may include one or more of a processor (e.g., a microprocessor), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or any suitable controller or processing device. The control circuit 120 may be configured to use phase-controlled dimming technology to control the controllable conductive devices of the load conditioning circuit 110 to turn FETs Q111 and Q112 on and off, thereby generating a dimming thermal voltage V across the lighting load 102 (e.g., between the dimming thermal terminal DH and the neutral terminal N). DH (e.g., phase control voltage). When the first FET Q111 is at the AC main line voltage V... AC When the first FET Q111 is turned on during the positive half-cycle, it can be configured to conduct the load current I. LOAD(e.g., load current I) LOAD The first part (of the circuit) runs from the hot terminal H through the first sensing resistor R113 to the circuit common terminal, and then through the second sensing resistor R114 and the body diode of the second FET Q112 to the dimming hot terminal DH. When the second FET Q112 is at the AC main line voltage V AC When turned on during the negative half-cycle, the second FET Q112 can be configured to conduct the load current I. LOAD (e.g., load current I) LOAD (The second part) flows from the dimming hot terminal DH through the second sensing resistor R114 to the circuit common terminal, and then through the first sensing resistor R113 and the body diode of the first FET Q111 to the hot terminal H.

[0046] Control circuit 120 can be configured to determine the AC main line voltage V of AC power supply 104. AC The time of the zero-crossing point. For example, the load control device 100 may include a zero-crossing detection circuit 130, which may be coupled to the hot terminal H and the neutral terminal N, and generate an indication of the AC main line voltage V. AC The zero-crossing signal V at the zero-crossing point ZC Then, the control circuit 120 can be configured relative to the AC main line voltage V. AC The zero-crossing point (e.g., based on the zero-crossing signal V) ZC At a predetermined time (e.g., at the trigger time or trigger angle), the FETs Q111 and Q112 of the load conditioning circuit 110 are turned on and / or turned off to generate a dimming thermal voltage V using phase-controlled dimming techniques such as forward phase-controlled dimming and / or reverse phase-controlled dimming. DH For example, control circuit 120 can use forward phase control dimming technology to control inductive loads and reverse phase control dimming technology to control capacitive loads. The dimming thermal voltage V... DH During each half-cycle, the control circuit 120 can be configured to control the controllable conductive device (e.g., FETs Q111, Q112) of the load conditioning circuit 110 to be non-conducting during non-conducting periods and conducting during conducting periods. Furthermore, the control circuit 120 can be configured to control the controllable conductive device of the load conditioning circuit 110 between a non-conducting state and a conducting state during transition periods (e.g., switching periods) between non-conducting and conducting periods. An example of a dimmer switch is described in more detail in commonly assigned U.S. Patent No. 8,664,881, entitled “TWO-WIREDIMMER SWITCH FOR LOW-POWER LOADS,” published March 4, 2014, the entire disclosure of which is hereby incorporated herein by reference.

[0047] The control circuit 120 can be configured to generate a dimming thermal voltage V across the lighting load 102 in each half-cycle. DH The control time (e.g., trigger time or phase angle) is adjusted in each half-cycle to control the amount of power delivered to the lighting load 102, thereby controlling the current intensity level L of the lighting load 102. PRES For example, the control circuit 120 can be configured to adjust the control time in each half-cycle to adjust the current intensity level L of the lighting load 102. PRES Towards target intensity level L TRGT Adjustments are made. The control circuit 120 can be configured to control FETs Q111 and Q112 using forward phase control dimming technology and / or reverse phase control dimming technology. When using forward phase control dimming technology, the control circuit 120 can de-conduct one or more of FETs Q111 and Q112 at the beginning of each half-cycle of the AC main line voltage (e.g., de-conducting the controllable conductor of the load conditioning circuit 110), and then turn on one or more of FETs Q111 and Q112 at a control time (e.g., trigger time) during that half-cycle (e.g., turning on the controllable conductor of the load conditioning circuit 110), after which the controllable conductor can remain on until the end of that half-cycle. When using reverse phase control dimming technology, the control circuit 120 can turn on one or more of the semiconductor switches Q111 and Q112 at the beginning of each half-cycle of the AC main line voltage (e.g., turn on the controllable conductive device of the load regulating circuit 110), and then turn off one or more of the semiconductor switches Q111 and Q112 at a control time during the half-cycle (e.g., turn off the controllable conductive device of the load regulating circuit 110), and after the half-cycle, the controllable conductive device can remain off until the end of the half-cycle.

[0048] The load regulation circuit 110 may further include: a first gate drive circuit 115 (e.g., a first closed-loop gate drive circuit) coupled to the gate of a first FET Q111 to control the first FET Q111; and a second gate drive circuit 116 (e.g., a second closed-loop gate drive circuit) coupled to the gate of a second FET Q112 to control the second FET Q112. The control circuit 120 may, for example, generate a first drive signal V. DR1 Second drive signal V DR2 The first drive signal and the second drive signal can be received by the first gate drive circuit 115 and the second gate drive circuit 116, respectively, to control FETs Q111 and Q112. The drive signal V DR1 V DR2The first gate drive circuit 115 and the second gate drive circuit 116, which can be respectively provided to the load conditioning circuit 110, are used to adjust the dimming thermal voltage V generated across the lighting load 102. DH Control time and / or load current I conducted through lighting load 102 LOAD The amplitude, for example, to control the current intensity level L of the lighting load 102. PRES The control circuit 120 can adjust the drive signal V. DR1 V DR2 The duty cycle (e.g., on-time) of each of them (e.g., for drive signal V) DR1 V DR2 Each of them uses the same duty cycle to adjust the current intensity level L of the lighting load 102. PRES Towards target intensity level L TRGT Adjustments will be made.

[0049] The first gate driving circuit 115 and the second gate driving circuit 116 can receive corresponding driving signals V from the control circuit 120. DR1 V DR2 and in response to the drive signal V DR1 V DR2 The corresponding FETs Q111 and Q112 are controlled to adjust the load current I conducted through the lighting load 102. LOAD The amplitude. For example, the first gate drive circuit 115 and the second gate drive circuit 116 can respond to the drive signal V. DR1 V DR2 And generate the corresponding gate control signal V GC1 V GC2 and the corresponding gate control signal V GC1 V GC2 The gates of the corresponding FETs Q111 and Q112 are supplied to turn FETs Q111 and Q112 on and off, respectively, and to control the current intensity level L of the lighting load 102. PRES Although in Figure 1 Not shown, but in some examples, the load control device 100 may include a first buffer circuit coupled between the gate of the first gate drive circuit 115 and the gate of the first FET Q111; and a second buffer circuit coupled between the gate of the second gate drive circuit 116 and the gate of the second FET Q112.

[0050] The load regulation circuit 110 may include a first feedback circuit and a second feedback circuit, such as a first sensing resistor R113 and a second sensing resistor R114, respectively. For example, the first sensing resistor R113 (e.g., the first feedback circuit) may be configured to generate a first feedback signal V. FB1It can have an indicator I of the load current I flowing through the first FET Q111 during the positive half-cycle. LOAD The amplitude of the first part. Furthermore, the second sensing resistor R114 (e.g., a second feedback circuit) can be configured to generate a second feedback signal V. FB2 It can have an indicator I of the load current flowing through the second FET Q112 during the negative half-cycle. LOAD The amplitude of the second part. First feedback signal V FB1 Second feedback signal V FB2 Together they can indicate the load current I conducted through the lighting load 102. LOAD The magnitude (e.g., load current I) LOAD (The sum of the first part and the second part). The first gate drive circuit 115 and the second gate drive circuit 116 can be configured to receive the first feedback signal V, respectively. FB1 Second feedback signal V FB2 and respectively respond to the first feedback signal V FB1 Second feedback signal V FB2 (e.g., using closed-loop control) to generate the first gate control signal V GC1 Second gate control signal V GC2 Since the first gate drive circuit 115 and the second gate drive circuit 116 use closed-loop control to generate the first gate control signal V. GC1 Second gate control signal V GC2 The first gate control signal V GC1 Second gate control signal V GC2 The amplitude can indicate the load current I. LOAD The amplitude. An example of a load control device providing closed-loop control of load current conducted through a lighting load is described in more detail in U.S. Patent No. 11,569,733, entitled “Load Control Device Having a Closed-Loop Gate Drive Circuit Including Overcurrent Protection,” issued January 31, 2023, the entire disclosure of which is incorporated herein by reference.

[0051] The first gate drive circuit 115 can receive the first feedback signal V. FB1 And can respond to the first drive signal V DR1 and the first feedback signal V FB1 And generate the first gate control signal V for controlling the first FET Q111 GC1 For example, the first gate drive circuit 115 can be configured to respond to the first feedback signal V. FB1The amplitude of the first gate control signal V is adjusted accordingly. GC1 The amplitude, so as to reduce the load current I LOAD The amplitude is directed towards the first target signal V by the first gate drive circuit 115. TRGT1 The target current, indicated by the amplitude, is adjusted. The first gate drive circuit 115 can be configured to respond to the first target signal V using closed-loop control (e.g., as described in more detail below). TRGT1 and the first feedback signal V FB1 And generate the load current I conducted through the first FET Q111. LOAD The amplitude of the first gate control signal V GC1 The first gate drive circuit 115 can be configured to receive a first limit signal V. LMT1 This signal can also be generated by the control circuit 120. The first gate drive circuit 115 can be configured to respond to the first limit signal V. LMT1 In the dimming heating voltage V DH During the conduction period of each half-cycle, a first target signal V is generated to control the first FET Q111. TRGT1 For example, the first target signal V of the first gate drive circuit 115 TRGT1 The amplitude can be set to a first maximum current limit I. LMT1 The first gate control circuit 115 can control the load current I during the on-time period of each positive half-cycle. LOAD The amplitude is controlled to the first maximum current limit.

[0052] The first gate drive circuit 115 can be configured to respond to the first drive signal V. DR1 In the dimming heating voltage V DH During the transition period of each half-cycle, a first target signal V is generated to control the first FET Q111. TRGT1 In some examples, the first target signal V of the first gate drive circuit 115 TRGT1 It can be based on the first driving signal V DR1 The shaped (e.g., waveform-shaped) target signal, and the first gate drive circuit 115 is responsive to the shaped target signal and the first feedback signal V. FB1 And generate the first gate control signal V for turning on the first FET Q111 GC1 To adjust the dimming voltage V during the transition period DH Shaping is performed (e.g., as described in more detail below). For example, control circuit 120 can be configured to generate a first drive signal V. DR1 Furthermore, the first gate drive circuit 115 can be configured to respond to the first drive signal V. DR1 And for the target signal VTRGT1 To undergo cosmetic surgery (e.g., to begin cosmetic surgery).

[0053] Similarly, the second gate drive circuit 116 can receive the second feedback signal V. FB2 And can respond to the second drive signal V DR2 and the second feedback signal V FB2 And generate a second gate control signal V for controlling the first FET Q111 GC1 For example, the second gate drive circuit 116 can be configured to respond to the second feedback signal V. FB2 The amplitude of the second gate control signal V is adjusted accordingly. GC2 The amplitude, so as to reduce the load current I LOAD The amplitude is directed towards the second target signal V by the second gate drive circuit 116. TRGT2 The target current indicated by the amplitude is adjusted. The second gate drive circuit 116 can be configured to respond to the second target signal V using closed-loop control (e.g., as described in more detail below). TRGT2 and the second feedback signal V FB2 And generate the load current I conducted through the second FET Q112. LOAD The amplitude of the second gate control signal V GC2 The second gate drive circuit 116 can be configured to receive a second limit signal V. LMT2 This signal can also be generated by the control circuit 120. The second gate drive circuit 116 can be configured to respond to the second limit signal V. LMT2 In the dimming heating voltage V DH During the conduction period of each half-cycle, a second target signal V is generated to control the second FET Q112. TRGT2 For example, the second target signal V of the second gate drive circuit 116 TRGT2 The amplitude can be set to a second maximum current limit I. LMT2 The second gate control circuit 116 can control the load current I during the on-time period of each negative half-cycle. LOAD The amplitude is controlled to the second maximum current limit.

[0054] The second gate drive circuit 116 can be configured to respond to the second drive signal V. DR2 In the dimming heating voltage V DH During the transition period of each half-cycle, a second target signal V is generated to control the second FET Q112. TRGT2 In some examples, the second target signal V of the second gate drive circuit 116 TRGT2 It can be based on the second driving signal V DR2The shaped (e.g., waveform-shaped) target signal, and the second gate drive circuit 116 is responsive to the shaped target signal and the second feedback signal V. FB2 And generate the second gate control signal V for turning on the second FET Q112. GC2 To adjust the dimming voltage V during the transition period DH Shaping is performed (e.g., as described in more detail below). For example, the control circuit 120 can be configured to generate the second drive signal V. DR2 Furthermore, the second gate drive circuit 116 can be configured to respond to the second drive signal V. DR2 And regarding the second target signal V TRGT2 To undergo cosmetic surgery (e.g., to begin cosmetic surgery).

[0055] The load regulation circuit 110 (e.g., the first gate drive circuit 115 and the second gate drive circuit 116) can be configured to provide overcurrent protection (e.g., inherent overcurrent protection and / or current limiting protection) for the load control device 100. In some examples, the first gate drive circuit 115 and the second gate drive circuit 116 can be configured to respond to a corresponding gate control signal V. GC1 V GC2 And limit the load current I conducted through the corresponding FETs Q111 and Q112. LOAD The amplitude. For example, when the first FET Q111 is turned on during the positive half-cycle, the first gate drive circuit 115 can be configured to conduct the load current I through the first FET Q111. LOAD The amplitude of the first part is limited by the first limiting signal V. LMT1 Indicated first maximum current limit I LMT1 Similarly, when the second FET Q112 is turned on during the negative half-cycle, the second gate drive circuit 116 can be configured to drive the load current I conducted through the second FET Q112. LOAD The amplitude of the second part is limited by the second limiting signal V. LMT2 Indicated second maximum current limit I LMT2 For example, the second maximum current limit I LMT2 It can be equal to the first maximum current limit I. LMT1 .

[0056] The load regulation circuit 110 may include a first overcurrent protection (OCP) circuit 117 and a second OCP circuit 118 for detecting overcurrent conditions in FETs Q111 and Q112, respectively, and controlling FETs Q111 and Q112, respectively, in response to detecting the overcurrent condition. For example, the first overcurrent protection circuit 117 may be configured to detect the overcurrent condition and, during a first tripping time T from the detection of the overcurrent condition... TRIP1 This then disables the first FET Q111. Similarly, the second overcurrent protection circuit 118 can be configured to detect the overcurrent condition and trip during a second tripping time T from the detection of the overcurrent condition. TRIP2 This then disables the second FET Q112. For example, the first overcurrent threshold I... TH OCP It can be equal to the second overcurrent threshold I. TH OCP2 And the first tripping time period T TRIP1 It can be equal to the second tripping time period T. TRIP2 The first overcurrent protection circuit 117 and the second overcurrent protection circuit 118 can be configured to receive a corresponding overcurrent protection (OCP) enable signal V. OCP-EN1 V OCP-EN2 The signal can be generated by control circuit 120 to enable overcurrent protection circuits 117 and 118 to detect overcurrent conditions and de-energize FETs Q111 and Q112. For example, control circuit 120 can be configured to enable overcurrent protection circuits 117 and 118 during the on-time period of each half-cycle.

[0057] The first overcurrent protection circuit 117 can receive (e.g., respond to) the first gate control signal V generated by the first gate drive circuit 115. GC1 The second overcurrent protection circuit 118 can receive (e.g., responsive to) the second gate control signal V generated by the second gate drive circuit 116. GC2 Because the first gate drive circuit 115 and the second gate drive circuit 116 use closed-loop control to generate the first gate control signal V. GC1 Second gate control signal V GC2 And the first gate control signal V GC1 Second gate control signal V GC2 The amplitude can indicate the load current I. LOAD The amplitude of the first overcurrent protection circuit 117 and the second overcurrent protection circuit 118 can be configured to respond to the first gate control signal V, respectively. GC1 Second gate control signal V GC2 And determine the load current I LOADOvercurrent conditions (e.g., in the first FET Q111 and / or the second FET Q112). For example, the first overcurrent protection circuit 117 can be configured to determine the first gate control signal V. GC1 When to indicate the load current I during the positive half-cycle LOAD The amplitude is at the first maximum current limit I LMT1 This is used to detect overcurrent conditions. Furthermore, the second overcurrent protection circuit 118 can be configured to determine the second gate control signal V... GC2 When to indicate the load current I during the negative half-cycle LOAD The amplitude is at the second maximum current limit I LMT2 This is used to detect overcurrent conditions.

[0058] The first overcurrent protection circuit 117 and the second overcurrent protection circuit 118 can be configured to control the first gate drive circuit 115 and the second gate drive circuit 116 respectively, so as to de-conduct the corresponding FETs Q111 and Q112 in response to detecting an overcurrent condition. The first gate drive circuit 115 and the second gate drive circuit 116 can be configured to respectively turn on the first gate control signal V GC1 Second gate control signal V GC2 The amplitude is driven to approximately zero volts to de-conduct the corresponding FETs Q111 and Q112. For example, the first gate drive circuit 115 can be configured to drive the first target signal V of the first gate drive circuit 115 to approximately zero volts to de-conduct the corresponding FETs Q111 and Q112. TRGT1 The amplitude is controlled to approximately zero volts to control the first gate control signal V. GC1 The amplitude is controlled to approximately zero volts. Furthermore, the second gate drive circuit 116 can be configured to control the amplitude of the second target signal V of the second gate drive circuit 116 to approximately zero volts. TRGT2 The amplitude is controlled to approximately zero volts to control the second gate control signal V. GC1 The amplitude is controlled to approximately zero volts. Although Figure 1 The load regulation circuit 110 is shown to include two different overcurrent protection circuits (e.g., a first overcurrent protection circuit 117 and a second overcurrent protection circuit 118), but the load regulation circuit 110 may also include a single overcurrent protection circuit that is responsive to a first gate control signal V. GC1 Second gate control signal V GC2 Both can be configured to control the first gate drive circuit 115 and the second gate drive circuit 116 in response to the detection of an overcurrent condition.

[0059] The load control device 100 may include a user interface 132. The user interface 132 may include one or more actuators (e.g., buttons) for receiving user input and / or one or more visual indicators for providing user feedback. For example, the user interface 132 may include a toggle actuator and / or an intensity adjustment actuator (e.g., a slider or a pair of up and down buttons) for controlling the lighting load 102. Control circuitry 120 may be configured to control load regulation circuitry 110 in response to actuation of the actuators of the user interface 132 to control the amount of power delivered to the lighting load 102. Furthermore, the user interface 132 may also include one or more light sources, such as light-emitting diodes (LEDs), for illuminating the visual indicators, for example, providing the status and / or current intensity level L of the lighting load 102. PRES Visual indicators, and / or selected preset visual indicators. For example, user interface 132 may include a vertically oriented linear array of visual indicators. Control circuitry 120 may be coupled to a light source for illuminating the visual indicators of user interface 132 to provide feedback.

[0060] The load control device 100 may include communication circuitry 134, such as wired or wireless communication circuitry. Communication circuitry 134 may be communicatively coupled to control circuitry 120 for communicating (e.g., sending and receiving) messages (e.g., digital messages). Communication circuitry 134 may be implemented as an external integrated circuit (IC) or as internal circuitry of control circuitry 120. For example, communication circuitry 134 may include a radio frequency (RF) transceiver coupled to an antenna for transmitting and / or receiving RF signals. Communication circuitry 120 may also include, for example, an RF transmitter for transmitting RF signals, an RF receiver for receiving RF signals, or an IR transmitter and / or receiver for transmitting and / or receiving infrared (IR) signals. Control circuitry 120 may be configured to receive messages including commands (e.g., control data) for controlling the lighting load 102 via communication circuitry 134. Control circuitry 120 may be configured to transmit messages including status information (e.g., feedback information) via communication circuitry 134.

[0061] The load control device 100 may include a memory 136. The memory 136 may be communicatively coupled to the control circuitry 120 for storing and / or retrieving, for example, operating settings, such as the current intensity level L of the lighting load 102. PRESMemory 136 may be implemented as an external integrated circuit (IC) or internal circuitry of control circuitry 120. Memory 136 may include a computer-readable or machine-readable storage medium that maintains computer-executable instructions to perform one or more programs and / or functions as described herein. For example, memory 136 may include computer-executable or machine-readable instructions that, when executed by control circuitry, configure control circuitry to provide one or more portions of the processes described herein. Control circuitry 120 may access instructions from memory 136 for execution to cause control circuitry 120 to operate as described herein or to operate one or more other means as described herein. Memory 136 may include computer-executable instructions for executing configuration software. For example, operating characteristics stored in memory 136 may be configured during the configuration process of the load control device 100.

[0062] Load control device 100 may include power supply 138. This power supply 140 may receive AC mains voltage V. AC It can generate one or more direct current (DC) voltages to power the circuitry of the load control device 100. For example, the power supply 140 can be configured to generate a first DC supply voltage, such as a FET supply voltage V. FET-SUP (For example, approximately 12V) is used to power the gate drive circuits 115 and 116 to drive the corresponding FETs Q111 and Q112. Furthermore, this power supply 140 can be configured to generate a second DC voltage, such as the supply voltage V. CC It is used to supply power to the control circuit 120 and / or other low-voltage circuits of the load control device 100.

[0063] Figure 2 It is a load control device 200 (such as Figure 1 The block diagram shows an example load regulation circuit 210 of the load control device 100. This load regulation circuit 210 may include a field-effect transistor (FET) Q212, which may be coupled in series to a lighting load (e.g., lighting load 102) for controlling the load current I conducted through the lighting load. LOAD This controls the current intensity level L of the lighting load. PRES . Figure 2 The load regulation circuit 210 shown can be Figure 1 An example of half of the load regulation circuit 110 shown. For example, the FET Q212 could be an example of FET Q111 and / or FET Q212, and Figure 2 The circuit system of the load regulation circuit 210 shown can be replicated for each of FETs Q111 and Q112 to achieve... Figure 1The load regulation circuit 110 (e.g., a FET reverse-connected in series between the hot terminal H and the dimming hot terminal DH) can be coupled to the hot terminal (e.g., hot terminal H) of the load control device 200 to receive the AC mainline voltage V. AC For example, the load regulation circuit 210 may be coupled in series between the hot terminal of the load control device 200 and the lighting load (e.g., via a body diode with an additional FET in the load regulation circuit 210). In some examples, the load regulation circuit 210 may include a single FET (e.g., as shown in the image). Figure 2 The FET Q212 shown is shown, and the load regulation circuit 210 can be coupled inside a full-wave bridge rectifier (e.g., where the full-wave bridge rectifier is coupled between the hot terminal H and the dimming hot terminal DH, and the circuit common terminal is coupled to the dimming hot terminal DH).

[0064] The load control device 200 may include, for example, a control circuit 250 of digital control circuitry, for controlling the load regulating circuit 210 to conduct load current I. LOAD This lighting load allows for the adjustment of its current intensity level L. PRES For example, the control circuit 250 can be configured to operate at high strength level L. HE (e.g., approximately 100%) and lower strength grade L LE Adjust the current intensity level L of the lighting load between approximately 0.1-5% (e.g., 0.1-5%). PRES The control circuit 250 may include one or more of a processor (e.g., a microprocessor), a microcontroller, a programmable logic device (PLD), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or any suitable controller or processing device. The control circuit 250 may be configured to use phase-controlled dimming technology to control the controllable conductive device of the load conditioning circuit 210 to turn FET Q212 on and off, thereby generating a dimming thermal voltage V across the lighting load. DH (e.g., phase control voltage). In the dimming heating voltage V... DH During each half-cycle, the control circuit 250 can be configured to control the load conditioning circuit 210 such that FETQ212 is not turned on during the non-conducting period and is turned on during the conducting period. In addition, the control circuit 250 can be configured to control the load conditioning circuit 210 to control FETQ212 between the non-conducting state and the conducting state during the transition period (e.g., switching period) between the non-conducting period and the conducting period.

[0065] The load regulation circuit 210 may include a feedback circuit, such as one coupled in series with FET Q212, for conducting load current I. LOADThe sensing resistor R214 (e.g., one of resistors R113 and R114) is used. Furthermore, the load regulation circuit 210 may include a gate drive circuit 220 (e.g., one of gate drive circuits 115 and 116) coupled to the gate of FET Q212 for turning FET Q212 on and off. The control circuit 250 can control the drive signal V. DR (For example, drive signal V) DR The amplitude of the drive signal (which can be controlled to be high or low) can be received by the gate drive circuit 220 to control FET Q212. This drive signal V... DR1 It can be provided to the gate drive circuit 220 for adjusting the dimming thermal voltage V generated across the lighting load. DH Control time and / or load current I conducted through lighting load LOAD The amplitude, for example, to control the current intensity level L of the lighting load. PRES The control circuit 250 can be configured to adjust the drive signal V. DR The duty cycle (e.g., on time) is used to adjust the current intensity level L of the lighting load. PRES Towards target intensity level L TRGT Adjustments will be made.

[0066] The gate drive circuit 220 can receive a drive signal V from the control circuit 250. DR and in response to the drive signal V DR The FET Q212 is controlled to adjust the load current I conducted through the lighting load. LOAD The amplitude. For example, the gate drive circuit 220 can respond to the drive signal V. DR The gate control signal V is generated to control FET Q212. GC The load regulation circuit 210 may include a buffer circuit 216, which is coupled in series between the gate drive circuit 220 and the gate of FET Q212. The buffer circuit 216 can receive a control signal V from the gate drive circuit 220. GC And can buffer the gate control signal V GC To generate a gate voltage V at the gate of FET Q212. G Gate signal V G The conductivity of FET Q212 can be controlled. For example, the gate signal V... G via gate control signal V GC The FET Q212 can be turned on or off. In some examples, the load regulation circuit 210 may not include the buffer circuit 216.

[0067] The gate drive circuit 220 can be configured to receive a feedback signal V that can be generated by the sensing resistor R214 (e.g., a feedback circuit).FB The feedback signal V FB It can have an indicator I of the load current flowing through FET Q212 LOAD The amplitude of the feedback signal V. FB The amplitude (e.g., the voltage generated across the sensing resistor R214) can be related to the load current I. LOAD The amplitude is proportional to the value. The gate drive circuit 220 can be configured to respond to the feedback signal V. FB (e.g., using closed-loop control) to generate the gate control signal V GC Because the gate drive circuit 212 uses closed-loop control to generate the gate control signal V. GC The gate control signal V GC The amplitude can indicate the load current I. LOAD The amplitude. Furthermore, in some examples, the control circuit 250 can receive a feedback signal V. FB Furthermore, the control circuit can be configured to operate based on the feedback signal V. FB (for example, due to the load current I) LOAD The amplitude and the feedback signal V generated by the sensing resistor R214 FB The load current I conducted through FET Q212 is determined by the magnitude of the load current (which is proportional to the amplitude of the load current). LOAD The point crossing zero.

[0068] In order to provide the load current I LOAD For closed-loop control of the amplitude, the gate drive circuit 220 may include an operational amplifier circuit 222. The operational amplifier circuit 222 may be configured to receive a feedback signal V from the sensing resistor R214. FB The operational amplifier circuit 222 may also have an inverting input terminal configured to receive the target signal V. TRGT The non-inverting input terminal of the target signal indicates the target amplitude I. TRGT The load current I can be controlled towards the target amplitude. LOAD The amplitude of the target signal V. The operational amplifier circuit 222 can be based on this target signal V. TRGT and the feedback signal V FB To generate the gate control signal V at the output terminal GC For example, the operational amplifier circuit 222 can adjust the gate control signal V. GC To control FET Q212, thereby directing it toward the target signal V. TRGT The amplitude indicates the target amplitude I TRGT Controlling load current I LOAD The amplitude. Operational amplifier circuit 222 can refer to the common terminal of gate drive circuit 220 (e.g., feedback signal V). FB (Referencing common terminal). As mentioned earlier, the feedback signal VFB The amplitude can be related to the load current I. LOAD The amplitude is proportional to the load current I. Therefore, the operational amplifier circuit 222 can respond to the load current I. LOAD The amplitude of the gate control signal V is controlled by the value of the gate control signal. GC The amplitude. Some lighting loads, such as LED light sources, are capacitive loads, which may cause changes in the load voltage across the lighting load (e.g., dimming thermal voltage). These changes do not represent the load current I. LOAD The amplitude (e.g., with load current I) LOAD The amplitude is proportional to the signal strength. Since both the sensing resistor R214 and the operational amplifier circuit 222 are referenced to a common terminal, the operational amplifier circuit 222 can respond to (e.g., only to) the load current I. LOAD The amplitude is independent of the amplitude of the load voltage across the lighting load.

[0069] The gate drive circuit 220 may include a target voltage setting circuit 224, which may be configured to generate a target signal V received by the operational amplifier circuit 222. TRGT The target voltage setting circuit 224 of the gate drive circuit 220 can be configured to receive a limiting signal V. LMT The limiting signal can be generated by the control circuit 250. The target voltage setting circuit 224 can be configured to respond to the limiting signal V. LMT In the dimming thermal voltage V DH During the conduction period of each half-cycle, a target signal V is generated to control the FETQ212. TRGT The target voltage setting circuit 224 can be configured to set the voltage based on the limiting signal V. LMT (e.g., limiting signal V) LMT The amplitude of the target signal V is used to set the target signal V. TRGT The amplitude. For example, the target signal V of the first gate drive circuit 115. TRGT The amplitude (e.g., based on the limiting signal V) LMT Maximum current limit I can be set. LMT The gate control circuit 220 can control the load current I during the on-time period of each half-cycle. LOAD The amplitude is controlled to this maximum current limit. For example, to limit the maximum current I... LMT The amplitude control is given by two different corresponding amplitudes, and the control circuit 250 can be configured to generate a limiting signal V with the two amplitudes. LMT For example, a first amplitude such as the lower limit (e.g., approximately the circuit common terminal or zero volts) and a second amplitude such as the upper limit (e.g., approximately the supply voltage V). CC For example, the control circuit 250 can be configured to adjust the limit signal V. LMTThe amplitude (e.g., adjusted to approximately the common terminal of the circuit) is used to make the target signal V TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 This limits the maximum current I. LMT Adjust to the first limit amplitude I MAG1 (For example, approximately 8A). Furthermore, the control circuit 250 can be configured to adjust the limit signal V. LMT The amplitude (e.g., adjusted to approximately the supply voltage V) CC ), to transmit the target signal V TRGT The amplitude is adjusted to the second limiting signal amplitude V. MAG2 This limits the maximum current I. LMT Adjust to the second limit amplitude I MAG2 (For example, approximately 20A). In some examples, the control circuit 250 can be configured to adjust the limit signal V. LMT The amplitude, so as to make the target signal V TRGT The amplitude of the first limiting signal amplitude V MAG1 With the second limiting signal amplitude V MAG2 Adjustments are made between these values ​​to limit the maximum current I. LMT First limiting amplitude I MAG1 With the second limiting amplitude I MAG2 Adjustments are made between these parameters. For example, the maximum current limit I... LMT The amplitude can be compared with the limiting signal V LMT The amplitude is proportional to the value. The control circuit 250 may, for example, include a digital-to-analog converter (DAC) for adjusting the limiting signal V. LMT The amplitude. Furthermore, the control circuit 250 may include a filter circuit (e.g., a resistor-capacitor filter circuit) to generate an adjustment limit signal V in response to a pulse width modulation (PWM) signal. LMT The amplitude.

[0070] The gate drive circuit 220 may further include an on circuit 226 and an off circuit 228 for controlling the target signal V during the transition period between the non-conducting and conducting periods of each half-cycle (e.g., depending on whether the control circuit 250 uses forward phase control dimming or reverse phase control dimming). TRGT The generation of the target voltage setting circuit 224 is configured to, during the transition period, base the target voltage setting circuit 224 on the turn-on signal V generated by the turn-on circuit 226 when using positive phase control dimming technology. T-ON To generate the target signal V TRGT The enabling circuit 226 can be configured to receive a drive voltage V from the control circuit 250. DR And generate the enable signal V T-ONWhen using positive phase control dimming technology, the target voltage setting circuit 224 can be based on the on signal V during the transition period. T-ON And then during the conduction period, based on the limiting signal V LMT To generate the target signal V TRGT .

[0071] The enabling circuit 226 can be configured to respond to the control drive signal V from the control circuit 250. DR To turn on FET Q212 during the control time of half-cycle (e.g., in response to drive signal V). DR The amplitude of the signal becomes high at the control time during each half-cycle, and the turn-on signal V is generated. T-ON (For example, turn on signal V) T-ON The amplitude is controlled to be above approximately zero volts. For example, the target voltage setting circuit 224 can be configured to set the target signal V during the transition period. TRGT The amplitude control is approximately equal to the turn-on signal V. T-ON The amplitude. In some examples, the enable circuit 226 can generate an enable signal V. T-ON So that the target signal V TRGT It has, for example, a linear or exponential shape during the transition period. In other examples, the turn-on circuit 226 may be based on a drive signal V. DR (e.g. from drive signal V) DR The shaped target signal V is generated starting when the amplitude becomes high. TRGT (For example, having an amplitude with respect to time adjustment during the transition period). During the transition period of the positive half-cycle, the gate drive circuit 220 can be based on the gate control signal V. GC The gate drive circuit 220 controls FET Q212 in the linear region to adjust its impedance (e.g., drain-source impedance). This gate drive circuit 220 controls FET Q212 in response to the feedback signal V. FB By adjusting the impedance of FET Q212, the signal is directed toward the target signal V. TRGT Indicated target amplitude I TRGT Controlling load current I LOAD The amplitude of the load current I LOAD The shape follows the target signal V for most or all of the transition period. TRGT Shape (e.g., turn-on signal V) T-ON (shape).

[0072] When using reverse phase control dimming technology, the target voltage setting circuit 224 can be configured to, during the transition period, base its signal on the off signal V generated by the off circuit 228. T-OFF To generate the target signal V TRGTThe shutdown circuit 228 can be configured to receive a drive voltage V from the control circuit 250. DR And generate a turn-off signal V T-OFF Furthermore, the shutdown circuit 228 can be configured to receive a drain voltage signal V from the drain voltage sensing circuit 218. DV (For example, a second feedback signal), the drain voltage sensing circuit 218 can be coupled to FET Q212 (for example, coupled to the drain of FET Q212). The drain voltage sensing circuit 218 can detect the amplitude of the voltage generated across FET Q212 and can generate a drain voltage signal V. DV This causes the drain voltage signal V to... DV The amplitude indicates the magnitude of the voltage across FET Q212. When using reverse phase control dimming technology, this target voltage setting circuit 224 can set the voltage based on the limit signal V during the on-time period. LMT And during the transition period based on the turn-off signal V T-ON and drain voltage signal V DV To generate the target signal V TRGT .

[0073] The shutdown circuit 228 can be configured to respond to the control drive signal V controlled by the control circuit 250. DR To de-conduct FET Q212 during the control time of half-cycle (e.g., in response to drive signal V). DR The amplitude of becomes low at the control time and further responds to the drain voltage signal V. DV ), and begin to target the turn-off signal V T-OFF Perform shaping (e.g., start towards the zero-volt control off signal V) T-OFF (amplitude). For example, the target voltage setting circuit 224 can be configured to set the target signal V during the transition period. TRGT The amplitude control is approximately equal to the turn-off signal V. T-OFF The amplitude. In some examples, the shutdown circuit 228 can generate a shutdown signal V. T-OFF So that the target signal V TRGT It has, for example, a linear or exponential shape during the transition period. In other examples, the shutdown circuit 228 may be based on the drive signal V. DR and / or drain voltage signal V DV To generate the shaped target signal V TRGT (For example, having an amplitude with respect to time adjustment during the transition period). During the transition period of the negative half-cycle, the gate drive circuit 220 can be based on the gate control signal V. GC The gate drive circuit 220 controls FET Q212 in the linear region to adjust its impedance (e.g., drain-source impedance). This gate drive circuit 220 controls FET Q212 in response to the feedback signal V.FB By adjusting the impedance of FETQ212, the signal is directed towards the target signal V. TRGT Indicated target amplitude I TRGT Controlling load current I LOAD The amplitude of the load current I LOAD The shape follows the target signal V for most or all of the transition period. TRGT Shape (e.g., off signal V) T-OFF (shape).

[0074] The target voltage setting circuit 224 can be based on a limit signal V from the control circuit 250. LMT The enable signal V from enable circuit 226 T-ON (e.g., in response to drive signal V) DR ) and / or the shutdown signal V from the shutdown circuit 228 T-OFF (e.g., in response to drive signal V) DR To generate the target signal V TRGT For example, the target voltage setting circuit 224 can be used as a combination circuit and will limit the signal V. LMT , Enable signal V T-ON and / or turn-off signal V T-OFF One or more of them are combined to generate the target signal V. TRGT The gate drive circuit 220 (e.g., operational amplifier circuit 222) is responsive to the target signal V. TRGT and feedback signal V FB And generate gate control signal V GC During the conduction period of each half-cycle, the gate drive circuit 220 can be based on the gate control signal V. GC To control FET Q212 in the saturation region.

[0075] The gate drive circuit 220 of the load regulation circuit 210 can be configured to provide overcurrent protection (e.g., inherent overcurrent protection and / or current limiting protection) for the load control device 200. In some examples, the gate drive circuit 220 can be configured to respond to a gate control signal V. GC And limit the load current I conducted through FET Q212 LOAD The amplitude. For example, when FETQ212 is turned on, the gate drive circuit 220 can be configured to conduct the load current I through FETQ212. LOAD The amplitude is limited by the limiting signal V LMT Indicated maximum current limit I LMT When the load current I is conducted through FET Q212 LOAD The amplitude is at the maximum current limit I LMTAt that time, FET Q212 can operate in the linear region.

[0076] The load regulation circuit 210 may also include an overcurrent protection (OCP) circuit 230 (e.g., overcurrent protection circuits 117, 118). The overcurrent protection circuit 230 may include an overcurrent detection circuit 232 and an overcurrent control circuit 234. The overcurrent detection circuit 232 may be configured to detect an overcurrent condition and generate an overcurrent detection signal V indicating the overcurrent condition. OCD The overcurrent detection circuit 232 of the overcurrent protection circuit 230 can receive (e.g., respond to) the gate control signal V generated by the gate drive circuit 220. GC Because the gate drive circuit 220 uses closed-loop control to generate the gate control signal V. GC1 And the gate control signal V GC The amplitude indicates the load current I. LOAD The amplitude of the overcurrent detection circuit 232 is such that it can be configured to respond to the gate control signal V. GC And detecting (e.g., in FET Q212) the load current I LOAD The overcurrent condition in the circuit. For example, the first gate drive circuit 115 can be configured to determine the gate control signal V. GC When to indicate load current I LOAD The amplitude is at the maximum current limit I LMT This is used to detect overcurrent conditions.

[0077] The overcurrent detection circuit 232 can be configured to receive an overcurrent protection (OCP) enable signal V from the control circuit 250. OCP-EN This is used to enable and disable the overcurrent protection circuit 230. The overcurrent detection circuit 232 can be configured to detect when the overcurrent protection circuit 230 is enabled (e.g., in response to an overcurrent protection enable signal V). OCP-EN ), control overcurrent detection signal V OCD To indicate an overcurrent condition. The overcurrent detection circuit 232 can be configured to trip during a tripping period T from the first detection of an overcurrent condition. TRIP Then, control the overcurrent detection signal V OCD To indicate overcurrent conditions. The control circuit 250 can be configured to enable the overcurrent protection circuit 230 (e.g., during the conduction period of each half-cycle) to indicate overcurrent conditions. Figure 5 and Figures 7-10 (As shown). For example, when operating using positive phase control technology, the control circuit 250 can [operate from control time t] CNTL After a certain time delay, an OCP enable signal V is generated. OCP-EN (For example, the OCP enable signal V) OCP-EN Towards the supply voltage VCC (Drive is high). For example, the control circuit 250 can be activated from the control time t. CNTL Start time period T T-ON (For example, approximately 50 microseconds) after which an OCP enable signal V is generated. OCP-EN The control circuit can enable the OCP signal V at the next zero-crossing event. OCP-EN (For example, towards the circuit common terminal) Driven low. Thus, the control circuit 250 can be configured to enable the overcurrent protection circuit 230 during the conduction period of each half-cycle.

[0078] The overcurrent control circuit 234 can be configured to receive an overcurrent detection signal V from the overcurrent detection circuit 232. OCD and in the overcurrent detection signal V OCD Control current detection signal V OCD After indicating an overcurrent condition, an overcurrent protection signal V is generated to prevent FETQ212 from conducting. OCP The overcurrent control circuit 234 can be configured to respond to an overcurrent detection signal V. OCD Control overcurrent detection signal V OCD The gate drive circuit 220 is controlled to prevent FET Q212 from conducting by indicating an overcurrent condition. The gate drive circuit 220 can be configured to control the gate control signal V... GC The amplitude is driven to approximately zero volts in response to the overcurrent protection signal V. OCP This prevents FET Q212 from conducting. For example, the target voltage setting circuit 224 can be configured to receive an overcurrent protection signal V. OCP and the target signal V of the first gate drive circuit 115 TRGT The amplitude is controlled to approximately zero volts to control the gate control signal V. GC The amplitude is controlled to approximately zero volts.

[0079] The overcurrent control circuit 234 can be configured to trip during a time period T from the time the overcurrent detection circuit 232 first detects an overcurrent condition. TRIP Subsequently, FET Q212 is de-energized. The overcurrent overcurrent control circuit 234 can be configured to latch FET Q212 into a non-energized state for the remainder of the current half-cycle in response to detecting an overcurrent condition. The overcurrent overcurrent control circuit 234 can be configured to receive an overcurrent protection reset signal V. OCP-RST The signal can be generated by the control circuit 250, and the overcurrent overload control circuit 234 can be configured to respond to the overcurrent protection reset signal V. OCP-RST Unlocking FET Q212 from its non-conducting state allows it to respond to the gate control signal V. GCThis causes it to be turned on again. For example, the control circuit 250 can be configured to control the overcurrent protection reset signal V at the end of each half-cycle. OCP-RST This unlocks FET Q212 from the non-conducting state.

[0080] The control circuit 250 can be configured to receive an overcurrent detection signal V from the overcurrent detection circuit 232. OCD and in response to the overcurrent detection signal V OCD The load control device 200 is provided with overcurrent protection (e.g., redundant overcurrent protection). For example, when the overcurrent detection signal V... OCD When an overcurrent condition is indicated, the control circuit 250 can be configured to control the drive signal V. DR This prevents FET Q212 from conducting. If the overcurrent condition continues to repeat (e.g., for multiple half-cycles, such as 10 consecutive half-cycles), the control circuit 250 can be configured to turn off the lighting load for a period of time (e.g., a few seconds) using FET Q212, and then attempt to turn the lighting load back on.

[0081] When using forward phase control dimming technology, the control circuit 250 can control the drive signal V at the beginning of a half-cycle. DR To turn off FET Q212 (e.g., turn off the drive signal V) DR The amplitude is controlled to be low towards the common terminal of the circuit. Furthermore, this control circuit 250 can control the overcurrent protection enable signal V. OCP-EN The overcurrent protection circuit 230 is disabled during the non-conducting period of the half-cycle. During the control time of the half-cycle, the control circuit 250 can be configured to control the drive signal V. DR To turn on FET Q212 (e.g., to turn on the drive signal V) DC The amplitude is oriented towards the supply voltage V CC Control is high), so that the drive signal V DR An edge (e.g., rising edge) is generated in response to the drive signal V. DR At this edge, the target voltage setting circuit 224 can set the target voltage V during the transition period of a half-cycle. TRGT Set to equal to the enable signal V T-ON As mentioned above, the conduction signal V T-ON It can be shaped. At the start of the conduction period (e.g., at the end of the transition period), the control circuit 250 can be configured to control the overcurrent protection enable signal V. OCP-EN To enable the overcurrent protection circuit 230 and control the limiting signal V LMT To set the maximum current limit I LMT The gate drive circuit 220 can control the load current I during the half-cycle conduction period, adjusting the amplitude of the load current I. LOADThe amplitude is controlled to the maximum current limit.

[0082] When using reverse phase control dimming technology, the control circuit 250 can control the drive signal V at the beginning of a half-cycle. DR To turn on FET Q212 (e.g., to turn on the drive signal V) DR The amplitude is oriented towards the supply voltage V CC (Control is high). In some examples, the control circuit 250 may have already set the drive signal V at the beginning of the half-cycle. DR The amplitude is oriented towards the supply voltage V CC With the drive signal high, the control circuit 250 only needs to maintain the drive signal V. DR The amplitude is adjusted to turn on FET Q212 at the start of a half-cycle. Furthermore, the control circuit 250 can control the overcurrent protection enable signal V. OCP-EN To enable the overcurrent protection circuit 230 and control the limiting signal V LMT To set the maximum current limit I LMT The gate control circuit 220 can control the load current I during the half-cycle conduction period, adjusting the amplitude of the load current I. LOAD The amplitude is controlled to this maximum current limit. During the control time of the half-cycle, the control circuit 250 can be configured to control the drive signal V. DR To turn off FET Q212 (e.g., turn off the drive signal V) DC The amplitude is controlled to be low at the common terminal of the circuit, so that the drive signal V DR An edge (e.g., falling edge) is generated during the conduction period. At the end of the conduction period (e.g., at the beginning of the transition period), the control circuit 250 can be configured to control the overcurrent protection enable signal V. OCP-EN To disable the overcurrent protection circuit 230.

[0083] In response to drive signal V DR At the edge, the gate drive circuit 220 can be configured to decrease (e.g., begin to decrease) the target voltage V with respect to time. TRGT The amplitude. For example, the shutdown circuit 228 can turn off the shutdown signal V. T-OFF The amplitude is set to a predetermined value, for example, approximately the circuit common terminal, to limit the maximum current I. LMT The amplitude is set to the first limit amplitude I. MAG1 (For example, approximately 8A). Thereafter, the shutdown circuit 228 can gradually decrease the shutdown signal V. T-OFF The amplitude is until the drain voltage signal V from the drain voltage sensing circuit 218 is reached. DV Indicates that the voltage across FET Q212 has started to rise (e.g., has exceeded the drain voltage threshold V). THThis indicates that the FET has begun to de-conduct. Once the magnitude of the voltage generated across FET Q212 (e.g., determined by the drain voltage signal V) is reached... DV The indicated amplitude exceeds the drain voltage threshold V. TH The shutdown circuit 228 can begin to turn off the shutdown signal V. T-OFF From the current amplitude (e.g., in the drain voltage signal V) DV The voltage across FET Q212 indicates that the voltage level has exceeded the drain voltage threshold V. TH The amplitude of the voltage is shaped to zero volts. The target voltage setting circuit 224 can set the target voltage V during the remainder of the half-cycle transition period. TRGT Set to equal to the off signal V T-OFF .

[0084] The load control device 200 can be configured to control a capacitive load using reverse phase control dimming technology. The capacitive load may be characterized by a large capacitance that needs to be charged when the capacitive load is turned on and / or during normal operation as it discharges. The capacitance of the capacitive load may require a considerable charging current to be drawn by the load control device 200 to charge the capacitor when it is first turned on and / or during recharging in each half-cycle. When using reverse phase control dimming technology, the control circuit 250 can be configured to control the limit signal V. LMT To transmit the target signal V TRGT The amplitude is adjusted to the second limiting signal amplitude V. MAG2 (e.g., during the length of the conduction period), thereby limiting the maximum current I. LMT The amplitude is set to, for example, a second limiting amplitude I. MAG2 A larger amplitude (e.g., approximately 20A) is used to allow FETQ212 to properly conduct the charging current of the capacitive load. Since the charging current may only last for a short time, the conduction of the charging current may not damage FETQ212, and the overcurrent protection circuit 230 may not need to turn off FETQ212 to protect it.

[0085] Furthermore, the load control device 200 can be configured to control inductive loads using forward phase control dimming technology. Some inductive loads may saturate when an unbalanced current with a direct current (DC) component is conducted through them. For example, when an inductive load conducts an unbalanced current with a large peak amplitude above the saturation threshold in at least one half-cycle of a half-cycle, the inductive load may be prone to overheating and / or damage. In some cases, the saturation threshold may be less than the maximum current limit I of the overcurrent protection circuit 230. LMT Therefore, when using positive phase control dimming technology, the control circuit 250 can be configured to control the limiting signal V. LMTTo transmit the target signal V TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 This limits the maximum current I. LMT The amplitude is set to, for example, a first limiting amplitude I. MAG1 A smaller amplitude (e.g., approximately 8A) is used to allow the overcurrent protection circuit 230 to properly protect the inductive load from large load currents. This first limiting amplitude I... MAG1 It can be less than the second limit amplitude I MAG2 For example, this can prevent inductive loads from saturating and / or overheating when using positive phase control technology.

[0086] However, in some examples, the load control device 200 can be configured to control the capacitive load using a forward phase control dimming technique. When FET Q212 is turned on at the control time (e.g., trigger time) in each half-cycle, the capacitive load can be configured to conduct a large but short-lived charging current spike to charge the capacitance of the capacitive load. If the capacitive load cannot conduct the large charging current spike, it may not function properly during normal operation (e.g., the capacitive load will be unable to establish an internal power supply or bus voltage to operate its electrical components, and / or FET Q212 may operate in the linear region and block the charging current). However, the amplitude of the charging current spike may exceed the maximum current limit I. LMT When using positive phase control dimming technology (e.g., to accommodate inductive loads), this maximum current limit can be set to a first limit amplitude I. MAG1 As a result, capacitive loads may not be able to draw charging current properly through FET Q212, and the capacitance of the capacitive load may take longer to charge, which could affect the current intensity level L of the lighting load. PRES Flickering and / or unexpected adjustments occur.

[0087] Therefore, in some examples, when using positive phase control dimming technology, the control circuit 250 can be configured to increase the maximum current limit I for a short period of time after (e.g., immediately after) the control time (e.g., the trigger time). LMT The amplitude, and then the maximum current I is limited during the remainder of the conduction period of that half-cycle. LMT Adjust to a smaller amplitude. For example, the control circuit 250 can be configured to adjust the amplitude during the pulse period T starting from the charging time. PULSE Internal maximum current limit I LMT Adjusted to the second limiting amplitude I MAG2 And then during the remainder of the conduction period of that half-cycle, the maximum current I is limited. LMT Adjusted to the first limiting amplitude I MAG1For example, the control circuit 250 can control the pulse duration T. PULSE The length is set to the first time period T P1 (e.g., about 500µs) to allow the capacitor of the capacitive load to charge properly in each half-cycle.

[0088] In some examples, the load control device 200 may be configured to control an incandescent lamp (e.g., a resistive load) using positive phase control dimming technology. An incandescent lamp may have low resistance when it is not energized (e.g., off) and is therefore cold. The resistance of the incandescent lamp may increase after it has been energized for a period of time (e.g., and thus becomes hot). Due to its low resistance when cold, the incandescent lamp may draw more current (e.g., surge current) when it is first turned on than after it has been energized for a period of time. The magnitude of the surge current conducted by the incandescent lamp when it is first turned on may exceed the maximum current limit I. LMT First limit amplitude I MAG1 And so, if the maximum current limit I LMT Set to the first limiting amplitude I MAG1 If this happens, the incandescent lamp load may not be able to properly conduct the surge current. This could cause the incandescent lamp to take longer to heat up, potentially affecting the lamp's current intensity rating (L). PRES It takes longer to reach the appropriate level—even during the pulse duration T. PULSE During the period (e.g., the length of the first time period T) P1 The maximum current limit I has been increased. LMT The amplitude (e.g., the second limiting amplitude I) MAG2 The same applies. Therefore, when the lighting load is turned on, the control circuit 250 can be configured to increase (e.g., temporarily increase) the pulse duration T for a period of time. PULSE The length is adjusted to allow the incandescent lamp to conduct surge current. For example, when the lighting load is turned on, the control circuit 250 can be configured to return to the first time period T. P1 Previously, the pulse duration T was divided into multiple half-cycles (e.g., approximately 120 half-cycles). PULSE The length increases to the second time period T P2 (For example, approximately 2,000 µs).

[0089] In some examples, when using positive phase control dimming technology, the control circuit 250 can be configured to limit the maximum current I for a short period of time after (e.g., immediately after) the control time (e.g., the trigger time). LMT The amplitude increases to a constant amplitude, and then the maximum current limit I decreases with respect to time. LMT The amplitude, and then the maximum current I is limited during the remainder of the half-cycle conduction period. LMTMaintain a smaller amplitude. For example, the control circuit 250 can be configured to maintain a smaller amplitude during the first time period T. P1 Internal maximum current limit I LMT Adjusted to the second limiting amplitude I MAG2 And then during the adjustment period T ADJ Internal maximum current limit I LMT The amplitude is from the second limit amplitude I MAG2 Reduce (e.g., linearly reduce) to the first limiting amplitude I MAG1 Then, during the remainder of that half-cycle, the maximum current I is limited. LMT Maintain at the first limit amplitude I MAG1 .

[0090] Furthermore, in some examples, when using positive phase control dimming technology, the control circuit 250 can be configured to increase the dimming time T after (e.g., immediately after) the control time (e.g., the trigger time). R-UP Internal maximum current limit I increases over time LMT The amplitude, up to the maximum current limit I. LMT Reaching the second limit amplitude I MAG2 Limit the maximum current I LMT Maintain at the second limit amplitude I MAG2 A period of time (e.g., pulse period T) PULSE During the decreasing period T R-DOWN Internal maximum current limit I for time reduction LMT The amplitude, up to the maximum current limit I. LMT Reaching the second limit amplitude I MAG1 (For example, then limit the maximum current I during the remainder of the conduction period of that half-cycle) LMT Maintain at the second limit amplitude I MAG1 The control circuit 250 can adjust the maximum current limit I using linear adjustment, step adjustment, or other shapes during the rising and / or falling periods. LMT .

[0091] Furthermore, the control circuit 250 can be configured to determine whether the load control device 200 is connected to an inductive load, and adjust the maximum current limit I when the load control device 200 is connected to an inductive load. LMT The amplitude. For example, if the load current I conducted through FET Q212 LOAD The amplitude (e.g., determined by the feedback signal V) FB (Indicated) and AC main line voltage V AC Out of phase (e.g., if caused by feedback signal V) FB Indicated load current I LOAD The zero-crossing point and the zero-crossing signal V ZCIndicated AC main line voltage V AC If the zero-crossing point is misaligned, the control circuit 250 can be configured to determine that the load control device 200 is connected to an inductive load. When the control circuit 250 determines that the load control device 200 is connected to an inductive load, the control circuit 250 can control the limiting signal V while using positive phase control dimming technology. LMT To limit the maximum current I LMT The amplitude is set to the first limit amplitude I. MAG1 In some examples, when the control circuit 250 determines that the load control device 200 is connected to an inductive load, the control circuit 250 can control the limiting signal V while using positive phase control dimming technology. LMT During the pulse period T PULSE Internal maximum current limit I LMT The amplitude is set to the second limiting amplitude I. MAG2 And then during the remainder of the conduction period of that half-cycle, the maximum current I is limited. LMT The amplitude is set to the first limit amplitude I. MAG1 .

[0092] Figure 3 An example of a load control device using positive phase control dimming technology is shown (e.g. Figure 1 The load control device 100 and / or shown Figure 2 The waveform example shown illustrates the operation of the load control device 200. As described herein, this load control device receives AC mains voltage from an AC power source and generates a dimming thermal voltage V at the dimming thermal terminal of the load control device for controlling the lighting load. DH .like Figure 3 As shown, when using positive phase control dimming technology, the control circuit (e.g., control circuit 120 and / or control circuit 250) can be inactive during the non-conducting period T at the beginning of each half-cycle. NC During this period, the controllable conductive device is de-conducted; at the control time (e.g., trigger time) of this half-cycle period, the controllable conductive device is turned on; and during the on-time T... CON The controllable conductive device remains on during this period until the end of the half-cycle. The control circuit can control the transition time T during each half-cycle. TRAN During this period, the controllable conductive device is controlled between a non-conducting state and a conducting state. For example, the controllable conductive device may include two semiconductor switches, such as two FETs connected in reverse series (e.g., as shown in the image). Figure 1 (As shown). Furthermore, it should be understood that, Figures 3 to 10 The dimming heating voltage V shown in the figure DHThe slopes at the transition from zero volt and back to zero volt are exaggerated for illustrative purposes. The control circuit can generate one or more drive signals to control the conduction of the controllable conductive device. For example, the control circuit can generate a first drive signal V. DR1 This allows the first semiconductor switch (e.g., the first FET Q111 of the load conditioning circuit 110) to be turned on during the positive half-cycle, and can generate the second drive signal V. DR2 This causes the second semiconductor switch (e.g., the second FET Q112 of the load conditioning circuit 110) to turn on during the negative half-cycle. For example, the first drive signal V DR1 Second drive signal V DR2 It can be a pulse width modulation signal.

[0093] The load control device can generate a target signal (e.g., a first target signal V) for controlling the load current conducted through the lighting load. TRGT1 Second target signal V TRGT2 For example, as described herein, the first gate drive circuit of the load control device (e.g., first gate drive circuit 115 and / or gate drive circuit 220) may receive a first drive signal V. DR1 The first drive signal can control the time t during each positive half-cycle of the AC main line voltage. CTNL1 It is driven high at (e.g., trigger time). The first gate drive circuit can respond to the first drive signal V. DR1 And begin targeting the first target signal V TRGT1 The shaping can be performed during the opening period (e.g., during transition period T). TRAN During the period) for the first target signal V TRGT1 Shaping is performed. The first gate drive circuit can use the first target signal V. TRGT1 To turn on the first semiconductor switch, and during the remainder of the positive half-cycle (e.g., during the on-time T) CON During this period, the first semiconductor switch remains on. Similarly, the second gate drive circuit of the load control device (e.g., second gate drive circuit 116 and / or gate drive circuit 220) can receive the second drive signal V. DR2 The second drive signal can control the time t during each negative half-cycle of the AC main line voltage. CNTL2 It is driven high at (e.g., at the trigger time). The second gate drive circuit can respond to the second drive signal V. DR2 And for the second target signal V TRGT2 Shaping can be performed during the opening period (e.g., during transition time T). TRAN During the period, the second target signal V TRGT2Shaping is performed. The second gate drive circuit can use the second target signal V. TRGT2 This enables the second semiconductor switch to be turned on and maintains the second semiconductor switch on during the remainder of the negative half-cycle.

[0094] At the end of each negative half-cycle of the AC main line voltage (e.g., near the zero-crossing point of the AC main line voltage), the first drive signal V... DR1 It can be driven low by the control circuit, and the first gate drive circuit can control the first target signal V during the off-time period. TRGT1 Shaping is performed. Similarly, at the end of each positive half-cycle of the AC main line voltage (e.g., near the zero-crossing point of the AC main line voltage), the second drive signal V... DR2 It can be driven low by the control circuit, and the second gate drive circuit can control the second target signal V during the off-time period. TRGT2 Shaping is performed. Therefore, the first target signal V TRGT1 Second target signal V TRGT2 They can be shaped on their rising and falling edges. Alternatively, when using positive phase control dimming technology, the first target signal V TRGT1 Second target signal V TRGT2 They can be shaped only along their rising edges, not their falling edges.

[0095] Figure 4 An example of a load control device using reverse phase control dimming technology is shown (e.g., Figure 1 The load control device 100 and / or shown Figure 2 The waveform example shown illustrates the operation of the load control device 200. Similar to the operation of the load control device with positive phase control dimming technology described herein, this load control device receives AC mains voltage from an AC power source and generates a dimming thermal voltage V at its dimming thermal terminal for controlling the lighting load. DH .like Figure 4 As shown, when using reverse phase control dimming technology, the control circuit can start the conduction period T at the beginning of each half-cycle. CON The controllable conductive device is turned on during the period, and turned off at the control time (e.g., trigger time) during the half-cycle, and remains off for the non-conducting period T. NC The controllable conductive device remains on during this period until the end of the half-cycle. The control circuit can control the transition time T during each half-cycle. TRANDuring this process, the controllable conductive device is controlled between a non-conducting state and a conducting state. For example, the controllable conductive device may include two semiconductor switches, such as two FETs connected in reverse series. The control circuit may generate one or more drive signals to control the conduction of the controllable conductive device. For example, the control circuit may generate a first drive signal V. DR1 This causes the first semiconductor switch (e.g., the first FET Q111 of the load conditioning circuit 110) to be turned on during the positive half-cycle. The control circuit can generate a second drive signal V. DR2 This causes the second semiconductor switch (e.g., the second FET Q112 of the load conditioning circuit 110) to turn on during the negative half-cycle. For example, the first drive signal V DR1 Second drive signal V DR2 It can be a pulse width modulation signal.

[0096] The load control device can generate a target signal (e.g., a first target signal V) for controlling the load current conducted through the lighting load. TRGT1 Second target signal V TRGT2 For example, as described herein, the first gate drive circuit of the load control device (e.g., first gate drive circuit 115 and / or gate drive circuit 220) may receive a first drive signal V. DR1 The first drive signal can be high at the beginning of each positive half-cycle, causing the controllable conductive device to be turned on at the beginning of each positive half-cycle. The first drive signal V DR-1a The control time t during each positive half-cycle of the AC main line voltage can be determined. CNTL1 It is driven low at (e.g., trigger time). The first gate drive circuit can respond to the first drive signal V. DR1 And begin targeting the first target signal V TRGT-1a Shaping can be performed during off-peak periods (e.g., during transition period T). TRAN During the period) for the first target signal V TRGT1 Shaping is performed. The first gate drive circuit can use the first target signal V. TRGT1 The first semiconductor switch is de-energized, and during the remainder of the positive half-cycle (e.g., during the non-conducting period T) NC During this period, the first semiconductor switch remains on. Similarly, the second gate drive circuit of the load control device (e.g., second gate drive circuit 116 and / or gate drive circuit 220) can receive the second drive signal V. DR2 The second drive signal can be high at the beginning of each negative half-cycle, causing the controllable conductive device to be turned on at the beginning of each negative half-cycle. The second drive signal V DR2The control time t during each negative half-cycle of the AC main line voltage can be determined. CNTL2 The load control device is driven low at a time such as the trigger time. The second drive signal V is responsive to this second drive signal. DR2 And begin targeting the second target signal V TRGT2 Shaping can be performed during off-peak periods (e.g., during transition period T). TRAN During the period) for the second target signal V TRGT2 Shaping is performed. The second gate drive circuit can use the second target signal V. TRGT2 To enable the second semiconductor switch to operate during the remainder of the negative half-cycle (e.g., during the non-conducting period T). NC During the period) it is connected.

[0097] At the end of each positive half-cycle of the AC main line voltage (e.g., near the zero-crossing point of the AC main line voltage), the first drive signal V... DR1 It can be driven high by the control circuit, and the first gate drive circuit can control the first target signal V during the on-time period. TRGT1 Shaping is performed. Similarly, at the end of each negative half-cycle of the AC main line voltage (e.g., near the zero-crossing point of the AC main line voltage), the second drive signal V... DR2 It can be driven high by the control circuit, and the second gate drive circuit can control the second target signal V during the on-time period. TRGT2 Shaping is performed. Therefore, the first target signal V TRGT1 Second target signal V TRGT2 They can be shaped on their rising and falling edges. Alternatively, when using reverse phase control dimming technology, the first target signal V TRGT1 Second target signal V TRGT2 It can be shaped only on its falling edge, but not on its rising edge.

[0098] Figure 5 Waveform examples illustrating the operation of a gate drive circuit (e.g., gate drive circuit 220) that uses positive phase control dimming technology to turn on a semiconductor switch (e.g., FET Q212). Figure 5 In the waveform, the lighting load may not have experienced a current event (e.g., a short circuit in the lighting load) or a surge current event (e.g., a surge current conducted to the lighting load). As described herein, the load control device (e.g., Figure 1 The load control device 100 and / or Figure 2 The load control device 200 can receive AC mains voltage from an AC power source and can use phase control dimming technology to generate a dimming thermal voltage V at the dimming thermal terminal of the load control device for controlling the lighting load. DH(e.g., phase control voltage). The load control device may include two gate drive circuits, wherein the first gate drive circuit (e.g., Figure 1 The first gate drive circuit 115 shown controls the first semiconductor switch (e.g., the first FET Q111) during the positive half-cycle. Figure 5 As shown), the second gate drive circuit (e.g.) Figure 1 The second gate drive circuit 116 shown controls the second semiconductor switch (e.g., the second FET Q112) during the negative half-cycle. The operation of the second gate drive circuit during the negative half-cycle can be compared with... Figure 5 The first gate drive circuit shown operates identically during the positive half-cycle.

[0099] The gate drive circuit of the load control device can receive a drive signal V from a control circuit (e.g., control circuit 120 and / or control circuit 250). DR This control circuit can control time t. CNTL The drive signal V will be located at (e.g., trigger time). DR The amplitude (e.g., towards the DC supply voltage V) CC The control is set to high. This gate drive circuit is responsive to the drive signal V from the control circuit. DR And generate the target signal V TRGT The gate drive circuit can respond to the drive signal V. DR Driven to high and begin targeting signal V TRGT Shaping is performed. This gate drive circuit can be activated during the on-time T... T-ON Within approximately 50 microseconds, the target signal V... TRGT Shaping is performed. In some examples, such as when using positive phase control, the transition time T... TRAN It can be equal to the start time period T T-ON The gate drive circuit can use the enable signal V generated by the enable circuit (e.g., enable circuit 226). T-ON (not shown) to generate the target signal V TRGT For example, such as Figure 5 As shown, during the opening time period T T-ON During this period, signal V is activated. T-ON It can have the same voltage as the target voltage V TRGT The same shape. This gate drive circuit can respond to the turn-on signal V. T-ON Shaping is performed to adjust the target signal V. TRGT Shaping is performed. In some examples, the enable signal V is used. T-ON It can be opened during the time period T T-ON The inner part is defined by an "S" shape. This gate drive circuit can be turned on during the turn-on period T. T-ON Signal V will be activated when the process ends. T-ONThe amplitude control is the first limit signal amplitude V. MAG1 The gate drive circuit can be turned on during the turn-on period T. T-ON During this period, the target signal V TRGT Set to equal to the enable signal V T-ON The amplitude.

[0100] During the opening time period T T-ON The gate drive circuit can then be configured based on the enable signal V. T-ON and limiting signal V LMT To set the target signal V TRGT The limiting signal V LMT The amplitude can be at the second amplitude (e.g., approximately the supply voltage V). CC The voltage varies between a threshold signal V and a first amplitude (e.g., approximately the circuit common terminal or zero volts). As described herein, the control circuit can limit the signal V. LMT The amplitude is set to a second amplitude or a first amplitude (e.g., one or more values ​​between the upper limit amplitude and the first amplitude) to control the maximum current limit I of the load control device. LMT The amplitude. In Figure 5 In the waveform, during the opening time period T T-ON At the end, the limiting signal V LMT The amplitude is set to the second amplitude, and so, during the opening time period T T-ON At the end, the target signal V TRGT The amplitude can be equal to the amplitude V of the second limiting signal. MAG2 .

[0101] In addition, during the opening time period T T-ON Subsequently, the control circuit can control the overcurrent protection enable signal V. OCP-EN This enables the overcurrent protection circuit. In some examples, this control circuit can be activated during the time period T. T-ON After a delay period (e.g., approximately 50 microseconds) following the end of the process, the overcurrent protection enable signal V is controlled. OCP-EN This enables the overcurrent protection circuit. As described herein, the overcurrent detection circuit can be configured to trip during a tripping time T from the initial detection of an overcurrent condition. TRIP Then, control the overcurrent detection signal V OCD To indicate overcurrent conditions. The control circuit can be configured to enable the overcurrent protection circuit during the conduction period of each half-cycle, for example... Figure 5 As shown. For example, when operating using positive phase control technology, this control circuit can be activated during the on-time period T. T-ON Then the OCP enable signal V OCP-EN The amplitude (e.g. towards the supply voltage V) CCThe drive is high. This control circuit can enable the OCP signal V at and / or near the next zero-crossing event. OCP-EN The amplitude (e.g., towards the circuit common terminal) is driven low. Thus, the control circuit can be configured to enable the overcurrent protection circuit during the conduction period of each half-cycle.

[0102] The gate drive circuit can be based on the target signal V. TRGT and indicates the load current I conducted through the semiconductor switch LOAD Amplitude feedback signal V FB (not shown) to generate the gate control signal V GC The gate drive circuit can respond to the feedback signal V. FB Adjust the gate control signal V based on its amplitude. GC The amplitude. For example, the gate drive circuit can respond to the feedback signal V. FB Adjust the gate control signal V based on its amplitude. GC The amplitude, so as to reduce the load current I LOAD The amplitude is adjusted toward the target current, which, for example, is determined by the target signal V. TRGT Amplitude indication.

[0103] When the opening time period T T-ON End target signal V TRGT The amplitude is equal to the amplitude of the second limiting signal V. MAG2 At that time, the gate drive circuit can control the gate control signal V. GC The amplitude, in order to attempt to reduce the load current I LOAD The amplitude is controlled to the second limit amplitude I. MAG2 (For example, approximately 20A). However, lighting loads may not require a second limiting amplitude I. MAG2 And the gate control signal V GC The amplitude may deviate from the target signal V TRGT The amplitude. When during the opening time period T T-ON Then the target signal V TRGT The amplitude is equal to the second limiting amplitude I. MAG2 At that time, the gate drive circuit can control the gate control signal V. GC The amplitude, in order to attempt to reduce the load current I LOAD The amplitude is controlled to the maximum current level I. MAX (For example, approximately 20A). However, if the lighting load has not experienced an overcurrent event (e.g., a short circuit in the lighting load) or a surge current event (e.g., a surge current conducted to a lighting load such as an incandescent lamp load), and the input capacitor of the lighting load has not experienced a current surge, then the gate control signal V... GC The amplitude may not be driven to the second limit amplitude I. MAG2 ,likeFigure 5 As shown.

[0104] Because the gate drive circuit uses closed-loop control based on the feedback signal V FB To adjust the gate control signal V GC The amplitude of the gate control signal V GC The magnitude can indicate (e.g., proportional to) the load current I. LOAD The current amplitude. Therefore, as Figure 5 As shown, the load current I LOAD It can have a gate control signal V GC Same shape.

[0105] Figure 6 Waveform examples illustrating the operation of a gate drive circuit (e.g., gate drive circuit 220) that uses reverse phase control dimming technology to de-energize a semiconductor switch (e.g., FET Q212). Load control device (e.g.) Figure 1 The load control device 100 and / or Figure 2 The load control device 200 can receive AC main line voltage from the AC power supply and can use phase control dimming technology to generate a dimming thermal voltage V at the dimming thermal terminal of the load control device. DH (e.g., phase control voltage). The load control device may include two gate drive circuits, wherein the first gate drive circuit (e.g., Figure 1 The first gate drive circuit 115 shown controls the first semiconductor switch (e.g., the first FET Q111) during the positive half-cycle. Figure 9 As shown), the second gate drive circuit (e.g.) Figure 1 The second gate drive circuit 116 shown controls the second semiconductor switch (e.g., the second FET Q112) during the negative half-cycle. The operation of the second gate drive circuit during the negative half-cycle can be compared with... Figure 6 The first gate drive circuit shown operates identically during the positive half-cycle. Furthermore, it should be understood that... Figure 6 The dimming heating voltage V shown in the figure DH1 The slope at the transition to zero is exaggerated, for example... Figure 6 Other signals shown (such as the drain voltage sensing signal V) DV , shutdown signal V T-OFF Target signal V TRGT Gate control signal V GC and / or load current I LOAD Changes and correlations between )

[0106] The gate drive circuit of the load control device can receive a drive signal V from a control circuit (e.g., control circuit 120 and / or control circuit 250). DRThis control circuit can apply the drive signal V at the beginning of the half-cycle of the AC main line voltage. DR (e.g., towards DC power supply voltage V) CC The gate drive is high. This gate drive circuit is responsive to the drive signal V from the control circuit. DR And generate the target signal V TRGT This control circuit can control time t. CNTL The drive signal V will be located at (e.g., trigger time). DR Drive is low. During control time t CNTL Previously, the gate drive circuit could be configured to be based on a turn-off signal V generated by a turn-off circuit (e.g., turn-off circuit 228). T-OFF (not shown) and limit signal V LMT To set the target signal V TRGT The limiting signal V LMT The amplitude can be at the second amplitude (e.g., the supply voltage V). CC The value varies between the limit signal V and a first amplitude (e.g., approximately the circuit common terminal). As described herein, this control circuit can limit the signal V. LMT The amplitude is set to a second amplitude or a first amplitude (e.g., one or more values ​​between the upper limit amplitude and the first amplitude) to control the maximum current limit I of the load control device. LMT The amplitude. In Figure 6 In the waveform, the limiting signal V LMT The amplitude is set to the second amplitude at the beginning of the half-cycle, and thus, the target signal V TRGT The amplitude can be equal to the amplitude V of the second limiting signal. MAG2 In response to the control circuit at control time t CNTL The drive signal V will be used. DR When the amplitude drive is low, the gate drive circuit can drive the target signal V. TRGT The amplitude is reduced to a predetermined value, such as the first limit signal amplitude V. MAG1 During the opening time period T T-ON At the end, the target signal V TRGT The amplitude can be equal to the amplitude V of the second limiting signal. MAG2 .

[0107] When the target voltage V TRGT The amplitude is from the second limiting signal amplitude V MAG2 Reduce to the first limiting signal amplitude V MAG1 Subsequently, the gate drive circuit can, while monitoring the characteristics of the semiconductor switch (e.g., the voltage generated across the semiconductor switch), reduce (e.g., gradually decrease with respect to time) the target signal V. TRGTThe amplitude. For example, the gate drive circuit can receive a drain voltage sensing signal V from a drain voltage sensing circuit (e.g., drain voltage sensing circuit 218). DV The drain voltage sensing signal V DV This indicates the magnitude of the voltage across the semiconductor switch. When the semiconductor switch is turned on, the magnitude of the voltage across it is very small (e.g., approximately zero volts). When the target voltage V... TRGT When the amplitude of the voltage decreases to a level that causes the semiconductor switch to become non-conductive, the amplitude of the voltage across the semiconductor switch can begin to increase, thereby causing the drain voltage sensing signal V to... DV The amplitude increases, such as Figure 6 As shown. This gate current sensing circuit can determine the drain voltage sensing signal V. DV When does the amplitude exceed the drain voltage threshold V? TH (For example, approximately 1V).

[0108] In some examples, the gate drive circuit can begin to drive the target signal V. TRGT The voltage is shaped from the current value toward zero volts. For example, when the gate drive circuit detects that the voltage across the semiconductor switch has begun to increase in amplitude, the drain voltage sensing signal V... DV The amplitude exceeds the drain voltage threshold V TH At that time, the gate drive circuit can begin to transmit the target signal V. TRGT Shape the current value toward zero volts, for example... Figure 6 As shown. This gate drive circuit can operate during the turn-off period T. T-OFF Within approximately 40 microseconds, the target signal V... TRGT Shaping is performed. In some examples, such as when using reverse phase control, the transition time T... TRAN It can be equal to the start time period T T-OFF The gate drive circuit can use the turn-off signal V generated by the turn-off circuit. T-OFF To generate the target signal V TRGT For example, such as Figure 6 As shown, during the shutdown period T T-OFF During this period, the off signal V T-OFF It can have the same voltage as the target voltage V TRGT They have the same shape. Therefore, this gate drive circuit can use the drain voltage sensing signal V. DV As a trigger signal, it allows the gate drive circuit to begin responding to the turn-off signal V. T-OFF (for example, and the target signal V) TGRT Waveform shaping is performed. Alternatively, the gate drive circuit can perform waveform shaping on the target signal V. TRGT Waveform shaping is performed regardless of the drain voltage sensing signal V. DVHow much amplitude does it have? For example, the gate drive circuit can drive the target signal V. TRGT The amplitude is from the second limiting signal amplitude V MAG2 Reduce to the first limiting signal amplitude V MAG1 Then (for example, immediately afterward), for the target signal V TRGT Shaping is performed. This gate drive circuit can be based on the drain voltage sensing signal V. DV The amplitude of the turn-off signal V is configured in a shape such as an S-shape according to a pre-configured form. T-OFF (for example, and the target signal V) TRGT The gate drive circuit can perform shaping during the off-time T. T-OFF During the first part of the period, the turn-off signal V is in the first shape. T-OFF Perform plastic surgery, and during the off-time period T T-OFF During the second part of the period, the turn-off signal V is in the second shape. T-OFF Perform shaping (e.g., to form an S-shape).

[0109] As described in this article, this gate drive circuit can be based on the target signal V. TRGT and indicates the load current I conducted through the lighting load. LOAD Amplitude feedback signal V FB (not shown) to generate the gate control signal V GC As described herein, this gate drive circuit is responsive to the feedback signal V. FB Adjust the gate control signal V based on its amplitude. GC The amplitude. For example, such as Figure 6 As shown, the gate drive circuit can respond to the feedback signal V FB Adjust the gate control signal V based on its amplitude. GC The amplitude of the load current I is thus reduced. LOAD The amplitude is adjusted toward the target current. This gate drive circuit can adjust the gate control signal V... GC The amplitude is adjusted to zero volts to de-conduct the semiconductor switch, thereby controlling the amplitude of the load current conducted through the lighting load to zero amperes. This is because the gate drive circuit uses closed-loop control based on the feedback signal V. FB To adjust the gate control signal V GC The amplitude of the gate control signal V GC The magnitude can indicate (e.g., proportional to) the load current I. LOAD The current amplitude. Therefore, as Figure 6 As shown, the load current I LOAD It can have a gate control signal V GC Same shape.

[0110] In some examples, the control circuit can control the overcurrent protection enable signal V at the zero-crossing point of the AC main line voltage at the beginning of the half-cycle. OCP-EN This enables the overcurrent protection circuit. As described herein, the overcurrent detection circuit can be configured to trip during a tripping time T from the initial detection of an overcurrent condition. TRIP Then, control the overcurrent detection signal V OCD This indicates an overcurrent condition. The control circuit can be configured to enable the overcurrent protection circuit during the conduction period of each half-cycle. For example, when operating using reverse phase control technology, the control circuit can enable the OCP signal V at the zero-crossing point at the beginning of the half-cycle of the AC main line voltage. OCP-EN The amplitude (e.g. towards the supply voltage V) CC The drive is high. This control circuit can control time t. CNTL The OCP enable signal V will be used. OCP-EN The amplitude (e.g., towards the circuit common terminal) is driven low. For example, as Figure 6 As shown, the OCP enable signal V OCP-EN Can be used with limiting signal V LMT Similarly, the control circuit can be configured to enable the overcurrent protection circuit during the on-time period of each half-cycle.

[0111] Figure 7 Waveform examples illustrating the operation of a gate drive circuit (e.g., gate drive circuit 220) that uses positive phase control dimming technology to turn on a semiconductor switch (e.g., FET Q212). Figure 7 In the waveform, the lighting load can be an inductive load. This load control device (e.g.) Figure 1 The load control device 100 and / or Figure 2 The load control device 200 can receive AC main line voltage from the AC power supply and can perform phase control on the AC line voltage to generate a dimming thermal voltage V for controlling the lighting load at the dimming thermal terminal of the load control device. DH (e.g., phase control voltage). The load control device may include two gate drive circuits, wherein the first gate drive circuit (e.g., Figure 1 The first gate drive circuit 115 shown controls the first semiconductor switch (e.g., the first FET Q111) during the positive half-cycle. Figure 7 As shown), the second gate drive circuit (e.g.) Figure 1 The second gate drive circuit 116 shown controls the second semiconductor switch (e.g., the second FET Q112) during the negative half-cycle. The operation of the second gate drive circuit during the negative half-cycle can be compared with... Figure 7 The first gate drive circuit shown operates identically during the positive half-cycle.

[0112] exist Figure 7 During the operation of the gate drive circuit, the control circuit can determine that the lighting load is an inductive load. The control circuit can be configured to adjust the limit signal V of the closed-loop gate drive circuit based on the lighting load being an inductive load. LMT The amplitude is set to a first amplitude (e.g., approximately the circuit common terminal). For example, this control circuit can limit the signal V during the entire conduction period of half a cycle of the AC main line voltage. LMT The amplitude is set to the first amplitude. This is due to the limiting signal V. LMT The amplitude is set to the first amplitude, and the target signal V TRGT The amplitude can be set to the first limit signal amplitude V at the end of the open period. MAG1 This can limit the maximum current I LMT The amplitude is set to the first limit amplitude I. MAG1 (For example, approximately 8A). For example, as about Figure 5 As mentioned above, during the opening time period T T-ON The gate drive circuit can then be configured based on the enable signal V. T-ON and limiting signal V LMT To set the target signal V TRGT The amplitude.

[0113] Although limiting signal V LMT The amplitude can vary between the second amplitude and the first amplitude, but the control circuit can limit the signal V based on the lighting load being an inductive load. LMT The amplitude is set to the first amplitude. Since the lighting load is inductive, it may not require the surge current that in incandescent or capacitive lighting loads might need to conduct. Therefore, this control circuit can limit the signal V for the entire conduction period of half a cycle of the AC mains voltage. LMT The amplitude is set to the first amplitude (e.g., the limiting signal V is not applied during the half-cycle conduction time). LMT (Increase to the second amplitude). Furthermore, the signal V will be limited during the half-cycle. LMT Maintaining the first amplitude ensures that the inductive load does not overheat and / or become damaged, because the first amplitude will prevent load current with a large amplitude from being conducted through the inductive load, and / or prevent the load from conducting asymmetrical current with a large peak amplitude above the saturation threshold.

[0114] Therefore, when using positive phase control dimming technology, this control circuit will limit the signal V. LMT The amplitude is limited to the first amplitude to limit the target signal V. TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 This limits the maximum current I. LMT The amplitude is set to, for example, a first limiting amplitude I.MAG1 A smaller amplitude (e.g., about 8A) is used to allow the overcurrent protection circuit to properly protect the inductive load from large load currents.

[0115] Figure 8 Waveform examples illustrating the operation of a gate drive circuit (e.g., gate drive circuit 220) that uses positive phase control dimming technology to turn on a semiconductor switch (e.g., FET Q212). Figure 8 In the waveform, the control circuit can be configured to adjust the limiting signal V, for example, using pulses, during the conduction period of half a cycle of the AC main line voltage. LMT For example, the control circuit can start from control time t. CTNL1 (For example, during the opening time period T) T-ON The pulse period T that begins afterward PULSE Internal limit signal V LMT The amplitude is set to the second amplitude (e.g., the supply voltage V). CC And then, for the remainder of the conduction period of that half-cycle, the limiting signal V will be... LMT Adjust to the first amplitude (e.g., approximately the common terminal of the circuit).

[0116] The load control device (e.g.) Figure 1 The load control device 100 and / or Figure 2 The load control device 200 can receive AC main line voltage from an AC power source and can phase control the AC line voltage to generate a dimming thermal voltage VDH (e.g., a phase control voltage) for controlling the lighting load at the dimming thermal terminal of the load control device. The load control device may include two gate drive circuits, wherein the first gate drive circuit (e.g., ...) Figure 1 The first gate drive circuit 115 shown controls the first semiconductor switch (e.g., the first FET Q111) during the positive half-cycle. Figure 8 As shown), the second gate drive circuit (e.g.) Figure 1 The second gate drive circuit 116 shown controls the second semiconductor switch (e.g., the second FET Q112) during the negative half-cycle. The operation of the second gate drive circuit during the negative half-cycle can be compared with... Figure 8 The first gate drive circuit shown operates identically during the positive half-cycle.

[0117] exist Figure 8 During the operation of the gate drive circuit, the control circuit can operate from the control time t CTNL1 The initial pulse period T PULSE The limiting signal V of the closed-loop gate drive circuit is internally applied. LMT The amplitude is set to the second amplitude (e.g., the supply voltage V). CCAnd then, for the remainder of the conduction period of that half-cycle, the limiting signal V will be... LMT Adjust to the first amplitude (e.g., approximately the circuit common terminal). For example, the control circuit can be turned on at time T. T-ON The subsequent pulse period T PULSE Internal limit signal V LMT The amplitude is set to the second amplitude, and then during the opening time period T T-ON At the end, the signal V will be limited for the remainder of the conduction period of that half-cycle. LMT Adjusted to the first amplitude. Therefore, the target signal V TRGT During the pulse period T PULSE The period is set to the second limiting signal amplitude V MAG2 And then during the pulse period T PULSE The first limiting signal amplitude V is set at the end of the conduction period and during the remaining half of the half-cycle of the AC main line voltage. MAG1 Thus, the control circuit can operate during the pulse period T. PULSE Maximum current limit I during the period LMT The amplitude is set to the second limiting amplitude I. MAG1 (e.g., approximately 20A), and then during the pulse period T PULSE The maximum current I will be limited at the end of the conduction period and during the remaining half of the half-cycle of the AC main line voltage. LMT The amplitude is set to the first limit amplitude I. MAG1 (For example, approximately 8A). For example, as about Figure 5 As mentioned above, during the opening time period T T-ON The gate drive circuit can then be configured based on the enable signal V. T-ON and limiting signal V LMT To set the target signal V TRGT .

[0118] Therefore, by using a pulse period T during a portion of the conduction period of half a cycle of the AC main line voltage... PULSE (for example, and will limit signal V) LMT The amplitude is set to a second amplitude), and the control circuit is configured to allow the lighting load (e.g., when the lighting load is an incandescent or capacitive load) to operate during the pulse period T. PULSE During this period, surge current is conducted because the second amplitude will allow surge current to be conducted through the lighting load. Furthermore, through the pulse period T... PULSE The signal V will be limited thereafter and for the remainder of the half-cycle conduction period. LMTSet to a first amplitude, the control circuit is configured to allow the lighting load (e.g., when the lighting load is inductive) to avoid overheating and / or damage due to saturation, because the first amplitude will prevent load current with a large amplitude from being conducted through the lighting load, and / or may prevent the load from conducting asymmetrical current with a large peak amplitude above the saturation threshold.

[0119] Therefore, when using positive phase control dimming technology, this control circuit can operate during the pulse period T. PULSE During this period, signal V will be limited. LMT The amplitude is set to the second amplitude to make the target signal V TRGT The amplitude is adjusted to the second limiting signal amplitude V. MAG2 Thus, during the pulse period T PULSE Maximum current limit I during the period LMT The amplitude is set to, for example, a second limiting amplitude I. MAG2 A larger amplitude value (e.g., approximately 20A) is used to allow the lighting load to conduct a larger surge current for a portion of the half-cycle; and during the pulse period T PULSE The signal V will then be limited for the remainder of the half-cycle. LMT The amplitude is set to the first amplitude to make the target signal V TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 This limits the maximum current I. LMT The amplitude is set to, for example, a first limiting amplitude I. MAG1 A smaller amplitude (e.g., about 8A) is used to allow the overcurrent protection circuit to properly protect the inductive load from large load currents.

[0120] Pulse duration T PULSE The length (e.g., duration) can be adjustable (e.g., duration can be variable). For example, the control circuit can use pulse periods T with longer or shorter lengths during certain time periods and / or based on the load type. PULSE For example, in one example, the pulse duration T PULSE The pulse duration can range from approximately 2,000 microseconds to as short as approximately 500 microseconds. Other pulse durations T can also be used. PULSE . Figure 9 Waveform examples illustrating the operation of a gate drive circuit (e.g., gate drive circuit 220) that uses positive phase control dimming technology to turn on a semiconductor switch (e.g., FET Q212). Figure 9 In the waveform, the control circuit can be configured, for example, to limit the signal V. LMT The amplitude is set to different levels over a period of time to adjust the limiting signal V during the conduction period of half a cycle of the AC main line voltage. LMT For example, the control circuit can start from control time t.CTNL1 (For example, during the opening time period T) T-ON The pulse period T that begins afterward PULSE Internal limit signal V LMT The amplitude is set to the second amplitude (e.g., the supply voltage V). CC And then, for the remainder of the conduction period of that half-cycle, the limiting signal V will be... LMT Adjust to the first amplitude (e.g., approximately the common terminal of the circuit).

[0121] In some examples, the control circuit can control the pulse duration T PULSE The length is set to the first time period T P1 (e.g., approximately 500 microseconds), to allow, for example, the capacitor of a capacitive load to charge properly in each half-cycle; or to be set to a second time period T. P2 (For example, approximately 2,000 microseconds) to, for example, allow the incandescent lamp load to heat up. Furthermore, in some examples, the control circuit can time the pulse period T within a specific number of line cycles after the lighting load is energized (e.g., only within a specific number of line cycles after the lighting load is energized). PULSE Set as the first time period T P1 Or the second time period T P2 For example, this control circuit can control the pulse duration T over multiple line cycles (e.g., approximately 120 half-cycles) after the lighting load is turned on. PULSE The length is set to the first time period T P1 Or the second time period T P2 Furthermore, after the first number of line cycles, the control circuit can limit the signal V for the entire conduction period of a future half-cycle. LMT The amplitude is set to the first amplitude.

[0122] In some (e.g., alternative) examples, the control circuitry can adjust the pulse duration T during operation—such as when starting or energizing a lighting load. PULSE The duration of the pulse. For example, the control circuit can limit the pulse period T within a first initial number of line cycles (e.g., approximately 120 half-cycles) of the AC main line voltage. PULSE Set as the second time period T P2 And then, within a second subsequent number of line cycles (e.g., permanently) of the AC main line voltage, the pulse period T... PULSE Set as the first time period T P1 The second time period T P2 It can be greater than the first time period T P1(For example, approximately 2,000 microseconds and 500 microseconds respectively). Therefore, the control circuit can, for example, respond to energizing the lighting load (e.g., only for a specific number of line cycles after energizing the lighting load) and pulse duration T within a specific number of line cycles. PULSE The duration is set to more than one value.

[0123] The load control device (e.g.) Figure 1 The load control device 100 and / or Figure 2 The load control device 200 can receive AC main line voltage from an AC power source and can phase control the AC line voltage to generate a dimming thermal voltage VDH (e.g., a phase control voltage) for controlling the lighting load at the dimming thermal terminal of the load control device. The load control device may include two gate drive circuits, wherein the first gate drive circuit (e.g., ...) Figure 1 The first gate drive circuit 115 shown controls the first semiconductor switch (e.g., the first FET Q111) during the positive half-cycle. Figure 9 As shown), the second gate drive circuit (e.g.) Figure 1 The second gate drive circuit 116 shown controls the second semiconductor switch (e.g., the second FET Q112) during the negative half-cycle. The operation of the second gate drive circuit during the negative half-cycle can be compared with... Figure 9 The first gate drive circuit shown operates identically during the positive half-cycle.

[0124] Therefore, when using positive phase control dimming technology, this control circuit can operate during the pulse period T. PULSE During this period, signal V will be limited. LMT The amplitude is set to the second amplitude to make the target signal V TRGT The amplitude is adjusted to the second limiting signal amplitude V. MAG2 Thus, during the pulse period T PULSE Maximum current limit I during the period LMT The amplitude is set to, for example, a second limiting amplitude I. MAG2 A larger amplitude value (e.g., approximately 20A) to allow the lighting load to conduct larger surge currents; and during the pulse period T PULSE The signal V will then be limited for the remainder of the half-cycle. LMT The amplitude is set to the first amplitude to make the target signal V TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 This limits the maximum current I. LMT The amplitude is set to, for example, a first limiting amplitude I. MAG1A smaller amplitude (e.g., approximately 8A) is used to allow the overcurrent protection circuit to properly protect the inductive load from large load currents. Furthermore, the control circuit can, during operation—such as when starting a lighting load or supplying power to a lighting load channel—e.g., by using a pulse period T... PULSE The duration from the second time period T P2 Reduced to the first time period T P1 (e.g., reduced from approximately 2,000 µs to approximately 500 µs) to adjust pulse periods T across multiple line cycles of the AC main line voltage. PULSE Duration or time period T P Furthermore, in some examples, during the pulse duration T... PULSE Set as the second time period T P2 After several circuit cycles, the control circuit can completely stop using the pulse period T. PULSE Until the lighting load is turned off (e.g., the control circuit can limit the signal V). LMT Reduced to a lower value (e.g., approximately the circuit common terminal). Therefore, this control circuit can limit the maximum current I. LMT Gradually transition from larger amplitude values ​​to smaller amplitude values ​​(e.g., to accommodate various types of lighting loads).

[0125] In some examples, the control device (e.g.) Figure 1 The load control device 100 and / or Figure 2 The load control device 200 may include a digital-to-analog converter (DAC), and the control circuitry of the control device may be configured to limit the signal V during the on-time period of half a cycle of the AC main line voltage. LMT The amplitude at the second amplitude (e.g., supply voltage V) CC The time-varying adjustment (e.g., linear adjustment) between the first amplitude (e.g., approximately the circuit common terminal) and the second amplitude can be used. For example, the control circuit can use a digital-to-analog converter to set the limit signal V. LMT The amplitude, and adjust the limiting signal V. LMT The amplitude, so as to make the target signal V TRGT The amplitude of the second limiting signal amplitude V MAG2 With the amplitude V of the first limiting signal MAG1 Adjustments can be made between these intervals (e.g., linear adjustment). In this way, the control circuit can limit the maximum current I during half a cycle of the AC main line voltage. LMT Gradually transition from larger amplitude values ​​to smaller amplitude values ​​(e.g., to accommodate various types of lighting loads).

[0126] Figure 10 The diagram illustrates the limiting signal V during the conduction period of a half-cycle of the AC main line voltage. LMTAn example of a waveform where the amplitude is adjusted with respect to time between the second and first amplitudes. Figure 10 Waveform examples illustrating the operation of a gate drive circuit (e.g., gate drive circuit 220) that uses positive phase control dimming technology to turn on a semiconductor switch (e.g., FET Q212). Figure 10 In the waveform, the control circuit can be configured to adjust the limiting signal V, for example, using pulses, during the conduction period of half a cycle of the AC main line voltage. LMT For example, the control circuit can start from control time t. CTNL1 (e.g., at opening time T) T-ON The pulse period T that begins afterward PULSE Internal limit signal V LMT The amplitude is set to the second amplitude (e.g., the supply voltage V). CC ), across adjustment period T ADJ Limit signal V LMT The amplitude is adjusted from the second amplitude to the first amplitude (e.g., approximately the circuit common terminal or zero volts), and then the limiting signal V is applied for the remainder of the conduction period of that half-cycle. LMT The amplitude remains at the first amplitude.

[0127] The load control device (e.g.) Figure 1 The load control device 100 and / or Figure 2 The load control device 200 can receive AC main line voltage from an AC power source and can phase control the AC line voltage to generate a dimming thermal voltage VDH (e.g., a phase control voltage) for controlling the lighting load at the dimming thermal terminal of the load control device. The load control device may include two gate drive circuits, wherein the first gate drive circuit (e.g., ...) Figure 1 The first gate drive circuit 115 shown controls the first semiconductor switch (e.g., the first FET Q111) during the positive half-cycle. Figure 10 As shown), the second gate drive circuit (e.g.) Figure 1 The second gate drive circuit 116 shown controls the second semiconductor switch (e.g., the second FET Q112) during the negative half-cycle. The operation of the second gate drive circuit during the negative half-cycle can be compared with... Figure 10 The first gate drive circuit shown operates identically during the positive half-cycle.

[0128] like Figure 10 As shown, this control device can adjust the voltage across the adjustment period T during the conduction period of half a cycle of the AC main line voltage. ADJ Linear adjustment of the limiting signal V between the second amplitude and the first amplitude LMTThe amplitude. Although illustrated as a linear adjustment between the second and first amplitudes, the control circuit can use other shapes (e.g., multiple discrete steps between the second and first amplitudes) to variably adjust the limiting signal V. LMT In addition, such as Figure 10 As shown, this control circuit can be activated during the time period T. T-ON The subsequent pulse period T PULSE Internal limit signal V LMT The amplitude is set to a second amplitude. For example, this control circuit can set the pulse duration T... PULSE The length is set to the first time period T P1 (For example, approximately 500 microseconds). Then, during the pulse period T... PULSE Subsequently, the control circuit can linearly adjust the limiting signal V between the second amplitude and the first amplitude during the conduction period of half a cycle of the AC main line voltage. LMT The amplitude. Then, the control circuit can limit the signal V for the remainder of the conduction period of that half-cycle. LMT The setting remains at the first amplitude. Therefore, during the conduction period of half a cycle of the AC main line voltage, this control circuit can span the adjustment period T. ADJ Limit the maximum current I LMT The amplitude gradually changes from larger to smaller values ​​(e.g., to accommodate various types of lighting loads). The control circuit can execute the limiting signal V within a specific number of half-cycles of the AC mains voltage (e.g., a specific number after the lighting load is turned on). LMT The control circuit can either linearly adjust the second amplitude between the first amplitude and the second amplitude, or it can execute the limiting signal V during all half cycles of the AC main line voltage. LMT Linear adjustment.

[0129] Therefore, when using positive phase control dimming technology, this control circuit can adjust the dimming time across the adjustment period T during the conduction period of half a cycle of the AC main line voltage. ADJ Adjust the limiting signal V between the second amplitude and the first amplitude. LMT The amplitude, so as to make the target signal V TRGT The amplitude of the second limiting signal amplitude V MAG2 With the amplitude V of the first limiting signal MAG1 Adjustments are made between these intervals (e.g., linear adjustments), which in turn allow for adjustments across the adjustment period T during the conduction period of a half-cycle of the AC main line voltage. ADJ Limit the maximum current I LMT In such as the second limiting amplitude I MAG2 Larger amplitude values ​​(e.g., approximately 20A) and such as the first limiting amplitude I MAG1Adjustments can be made between smaller amplitudes (approximately 8A) (e.g., linear adjustment). This allows the lighting load to be adjusted within the pulse duration T. PULSE During the period and adjustment period, it conducts larger surge currents and also allows the overcurrent protection circuit to properly protect inductive loads from large load currents.

[0130] Figure 11A This is a flowchart of an example process 1100 for setting the maximum current limit of a load control device based on the type of phase control technology configured thereon. This process 1100 can be performed by a load control device (e.g., Figure 1 The load control device 100 and / or shown Figure 2 The control circuitry (e.g., control circuitry 120 and / or control circuitry 250) of the load control device 200 is executed to control the drive circuitry (e.g., gate drive circuitry 115, gate drive circuitry 116, and / or gate drive circuitry 220) of the load control device. The control circuitry may execute process 1100 at startup, in response to a command to control the electrical load, and / or periodically. In some examples, the control circuitry may execute process 1100 in response to receiving a command to control the power supplied to the lighting load. Alternatively or additionally, the control circuitry may execute process 1100 during each half-cycle of the AC power supply.

[0131] The control circuit can execute process 1100 to determine how to adjust the limit signal V. LMT The amplitude is used to control the maximum current limit I. LMT As described herein, this gate drive circuit can be based on a limiting signal V. LMT To generate the target signal V TRGT This is used to control the semiconductor switch to control the power supplied to the lighting load. Also as described herein, the gate drive circuit can control the load current I conducted through the semiconductor switch. LOAD The amplitude is limited by the limiting signal V LMT Indicated maximum current limit I LMT Thus, the limiting signal V LMT The amplitude of the voltage can determine the load current I conducted through the semiconductor switch. LOAD Amplitude limits (e.g., maximum current rating I) LMT As described in this article, this control circuit can generate limiting signals V with multiple different amplitudes. LMT Such as the first limiting signal amplitude V MAG1 (e.g., configured to limit maximum current I) LMT Adjusted to the first limiting amplitude I MAG1 ) and the second limiting signal amplitude V MAG2 (e.g., configured to limit maximum current I) LMT Adjusted to the second limiting amplitude IMAG2 ).

[0132] At 1102, the control circuit determines whether to use a positive phase control technique to control the lighting load. The control circuit can determine which technique to use based on one or more factors. The control circuit can be configured (e.g., pre-configured) to use a specific phase control technique. In some examples, the control circuit can determine the phase control technique based on the type of lighting load coupled to the load control device. For example, when the load current I conducted through the semiconductor switch... LOAD The amplitude (e.g., determined by the feedback voltage V) FB (Indicated) and AC main line voltage V AC In out-of-phase conditions (e.g., if the load current I is conducted through a semiconductor switch) LOAD The zero-crossing point and the zero-crossing signal V ZC Indicated AC main line voltage V AC (If the zero-crossing point is not aligned), the control circuit can determine that the lighting load is an inductive load.

[0133] If at 1102 the control circuit determines that forward phase control technology should not be used to control the lighting load (e.g., it determines that reverse phase control technology should be used to control the lighting load), then the control circuit can limit the maximum current I at 1104. LMT The amplitude is set to the first level. In some examples, this first level can be a second amplitude, such as a second limit amplitude I. MAG2 (For example, approximately 20A). For instance, the control circuit may limit the maximum current I during the entire on-time period of each half-cycle of the power supplied to the electrical load under the control of the load control device. LMT The amplitude is set to the first level. As described in this article, this control circuit can limit the signal V. LMT The amplitude is set to an upper value (e.g., approximately the supply voltage V). CC ), to transmit the target signal V TRGT The amplitude is adjusted to the second limiting signal amplitude V. MAG2 This, in turn, limits the maximum current I. LMT Adjusted to Level 1. For example, such as Figure 6 The waveform shows the limiting signal V. LMT It can be opened during the time period T T-ON The value is set to the upper value at the end, and so it is during the start time period T. T-ON At the end, the target signal V TRGT It can be equal to the amplitude of the second limiting signal V MAG2 Therefore, if the control circuit is configured to use a phase control technique other than forward phase control (such as reverse phase control or center phase control), the control circuit can limit the maximum current I. LMTThe amplitude is set to the first level.

[0134] If the control circuit determines at 1102 to use positive phase control technology to control the lighting load, then the control circuit can limit the maximum current I during the pulse period at 1106. LMT The amplitude is set to the second level. In some examples, this second level can be a second amplitude, such as a second limit amplitude I. MAG2 (Approximately 20A). This control circuit can be activated during the time period T. T-ON (e.g. from control time t) CTNL1 After the start and during the pulse period T PULSE During the duration, the maximum current limit I will be applied. LMT The amplitude is set to the second level. In some examples, the pulse duration T PULSE It can be approximately 500µs.

[0135] At 1108, before exiting process 1100, the control circuit can limit the maximum current I during the remaining portion of the conduction period of half a cycle of the AC main line voltage. LMT The amplitude is set to the third level. In some examples, this third level can be equal to the first amplitude, such as the first limit amplitude I. MAG1 (For example, approximately 8A). Thus, the control circuit can operate during the pulse period T. PULSE Maximum current limit I at the end LMT The system is adjusted from Level 1 to Level 2, and the maximum current limit I is applied during the remaining portion of the conduction period of the half-cycle of the AC main line voltage. LMT It remains at level two. This control circuit can limit the signal V. LMT The amplitude is set to a lower value (e.g., approximately the common terminal of the circuit) to reduce the target signal V. TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 This, in turn, limits the maximum current I. LMT Adjust to level three. At the start of the next half-cycle of the AC main line voltage, the control circuit can restart process 1100 (e.g., or roll back to 1106).

[0136] Thus, the control circuit can operate during the pulse period T. PULSE At the end of the conduction period and for the remainder of the half-cycle of the AC main line voltage, the maximum current limit I will be applied. LMT The amplitude is set to the third level. Therefore, using process 1100, when using positive phase control technology, this control circuit can operate during the pulse period T. PULSE Internal maximum current limit I LMTThe amplitude is set to the second level to allow the capacitance of the capacitive load to charge properly in each half-cycle and / or to allow the incandescent load to heat up during the pulse period T. PULSE The maximum current I will be limited at the end of the cycle and for the remainder of the half-cycle conduction period. LMT The amplitude is set to the third level to ensure that the inductive load does not conduct load current with a peak amplitude higher than the saturation threshold, and / or to prevent the load from conducting asymmetrical current with a large peak amplitude higher than the saturation threshold.

[0137] Figure 11B This is a flowchart of an example process 1120 for setting the maximum current limit of a load control device based on the type of phase control technology configured thereon. This process 1120 can be performed by a load control device (e.g., Figure 1 The load control device 100 and / or shown Figure 2 The control circuitry (e.g., control circuitry 120 and / or control circuitry 250) of the load control device 200 shown executes to control the drive circuitry (e.g., gate drive circuitry 115, gate drive circuitry 116, and / or gate drive circuitry 220) of the load control device. The control circuitry may execute process 1100 upon startup, in response to a command to control the electrical load, and / or periodically. In some examples, the control circuitry may execute process 1120 in response to receiving a command to control the power supplied to the lighting load. Alternatively or additionally, the control circuitry may execute process 1120 during each half-cycle of the AC power supply.

[0138] The control circuit can execute process 1120 to determine how to control the overcurrent protection (OCP) circuit of the load control device (e.g., Figure 1 The first OCP circuit 117 or the second OCP circuit 118 and / or Figure 2 How does the OCP circuit 230 control the gate drive circuit (e.g., the one supplied to the load control device)? Figure 1 The first gate drive circuit 115 or the second gate drive circuit 116 and / or Figure 2 The drive signal V of the gate drive circuit 220) DR And how to control the limiting signal V LMT The amplitude is used to control the maximum current limit I of the load control device. LMT .

[0139] At position 1122, this control circuit can detect the AC main line voltage V of the AC power supply. AC The zero-crossing point. For example, the load control device may include a zero-crossing detection circuit (e.g., zero-crossing detection circuit 130) that can be coupled to the hot terminal H and the neutral terminal N of the load control device and can generate an indication of the AC main line voltage V. ACThe zero-crossing signal V at the zero-crossing point ZC As described herein, the control circuit can determine the timing for turning one or more semiconductor switches on and / or off based on the zero-crossing point of the AC mains voltage.

[0140] At 1124, the control circuit determines whether to use a positive phase control technique to control the lighting load. The control circuit can determine which technique to use based on one or more factors. The control circuit can be configured (e.g., pre-configured) to use a specific phase control technique. In some examples, the control circuit can determine the phase control technique based on the type of lighting load coupled to the load control device. For example, when the load current I conducted through the semiconductor switch... LOAD The amplitude (e.g., determined by the feedback signal V) FB (Indicated) and AC main line voltage V AC Out-of-phase (e.g., if the feedback signal V) FB Indicated load current I LOAD The zero-crossing point and the zero-crossing signal V ZC Indicated AC main line voltage V AC (If the zero-crossing point is not aligned), the control circuit can determine that the lighting load is an inductive load.

[0141] If the control circuit determines at 1124 to use positive phase control technology to control the lighting load, then the control circuit can wait for the control time t at 1126. CNTL The control circuit can be configured to generate a dimming thermal voltage V across the lighting load in each half-cycle. DH Each half-cycle adjusts the control time (e.g., trigger time or phase angle) to control the amount of power delivered to the lighting load, thereby controlling the current intensity level L of the lighting load. PRES For example, the control circuit can be configured to adjust the control time t in each half-cycle. CNTL To determine the current intensity level L of the lighting load PRES Towards target intensity level L TRGT Adjustments will be made.

[0142] At position 1128, this control circuit controls the drive signal V. DR This signal can be received by the gate drive circuit for controlling the semiconductor switch. The drive signal V DR It can be provided to the gate drive circuit for adjusting the dimming thermal voltage V generated across the lighting load. DH Control time and / or load current I conducted through lighting load LOAD The amplitude, for example, to control the current intensity level L of the lighting load. PRES The control circuit can be configured to adjust the drive signal V. DRThe duty cycle (e.g., on time) is used to adjust the current intensity level L of the lighting load. PRES Towards target intensity level L TRGT Adjustments are required when operating using positive phase control techniques (e.g., ...). Figure 5 and Figures 7 to 10 As shown, this control circuit can control the drive signal V at the beginning of a half-cycle. DR To deactivate the semiconductor switch (e.g., to deactivate the drive signal V) DR The amplitude is oriented towards the supply voltage V CC (Control is high), and then at control time t CNTL Control drive signal V DR This is to turn on the semiconductor switch.

[0143] At 1130, the control circuit can wait for an activation time period T. T-ON (For example, approximately 50 microseconds). In some examples, as described herein, the control circuit can be activated during the turn-on time period T. T-ON Internal target signal V TRGT Shaping is performed to adjust the target signal V. TRGT Shaping is performed. At 1132, this control circuit can be activated during the time period T. T-ON Then the OCP enable signal V OCP-EN The drive is high to enable the OCP circuit of the load control device. The control circuit can then activate the OCP enable signal V at the next zero-crossing event. OCP-EN (For example, towards the circuit common terminal) Driven low. Thus, the control circuit can be configured to enable the overcurrent protection circuit during the conduction period of each half-cycle.

[0144] At 1134, the control circuit can control the maximum current level I. LMT The amplitude is set to a first positive phase control level. In some examples, this first positive phase control level may be a second amplitude (e.g., approximately 20A). As described herein, the gate drive circuit may be based on a limit signal V. LMT To generate the target signal V TRGT This is used to control the semiconductor switch to control the power supplied to the lighting load. Also as described herein, the gate drive circuit can control the load current I conducted through the semiconductor switch. LOAD The amplitude is limited by the limiting signal V LMT Indicated maximum current limit I LMT Thus, the limiting signal V LMT The amplitude can determine the maximum current level I. LMT .

[0145] At position 1136, the control circuit can operate during pulse period T. PULSE The maximum current will be limited I during the duration.LMT The amplitude is set to a positive phase control level (e.g., second amplitude). In some examples, the pulse duration T... PULSE The pulse duration can be approximately 500µs. Furthermore, in some examples, the control circuitry allows adjustment of the pulse duration T. PULSE The duration of the pulse can be adjusted, for example, over multiple half-cycles of the AC mains voltage after the electrical load is turned on. For instance, the control circuit can be configured to adjust the pulse duration T over multiple half-cycles (e.g., approximately 120 half-cycles) after the electrical load is turned on. PULSE Set as the second time period T P2 (For example, approximately 2,000 µs), and after these multiple half-cycles, the pulse period T is applied during the subsequent half-cycle of the AC main line voltage. PULSE Change to the first time period T P1 (For example, approximately 500µs).

[0146] At 1138, this control circuit can limit the maximum current I. LMT The amplitude is set to a second positive phase control level. In some examples, this second positive phase control level may be a first amplitude (e.g., a first limiting amplitude I). MAG1 (e.g., approximately 8A). This control circuit can limit the signal V. LMT The amplitude of the signal is set to a first amplitude (e.g., approximately the common terminal of the circuit) to convert the target signal V TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 This, in turn, limits the maximum current I. LMT Adjust to the first value.

[0147] At 1140, the control circuit can wait for the AC main line voltage V. AC The end of a half-cycle. This control circuit can be based on the AC main line voltage V. AC The zero-crossing point is used to detect the AC main line voltage V. AC The end of the half-cycle. At 1142, the control circuit can disable the OCP circuit, for example by controlling the AC main line voltage V. AC The zero-crossing event will enable the OCP signal V. OCP-EN Drive is low. This control circuit can operate at AC mains voltage V. AC At the start of the next half-cycle, the OCP enable signal V will be... OCP-EN (For example, towards the common terminal of the circuit) Drive low to disable the OCP circuit.

[0148] Thus, the control circuit can operate during the pulse period T. PULSE At the end of the conduction period and for the remainder of the half-cycle of the AC main line voltage, the maximum current limit I will be applied. LMTThe amplitude is set to the second positive phase control level. Therefore, using process 1120, when using positive phase control technology, the control circuit can control the pulse period T. PULSE Internal maximum current limit I LMT The amplitude is set to the first positive phase control level (e.g., the second amplitude) to allow the capacitance of the capacitive load to charge properly in each half-cycle and / or to allow the incandescent lamp load to heat up during the pulse period T. PULSE The maximum current I will be limited at the end of the cycle and for the remainder of the half-cycle conduction period. LMT The amplitude is set to the second positive phase control level (e.g., the first amplitude) to ensure that the inductive load does not conduct load current with an amplitude higher than the saturation threshold.

[0149] If at 1124 the control circuit determines that forward phase control is not used to control the lighting load (e.g., it determines that reverse phase control is used to control the lighting load), then the control circuit can enable the OCP circuit at 1144 (e.g., as described with respect to 1132). At 1146, the control circuit can set the magnitude of the maximum current level to the reverse phase control level. In some examples, this reverse phase control level can be a high level (e.g., approximately 20A). As described herein, the gate drive circuit can be based on a limit signal V LMT To generate the target signal V TRGT This is used to control the semiconductor switch to control the power supplied to the lighting load. Also as described herein, the gate drive circuit can control the load current I conducted through the semiconductor switch. LOAD The amplitude is limited by the limiting signal V LMT Indicated maximum current limit I LMT Thus, the limiting signal V LMT The amplitude can determine the maximum current level I. LMT .

[0150] At position 1148, the control circuit can wait for a control time t. CNTL The control circuit can be configured to generate a dimming thermal voltage V across the lighting load in each half-cycle. DH Adjust control time t per half cycle CNTL (e.g., trigger time or phase angle) to control the amount of power delivered to the lighting load, thereby controlling the current intensity level L of the lighting load. PRES For example, the control circuit can be configured to adjust the control time t in each half-cycle. CNTL To determine the current intensity level L of the lighting load PRES Towards target intensity level L TRGT Adjustments will be made.

[0151] At 1150, this control circuit can control the drive signal V.DR This signal can be received by the gate drive circuit for controlling the semiconductor switch. The drive signal V DR It can be provided to the gate drive circuit for adjusting the dimming thermal voltage V generated across the lighting load. DH Control time and / or load current I conducted through lighting load LOAD The amplitude, for example, to control the current intensity level L of the lighting load. PRES The control circuit can be configured to adjust the drive signal V. DR The duty cycle (e.g., on time) is used to adjust the current intensity level L of the lighting load. PRES Towards target intensity level L TRGT Adjustments are required when operating using reverse phase control techniques (e.g., as...). Figure 6 As shown, this control circuit can control the drive signal V at the beginning of a half-cycle. DR To turn on the semiconductor switch (e.g., to turn on the drive signal V) DR The amplitude is oriented towards the supply voltage V CC (Control is high), and then at control time t CNTL Control drive signal V DR This is to prevent the semiconductor switch from conducting.

[0152] At 1152, the control circuit can, for example, enable the OCP signal V. OCP-EN The drive is low to disable the OCP circuit, and then process 1120 can exit. For example, the control circuit can be set to low during the shutdown period T. T-OFF Initially, the OCP enable signal V is set. OCP-EN Drive is low. This control circuit can operate at AC mains voltage V. AC At the start of the next half-cycle, the OCP enable signal V will be... OCP-EN (For example, towards the common terminal of the circuit) drive high to enable the OCP circuit.

[0153] Figure 11C This is a flowchart of an example process 1160 for adjusting the maximum current limit of a load control device during a pulse period in response to a command to turn on an electrical load. This process 1160 can be performed by a load control device (e.g., Figure 1 The load control device 100 and / or shown Figure 2The control circuitry (e.g., control circuitry 120 and / or control circuitry 250) of the load control device 200 shown executes to control the drive circuitry (e.g., gate drive circuitry 115, gate drive circuitry 116, and / or gate drive circuitry 220) of the load control device. The control circuitry may execute process 1160 upon startup, in response to a command to control the electrical load, and / or periodically. For example, the control circuitry may execute process 1160 in response to a command to turn on the electrical load. The control circuitry may execute process 1160 to adjust the pulse duration of the maximum current limit upon startup to accommodate different load types. The control device may execute process 1160 when configured with positive phase control technology. The control circuitry may combine process 1160 with other processes described herein (e.g., process 1100 and / or process 1120).

[0154] At 1162, the control circuit determines whether an enable command has been received. If no enable command is received, the control circuit exits process 1160. If an enable command is received at 1162, the control circuit can, at 1164, set the pulse duration T within the first time period. PULSE The length (e.g., duration) is set to a first value. For example, as described in this article, the pulse duration T PULSE The length (e.g., duration) can be adjustable. For example, the control circuit can adjust the pulse duration T within a first initial number of line cycles (e.g., approximately 60 half-cycles) of the AC main line voltage. PULSE Set as the first time period T P1 The first time period T P1 It can be approximately 2,000 µs. This is achieved by dividing the pulse duration T over a period of time (e.g., approximately 120 half-cycles). PULSE The length is set to a first value (e.g., about 2,000 µs), and the control circuit allows the capacitance of the capacitive load to charge properly in each half-cycle (e.g., allowing sufficient inrush current) and / or allows the incandescent load to heat up in the first time period.

[0155] At position 1166, the control circuit can control the pulse duration T. PULSE The length (e.g., duration) is set to a second value (e.g., until the electrical load is turned off), and then process 1160 can exit. For example, the control circuit can set the pulse duration T... PULSE Set as the second time period T P2 The second time period T P2 It can be approximately 500µs. This is achieved by extending the pulse duration T after a certain period of time. PULSE The length is set to a second value (e.g., about 500µs), and the control circuit ensures that the inductive load does not conduct load current with an amplitude higher than the saturation threshold.

[0156] In some examples, the control circuitry can set the pulse duration to a second value within a second subsequent number of line cycles (e.g., approximately 60 half-cycles) of the AC main line voltage. In such examples, after the second subsequent number of line cycles of the AC main line voltage, the control circuitry can be configured to limit the signal V. LMT Reduced to a lower value (e.g., approximately the common terminal of the circuit), this can be achieved during the pulse period T. PULSE The target signal V will be used during the line cycle of the AC main line voltage after the application. TRGT The amplitude is adjusted to the first limiting signal amplitude V. MAG1 Therefore, the control circuit can, for example, respond to energizing the lighting load (e.g., only for a specific number of line cycles after energizing the lighting load) and pulse the duration T for a specific number of line cycles. PULSE The length is set to more than one value.

[0157] Figure 12 This is a flowchart of an example process 1200 for controlling the maximum current limit of a load control device based on whether the electrical load coupled to the load control device is an inductive load. This process 1200 can be controlled by a load control device (e.g., Figure 1 The load control device 100 and / or shown Figure 2 The control circuitry (e.g., control circuitry 120 and / or control circuitry 250) of the load control device 200 is executed to control the drive circuitry (e.g., gate drive circuitry 115, gate drive circuitry 116, and / or gate drive circuitry 220) of the load control device. This control circuitry may execute process 1200 at startup, in response to a command to control the electrical load, and / or periodically. The control circuitry may execute process 1200 to determine how to set the amplitude of the maximum current limit differently for different types of inductive loads.

[0158] At position 1202, the control circuit can monitor one or more signals to determine whether the electrical load is inductive. For example, if the load current I conducted through the semiconductor switch... LOAD The amplitude (e.g., determined by the feedback voltage V) FB (Indicated) and AC main line voltage V AC Out of phase (e.g., if caused by feedback signal V) FB Indicated load current I LOAD The zero-crossing point and the zero-crossing signal V ZC Indicated AC main line voltage V AC If the zero-crossing point is misaligned, the control circuit can be configured to determine that the load control device is connected to an inductive load. If the control circuit determines the load current I conducted through the semiconductor switch... LOAD The amplitude and AC main line voltage V ACIf they are in phase, the control circuit can determine that it is not coupled to the inductive load.

[0159] If the control circuit determines at 1204 that the load control device is connected to a non-inductive load, then the control circuit can set the AC main line voltage V at 1206. AC During the conduction period, the maximum current level I will be LMT The amplitude is set to the non-inductive load level. In some examples, this non-inductive load level may be a second amplitude (e.g., approximately 20A). Figure 5 As shown, this gate drive circuit can be based on the limiting signal V LMT To generate the target signal V TRGT This is used to control the semiconductor switch to control the power supplied to the lighting load. Also as described herein, the gate drive circuit can control the load current I conducted through the semiconductor switch. LOAD The amplitude is limited by the limiting signal V LMT Indicated maximum current limit I LMT Thus, the limiting signal V LMT The amplitude can determine the maximum current level I. LMT Therefore, when coupled to a non-inductive load such as an incandescent lamp load or a capacitive load, this control circuit can limit the maximum current I. LMT The amplitude is set to the non-inductive load level to, for example, allow the electrical load to conduct a larger surge current for a portion of the half-cycle (e.g., in the case of a capacitive load) and / or allow the electrical load to heat up after being turned on (e.g., in the case of an incandescent load).

[0160] If the control circuit determines at 1204 that the load control device is connected to an inductive load, then the control circuit can limit the maximum current I at 1208. LMT The amplitude is set to one or more inductive load levels. In some examples, this inductive load level can be a single level, such as a first amplitude (e.g., approximately 8A), for example... Figure 7 As shown. In other examples, the inductive load level can be a combination of two different levels, such as a second amplitude and a first amplitude, for example, as... Figure 8 and Figure 9 As shown. For example, the inductive load level may include a pulse duration T. PULSE The first level used internally, and in the AC main line voltage V ACThe second level is used during the remainder of the conduction period. Furthermore, in some examples, the inductive load level may include multiple different levels, such that during the conduction period of a half-cycle of the AC main line voltage, the inductive load level varies with time between a first level (e.g., a second amplitude) and a second level (e.g., a first amplitude). In some cases, the inductive load level may vary linearly between the first and second levels during the adjustment period, for example, as... Figure 10 As shown. As described herein, when connected to an inductive load, this control circuit can be configured with positive phase control technology.

[0161] Therefore, when connected to an inductive load, this control circuit can be configured to limit the maximum current I. LMT The amplitude is set to one or more inductive load levels to allow the overcurrent protection circuit to properly protect the inductive load from large load currents. For example, the one or more inductive load levels can be set to prevent the inductive load from overheating or saturating when using positive phase control technology.

Claims

1. A load control device configured to control the power supplied from an AC power source to an electrical load, the load control device comprising: A controllable conductive device adapted to be coupled in series between an AC power source and an electrical load, wherein the AC power source is configured to generate an AC main line voltage, and wherein the controllable conductive device includes a semiconductor switch configured to conduct load current through the electrical load. A closed-loop gate drive circuit coupled to the semiconductor switch and configured to turn the semiconductor switch on or off at a control time during half a cycle of the AC main line voltage, wherein the closed-loop gate drive circuit is configured to limit the amplitude of the load current conducted through the semiconductor switch to a maximum current limit. as well as Control circuit, the control circuit being configured to: A drive signal is generated to adjust the control time of the semiconductor switch during each half-cycle of the AC main line voltage, thereby controlling the amount of power delivered to the electrical load. The drive signal is controlled to turn on the semiconductor switch at a control time during half a cycle of the AC main line voltage, thereby keeping the semiconductor switch on during the on-time period of the half cycle of the AC main line voltage. During the conduction period of the half-cycle of the AC main line voltage and for a period of time after the control time, the maximum current limit of the closed-loop gate drive circuit is set to a first limit. as well as During the conduction period of the half-cycle of the AC main line voltage, after the expiration of the time period, the maximum current limit of the closed-loop gate drive circuit is set to a second limit, wherein the second limit is less than the first limit.

2. The load control device as claimed in claim 1, wherein the control circuit is configured to: During a pulse period beginning at the control time within the half-cycle of the AC main line voltage, the maximum current limit is set to the first limit; and At the end of the pulse period and during the remainder of the conduction period of the half-cycle of the AC main line voltage, the maximum current limit is set to the second limit.

3. The load control device as claimed in claim 2, wherein the pulse duration is approximately 500 microseconds.

4. The load control device of claim 2, wherein the control circuit is configured to set the maximum current limit to the first limit during the pulse period to allow the capacitance of the capacitive load to charge during the half-cycle of the AC mainline voltage.

5. The load control device as claimed in claim 2, wherein the control circuit is configured to: During the initial plurality of half-cycles of the AC main line voltage after the electrical load is turned on, during the pulse period following the control time of the semiconductor switch, the maximum current limit of the closed-loop gate drive circuit is set to the first limit; and After the initial plurality of half-cycles of the AC main line voltage, while controlling the power of the electrical load, the maximum current limit of the closed-loop gate drive circuit is set to the second limit at the control time during the subsequent half-cycles of the AC main line voltage after the initial plurality of half-cycles.

6. The load control device of claim 5, wherein the control circuit is configured to shorten the duration of the pulse period during the initial plurality of half-cycles of the AC main line voltage after the electrical load is turned on.

7. The load control device of claim 2, wherein the control circuit is configured to: During multiple half-cycles after the electrical load is turned on, the length of the pulse period is set to a second time period; and After the plurality of half cycles and while controlling the power to the electrical load, the length of the pulse period is set as a first time period.

8. The load control device of claim 7, wherein the first time period is approximately 500 microseconds, the second time period is approximately 2,000 microseconds, and the plurality of half-cycles is approximately 120 half-cycles.

9. The load control device of claim 2, wherein the control circuit is configured to: The maximum current limit is adjusted within a range from the first limit to the second limit over multiple half-cycles of the AC main line voltage.

10. The load control device of claim 9, wherein the control circuit is configured to: During the plurality of half-cycles of the AC main line voltage, the maximum current limit is linearly reduced within the range of values ​​from the first limit to the second limit.

11. The load control device as claimed in claim 1, wherein, When operated with positive phase control technology, the control circuit is configured as follows: While controlling the power to the electrical load, the maximum current limit of the closed-loop gate drive circuit is set to the first limit for a period of time after the control time of the semiconductor switch during the on-time period of each half-cycle of the AC main line voltage. as well as While controlling the power to the electrical load, after the expiration of the period during the conduction period of each half-cycle of the AC main line voltage, the maximum current limit of the closed-loop gate drive circuit is set to the second limit.

12. The load control device as claimed in claim 11, wherein, When operated with reverse phase control technology, the control circuit is configured as follows: While controlling the power to the electrical load, the maximum current limit of the closed-loop gate drive circuit is set to a third limit during the entire on-time period of each half-cycle of the AC main line voltage.

13. The load control device of claim 12, wherein the third limitation is equal to the first limitation.

14. The load control device of claim 1, wherein the closed-loop gate drive circuit is configured as follows: The system generates a target signal in response to the control circuit, receives a feedback signal indicating the amplitude of the load current conducted through the semiconductor switch, and generates a gate control signal in response to the target signal and the feedback signal. The semiconductor switch of the controllable conductive device is configured to be turned on and off in response to the gate control signal.

15. The load control device as claimed in claim 1, wherein, When using positive phase control technology, the control circuit is configured as follows: The drive signal is controlled to de-energize the semiconductor switch at the beginning of each half-cycle of the AC main line voltage. as well as During the control of the power to the electrical load, the drive signal is controlled to turn on the semiconductor switch at the control time during each half-cycle of the AC main line voltage and throughout the remainder of each half-cycle of the AC main line voltage.

16. The load control device as claimed in claim 15, wherein, When using reverse phase control technology, the control circuit is configured as follows: The drive signal is controlled to turn on the semiconductor switch at the beginning of each half-cycle of the AC main line voltage; as well as The drive signal is controlled to de-energize the semiconductor switch at the control time during each half-cycle of the AC main line voltage.

17. The load control device of claim 1, wherein the control circuit is configured to control the semiconductor switch to be non-conducting during a non-conducting period and to be conducting during a conducting period during one or more half-cycles of the AC main line voltage, so as to control the amount of power delivered to the electrical load.

18. A load control device configured to control the power supplied from an AC power source to an electrical load, the load control device comprising: A controllable conductive device adapted to be coupled in series between an AC power source and an electrical load, wherein the AC power source is configured to generate an AC main line voltage, and wherein the controllable conductive device includes a semiconductor switch configured to conduct load current through the electrical load. A closed-loop gate drive circuit coupled to the semiconductor switch and configured to turn the semiconductor switch on or off at a control time during half a cycle of the AC main line voltage, wherein the closed-loop gate drive circuit is configured to limit the amplitude of the load current conducted through the semiconductor switch to a maximum current limit, wherein the maximum current limit is adjustable between a first limit and a second limit. as well as Control circuit, the control circuit being configured to: A drive signal is generated to adjust the control time of the semiconductor switch during each half-cycle of the AC main line voltage, thereby controlling the amount of power delivered to the electrical load. The electrical load is determined to be an inductive load; and The maximum current limit of the closed-loop gate drive circuit is set to the second limit based on the fact that the electrical load is an inductive load.

19. The load control device of claim 18, wherein the control circuit is configured to determine that the electrical load is an inductive load based on the fact that the amplitude of the load current conducted through the semiconductor switch is out of phase with the AC main line voltage.

20. The load control device of claim 19, further comprising: A zero-crossing detection signal, configured to generate a zero-crossing signal indicating the zero-crossing point of the AC main line voltage; as well as A feedback resistor, which is coupled in series to the semiconductor switch and configured to generate a feedback signal; The control circuit is configured to determine the zero-crossing point of the AC main line voltage based on the zero-crossing signal generated by the zero-crossing detection signal, and to determine the zero-crossing point of the load current conducted through the semiconductor switch based on the feedback signal generated by the feedback resistor.

21. The load control device of claim 20, wherein when the zero-crossing point of the load current conducted through the semiconductor switch is not aligned with the zero-crossing point of the AC main line voltage, the control device is configured to determine that the load current conducted through the semiconductor switch is out of phase with the AC main line voltage.

22. The load control device of claim 18, wherein the control circuit is configured to determine operation using a positive phase control technique based on the electrical load being an inductive load.

23. The load control device of claim 18, wherein the control circuit is configured to detect whether it operates according to a reverse phase control technique or a forward phase control technique based on the electrical load; in, When operated with reverse phase control technology, the control circuit is configured to set the maximum current limit of the closed-loop gate drive circuit to the first limit.

24. The load control device of claim 23, wherein when operating with the positive phase control technique and based on the fact that the electrical load is not an inductive load, the control circuit is configured such that the maximum current limit of the closed-loop gate drive circuit is set to the first limit.

25. The load control device of claim 23, wherein when operating with the positive phase control technique and based on the fact that the electrical load is not an inductive load, the control circuit is configured to set the maximum current limit of the closed-loop gate drive circuit to the first limit for a period of time after the control time during the on-time period of the half-cycle of the AC main line voltage, and to set the maximum current limit to the second limit after the expiration of the period of time during the on-time period of the half-cycle of the AC main line voltage.

26. A load control device configured to control the power supplied from an AC power source to an electrical load, the load control device comprising: A controllable conductive device adapted to be coupled in series between an AC power source and an electrical load, wherein the AC power source is configured to generate an AC main line voltage, and wherein the controllable conductive device includes a semiconductor switch configured to conduct load current through the electrical load. A closed-loop gate drive circuit coupled to the semiconductor switch and configured to turn the semiconductor switch on or off at a control time during half a cycle of the AC main line voltage, wherein the closed-loop gate drive circuit is configured to limit the amplitude of the load current conducted through the semiconductor switch to a maximum current limit. as well as Control circuit, the control circuit being configured to: During the initial multiple half-cycles of the AC main line voltage after the electrical load is turned on: During the conduction period of each half-cycle of the AC main line voltage in the initial plurality of half-cycles, and for a period of time after the control time of the semiconductor switch, the maximum current limit of the closed-loop gate drive circuit is set to a first limit. as well as After the expiration of a certain period during the conduction period of each half-cycle of the AC main line voltage in the initial plurality of half-cycles, the maximum current limit of the closed-loop gate drive circuit is set to a second limit, wherein the second limit is less than the first limit; and After the initial plurality of half-cycles of the AC main line voltage, while controlling the power of the electrical load, the maximum current limit of the closed-loop gate drive circuit is set to the second limit during the control time in the subsequent half-cycles of the AC main line voltage after the initial plurality of half-cycles and during the entire conduction period.

27. The load control device of claim 26, wherein the control circuit is configured to determine to operate with a positive phase control technique.

28. The load control device of claim 26, wherein the time period is based on the initial plurality of half cycles of the AC main line voltage.

29. The load control device of claim 26, wherein the control circuit is configured to shorten the duration of the pulse period during the initial plurality of half-cycles of the AC main line voltage after the electrical load is turned on.

30. The load control device of claim 26, wherein the control circuitry is configured to set the maximum current limit to the first limit during a pulse period to allow the capacitance of the capacitive load to charge during the half-cycle of the AC mainline voltage.

31. The load control device of claim 26, wherein the control circuit is configured to: The maximum current limit is adjusted within a range from the first limit to the second limit over multiple half-cycles of the AC main line voltage.

32. A load control device configured to control the power supplied from an AC power source to an electrical load, the load control device comprising: A controllable conductive device adapted to be coupled in series between an AC power source and an electrical load, wherein the AC power source is configured to generate an AC main line voltage, and wherein the controllable conductive device includes a semiconductor switch configured to conduct load current through the electrical load. A control circuit configured to generate a drive signal to adjust the control time of the semiconductor switch during each half-cycle of the AC main line voltage, thereby controlling the amount of power delivered to the electrical load. as well as A closed-loop gate drive circuit, coupled to the semiconductor switch, is configured to: Receive the drive signal from the control circuit; In response to the drive signal, the semiconductor switch is turned on or off at the control time during half a cycle of the AC main line voltage. as well as The amplitude of the load current conducted through the semiconductor switch is limited to a maximum current limit, wherein the closed-loop gate drive circuit is configured to adjust the maximum current limit from a first limit to a second limit during the on-time of half a cycle of the AC main line voltage, wherein the second limit is less than the first limit.

33. The load control device of claim 32, wherein the closed-loop gate drive circuit is configured to: turn on the semiconductor switch at the control time when operating with a forward phase control technique; and turn off the semiconductor switch at the control time when operating with a reverse phase control technique.

34. The load control device of claim 32, wherein the closed-loop gate drive circuit is configured to receive a feedback signal indicating the magnitude of the load current and, in response to the feedback signal, generate a gate control signal for turning the semiconductor switch on or off.

35. The load control device of claim 34, wherein the closed-loop gate drive circuit includes an operational amplifier circuit configured to control the amplitude of the gate control signal in response to the amplitude of the load current.

36. The load control device of claim 34, wherein the closed-loop gate drive circuit includes an operational amplifier circuit configured to generate the gate control signal based on the feedback signal and a target signal, wherein the target signal indicates a target amplitude of the load current.

37. The load control device of claim 36, wherein the closed-loop gate drive circuit includes an on circuit and an off circuit for controlling the generation of the target signal.

38. The load control device of claim 37, wherein the turn-on circuit is configured to generate the target signal when the load control device is configured to operate using a forward phase control dimming technique, and wherein the turn-off circuit is configured to generate the target signal when the load control device is configured to operate using a reverse phase control dimming technique.

39. A method performed by a load control device configured to control power supplied from an AC power source to an electrical load, the method comprising: A drive signal is generated to adjust the control time of the semiconductor switch of the load control device during each half-cycle of the AC main line voltage, thereby controlling the amount of power delivered to the electrical load. The drive signal is controlled to turn on the semiconductor switch at a control time during half a cycle of the AC main line voltage, thereby keeping the semiconductor switch on during the on-time period of the half cycle of the AC main line voltage. During the conduction period of the half-cycle of the AC main line voltage and for a period of time after the control time, the maximum current limit of the closed-loop gate drive circuit is set to a first limit, wherein the closed-loop gate drive circuit is configured to limit the amplitude of the load current conducted through the semiconductor switch to the maximum current limit. as well as During the conduction period of the half-cycle of the AC main line voltage, after the expiration of the time period, the maximum current limit of the closed-loop gate drive circuit is set to a second limit, wherein the second limit is less than the first limit.

40. The method of claim 39, further comprising: During the pulse period that begins at the control time during the half-cycle of the AC main line voltage, the maximum current limit is set to the first limit; as well as At the end of the pulse period and during the remainder of the conduction period of the half-cycle of the AC main line voltage, the maximum current limit is set to the second limit.

41. The method of claim 40, wherein the pulse duration is approximately 500 microseconds.

42. The method of claim 40, further comprising: The maximum current limit is set to the first limit during the pulse period to allow the capacitance of the capacitive load to charge during the half-cycle of the AC main line voltage.

43. The method of claim 40, further comprising: During the initial multiple half-cycles of the AC main line voltage after the electrical load is turned on, during the pulse period after the control time of the semiconductor switch, the maximum current limit of the closed-loop gate drive circuit is set to the first limit. as well as After the initial plurality of half-cycles of the AC main line voltage, while controlling the power of the electrical load, the maximum current limit of the closed-loop gate drive circuit is set to the second limit at the control time during the subsequent half-cycles of the AC main line voltage after the initial plurality of half-cycles.

44. The method of claim 43, further comprising: During the initial plurality of half-cycles of the AC main line voltage after the electrical load is turned on, the duration of the pulse period is shortened.

45. The method of claim 40, further comprising: During multiple half-cycles after the electrical load is turned on, the length of the pulse period is set as a second time period; as well as After the plurality of half cycles and while controlling the power to the electrical load, the length of the pulse period is set as a first time period.

46. ​​The method of claim 45, wherein the first time period is approximately 500 microseconds, the second time period is approximately 2,000 microseconds, and the plurality of half-cycles is approximately 120 half-cycles.

47. The method of claim 40, further comprising: The maximum current limit is adjusted within a range from the first limit to the second limit over multiple half-cycles of the AC main line voltage.

48. The method of claim 47, further comprising: During the plurality of half-cycles of the AC main line voltage, the maximum current limit is linearly reduced within the range of values ​​from the first limit to the second limit.

49. The method of claim 39, wherein, When operated with positive phase control technology, the method further includes: While controlling the power to the electrical load, during the on-time period of each half-cycle of the AC main line voltage, and for a period of time after the control time of the semiconductor switch, the maximum current limit of the closed-loop gate drive circuit is set to the first limit; and While controlling the power to the electrical load, after the expiration of the period during the conduction period of each half-cycle of the AC main line voltage, the maximum current limit of the closed-loop gate drive circuit is set to the second limit.

50. The method of claim 49, wherein, When operated with reverse phase control technology, the method further includes: While controlling the power to the electrical load, the maximum current limit of the closed-loop gate drive circuit is set to a third limit during the entire on-time period of each half-cycle of the AC main line voltage.

51. The method of claim 50, wherein the third limitation is equal to the first limitation.

52. The method of claim 39, wherein, When using positive phase control technology, the method further includes: Control the drive signal to de-energize the semiconductor switch at the beginning of each half-cycle of the AC main line voltage; and During the control of the power to the electrical load, the drive signal is controlled to turn on the semiconductor switch at the control time during each half-cycle of the AC main line voltage and throughout the remainder of each half-cycle of the AC main line voltage.

53. The method of claim 52, wherein, When using reverse phase control technology, the method further includes: Control the drive signal to turn on the semiconductor switch at the beginning of each half-cycle of the AC main line voltage; and The drive signal is controlled to de-energize the semiconductor switch at the control time during each half-cycle of the AC main line voltage.

54. The method of claim 39, further comprising: During one or more half-cycles of the AC main line voltage, the semiconductor switch is controlled to be non-conducting during non-conducting periods and conduct during conducting periods to control the amount of power delivered to the electrical load.

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