Display panel, display device and method of manufacturing a display panel

Abstract

A display panel includes a display area, one or more scan circuits located in a peripheral area, a plurality of connection lines located in an area between the display area and the one or more scan circuits, the plurality of connection lines configured to provide signals to a row of pixel drive circuits in the display area, and a plurality of electrodes located in the area between the display area and the one or more scan circuits. The plurality of electrodes includes a plurality of output electrodes respectively connected to output signal lines. Each output electrode of the plurality of output electrodes is positioned such that a respective output signal line connected to the respective output electrode extends substantially parallel to a first direction to connect to a corresponding terminal in a pixel drive circuit in the display panel. The plurality of connection lines extend along a second direction different from the first direction.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a display panel, a display device, and a method for manufacturing the display panel. Background Technology

[0002] Display technology has advanced significantly, enabling advancements in applications such as consumer electronics, automotive displays, industrial panels, and augmented reality devices. Among various display technologies, active-matrix organic light-emitting diode (AMOLED) displays are widely used due to their high contrast, fast response time, and power efficiency. These characteristics make AMOLED displays particularly suitable for high-resolution and flexible display applications. Summary of the Invention

[0003] In one aspect, this disclosure provides a display panel, comprising: a display area; one or more scanning circuits located in a peripheral area outside the display area; a plurality of connecting lines located in a region between the display area and the one or more scanning circuits, the plurality of connecting lines being configured to provide signals to a row of pixel driving circuitry in the display area; and a plurality of electrodes located in the region between the display area and the one or more scanning circuits; wherein the plurality of electrodes includes a plurality of output electrodes respectively connected to output signal lines; each of the plurality of output electrodes is positioned such that a corresponding output signal line connected to the corresponding output electrode extends substantially parallel to a first direction to connect to a corresponding terminal in the pixel driving circuitry in the display panel; and the plurality of connecting lines extend along a second direction different from the first direction.

[0004] Optionally, the plurality of electrodes includes a first input electrode, a first output electrode, a second input electrode, and a second output electrode; the first input electrode, the first output electrode, the second input electrode, and the second output electrode are arranged sequentially along the first direction; and the first input electrode, the second input electrode, the first output electrode, and the second output electrode are arranged sequentially along the second direction.

[0005] Optionally, the plurality of electrodes includes a first input electrode, a first output electrode, a second input electrode, and a second output electrode; the first input electrode, the first output electrode, the second input electrode, and the second output electrode are arranged sequentially along the first direction; and the first input electrode, the first output electrode, the second input electrode, and the second output electrode are arranged sequentially along the second direction.

[0006] Optionally, at least one connecting line adjacent to at least one of the plurality of electrodes includes one or more diagonal segments; and each of the one or more diagonal segments extends in a direction different from the first direction and different from the second direction.

[0007] Optionally, the orthographic projection of each of the plurality of electrodes on the substrate at least partially overlaps with the orthographic projection of two adjacent connecting lines on the substrate; and the gap between each electrode relative to the adjacent connecting lines is centered.

[0008] Optionally, each electrode includes a first portion located in a first signal line layer and a second portion located in a second signal line layer; the orthographic projection of the first portion on the substrate at least partially overlaps with the orthographic projection of the two adjacent connecting lines on the substrate; and the orthographic projection of the second portion on the substrate at least partially overlaps with the orthographic projection of the two adjacent connecting lines on the substrate.

[0009] Optionally, the width of the second portion along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate is within the range of 1 to 1.5 times the width of the corresponding connecting line along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate.

[0010] Optionally, the width of the second portion along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate is greater than or equal to 1.5 times the width of the corresponding connecting line along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate.

[0011] Optionally, the orthographic projection of each electrode on the substrate covers the orthographic projection of the corresponding connecting line on the substrate.

[0012] Optionally, each electrode includes a first portion located in a first signal line layer and a second portion located in a second signal line layer; the orthographic projection of the first portion on the substrate covers the orthographic projection of the corresponding connection line on the substrate; and the orthographic projection of the second portion on the substrate covers the orthographic projection of the corresponding connection line on the substrate.

[0013] Optionally, the width of the second portion along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate is in the range of 1 to 1.5 times the width of the corresponding connecting line along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate.

[0014] Optionally, the width of the second portion along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate is greater than or equal to 1.5 times the width of the corresponding connecting line along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate.

[0015] Optionally, the display panel includes a plurality of signal lines configured to provide signals to a row of pixel driving circuits; wherein the plurality of signal lines are connected to a corresponding scanning circuit in one or more scanning circuits; and the plurality of signal lines are alternately arranged in two different layers in the peripheral region of the display panel.

[0016] Optionally, the plurality of signal lines located in the peripheral area include a first reset voltage line, a second scan signal line, a gate line, a first scan signal line, a first light emission control signal line, a second light emission control signal line, and a second reset voltage line.

[0017] Optionally, the two different layers are a first gate metal layer and a second gate metal layer; the plurality of interconnects are located on a first signal line layer; the second gate metal layer is located on the side of the first gate metal layer away from the substrate; and the first signal line layer is located on the side of the second gate metal layer away from the substrate.

[0018] Optionally, the same layer is a first signal line layer; the plurality of connection lines are located in the first gate metal layer or the first signal line layer; and the second signal line layer is located on the side of the first signal line layer away from the first gate metal layer.

[0019] Optionally, the same layer is a second signal line layer; the plurality of connection lines are located in the first gate metal layer or the first signal line layer; and the second signal line layer is located on the side of the first signal line layer away from the first gate metal layer.

[0020] Optionally, the display panel further includes: a second scanning circuit; a third scanning circuit; a first connecting line that connects the second scanning signal line to the preceding stage of the second scanning circuit; and a second connecting line that connects the second light emission control signal line to the preceding stage of the third scanning circuit; the first connecting line and the second scanning signal line are located on two different layers; and the second connecting line and the second light emission control signal line are located on two different layers.

[0021] In another aspect, this disclosure provides a display device including the display panel described herein and one or more integrated circuits connected to the display panel.

[0022] In another aspect, this disclosure provides a method of manufacturing a display panel, comprising: forming a display area; forming one or more scanning circuits located in a peripheral region outside the display area; forming a plurality of connecting lines located in a region between the display area and the one or more scanning circuits, the plurality of connecting lines being configured to provide signals to a row of pixel driving circuits in the display area; and forming a plurality of electrodes located in the region between the display area and the one or more scanning circuits; wherein forming the plurality of electrodes includes forming a plurality of output electrodes respectively connected to output signal lines; each of the plurality of output electrodes is positioned such that a corresponding output signal line connected to the corresponding output electrode extends substantially parallel to a first direction to connect to a corresponding terminal in the pixel driving circuits in the display panel; and the plurality of connecting lines extend along a second direction different from the first direction. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a circuit diagram illustrating the structure of a pixel driving circuit in a display panel according to some embodiments of the present disclosure.

[0025] Figure 2 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0026] Figure 3 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure.

[0027] Figure 4 It is along Figure 3 Cross-sectional view of line A-A' in the middle.

[0028] Figure 5 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure.

[0029] Figure 6A This is a schematic diagram illustrating the structure of a portion of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure.

[0030] Figure 6B It is shown Figure 6A A schematic diagram of the structure of the semiconductor material layer in a portion of the corresponding scanning unit shown.

[0031] Figure 6C It is shown Figure 6A A schematic diagram of the structure of the first gate metal layer in a portion of the corresponding scanning unit shown.

[0032] Figure 6D It is shown Figure 6A A schematic diagram of the structure of the second gate metal layer in a portion of the corresponding scanning unit shown.

[0033] Figure 6E It is shown Figure 6A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the corresponding scanning unit shown.

[0034] Figure 6F It is shown Figure 6A A schematic diagram of the structure of the first signal line layer in a portion of the corresponding scanning unit shown.

[0035] Figure 7 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure.

[0036] Figure 8 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure.

[0037] Figure 9 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure.

[0038] Figure 10 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure.

[0039] Figure 11A The diagram illustrates a plurality of connection lines in a display panel according to some embodiments of the present disclosure, among a plurality of connection lines between the display area and one or more scanning circuits.

[0040] Figure 11B The diagram illustrates a plurality of connection lines in a display panel according to some embodiments of the present disclosure, among a plurality of connection lines between the display area and one or more scanning circuits.

[0041] Figure 12 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure.

[0042] Figure 13 This is a schematic diagram illustrating the structure of a portion of a scanning circuit according to some embodiments of the present disclosure.

[0043] Figure 14 The arrangement of output and input electrodes in the region between the display area and one or more scanning circuits is shown in some embodiments of the present disclosure.

[0044] Figure 15The arrangement of output and input electrodes in the region between the display area and one or more scanning circuits is shown in some embodiments of the present disclosure.

[0045] Figure 16 The arrangement of output and input electrodes in the region between the display area and one or more scanning circuits is shown in some embodiments of the present disclosure.

[0046] Figure 17 The arrangement of output and input electrodes in the region between the display area and one or more scanning circuits is shown in some embodiments of the present disclosure.

[0047] Figure 18 The diagram illustrates the connections between corresponding electrodes and corresponding connecting lines in some embodiments according to this disclosure.

[0048] Figure 19 The diagram illustrates the connections between corresponding electrodes and corresponding connecting lines in some embodiments according to this disclosure.

[0049] Figure 20 The diagram illustrates the connections between corresponding electrodes and corresponding connecting lines in some embodiments according to this disclosure.

[0050] Figure 21 The diagram illustrates the connections between corresponding electrodes and corresponding connecting lines in some embodiments according to this disclosure. Detailed Implementation

[0051] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0052] Organic light-emitting diode (OLED) display technology has been widely applied in fields such as flexible displays, smart medical devices, advanced driver assistance systems, and wearable devices. Despite the extensive use of AMOLED displays, challenges related to their lifespan and reliability remain key technical issues requiring further research and solutions. The lifespan of OLED materials and the instability of the threshold voltage of thin-film transistors (TFTs) jointly contribute to OLED image retention (display ghosting). Essentially, this phenomenon is caused by device performance degradation, where the display brightness of the OLED changes at the same driving voltage. As a result, information from the previous image can be retained in the subsequent image during image transitions.

[0053] To address the image retention issue in OLED displays, one solution is to develop high-performance OLED luminescent materials to extend the OLED's lifespan. Simultaneously, it's necessary to optimize TFT performance and enhance the stability of the active matrix drive to fundamentally slow down the degradation process of OLED devices. Another approach is to employ external compensation techniques, including designing external driving circuits and pixel brightness compensation methods, to indirectly mitigate the OLED image retention problem.

[0054] External compensation is achieved by writing the data voltage Vdata and the TFT threshold voltage Vth into the storage capacitor Cst through a compensation circuit, thereby reducing the impact of Vth drift on the driving current of the subsequent light-emitting stage. Before writing Vdata, the reset of critical nodes is crucial, including the source, drain, gate, and anode of the driving transistor. These resets must follow a specific sequence and require different reset voltages. Furthermore, the need for narrow bezels limits the number of GOA circuits, promoting the development of GOA output signal multiplexing technology. This technology allows output signals to be input to different pixel rows in a staggered manner. These staggered outputs include both advance and lag stages, requiring a considerable number of connection lines. Therefore, optimizing the layout of these connections is essential for achieving narrow bezels.

[0055] Figure 1 This is a circuit diagram illustrating the structure of a pixel driving circuit in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 1 In some embodiments, the pixel driving circuit PDC includes a driving transistor T3, a data writing transistor T4, a compensation transistor T2, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T1, a second reset transistor T7, and a storage capacitor Cst.

[0056] The first electrode of the first light-emitting control transistor T5 is coupled to the first voltage supply line Vdd, the second electrode of the first light-emitting control transistor T5 is coupled to the second node N2, and the gate of the first light-emitting control transistor T5 is coupled to the first light-emitting control signal line EM_N.

[0057] The first electrode of the data writing transistor T4 is coupled to the data line DL, the second electrode of the data writing transistor T4 is coupled to the second node N2, and the gate of the data writing transistor T4 is coupled to the gate line Gate.

[0058] The first electrode of the driving transistor T3 is coupled to the second node N2, the second electrode of the driving transistor T3 is coupled to the third node N3, and the gate of the driving transistor T3 is coupled to the first node N1.

[0059] The first electrode of the second light-emitting control transistor T6 is coupled to the third node N3, the second electrode of the second light-emitting control transistor T6 is coupled to the fourth node N4, and the gate of the second light-emitting control transistor T6 is coupled to the second light-emitting control signal line EM_N-4. Optionally, the second light-emitting control signal line EM_N-4 is connected to the second stage of the scanning circuit, the first light-emitting control signal line EM_N is connected to the first stage of the scanning circuit, and the second stage is four stages before the first stage.

[0060] The first electrode of the second reset transistor T7 is coupled to the second reset signal line Vint2, the second electrode of the second reset transistor T7 is coupled to the fourth node N4, and the gate of the second reset transistor T7 is coupled to the reset signal line Reset.

[0061] The first electrode of the first reset transistor T1 is coupled to the first reset voltage line Vint1, the second electrode of the first reset transistor T1 is coupled to node N1, and the gate of the first reset transistor T1 is coupled to the second scan signal line Scan_N-7.

[0062] The first electrode of the compensation transistor T2 is coupled to the third node N3, the second electrode of the compensation transistor T2 is coupled to the first node N1, and the gate of the compensation transistor T2 is coupled to the first scan signal line Scan_N.

[0063] The first electrode of the storage capacitor Cst is coupled to node N1, and the second electrode of the storage capacitor Cst is coupled to the first voltage supply line Vdd.

[0064] The cathode of the light-emitting element LE is coupled to the second voltage supply line Vss.

[0065] In some embodiments, the transistors in the pixel driving circuit are p-type transistors.

[0066] Figure 2 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figure 2 During one frame of an image, the operation of each first pixel driving circuit and each second pixel driving circuit includes a first time period t1, a second time period t2, a third time period t3, a fourth time period t4, a fifth time period t5, and a sixth time period t6.

[0067] During the first time period t1, the scan signal provided by the scan signal line Scan_N-7 is pulled low, turning on the first reset transistor T1. This allows the reset voltage provided by the first reset signal line Vint1 to be written to the first node N1.

[0068] During the second time period t2, the scan signal provided by the scan signal line Scan_N is pulled low, and the compensation transistor T2 is turned on. The scan signal provided by the scan signal line Scan_N-7 remains low, turning on the first reset transistor T1. This operation resets the third node N3.

[0069] During the third time period t3, the gate scan signal provided by the gate line is pulled low, thereby turning on the data write transistor T4. The scan signal provided by the scan signal line Scan_N-7 is pulled high, causing the first reset transistor T1 to turn off. The scan signal provided by the scan signal line Scan_N remains low, thereby turning on the compensation transistor T2. This operation causes the data voltage provided by the data line DL and the threshold voltage Vth of the drive transistor to be written to the first node N1.

[0070] During the fourth time period t4, both the scan signal provided by the scan signal line Scan_N and the gate scan signal provided by the gate line Gate are pulled high, while the reset control signal provided by the reset control signal line Reset is pulled low. The second reset transistor T7 is activated, allowing the reset voltage provided by the second reset signal line Vint2 to be written to the fourth node N4, thereby resetting the anode of the light-emitting element LE.

[0071] During the fifth time period t5, the light emission control signal provided by the second light emission control signal line EM_N-4 goes low, thereby activating the second light emission control transistor T6.

[0072] During the sixth time period t6, the light-emitting control signal provided by the first light-emitting control signal line EM_N is pulled low, activating the driving transistor T3, the first light-emitting control transistor T5, and the second light-emitting control transistor T6. This allows current to flow through the light-emitting element LE, thereby emitting light.

[0073] Before the data writing and emission phases, nodes N1, N2, N3, and N4 are reset sequentially. This reset process is coordinated with the surrounding GOA signals, with the early-stage GOA signals playing a crucial role in achieving the reset.

[0074] Therefore, this disclosure particularly provides a display panel, display device, and method of manufacturing a display panel, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display panel. In some embodiments, the display panel includes a display area; one or more scanning circuits located in a peripheral region outside the display area; a plurality of connecting lines located in a region between the display area and the one or more scanning circuits, the plurality of connecting lines being configured to provide signals to a row of pixel driving circuitry in the display area; and a plurality of electrodes located in a region between the display area and the one or more scanning circuits. Optionally, the plurality of electrodes includes a plurality of output electrodes respectively connected to output signal lines. Optionally, each of the plurality of output electrodes is positioned such that each output signal line connected to the respective output electrode extends substantially parallel to a first direction to connect to a corresponding terminal in the pixel driving circuitry in the display panel. Optionally, the plurality of connecting lines extend along a second direction different from the first direction.

[0075] Figure 3 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 3 In some embodiments, multiple signal lines configured to provide signals to a row of pixel driving circuitry are alternately arranged in two different layers in the peripheral region of the display panel. In some embodiments, the multiple signal lines located in the peripheral region include a first reset voltage line Vint1, a second scan signal line Scan_N-7, a gate line Gate, a first scan signal line Scan_N, a first light emission control signal line EM_N, a second light emission control signal line EM_N-4, and a second reset voltage line Vint2. In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are alternately arranged in two different layers in the peripheral region of the display panel. The inventors of this disclosure have found that alternating wiring results in a smaller spacing requirement between different layers than within the same layer, thereby reducing wiring space.

[0076] In some embodiments, the two distinct layers are a first gate metal layer and a second gate metal layer. Optionally, the second gate metal layer is located on the side of the first gate metal layer away from the substrate. See also Figure 3In some embodiments, the first reset voltage line Vint1, the gate line Gate, the first light emission control signal line EM_N, and the second reset voltage line Vint2 are located in the second gate metal layer; the second scan signal line Scan_N-7, the first scan signal line Scan_N, and the second light emission control signal line EM_N-4 are located in the first gate metal layer.

[0077] In some embodiments, the display panel further includes a first reset signal supply line SVint1 and a second reset signal supply line SVint2 located in the peripheral area. Optionally, the first reset signal line Vint1 and the second reset signal line Vint2 extend along a first direction DR1; the first reset signal supply line SVint1 and the second reset signal supply line SVint2 extend along a second direction DR2.

[0078] In some embodiments, the first reset signal supply line SVint1 and the second reset signal supply line SVint2 are located on a first signal line layer, which is located on the side of the second gate metal layer away from the first gate metal layer. The first reset signal supply line SVint1 is electrically connected to the first reset signal line Vint1 through a via, and the second reset signal supply line SVint2 is electrically connected to the second reset signal line Vint2 through a via.

[0079] In some embodiments, the display panel further includes one or more scanning circuits. In some embodiments, the one or more scanning circuits include a first scanning circuit Gate GOA, a second scanning circuit Scan GOA, and a third scanning circuit EMGOA. In some embodiments, the first scanning circuit Gate GOA is configured to provide a gate scan signal to the gate line Gate; the second scanning circuit Scan GOA is configured to provide a scan signal to a first scan signal line Scan_N; and the third scanning line EMGOA is configured to provide a light emission control signal to a first light emission control signal line EMG_N.

[0080] In some embodiments, the second scan signal line Scan_N-7 is configured to receive the output signal from the previous stage of the second scan circuit ScanGOA. The first stage can be configured to receive the output signal from the previous stage preceding the first stage (e.g., see...). Figure 13In some embodiments, the display panel further includes a first connection line CL1 that connects the second scan signal line Scan_N-7 to the front stage of the second scan circuit Scan GOA. Optionally, the first connection line CL1 and the second scan signal line Scan_N-7 are located on two different layers. In one example, the first connection line CL1 is located on the first signal line layer, and the second scan signal line Scan_N-7 is located on the first gate metal layer. Optionally, the first connection line CL1 extends along the second direction DR2, and the second scan signal line Scan_N-7 extends along the first direction DR1.

[0081] In some embodiments, the second light emission control signal line EM_N-4 is configured to receive an output signal from the front-end of the third scanning circuit EMGOA. In some embodiments, the display panel further includes a second connection line CL2 that connects the second light emission control signal line EM_N-4 to the front-end of the third scanning circuit EMGOA. Optionally, the second connection line CL2 and the second light emission control signal line EM_N-4 are located on two different layers. In one example, the second connection line CL2 is located on a first signal line layer, and the second light emission control signal line EM_N-4 is located on a first gate metal layer. Optionally, the second connection line CL2 extends along a second direction DR2, and the second light emission control signal line EM_N-4 extends along a first direction DR1. Optionally, the first connection line CL1 and the second connection line CL2 are located on the same layer.

[0082] In some embodiments, one or more scanning circuits may use dual-sided driving or single-sided driving. In one example, the first and third scanning circuits use dual-sided driving, and the second scanning circuit uses single-sided driving.

[0083] In some embodiments, the gate line, the first scan signal line Scan_N, the first light emission control signal line EM_N, and the second light emission control signal line EM_N-4 intersect with a plurality of connection lines CLLS between the display area AA and one or more scan circuits. In some embodiments, the display panel further includes a first intermediate line IML1 connecting the gate line and the first scan circuit Gate GOA, a second intermediate line IML2 connecting the first scan signal line Scan_N and the second scan circuit Scan GOA, a third intermediate line IML3 connecting the first light emission control signal line EM_N and the third scan circuit EM GOA, and a fourth intermediate line IML4 connecting the second light emission control signal line EM_N-4 and the second connection line CL2.

[0084] In some embodiments, the gate line (Gate) and the first intermediate line (IML1) are located on the same layer, for example, the second gate metal layer. In some embodiments, the first scan signal line (Scan_N) and the second intermediate line (IML2) are located on the same layer, for example, the first gate metal layer. In some embodiments, the first light emission control signal line (EM_N) and the third intermediate line (IML3) are located on the same layer, for example, the second gate metal layer. In some embodiments, the second light emission control signal line (EM_N-4) and the fourth intermediate line (IML4) are located on the same layer, for example, the first gate metal layer.

[0085] Figure 4 For along Figure 3 Cross-sectional view of line A-A'. (Refer to...) Figure 3 and Figure 4 In some embodiments, the display panel includes a substrate BS; a buffer layer BUF located on the substrate BS; a first gate metal layer Gate1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first gate metal layer Gate1 away from the substrate BS; a second gate metal layer Gate2 located on the side of the gate insulating layer GI away from the substrate BS; an interlayer dielectric layer ILD located on the side of the second gate metal layer Gate2 away from the substrate BS; a first signal line layer SD1 located on the side of the interlayer dielectric layer ILD away from the substrate BS; and a passivation layer PVX located on the side of the first signal line layer SD1 away from the substrate BS.

[0086] In some embodiments, the second scan signal line Scan_N-7, the first scan signal line Scan_N, and the second light emission control signal line EM_N-4 are located in the first gate metal layer. In some embodiments, the first reset voltage line Vint1, the gate line Gate, the first light emission control signal line EM_N, and the second reset voltage line Vint2 are located in the second gate metal layer. In some embodiments, the first reset signal supply line SVint1 and the second reset signal supply line SVint2 are located in the first signal line layer.

[0087] In some embodiments, the orthographic projection of a connection line in the plurality of connections in the first gate metal layer onto the substrate does not overlap with the orthographic projection of a connection line in the plurality of connections in the second gate metal layer onto the substrate. In an alternative embodiment, the orthographic projection of at least one connection line in the plurality of connections in the first gate metal layer onto the substrate at least partially overlaps with the orthographic projection of at least one connection line in the plurality of connections in the second gate metal layer onto the substrate.

[0088] In some embodiments, the interconnects in the plurality of interconnects in the first gate metal layer are equally spaced, and the interconnects in the plurality of interconnects in the second gate metal layer are equally spaced.

[0089] In some embodiments, the plurality of interconnects located on the first gate metal layer and the second gate metal layer are equally spaced. In alternative embodiments, at least two of the interconnects are spaced apart from each other by a different distance than the other interconnects are spaced apart from each other. In a particular example, the first scan signal line Scan_N is spaced apart from the first light emission control signal line EM_N by a first distance, and the other interconnects are spaced apart from each other by a second distance, wherein the first distance is greater than the second distance.

[0090] In some embodiments, the plurality of interconnects located on the first gate metal layer and the plurality of interconnects located on the second gate metal layer have the same linewidth. In an alternative embodiment, at least two of the plurality of interconnects have different linewidths.

[0091] Figure 5 This is a circuit diagram of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure. Each scanning unit may be a scanning unit of a first scanning circuit, a second scanning circuit, or a third scanning circuit. In one example, each scanning unit is a scanning unit of a first scanning circuit. (See reference...) Figure 5In some embodiments, each scanning unit includes a first control transistor GT1 to an eighth control transistor GT8, a first control capacitor GC1, and a second control capacitor GC2. In some embodiments, the gate of the first control transistor GT1 is electrically connected to a first clock signal terminal GCK1, the first electrode of the first control transistor GT1 is electrically connected to the input terminal GIN, and the second electrode of the first control transistor GT1 is electrically connected to a first node G1; the gate of the second control transistor GT2 is electrically connected to the first node G1, the first electrode of the second control transistor GT2 is electrically connected to the first clock signal terminal GCK1, and the second electrode of the second control transistor GT2 is electrically connected to a second node G2; the gate of the third control transistor GT3 is electrically connected to the first clock signal terminal GCK1, the first electrode of the third control transistor GT3 is electrically connected to a first power supply signal VGL, and the second electrode of the third control transistor GT3 is electrically connected to the second node G2; the gate of the fourth control transistor GT4 is electrically connected to the second node G2, the first electrode of the fourth control transistor GT4 is electrically connected to a second power supply signal VGH, and the second electrode of the fourth control transistor GT4 is electrically connected to the output terminal GOUT; the gate of the fifth control transistor GT5 is electrically connected to the third node G3, and the first electrode of the fifth control transistor GT5 is electrically connected to the second clock signal VGH. Signal terminal GCK2; the second electrode of the fifth control transistor GT5 is electrically connected to the output terminal GOUT; the gate of the sixth control transistor GT6 is electrically connected to the second node G2, the first electrode of the sixth control transistor GT6 is electrically connected to the second power supply signal VGH, and the second electrode of the sixth control transistor GT6 is electrically connected to the first electrode of the seventh control transistor GT7; the gate of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCK2, and the second electrode of the seventh control transistor GT7 is electrically connected to the first node G1; the gate of the eighth control transistor GT8 is electrically connected to the first power supply signal VGL, the first electrode of the eighth control transistor GT8 is electrically connected to the first node G1, and the second electrode of the eighth control transistor GT8 is electrically connected to the third node G3; the first plate GC11 of the first control capacitor GC1 is electrically connected to the second node G2, and the second plate GC12 of the first control capacitor GC1 is electrically connected to the second power supply signal VGH; the first plate GC21 of the second control capacitor GC2 is electrically connected to the third node G3, and the second plate GC22 of the second control capacitor GC2 is electrically connected to the output terminal GOUT. In one example, the first control transistor GT1 to the eighth control transistor GT8 can be P-type transistors or N-type transistors. In another example, the second power signal VGH provides a continuous high-level signal, while the first power signal VGL provides a continuous low-level signal.

[0092] Figure 6A This is a schematic diagram illustrating the structure of a portion of a corresponding scanning unit of a scanning circuit according to some embodiments of the present disclosure. Figure 6B It is shown Figure 6A A schematic diagram of the structure of the semiconductor material layer in a portion of the corresponding scanning unit shown. Figure 6C It is shown Figure 6A A schematic diagram of the structure of the first gate metal layer in a portion of the corresponding scanning unit shown. Figure 6D It is shown Figure 6A A schematic diagram of the structure of the second gate metal layer in a portion of the corresponding scanning unit shown. Figure 6E It is shown Figure 6A A schematic diagram of the structure of the interlayer dielectric layer in a portion of the corresponding scanning unit shown. Figure 6F It is shown Figure 6A A schematic diagram of the structure of the first signal line layer in a portion of the corresponding scanning unit shown. (Reference) Figures 6A to 6F In some embodiments, the semiconductor material layer includes the active layer ACT5 of the fifth control transistor GT5; the first gate metal layer includes the gate G5 of the fifth control transistor GT5 and the first electrode GC21 of the second control capacitor GC2; the second gate metal layer includes the second electrode GC22 of the second control capacitor GC2; and the first signal line layer includes the first electrode and the second electrode of the fifth control transistor GT5 and the output terminal GOUT. Optionally, the output terminal GOUT is connected to the second electrode GC22 of the second control capacitor GC2 through one or more vias extending through the interlayer dielectric layer. Figure 3 The grid lines described in the text (in) Figure 3 The symbol (represented as "Gate") is connected to the output terminal GOUT.

[0093] In some embodiments, the gate line is located in the second gate metal layer. For example... Figure 3 As shown, the inventors of this disclosure have discovered that by placing the gate line on the second gate metal layer, jumper adjustments are not required when the gate line intersects with a connection line located on the first signal line layer, thereby reducing the need for vias. The spacing between the connection line and the reset signal line can then be horizontally compressed, resulting in space optimization. This wiring scheme can be applied to situations where there is no gate metal layer pattern between the display area and the scanning circuitry, such as when there is no multiplexer unit between the display area and the scanning circuitry, or when the fan-out wiring is located outside the scanning circuitry.

[0094] In an alternative embodiment, the gate line is located on the first signal line layer, for example, with... Figures 6A to 6F The output terminal GOUT shown is located on the same layer.

[0095] Figure 7 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 7In some embodiments, multiple signal lines configured to provide signals to a row of pixel driving circuits are located on the same layer in the peripheral area of ​​the display panel. In some embodiments, the multiple signal lines located in the peripheral area include a first reset voltage line Vint1, a second scan signal line Scan_N-7, a gate line Gate, a first scan signal line Scan_N, a first light emission control signal line EM_N, a second light emission control signal line EM_N-4, and a second reset voltage line Vint2. In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located on the same layer in the peripheral area of ​​the display panel.

[0096] In some embodiments, the same layer is the first signal line layer. See also Figure 7 In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located in the first signal line layer.

[0097] In some embodiments, the display panel further includes a first reset signal supply line SVint1 and a second reset signal supply line SVint2 located in the peripheral area. Optionally, the first reset signal line Vint1 and the second reset signal line Vint2 extend along a first direction DR1; the first reset signal supply line SVint1 and the second reset signal supply line SVint2 extend along a second direction DR2.

[0098] In some embodiments, the first reset signal supply line SVint1 and the second reset signal supply line SVint2 are located in a second signal line layer, which is located on the side of the first signal line layer away from the substrate. The first reset signal supply line SVint1 is electrically connected to the first reset signal line Vint1 via a via, and the second reset signal supply line SVint2 is electrically connected to the second reset signal line Vint2 via a via.

[0099] In some embodiments, the display panel further includes one or more scanning circuits. In some embodiments, the one or more scanning circuits include a first scanning circuit Gate GOA, a second scanning circuit Scan GOA, and a third scanning circuit EMGOA. In some embodiments, the first scanning circuit Gate GOA is configured to provide a gate scan signal to the gate line Gate; the second scanning circuit Scan GOA is configured to provide a scan signal to a first scan signal line Scan_N; and the third scanning line EMGOA is configured to provide a light emission control signal to a first light emission control signal line EMG_N.

[0100] In some embodiments, the second scan signal line Scan_N-7 is configured to receive an output signal from the preceding stage of the second scan circuit ScanGOA. In some embodiments, the display panel further includes a first connection line CL1 that connects the second scan signal line Scan_N-7 to the preceding stage of the second scan circuit ScanGOA. Optionally, the first connection line CL1 and the second scan signal line Scan_N-7 are located on two different layers. In one example, the first connection line CL1 is located on a first gate metal layer, and the second scan signal line Scan_N-7 is located on a first signal line layer. Optionally, the first connection line CL1 extends along a second direction DR2, and the second scan signal line Scan_N-7 extends along a first direction DR1.

[0101] In some embodiments, the second light emission control signal line EM_N-4 is configured to receive an output signal from the front-end of the third scanning circuit EMGOA. In some embodiments, the display panel further includes a second connection line CL2 that connects the second light emission control signal line EM_N-4 to the front-end of the third scanning circuit EMGOA. Optionally, the second connection line CL2 and the second light emission control signal line EM_N-4 are located on two different layers. In one example, the second connection line CL2 is located on the first gate metal layer, and the second light emission control signal line EM_N-4 is located on the first signal line layer. Optionally, the second connection line CL2 extends along the second direction DR2, and the second light emission control signal line EM_N-4 extends along the first direction DR1.

[0102] The inventors of this disclosure discovered that, Figure 7 The layout depicted applies to situations where a gate metal layer pattern exists between the display area and one or more scanning circuits. Therefore, the connection lines between the display area and one or more scanning circuits can only use the first signal line layer, while the connection lines between adjacent scanning units in different stages can only use the gate metal layer (e.g., ...). Figure 7 (The first gate metal layer shown).

[0103] The inventors of this disclosure have discovered that a first gate metal layer lies beneath a second gate metal layer, and an inorganic insulating layer separates the two. Similarly, an inorganic layer separates the second gate metal layer from the first signal line layer. Therefore, the first gate metal layer offers advantages over the second gate metal layer in terms of interlayer spacing and insulation thickness. The use of the first gate metal layer reduces the overlap capacitance with the first signal line layer, thereby ensuring the integrity of the output signal waveform.

[0104] In some embodiments, the gate line, the first scan signal line Scan_N, the first light emission control signal line EM_N, and the second light emission control signal line EM_N-4 intersect with a plurality of connection lines CLLS between the display area AA and one or more scan circuits. In some embodiments, the display panel further includes a first intermediate line IML1 connecting the gate line and the first scan circuit Gate GOA, a second intermediate line IML2 connecting the first scan signal line Scan_N and the second scan circuit Scan GOA, a third intermediate line IML3 connecting the first light emission control signal line EM_N and the third scan circuit EM GOA, and a fourth intermediate line IML4 connecting the second light emission control signal line EM_N-4 and the second connection line CL2.

[0105] In some embodiments, the gate line (Gate) and the first intermediate line (IML1) are located on the same layer, for example, the first signal line layer. In some embodiments, the first scan signal line (Scan_N) and the second intermediate line (IML2) are located on the same layer, for example, the first signal line layer. In some embodiments, the first emission control signal line (EM_N) and the third intermediate line (IML3) are located on the same layer, for example, the first signal line layer. In some embodiments, the second emission control signal line (EM_N-4) and the fourth intermediate line (IML4) are located on the same layer, for example, the first signal line layer.

[0106] In an alternative embodiment, the gate line is located on the first signal line layer, and the first intermediate line IML1 is located on the second signal line layer; the first scan signal line Scan_N is located on the first signal line layer, and the second intermediate line IML2 is located on the second signal line layer; the first light emission control signal line EM_N is located on the first signal line layer, and the third intermediate line IML3 is located on the second signal line layer; the second light emission control signal line EM_N-4 is located on the first signal line layer, and the fourth intermediate line IML4 is located on the second signal line layer.

[0107] Figure 8 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 8In some embodiments, multiple signal lines configured to provide signals to a row of pixel driving circuits are located on the same layer in the peripheral area of ​​the display panel. In some embodiments, the multiple signal lines located in the peripheral area include a first reset voltage line Vint1, a second scan signal line Scan_N-7, a gate line Gate, a first scan signal line Scan_N, a first light emission control signal line EM_N, a second light emission control signal line EM_N-4, and a second reset voltage line Vint2. In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located on the same layer in the peripheral area of ​​the display panel.

[0108] In some embodiments, the same layer is the first signal line layer. See also Figure 8 In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located in the first signal line layer.

[0109] In some embodiments, the display panel further includes a first reset signal supply line SVint1 and a second reset signal supply line SVint2 located in the peripheral area. Optionally, the first reset signal line Vint1 and the second reset signal line Vint2 extend along a first direction DR1; the first reset signal supply line SVint1 and the second reset signal supply line SVint2 extend along a second direction DR2.

[0110] In some embodiments, the first reset signal supply line SVint1 and the second reset signal supply line SVint2 are located in a second signal line layer, which is located on the side of the first signal line layer away from the substrate. The first reset signal supply line SVint1 is electrically connected to the first reset signal line Vint1 via a via, and the second reset signal supply line SVint2 is electrically connected to the second reset signal line Vint2 via a via.

[0111] In some embodiments, the display panel further includes one or more scanning circuits. In some embodiments, the one or more scanning circuits include a first scanning circuit Gate GOA, a second scanning circuit Scan GOA, and a third scanning circuit EMGOA. In some embodiments, the first scanning circuit Gate GOA is configured to provide a gate scan signal to the gate line Gate; the second scanning circuit Scan GOA is configured to provide a scan signal to a first scan signal line Scan_N; and the third scanning line EMGOA is configured to provide a light emission control signal to a first light emission control signal line EMG_N.

[0112] In some embodiments, the second scan signal line Scan_N-7 is configured to receive an output signal from the front stage of the second scan circuit ScanGOA. In some embodiments, the display panel further includes a first connection line CL1 that connects the second scan signal line Scan_N-7 to the front stage of the second scan circuit ScanGOA. Optionally, the first connection line CL1 and the second scan signal line Scan_N-7 are located on the same layer. In one example, the first connection line CL1 and the second scan signal line Scan_N-7 are located on a first signal line layer. Optionally, the first connection line CL1 extends along a second direction DR2, and the second scan signal line Scan_N-7 extends along a first direction DR1.

[0113] In some embodiments, the second light emission control signal line EM_N-4 is configured to receive an output signal from the front-end of the third scanning circuit EMGOA. In some embodiments, the display panel further includes a second connection line CL2 that connects the second light emission control signal line EM_N-4 to the front-end of the third scanning circuit EMGOA. Optionally, the second connection line CL2 and the second light emission control signal line EM_N-4 are located on the same layer. In one example, the second connection line CL2 and the second light emission control signal line EM_N-4 are located on a first signal line layer. Optionally, the second connection line CL2 extends along a second direction DR2, and the second light emission control signal line EM_N-4 extends along a first direction DR1.

[0114] In some embodiments, the gate line, the first scan signal line Scan_N, the first light emission control signal line EM_N, and the second light emission control signal line EM_N-4 intersect with a plurality of connection lines CLLS between the display area AA and one or more scan circuits. In some embodiments, the display panel further includes a first intermediate line IML1 connecting the gate line and the first scan circuit Gate GOA, a second intermediate line IML2 connecting the first scan signal line Scan_N and the second scan circuit Scan GOA, a third intermediate line IML3 connecting the first light emission control signal line EM_N and the third scan circuit EM GOA, and a fourth intermediate line IML4 connecting the second light emission control signal line EM_N-4 and the second connection line CL2.

[0115] In some embodiments, the first intermediate line IML1 and the gate line are located on different layers. In one example, the gate line is located on a first signal line layer; and the first intermediate line IML1 is located on a second gate metal layer, with the first signal line layer located on the side of the second gate metal layer away from the substrate. Optionally, the second interconnect CL2 extends along a second direction DR2, the first intermediate line IML1 extends along a first direction DR1, and the gate line extends along the first direction DR1.

[0116] In some embodiments, the first intermediate line IML1 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0117] In some embodiments, the second intermediate line IML2 and the first scan signal line Scan_N are located on different layers. In one example, the first scan signal line Scan_N is located on the first signal line layer; and the second intermediate line IML2 is located on the first gate metal layer, with the first signal line layer located on the side of the first gate metal layer away from the substrate. Optionally, the second intermediate line IML2 extends along the first direction DR1, and the first scan signal line Scan_N extends along the first direction DR1.

[0118] In some embodiments, the second intermediate line IML2 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0119] In some embodiments, the third intermediate line IML3 and the first light-emitting control signal line EM_N are located on different layers. In one example, the first light-emitting control signal line EM_N is located on the first signal line layer; and the third intermediate line IML3 is located on the second gate metal layer, with the first signal line layer located on the side of the second gate metal layer away from the substrate. Optionally, the third intermediate line IML3 extends along the first direction DR1, and the first light-emitting control signal line EM_N extends along the first direction DR1.

[0120] In some embodiments, the third intermediate line IML3 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0121] In some embodiments, the fourth intermediate line IML4 is located on a different layer from the second connection line CL2 and the second light emission control signal line EM_N-4. In one example, the second connection line CL2 and the second light emission control signal line EM_N-4 are located on a first signal line layer; and the fourth intermediate line IML4 is located on a second signal line layer, which is located on the side of the first signal line layer away from the substrate. Optionally, the second connection line CL2 extends along a second direction DR2, the fourth intermediate line IML4 extends along a first direction DR1, and the second light emission control signal line EM_N-4 extends along a first direction DR1.

[0122] In some embodiments, the fourth intermediate line IML4 intersects with one or more connection lines CLS located between the second connection line CL2 and one or more scan circuits. Optionally, the one or more connection lines CLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the one or more connection lines CLS extend along the second direction DR2.

[0123] In an alternative embodiment, the fourth intermediate line IML4 is located in the first gate metal layer.

[0124] In an alternative embodiment, the fourth intermediate line IML4 is located in the second gate metal layer.

[0125] In an alternative embodiment, the gate line is located on the first signal line layer, and the first intermediate line IML1 is located on the second signal line layer; the first scan signal line Scan_N is located on the first signal line layer, and the second intermediate line IML2 is located on the second signal line layer; the first light emission control signal line EM_N is located on the first signal line layer, and the third intermediate line IML3 is located on the second signal line layer; the second light emission control signal line EM_N-4 is located on the first signal line layer, and the fourth intermediate line IML4 is located on the second signal line layer.

[0126] Figure 9 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 9 In some embodiments, multiple signal lines configured to provide signals to a row of pixel driving circuits are located on the same layer in the peripheral area of ​​the display panel. In some embodiments, the multiple signal lines located in the peripheral area include a first reset voltage line Vint1, a second scan signal line Scan_N-7, a gate line Gate, a first scan signal line Scan_N, a first light emission control signal line EM_N, a second light emission control signal line EM_N-4, and a second reset voltage line Vint2. In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located on the same layer in the peripheral area of ​​the display panel.

[0127] In some embodiments, the same layer is a second signal line layer. See also Figure 9 In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located in the second signal line layer.

[0128] In some embodiments, the display panel further includes a first reset signal supply line SVint1 and a second reset signal supply line SVint2 located in the peripheral area. Optionally, the first reset signal line Vint1 and the second reset signal line Vint2 extend along a first direction DR1; the first reset signal supply line SVint1 and the second reset signal supply line SVint2 extend along a second direction DR2.

[0129] In some embodiments, the first reset signal supply line SVint1 and the second reset signal supply line SVint2 are located in a first signal line layer, which is located on the side of the second signal line layer closest to the substrate. The first reset signal supply line SVint1 is electrically connected to the first reset signal line Vint1 via a via, and the second reset signal supply line SVint2 is electrically connected to the second reset signal line Vint2 via a via.

[0130] In some embodiments, the display panel further includes one or more scanning circuits. In some embodiments, the one or more scanning circuits include a first scanning circuit Gate GOA, a second scanning circuit Scan GOA, and a third scanning circuit EMGOA. In some embodiments, the first scanning circuit Gate GOA is configured to provide a gate scan signal to the gate line Gate; the second scanning circuit Scan GOA is configured to provide a scan signal to a first scan signal line Scan_N; and the third scanning line EMGOA is configured to provide a light emission control signal to a first light emission control signal line EMG_N.

[0131] In some embodiments, the second scan signal line Scan_N-7 is configured to receive an output signal from the preceding stage of the second scan circuit ScanGOA. In some embodiments, the display panel further includes a first connection line CL1 that connects the second scan signal line Scan_N-7 to the preceding stage of the second scan circuit ScanGOA. Optionally, the first connection line CL1 and the second scan signal line Scan_N-7 are located on two different layers. In one example, the first connection line CL1 is located on a first gate metal layer, and the second scan signal line Scan_N-7 is located on a second signal line layer. Optionally, the first connection line CL1 extends along a second direction DR2, and the second scan signal line Scan_N-7 extends along a first direction DR1.

[0132] In some embodiments, the second light emission control signal line EM_N-4 is configured to receive an output signal from the front-end of the third scanning circuit EMGOA. In some embodiments, the display panel further includes a second connection line CL2 that connects the second light emission control signal line EM_N-4 to the front-end of the third scanning circuit EMGOA. Optionally, the second connection line CL2 and the second light emission control signal line EM_N-4 are located on two different layers. In one example, the second connection line CL2 is located on the first gate metal layer, and the second light emission control signal line EM_N-4 is located on the second signal line layer. Optionally, the second connection line CL2 extends along the second direction DR2, and the second light emission control signal line EM_N-4 extends along the first direction DR1.

[0133] In some embodiments, the gate line, the first scan signal line Scan_N, the first light emission control signal line EM_N, and the second light emission control signal line EM_N-4 intersect with a plurality of connection lines CLLS between the display area AA and one or more scan circuits. In some embodiments, the display panel further includes a first intermediate line IML1 connecting the gate line and the first scan circuit Gate GOA, a second intermediate line IML2 connecting the first scan signal line Scan_N and the second scan circuit Scan GOA, a third intermediate line IML3 connecting the first light emission control signal line EM_N and the third scan circuit EM GOA, and a fourth intermediate line IML4 connecting the second light emission control signal line EM_N-4 and the second connection line CL2.

[0134] In some embodiments, the first intermediate line IML1 and the gate line are located on different layers. In one example, the gate line is located on the second signal line layer; and the first intermediate line IML1 is located on the first signal line layer, with the second signal line layer located on the side of the first signal line layer away from the substrate. Optionally, the second interconnect line CL2 extends along the second direction DR2, the first intermediate line IML1 extends along the first direction DR1, and the gate line extends along the first direction DR1.

[0135] In some embodiments, the first intermediate line IML1 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scan circuits. Optionally, the plurality of connection lines CLLS are located in the first gate metal layer (e.g., in the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along the second direction DR2.

[0136] In some embodiments, the second intermediate line IML2 and the first scan signal line Scan_N are located on different layers. In one example, the first scan signal line Scan_N is located on the second signal line layer; and the second intermediate line IML2 is located on the first signal line layer, with the second signal line layer located on the side of the first signal line layer away from the substrate. Optionally, the second intermediate line IML2 extends along the first direction DR1, and the first scan signal line Scan_N extends along the first direction DR1.

[0137] In some embodiments, the second intermediate line IML2 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scan circuits. Optionally, the plurality of connection lines CLLS are located in the first gate metal layer (e.g., in the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along the second direction DR2.

[0138] In some embodiments, the third intermediate line IML3 and the first light-emitting control signal line EM_N are located on different layers. In one example, the first light-emitting control signal line EM_N is located on the second signal line layer; and the third intermediate line IML3 is located on the first signal line layer, with the second signal line layer located on the side of the first signal line layer away from the substrate. Optionally, the third intermediate line IML3 extends along the first direction DR1, and the first light-emitting control signal line EM_N extends along the first direction DR1.

[0139] In some embodiments, the third intermediate line IML3 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scan circuits. Optionally, the plurality of connection lines CLLS are located in the first gate metal layer (e.g., in the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along the second direction DR2.

[0140] In some embodiments, the fourth intermediate line IML4 is located on a different layer from the second connection line CL2 and the second light emission control signal line EM_N-4. In one example, the second connection line CL2 is located on a first gate metal layer, the fourth intermediate line IML4 is located on a first signal line layer, the first signal line layer is located on the side of the first gate metal layer away from the substrate, and the second light emission control signal line EM_N-4 is located on a second signal line layer, the second signal line layer is located on the side of the first signal line layer away from the substrate. Optionally, the second connection line CL2 extends along a second direction DR2, the fourth intermediate line IML4 extends along a first direction DR1, and the second light emission control signal line EM_N-4 extends along a first direction DR1.

[0141] In some embodiments, the fourth intermediate line IML4 intersects with one or more connection lines CLS located between the second connection line CL2 and one or more scan circuits. Optionally, the one or more connection lines CLS are located in the first gate metal layer (e.g., in the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the one or more connection lines CLS extend along the second direction DR2.

[0142] The inventors of this disclosure discovered that, Figure 9 The layout shown is applicable when the gate metal layer pattern and the first signal line layer pattern coexist between the display area AA and one or more scan circuits. Examples of such products include designs with multiplexing units located at the corners or fan-outs with gate metal layer patterns, and cases where the fan-out includes the first signal line layer.

[0143] Figure 10 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 10In some embodiments, multiple signal lines configured to provide signals to a row of pixel driving circuits are located on the same layer in the peripheral area of ​​the display panel. In some embodiments, the multiple signal lines located in the peripheral area include a first reset voltage line Vint1, a second scan signal line Scan_N-7, a gate line Gate, a first scan signal line Scan_N, a first light emission control signal line EM_N, a second light emission control signal line EM_N-4, and a second reset voltage line Vint2. In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located on the same layer in the peripheral area of ​​the display panel.

[0144] In some embodiments, the same layer is a second signal line layer. See also Figure 10 In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located in the second signal line layer.

[0145] In some embodiments, the display panel further includes a first reset signal supply line SVint1 and a second reset signal supply line SVint2 located in the peripheral area. Optionally, the first reset signal line Vint1 and the second reset signal line Vint2 extend along a first direction DR1; the first reset signal supply line SVint1 and the second reset signal supply line SVint2 extend along a second direction DR2.

[0146] In some embodiments, the first reset signal supply line SVint1 and the second reset signal supply line SVint2 are located in a first signal line layer, which is located on the side of the second signal line layer closest to the substrate. The first reset signal supply line SVint1 is electrically connected to the first reset signal line Vint1 via a via, and the second reset signal supply line SVint2 is electrically connected to the second reset signal line Vint2 via a via.

[0147] In some embodiments, the display panel further includes one or more scanning circuits. In some embodiments, the one or more scanning circuits include a first scanning circuit Gate GOA, a second scanning circuit Scan GOA, and a third scanning circuit EMGOA. In some embodiments, the first scanning circuit Gate GOA is configured to provide a gate scan signal to the gate line Gate; the second scanning circuit Scan GOA is configured to provide a scan signal to a first scan signal line Scan_N; and the third scanning line EMGOA is configured to provide a light emission control signal to a first light emission control signal line EMG_N.

[0148] In some embodiments, the second scan signal line Scan_N-7 is configured to receive an output signal from the front stage of the second scan circuit ScanGOA. In some embodiments, the display panel further includes a first connection line CL1 that connects the second scan signal line Scan_N-7 to the front stage of the second scan circuit ScanGOA. Optionally, the first connection line CL1 and the second scan signal line Scan_N-7 are located on two different layers. In one example, the first connection line CL1 is located on a first signal line layer, and the second scan signal line Scan_N-7 is located on a second signal line layer. Optionally, the first connection line CL1 extends along a second direction DR2, and the second scan signal line Scan_N-7 extends along a first direction DR1.

[0149] In some embodiments, the second light emission control signal line EM_N-4 is configured to receive an output signal from the front-end of the third scanning circuit EMGOA. In some embodiments, the display panel further includes a second connection line CL2 that connects the second light emission control signal line EM_N-4 to the front-end of the third scanning circuit EMGOA. Optionally, the second connection line CL2 and the second light emission control signal line EM_N-4 are located on two different layers. In one example, the second connection line CL2 is located on a first signal line layer, and the second light emission control signal line EM_N-4 is located on a second signal line layer. Optionally, the second connection line CL2 extends along a second direction DR2, and the second light emission control signal line EM_N-4 extends along a first direction DR1.

[0150] In some embodiments, the gate line, the first scan signal line Scan_N, the first light emission control signal line EM_N, and the second light emission control signal line EM_N-4 intersect with a plurality of connection lines CLLS between the display area AA and one or more scan circuits. In some embodiments, the display panel further includes a first intermediate line IML1 connecting the gate line and the first scan circuit Gate GOA, a second intermediate line IML2 connecting the first scan signal line Scan_N and the second scan circuit Scan GOA, a third intermediate line IML3 connecting the first light emission control signal line EM_N and the third scan circuit EM GOA, and a fourth intermediate line IML4 connecting the second light emission control signal line EM_N-4 and the second connection line CL2.

[0151] In some embodiments, the first intermediate line IML1 and the gate line are located on different layers. In one example, the gate line is located on the second signal line layer; and the first intermediate line IML1 is located on the second gate metal layer, with the second signal line layer located on the side of the second gate metal layer away from the substrate. Optionally, the second connection line CL2 extends along the second direction DR2, the first intermediate line IML1 extends along the first direction DR1, and the gate line extends along the first direction DR1.

[0152] In some embodiments, the first intermediate line IML1 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0153] In some embodiments, the second intermediate line IML2 and the first scan signal line Scan_N are located on different layers. In one example, the first scan signal line Scan_N is located on the second signal line layer; and the second intermediate line IML2 is located on the first gate metal layer, with the second signal line layer located on the side of the first gate metal layer away from the substrate. Optionally, the second intermediate line IML2 extends along the first direction DR1, and the first scan signal line Scan_N extends along the first direction DR1.

[0154] In some embodiments, the second intermediate line IML2 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0155] In some embodiments, the third intermediate line IML3 and the first light-emitting control signal line EM_N are located on different layers. In one example, the first light-emitting control signal line EM_N is located on the second signal line layer; and the third intermediate line IML3 is located on the second gate metal layer, with the second signal line layer located on the side of the second gate metal layer away from the substrate. Optionally, the third intermediate line IML3 extends along the first direction DR1, and the first light-emitting control signal line EM_N extends along the first direction DR1.

[0156] In some embodiments, the third intermediate line IML3 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0157] In some embodiments, the fourth intermediate line IML4 is located on a different layer from the second connection line CL2, but on the same layer as the second light-emitting control signal line EM_N-4. In one example, the second connection line CL2 is located on a first signal line layer, the fourth intermediate line IML4 is located on a second signal line layer, the second signal line layer is located on the side of the first gate metal layer away from the substrate, and the second light-emitting control signal line EM_N-4 is located on the second signal line layer, the second signal line layer is located on the side of the first signal line layer away from the substrate. Optionally, the second connection line CL2 extends along a second direction DR2, the fourth intermediate line IML4 extends along a first direction DR1, and the second light-emitting control signal line EM_N-4 extends along a first direction DR1.

[0158] In some embodiments, the fourth intermediate line IML4 intersects with one or more connection lines CLS located between the second connection line CL2 and one or more scan circuits. Optionally, the one or more connection lines CLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the one or more connection lines CLS extend along the second direction DR2.

[0159] In some embodiments, the multiple connection lines between the display area and one or more scanning circuits include a plurality of connection lines that transmit signals from one or more in the front stage to one or more in the next stage. Figure 11A The diagram illustrates a plurality of connection lines in a display panel according to some embodiments of the present disclosure, among a plurality of connection lines between the display area and one or more scanning circuits. Figure 11A The arrows in the diagram indicate that multiple connection lines are configured to transmit signals from one or more in the preamplifier stage to one or more in the emulator stage.

[0160] In some embodiments, the plurality of connection lines between the display area and one or more scanning circuits include a plurality of connection lines that transmit signals from one or more downstream circuits to one or more upstream circuits. Figure 11B The diagram illustrates a plurality of connection lines in a display panel according to some embodiments of the present disclosure, among a plurality of connection lines between the display area and one or more scanning circuits. Figure 11B The arrows in the diagram indicate that multiple connection lines are configured to transmit signals from one or more in the subsequent stage to one or more in the preceding stage.

[0161] In some embodiments, the third scanning circuit is configured to provide a second light emission control signal from a third light emission control signal line. Optionally, the third light emission control signal line EM_N+4 is connected to the second stage of the third scanning circuit, and the first light emission control signal line EM_N is connected to the first stage of the third scanning circuit, with the first stage preceding the third stage by four stages.

[0162] Figure 12 The diagram illustrates the signal line layout of a row of pixel driving circuitry in a display panel according to some embodiments of the present disclosure. Figure 12 The display panel shown is Figure 10 The difference in the display panel shown is that the third scanning circuit is configured to provide a signal from the third light emission control signal line EM_N+4 to the gate of the second light emission control transistor in the pixel driving circuit of the corresponding row.

[0163] Reference Figure 12 In some embodiments, multiple signal lines configured to provide signals to a row of pixel driving circuits are located on the same layer in the peripheral area of ​​the display panel. In some embodiments, the multiple signal lines located in the peripheral area include a first reset voltage line Vint1, a second scan signal line Scan_N-7, a gate line Gate, a first scan signal line Scan_N, a first light emission control signal line EM_N, a third light emission control signal line EM_N+4, and a second reset voltage line Vint2. In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the third light emission control signal line EM_N+4, and the second reset voltage line Vint2 are located on the same layer in the peripheral area of ​​the display panel.

[0164] In some embodiments, the same layer is a second signal line layer. See also Figure 12 In some embodiments, the first reset voltage line Vint1, the second scan signal line Scan_N-7, the gate line Gate, the first scan signal line Scan_N, the first light emission control signal line EM_N, the second light emission control signal line EM_N-4, and the second reset voltage line Vint2 are located in the second signal line layer.

[0165] In some embodiments, the display panel further includes a first reset signal supply line SVint1 and a second reset signal supply line SVint2 located in the peripheral area. Optionally, the first reset signal line Vint1 and the second reset signal line Vint2 extend along a first direction DR1; the first reset signal supply line SVint1 and the second reset signal supply line SVint2 extend along a second direction DR2.

[0166] In some embodiments, the first reset signal supply line SVint1 and the second reset signal supply line SVint2 are located in a first signal line layer, which is located on the side of the second signal line layer closest to the substrate. The first reset signal supply line SVint1 is electrically connected to the first reset signal line Vint1 via a via, and the second reset signal supply line SVint2 is electrically connected to the second reset signal line Vint2 via a via.

[0167] In some embodiments, the display panel further includes one or more scanning circuits. In some embodiments, the one or more scanning circuits include a first scanning circuit Gate GOA, a second scanning circuit Scan GOA, and a third scanning circuit EMGOA. In some embodiments, the first scanning circuit Gate GOA is configured to provide a gate scan signal to the gate line Gate; the second scanning circuit Scan GOA is configured to provide a scan signal to a first scan signal line Scan_N; and the third scanning line EMGOA is configured to provide a light emission control signal to a first light emission control signal line EMG_N.

[0168] In some embodiments, the second scan signal line Scan_N-7 is configured to receive an output signal from the front stage of the second scan circuit ScanGOA. In some embodiments, the display panel further includes a first connection line CL1 that connects the second scan signal line Scan_N-7 to the front stage of the second scan circuit ScanGOA. Optionally, the first connection line CL1 and the second scan signal line Scan_N-7 are located on two different layers. In one example, the first connection line CL1 is located on a first signal line layer, and the second scan signal line Scan_N-7 is located on a second signal line layer. Optionally, the first connection line CL1 extends along a second direction DR2, and the second scan signal line Scan_N-7 extends along a first direction DR1.

[0169] In some embodiments, the third light emission control signal line EM_N+4 is configured to receive an output signal from a subsequent stage of the third scanning circuit EMGOA. In some embodiments, the display panel also includes a second connection line CL2 that connects the third light emission control signal line EM_N+4 to a subsequent stage of the third scanning circuit EMGOA. Optionally, the second connection line CL2 and the third light emission control signal line EM_N+4 are located on two different layers. In one example, the second connection line CL2 is located on a first signal line layer, and the third light emission control signal line EM_N+4 is located on a second signal line layer. Optionally, the second connection line CL2 extends along a second direction DR2, and the third light emission control signal line EM_N+4 extends along a first direction DR1.

[0170] In some embodiments, the gate line, the first scan signal line Scan_N, the first light emission control signal line EM_N, and the third light emission control signal line EM_N+4 intersect with a plurality of connection lines CLLS between the display area AA and one or more scan circuits. In some embodiments, the display panel further includes a first intermediate line IML1 connecting the gate line and the first scan circuit Gate GOA, a second intermediate line IML2 connecting the first scan signal line Scan_N and the second scan circuit Scan GOA, a third intermediate line IML3 connecting the first light emission control signal line EM_N and the third scan circuit EM GOA, and a fourth intermediate line IML4 connecting the third light emission control signal line EM_N+4 and the second connection line CL2.

[0171] In some embodiments, the first intermediate line IML1 and the gate line are located on different layers. In one example, the gate line is located on the second signal line layer; and the first intermediate line IML1 is located on the second gate metal layer, with the second signal line layer located on the side of the second gate metal layer away from the substrate. Optionally, the second connection line CL2 extends along the second direction DR2, the first intermediate line IML1 extends along the first direction DR1, and the gate line extends along the first direction DR1.

[0172] In some embodiments, the first intermediate line IML1 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0173] In some embodiments, the second intermediate line IML2 and the first scan signal line Scan_N are located on different layers. In one example, the first scan signal line Scan_N is located on the second signal line layer; and the second intermediate line IML2 is located on the first gate metal layer, with the second signal line layer located on the side of the first gate metal layer away from the substrate. Optionally, the second intermediate line IML2 extends along the first direction DR1, and the first scan signal line Scan_N extends along the first direction DR1.

[0174] In some embodiments, the second intermediate line IML2 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0175] In some embodiments, the third intermediate line IML3 and the first light-emitting control signal line EM_N are located on different layers. In one example, the first light-emitting control signal line EM_N is located on the second signal line layer; and the third intermediate line IML3 is located on the second gate metal layer, with the second signal line layer located on the side of the second gate metal layer away from the substrate. Optionally, the third intermediate line IML3 extends along the first direction DR1, and the first light-emitting control signal line EM_N extends along the first direction DR1.

[0176] In some embodiments, the third intermediate line IML3 intersects with a plurality of connection lines CLLS located between the display area AA and one or more scanning circuits. Optionally, the plurality of connection lines CLLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the plurality of connection lines CLLS extend along a second direction DR2.

[0177] In some embodiments, the fourth intermediate line IML4 is located on a different layer from the second connection line CL2 and on the same layer as the third light-emitting control signal line EM_N+4. In one example, the second connection line CL2 is located on a first signal line layer, the fourth intermediate line IML4 is located on a second signal line layer, the second signal line layer is located on the side of the first gate metal layer away from the substrate, and the third light-emitting control signal line EM_N+4 is located on the second signal line layer, the second signal line layer is located on the side of the first signal line layer away from the substrate. Optionally, the second connection line CL2 extends along a second direction DR2, the fourth intermediate line IML4 extends along a first direction DR1, and the third light-emitting control signal line EM_N+4 extends along a first direction DR1.

[0178] In some embodiments, the fourth intermediate line IML4 intersects with one or more connection lines CLS located between the second connection line CL2 and one or more scan circuits. Optionally, the one or more connection lines CLS are located on a first signal line layer (e.g., on the same layer as the first connection line CL1 and the second connection line CL2). Optionally, the one or more connection lines CLS extend along the second direction DR2.

[0179] The inventors of this disclosure have discovered that having a third light-emitting control signal line EM_N+4 for providing a second light-emitting control signal to the gate of a second light-emitting control transistor in a pixel driving circuit minimizes the impact on the overall layout. The layout of the signal lines described in this disclosure is fully compatible with the gate of the second light-emitting control transistor in the third scanning circuit that receives the second light-emitting control signal from the subsequent scanning unit.

[0180] Figure 13 This is a schematic diagram illustrating the structure of a portion of a scanning circuit according to some embodiments of the present disclosure. In one example, Figure 13 A portion of the third scanning circuit can be depicted. (Reference) Figure 13 In some embodiments, the scanning circuit includes one or more preceding stages PS (e.g., one or more preceding scan units) preceding the first stage S1 of the scanning circuit. In a particular example, the scanning circuit includes four preceding stages preceding the first stage S1. The four preceding stages are configured to provide second emission control signals for four rows of pixel driving circuitry corresponding to the first through fourth stages. The first stage of the one or more preceding stages is configured to receive a start signal, and the one or more preceding stages are configured to sequentially transmit signals downwards.

[0181] Depending on the connection requirements between the display area and one or more scanning circuits, the horizontal output signals of the scanning circuits, after passing through multiple connection lines, must be ordered from top to bottom to match the order of the pixel connection lines or via positions in the display area. In some embodiments, the display panel includes multiple output vias and multiple input vias in the region between the display area and one or more scanning circuits. Output vias are configured to receive output electrodes for connection to output signal lines. Input vias are configured to receive input electrodes for connection to input signal lines. In one example, the display panel includes two output vias and two input vias in the region between the display area and one or more scanning circuits.

[0182] In some embodiments, the display panel includes a plurality of output electrodes, each at least partially located in a plurality of output vias, and a plurality of input electrodes, each at least partially located in a plurality of input vias. Each of the plurality of output electrodes is connected to a corresponding connection line among a plurality of connection lines and to a corresponding output signal line, which in turn is connected to a corresponding electrode in a pixel driving circuit in the display area. Each of the plurality of input electrodes is connected to a corresponding connection line among a plurality of connection lines and to a corresponding input signal line, which in turn is connected to a corresponding scanning unit of a corresponding scanning circuit.

[0183] Figure 14 The diagram illustrates the arrangement of output and input electrodes in the region between a display area and one or more scanning circuits, according to some embodiments of the present disclosure. Reference Figure 14 The display panel includes a first output electrode out1, a second output electrode out2, a first input electrode in1, and a second input electrode in2 in the region between the display area and one or more scanning circuits. In some embodiments, at least two electrodes (e.g., the first output electrode out1 and the second input electrode in2) are arranged side-by-side along a first direction DR1, and a plurality of connection lines CLLS in the region between the display area and one or more scanning circuits extend along a second direction DR2. This arrangement requires horizontal cross-lines to route around the at least two electrodes for connection and output, which complicates the routing process and increases the horizontal space required at via locations.

[0184] Figure 15 The diagram illustrates the arrangement of output and input electrodes in the region between a display area and one or more scanning circuits, according to some embodiments of the present disclosure. Reference Figure 15 The display panel includes a first output electrode out1, a second output electrode out2, a first input electrode in1, and a second input electrode in2 in the region between the display area and one or more scanning circuits. In some embodiments, at least two electrodes (e.g., the first output electrode out1 and the second input electrode in2) are arranged in an alternating manner along a first direction DR1 and a second direction DR2.

[0185] Figure 16 The diagram illustrates the arrangement of output and input electrodes in the region between a display area and one or more scanning circuits, according to some embodiments of the present disclosure. Reference Figure 16The display panel includes a first output electrode out1, a second output electrode out2, a first input electrode in1, and a second input electrode in2 in the region between the display area and one or more scanning circuits. In some embodiments, at least two electrodes (e.g., the first output electrode out1 and the second input electrode in2) are arranged in an alternating manner along a first direction DR1 and a second direction DR2.

[0186] Figure 17 The illustration shows the arrangement of output and input electrodes in the region between a display area and one or more scanning circuits, according to some embodiments of the present disclosure. Reference Figure 17 The display panel includes a first output electrode out1, a second output electrode out2, a first input electrode in1, and a second input electrode in2 in the region between the display area and one or more scanning circuits. In some embodiments, at least two electrodes (e.g., the first output electrode out1 and the second input electrode in2) are arranged in an alternating manner along a first direction DR1 and a second direction DR2.

[0187] Figure 15 , Figure 16 and Figure 17 The difference lies in the vertical positional relationship between at least two electrodes (e.g., the first output electrode out1 and the second input electrode in2). This positioning depends primarily on the relative height of the signal corresponding to the sub-pixel located on the display area side.

[0188] exist Figure 15 In this configuration, the position of the second output electrode, out2, is constrained by the diagonal segment DS of the connecting line, bringing it closer to the upper boundary of the cell. This constraint is more pronounced the smaller the sub-pixel size. This arrangement is detrimental to narrowing the bezel when sub-pixel signals require a large linear connection space. Adjusting the via position by extending the connecting line introduces new challenges, as it consumes wiring space allocated for other horizontal signal transmissions.

[0189] Figure 16 The following solution is provided: pull down the second input electrode in2 and the second output electrode out2. This adjustment increases the blank area BA adjacent to the diagonal segment DS of the connecting line adjacent to the second output electrode out2, thereby expanding the vertical adjustment range of the second output electrode out2. The diagonal segment DS extends along a direction different from the first direction DR1 and different from the second direction DR2.

[0190] Figure 15 and Figure 16 Both show areas with relatively large line spacing. If the terminal positions are appropriate, this area can be compressed to reduce the horizontal space. For example... Figure 17As shown, after compression, the vertical adjustability of the second output electrode out2 decreases, but the horizontal space also decreases. This arrangement requires a balance between the use of horizontal and vertical space to allow for flexible adjustments based on actual application requirements.

[0191] Reference Figures 15 to 17 In some embodiments, the display panel includes multiple electrodes in a region between the display area and one or more scanning circuits. The multiple electrodes include multiple output electrodes respectively connected to output signal lines (e.g., in...). Figures 15 to 17 (Represented as out1 and out2). In one example, refer to... Figure 10 as well as Figures 15 to 17 The output signal lines include a fourth intermediate line IML4 and a first reset voltage line Vint1. In another example, a first output electrode out1 is connected to the fourth intermediate line IML4, and a second output electrode out2 is connected to the first reset voltage line Vint1. Each of the plurality of output electrodes is positioned such that each output signal line connected to the respective output electrode in the respective output via extends substantially parallel to a first direction DR1 to connect to a corresponding terminal in the pixel driving circuitry in the display panel. As used herein, the term "substantially parallel" means an angle ranging from 0 degrees to approximately 45 degrees, for example, 0 degrees to approximately 5 degrees, 0 degrees to approximately 10 degrees, 0 degrees to approximately 15 degrees, 0 degrees to approximately 20 degrees, 0 degrees to approximately 25 degrees, and 0 degrees to approximately 30 degrees.

[0192] As described above, the display panel includes multiple signal lines located in the peripheral area. In some embodiments, the multiple signal lines and the output signal line may share at least one signal line. In one particular example, the multiple signal lines located in the peripheral area include a first reset voltage line Vint1, a second scan signal line Scan_N-7, a gate line Gate, a first scan signal line Scan_N, a first light emission control signal line EM_N, a third light emission control signal line EM_N+4, and a second reset voltage line Vint2. In another example, the output signal lines include a fourth intermediate line IML4 and the first reset voltage line Vint1. The first reset voltage line Vint1 is one of the multiple signal lines and also one of the output signal lines.

[0193] In some embodiments, the plurality of signal lines includes at least one signal line that is not part of the output signal lines. In some embodiments, the output signal lines include at least one signal line that is not part of the plurality of signal lines.

[0194] In some embodiments, the plurality of electrodes includes a first input electrode in1, a first output electrode out1, a second input electrode in2, and a second output electrode out2. In some embodiments, reference is made to... Figure 16 and Figure 17The first input electrode in1, the first output electrode out1, the second input electrode in2, and the second output electrode out2 are arranged sequentially along the first direction DR1. The first input electrode in1, the second input electrode in2, the first output electrode out1, and the second output electrode out2 are arranged sequentially along the second direction DR2.

[0195] In some embodiments, reference Figure 15 The first input electrode in1, the first output electrode out1, the second input electrode in2, and the second output electrode out2 are arranged sequentially along the first direction DR1. The first input electrode in1, the first output electrode out1, the second input electrode in2, and the second output electrode out2 are arranged sequentially along the second direction DR2.

[0196] In some embodiments, reference Figure 17 At least one connecting line adjacent to at least one of the plurality of electrodes comprises a plurality of diagonal segments. Each of the plurality of diagonal segments extends along a direction different from the first direction DR1 and different from the second direction DR2.

[0197] exist Figure 7 and Figure 9 In the layout shown, the first gate metal layer is used for multiple interconnects CLLS (including first interconnect CL1 and second interconnect CL2), while the first signal line layer is used for horizontal output signal cross-layer routing. This configuration also facilitates the adjustment of the vertical signal sequence. When space is constrained and the first signal line layer alone cannot meet the requirements, the first signal line layer can be routed to the second signal line layer. Since the vertical interconnects are located on the first gate metal layer, the electrodes of the first signal line to the second signal line can be located within the vertical interconnect region.

[0198] Due to the edge difference between rounded corners and straight edges, it is important to ensure that the overlapping areas of the two electrodes are consistent. To achieve this, it is preferable to place the electrodes on a flat area without underlying wiring. However, when the electrodes must be placed on a first gate metal layer for multiple interconnects, the following two scenarios should be considered.

[0199] Figure 18 The diagram illustrates the connections between corresponding electrodes and corresponding connection lines in some embodiments according to this disclosure. (Refer to...) Figure 18When the width of each electrode RE is similar to the width and spacing of the corresponding connecting line CCL, the electrodes RE are centered between the gaps in these lines. However, in this configuration, the passivation layer PVX beneath each electrode RE is not flat, resulting in a difference between rounded corners and straight edges during exposure. Furthermore, the proximity of the passivation layer PVX and the first gate metal layer leads to steep overlapping edges, increasing the likelihood of shape deformation. The upper second signal line layer is prone to delamination under high stress, especially in curved screen products.

[0200] Figure 19 The diagram illustrates the connections between corresponding electrodes and corresponding connection lines in some embodiments according to this disclosure. (Refer to...) Figure 19 In order to solve Figure 18 To address the issue, each electrode RE is directly and centrally positioned on its corresponding connection line. This improves the flatness of the passivation layer PVX beneath each electrode RE, reduces the steepness of the interface slope, and enhances stability.

[0201] Figure 20 The diagram illustrates the connections between corresponding electrodes and corresponding connection lines in some embodiments according to this disclosure. (Refer to...) Figure 20 When the width of each electrode RE is significantly larger than the width and spacing of the corresponding connecting line CCL (e.g., approximately twice the size), each electrode RE is centered above the corresponding connecting line CCL, resulting in... Figure 18 The same issues observed in [the study] include uneven exposure and steep edge overlap.

[0202] Figure 21 The diagram illustrates the connections between corresponding electrodes and corresponding connection lines in some embodiments according to this disclosure. (Refer to...) Figure 21 Each electrode RE is centered in the gap between adjacent interconnects. This arrangement increases the distance between the passivation layer PVX and the first gate metal layer, ensuring better exposure of the passivation layer PVX and improving alignment with the upper second signal line layer SD2. This approach enhances structural stability and reduces stress-related issues.

[0203] The inventors of this disclosure have discovered that by strategically selecting the settings of individual electrode REs based on the relative size of the electrode REs and the underlying interconnects, this design can minimize defects and optimize performance, especially in demanding scenarios such as curved screen products.

[0204] In some embodiments, refer to Figures 18 to 21 , Figure 7 and Figure 9When multiple interconnects are located on the first gate metal layer and space is constrained, using only the first signal line layer cannot adequately transmit or reorder the horizontal output signals. In this case, a second signal line layer can be added as an auxiliary routing layer. Vias connecting the first signal line layer to the second signal line layer can be placed in the area of ​​the multiple interconnects.

[0205] Reference Figures 18 to 21 In some embodiments, each electrode RE includes a first portion located on a first signal line layer SD1 and a second portion located on a second signal line layer SD2. The first portion connects the second portion to a corresponding connection line CCL located on a first gate metal layer Gate1.

[0206] Reference Figure 18 When the width of the via connecting the first signal line layer SD1 and the second signal line layer SD2 is similar to the width and spacing of the corresponding connection lines CCL, the via can be centered between adjacent connection lines. This setup ensures optimal alignment and minimizes the risk of overlap capacitance or interference, thereby maintaining signal integrity.

[0207] In some embodiments, the orthographic projection of each electrode RE on the substrate BS at least partially overlaps with the orthographic projection of two adjacent interconnects on the substrate BS. Optionally, each electrode RE is centered with respect to the gap between adjacent interconnects.

[0208] In some embodiments, each electrode RE includes a first portion located on a first signal line layer SD1 and a second portion located on a second signal line layer SD2. Optionally, the orthographic projection of the first portion on the substrate BS at least partially overlaps with the orthographic projections of two adjacent connection lines on the substrate BS. Optionally, the orthographic projection of the second portion on the substrate BS at least partially overlaps with the orthographic projections of two adjacent connection lines on the substrate BS.

[0209] In some embodiments, the width of the second portion along the plane intersecting the respective electrodes RE, the plurality of connection lines, and the substrate BS (in Figure 18 (represented as w1) is the width of the corresponding connection line CCL along the plane intersecting with each electrode RE, multiple connection lines, and the substrate BS. Figure 18 The range is from 1 to 1.5 times that of w2.

[0210] Reference Figure 19 In some embodiments, the orthographic projection of each electrode RE on the substrate BS at least partially overlaps with the orthographic projection of the corresponding connection line on the substrate BS. Optionally, the orthographic projection of each electrode RE on the substrate BS covers the orthographic projection of the corresponding connection line on the substrate BS.

[0211] In some embodiments, each electrode RE includes a first portion located on a first signal line layer SD1 and a second portion located on a second signal line layer SD2. Optionally, the orthographic projection of the first portion on the substrate BS overlaps the orthographic projection of the corresponding connection line on the substrate BS. Optionally, the orthographic projection of the second portion on the substrate BS overlaps the orthographic projection of the corresponding connection line on the substrate BS.

[0212] In some embodiments, the width of the second portion along the plane intersecting the respective electrodes RE, the plurality of connection lines, and the substrate BS (in Figure 19 (represented as w1) is the width of the corresponding connection line CCL along the plane intersecting with each electrode RE, multiple connection lines, and the substrate BS. Figure 19 The range is from 1 to 1.5 times that of w2.

[0213] Reference Figure 20 In some embodiments, the orthographic projection of each electrode RE on the substrate BS at least partially overlaps with the orthographic projection of the corresponding connection line on the substrate BS. Optionally, the orthographic projection of each electrode RE on the substrate BS covers the orthographic projection of the corresponding connection line on the substrate BS.

[0214] In some embodiments, each electrode RE includes a first portion located on a first signal line layer SD1 and a second portion located on a second signal line layer SD2. Optionally, the orthographic projection of the first portion on the substrate BS overlaps the orthographic projection of the corresponding connection line on the substrate BS. Optionally, the orthographic projection of the second portion on the substrate BS overlaps the orthographic projection of the corresponding connection line on the substrate BS.

[0215] In some embodiments, the width of the second portion along the plane intersecting the respective electrodes RE, the plurality of connection lines, and the substrate BS (in Figure 20 (represented as w1) is greater than or equal to the width of the corresponding connection line CCL along the plane intersecting with each electrode RE, multiple connection lines, and the substrate BS (in Figure 20 It is represented as 1.5 times (w2).

[0216] Reference Figure 21 In some embodiments, the orthographic projection of each electrode RE on the substrate BS at least partially overlaps with the orthographic projection of two adjacent connection lines on the substrate BS. Optionally, each electrode RE is centered with respect to the gap between adjacent connection lines.

[0217] In some embodiments, each electrode RE includes a first portion located on a first signal line layer SD1 and a second portion located on a second signal line layer SD2. Optionally, the orthographic projection of the first portion on the substrate BS at least partially overlaps with the orthographic projections of two adjacent connection lines on the substrate BS. Optionally, the orthographic projection of the second portion on the substrate BS at least partially overlaps with the orthographic projections of two adjacent connection lines on the substrate BS.

[0218] In some embodiments, the width of the second portion along the plane intersecting the respective electrodes RE, the plurality of connection lines, and the substrate BS (in Figure 21 (represented as w1) is greater than or equal to the width of the corresponding connection line CCL along the plane intersecting with each electrode RE, multiple connection lines, and the substrate BS (in Figure 21 It is represented as 1.5 times (w2).

[0219] In some embodiments, the connection lines and signal lines of this disclosure have a linewidth of 3 μm or greater. The inventors of this disclosure have found that this helps to achieve lower resistance.

[0220] In some embodiments, the spacing between adjacent connection lines or signal lines located on the same layer in this disclosure is greater than or equal to 3 μm. The inventors of this disclosure have found that this prevents short circuits caused by adhesion and reduces parasitic capacitance.

[0221] In some embodiments, the orthographic projections of the connection lines and signal lines located in the first gate metal layer onto the substrate do not overlap with the orthographic projections of the connection lines and signal lines located in the second gate metal layer onto the substrate. Optionally, the distance between the orthographic projections of the connection lines or signal lines located in the first gate metal layer onto the substrate and the orthographic projections of the connection lines or signal lines located in the second gate metal layer onto the substrate is greater than or equal to 1 μm. The inventors of this disclosure have found that this prevents the formation of overlapping capacitance.

[0222] In some embodiments, when space is constrained, the orthographic projections of the connection lines and signal lines located on the first signal line layer onto the substrate may overlap with the orthographic projections of the connection lines and signal lines located on the second signal line layer onto the substrate. In some embodiments, when space is unconstrained, the orthographic projections of the connection lines and signal lines located on the first signal line layer onto the substrate do not overlap with the orthographic projections of the connection lines and signal lines located on the second signal line layer onto the substrate. The orthographic projections of the connection lines and signal lines located on the first or second signal line layer overlap with the orthographic projections of the connection lines and signal lines located on the first or second gate metal layer.

[0223] In some embodiments, vias connecting the first signal line layer and the second signal line layer are disposed in a flat area to ensure consistent engagement between straight edges and rounded edges.

[0224] In some embodiments, inter-layer jumpers require vias, which occupy considerable space. To enhance layout compression, vias should be staggered where possible. Vias should be kept at a sufficient distance from adjacent traces (e.g., greater than or equal to 2 μm) to prevent short circuits between different signals.

[0225] In some embodiments, vias must have stable dimensions to maintain structural integrity and reduce contact resistance. In one example, a via extending through the interlayer dielectric layer has a size of 2.5 × 2.5 μm. 2 The dimensions are as follows. In another example, the via extending through the passivation layer has a size of 3×3μm. 2 The size.

[0226] In some embodiments, the via cover should have sufficient coverage to ensure bonding stability. In one example, the coverage limit is greater than or equal to 1.5 μm.

[0227] In another aspect, the present invention provides a display device comprising a display panel manufactured by the methods described herein or by means thereof, and one or more integrated circuits connected to the display panel. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device.

[0228] In another aspect, the present invention provides a method for manufacturing a display panel. In some embodiments, the method includes: forming a display area; forming one or more scanning circuits located in a peripheral region outside the display area; forming a plurality of connecting lines located in a region between the display area and the one or more scanning circuits, the plurality of connecting lines being configured to provide signals to a row of pixel driving circuitry in the display area; and forming a plurality of electrodes located in the region between the display area and the one or more scanning circuits. Optionally, forming the plurality of electrodes includes forming a plurality of output electrodes respectively connected to output signal lines. Optionally, each of the plurality of output electrodes is positioned such that a corresponding output signal line connected to the corresponding output electrode extends substantially parallel to a first direction to connect to a corresponding terminal in the pixel driving circuitry in the display panel. Optionally, the plurality of connecting lines extend along a second direction different from the first direction.

[0229] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display panel, comprising: Display area; One or more scanning circuits located in a peripheral area outside the display area; Multiple connecting lines located in the area between the display area and the one or more scanning circuits, the multiple connecting lines being configured to provide signals to a row of pixel driving circuitry in the display area; as well as Multiple electrodes located in the region between the display area and the one or more scanning circuits; The plurality of electrodes includes a plurality of output electrodes that are respectively connected to the output signal line; Each of the plurality of output electrodes is positioned such that a corresponding output signal line connected to the respective output electrode extends substantially parallel to a first direction to connect to a corresponding terminal in the pixel driving circuitry of the display panel; and The plurality of connecting lines extend along a second direction different from the first direction.

2. The display panel of claim 1, wherein, The plurality of electrodes includes a first input electrode, a first output electrode, a second input electrode, and a second output electrode; The first input electrode, the first output electrode, the second input electrode, and the second output electrode are arranged sequentially along the first direction; and The first input electrode, the second input electrode, the first output electrode, and the second output electrode are arranged sequentially along the second direction.

3. The display panel of claim 1, wherein, The plurality of electrodes includes a first input electrode, a first output electrode, a second input electrode, and a second output electrode; The first input electrode, the first output electrode, the second input electrode, and the second output electrode are arranged sequentially along the first direction; and The first input electrode, the first output electrode, the second input electrode, and the second output electrode are arranged sequentially along the second direction.

4. The display panel of claim 1, wherein, At least one connecting line adjacent to at least one of the plurality of electrodes includes one or more diagonal segments; as well as Each of the one or more diagonal segments extends in a direction different from the first direction and different from the second direction.

5. The display panel according to any one of claims 1 to 4, wherein The orthographic projection of each of the plurality of electrodes on the substrate at least partially overlaps with the orthographic projection of the two adjacent connecting lines on the substrate. as well as The gap between each electrode and the adjacent connecting line is centered.

6. The display panel of claim 5, wherein, Each electrode includes a first portion located in the first signal line layer and a second portion located in the second signal line layer; The orthographic projection of the first portion on the substrate overlaps at least partially with the orthographic projection of the two adjacent connecting lines on the substrate. as well as The orthographic projection of the second portion on the substrate overlaps at least partially with the orthographic projection of the two adjacent connecting lines on the substrate.

7. The display panel of claim 6, wherein, The second portion extends along the width of the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate, within a range of 1 to 1.5 times the width of the corresponding connecting line along the plane intersecting the respective electrodes, the plurality of connecting lines, and the substrate.

8. The display panel of claim 6, wherein, The second portion has a width along a plane intersecting the respective electrode, the plurality of connection lines, and the substrate, which is greater than or equal to 1.5 times a width of the corresponding connection line along the plane intersecting the respective electrode, the plurality of connection lines, and the substrate.

9. The display panel of any one of claims 1 to 4, wherein, The respective electrode has a footprint on the substrate that covers a footprint of the corresponding connection line on the substrate.

10. The display panel of claim 9, wherein, The respective electrode includes a first portion located at a first signal line layer and a second portion located at a second signal line layer. The first portion has a footprint on the substrate that covers the footprint of the corresponding connection line on the substrate. The second portion has a footprint on the substrate that covers the footprint of the corresponding connection line on the substrate. The second portion has a width along a plane intersecting the respective electrode, the plurality of connection lines, and the substrate, which is in a range of 1 times to 1.5 times a width of the corresponding connection line along the plane intersecting the respective electrode, the plurality of connection lines, and the substrate.

11. The display panel of claim 10, wherein, The second portion has a width along a plane intersecting the respective electrode, the plurality of connection lines, and the substrate, which is greater than or equal to 1.5 times a width of the corresponding connection line along the plane intersecting the respective electrode, the plurality of connection lines, and the substrate.

12. The display panel of claim 10, wherein, 13. The display panel of any one of claims 1 to 12, comprising a plurality of signal lines configured to provide a signal to a row of pixel driving circuits; the plurality of signal lines are connected to a respective scan circuit of the one or more scan circuits; and wherein the plurality of signal lines are alternately arranged in two different layers in the peripheral region of the display panel. The plurality of signal lines located in the peripheral region include a first reset voltage line, a second scan signal line, a gate line, a first scan signal line, a first light emitting control signal line, a second light emitting control signal line, and a second reset voltage line.

14. The display panel of claim 13, wherein, The two different layers are a first gate metal layer and a second gate metal layer; 15. The display panel of claim 13, wherein, the plurality of connection lines are located at a first signal line layer; the second gate metal layer is located on a side of the first gate metal layer distal from the substrate; and the first signal line layer is located on a side of the second gate metal layer distal from the substrate. the plurality of connection lines are located at a first signal line layer in the peripheral region of the display panel; 16. The display panel of any one of claims 1 to 12, wherein, the plurality of connection lines are located at a first gate metal layer or the first signal line layer; and the second signal line layer is located on a side of the first signal line layer distal from the first gate metal layer. the plurality of connection lines are located at a second signal line layer in the peripheral region of the display panel; the plurality of connection lines are located at a first gate metal layer or a first signal line layer; and 17. The display panel of any one of claims 1 to 12, wherein, the second signal line layer is located on a side of the first signal line layer distal from the first gate metal layer.

18. The display panel of claim 14, further comprising: a second scan circuit; a third scan circuit; a first connection line connecting the second scan signal line to a preceding stage of the second scan circuit; and a second connection line connecting the third scan signal line to a preceding stage of the third scan circuit. ​ ​ a second connection line connecting the second light emission control signal line to a preceding stage of the third scan circuit; the first connection line and the second scan signal line are located on two different layers; and the second connection line and the second light emission control signal line are located on two different layers.

19. A display device comprising the display panel according to any one of claims 1 to 18, and one or more integrated circuits connected to the display panel.

20. A method of manufacturing a display panel, comprising: forming a display region; forming one or more scan circuits in a peripheral region outside the display region; forming a plurality of connection lines in a region between the display region and the one or more scan circuits, the plurality of connection lines being configured to provide signals to a row of pixel drive circuits in the display region; and forming a plurality of electrodes in a region between the display region and the one or more scan circuits; wherein forming the plurality of electrodes comprises forming a plurality of output electrodes respectively connected to output signal lines; each of the plurality of output electrodes is positioned such that a respective output signal line connected to the respective output electrode extends substantially parallel to a first direction to connect to a corresponding terminal in a pixel drive circuit in the display panel; and the plurality of connection lines extend along a second direction different from the first direction. ​

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