Tool for testing thermal resistance of power semiconductor device

Abstract

The utility model discloses a power semiconductor device thermal resistance test tool comprising a support platform, the upper surface of which is provided with a clamp assembly, and the lower surface of which is provided with a temperature control device; the clamp assembly comprises a substrate, and a pin fixing socket and a plurality of electrode switching holes which are arranged on the substrate; a plurality of plugging holes are formed in the pin fixing socket, and the plugging holes are electrically connected with the corresponding electrode switching holes; the first temperature sensor is embedded in the supporting platform; the substrate is connected with the supporting platform through the movable positioning structure, so that the to-be-tested semiconductor device abuts against or is separated from the first temperature sensor. The power semiconductor device thermal resistance test tool provided by the technical scheme of the utility model allows a complete thermal resistance test process to be directly carried out on a semiconductor device under the condition that test equipment is not replaced. Therefore, the number of hardware required in the testing process is reduced, the hardware cost is reduced, and the testing efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor device testing, in particular to a thermal resistance testing tool for power semiconductor devices. Background Art

[0002] At present, power semiconductor devices are developing rapidly towards miniaturization, high frequency and integration. As a result, many discrete power devices have been derived. Through-hole transistor outline (TO) package is a common discrete power device package. The pins of this packaged device need to pass through the mounting holes of the PCB board and be soldered on the PCB board. Among them, TO-247 package is a common form of TO package, which is mainly used in discrete power devices such as MOSFET and IGBT, and is suitable for medium, high voltage and high current fields.

[0003] The miniaturization and high frequency of power semiconductor devices also pose challenges to the thermal performance of the devices, and indirectly affect the design, working performance and safety of the devices. Thermal resistance is one of the characteristic parameters of the thermal characteristics of the device and an important technical indicator of semiconductor devices. It is defined as: the ratio of the temperature difference between the main heating junction on the semiconductor device and a reference point to the power consumption caused by the temperature difference on the device. Whether the thermal resistance of power semiconductor devices can be accurately tested is very important for evaluating the packaging of power semiconductor devices, predicting device performance changes and improving device reliability.

[0004] JEDEC (Joint Electronic Devices Council) is the world's leading semiconductor technology standard development organization. The JESD 51 series it released defines the principles and methods required for effective thermal testing of packages containing semiconductor chips. It is one of the thermal test standards currently implemented by most thermal resistance test systems, such as JESD51-1's "Integrated Circuit Thermal Measurement Methods. Electrical Test Methods" and JESD51-14's "Transient Dual Interface Test Method".

[0005] For some thermal resistance test systems based on the JESD51 series test standards, the K coefficient (coefficient relationship between junction voltage and junction temperature) needs to be corrected before obtaining and calculating thermal resistance parameters. Therefore, two test systems and test stations need to be set up. First, the K coefficient is corrected through one test system, and then the relevant parameters of thermal resistance calculation are tested through another test system. This brings many inconveniences to the detection of semiconductor devices and is not conducive to improving the detection cost.

[0006] At the same time, when testing TO-packaged semiconductor devices, the circuit connection is usually carried out by welding pins, which is inconvenient to operate and may cause certain damage to the device pins. Utility Model Content

[0007] The utility model aims to provide a thermal resistance testing tool for power semiconductor devices which can meet all the processes of supporting thermal resistance testing of power semiconductor devices in the same system and workstation.

[0008] In order to achieve the above object, the utility model provides a power semiconductor device thermal resistance test tool, which includes:

[0009] A support platform, wherein a fixture assembly is disposed on the upper surface of the support platform, and a temperature control device is disposed on the lower surface of the support platform, wherein the temperature control device is used to control the temperature of the upper surface of the support platform by heating or cooling;

[0010] The fixture assembly includes a substrate, a pin fixing socket and a plurality of electrode transfer holes arranged on the substrate;

[0011] The pin fixing socket is provided with a plurality of plug holes, the plug holes are used to be electrically connected to the pins of the semiconductor device to be tested in a plug-in manner, and the plug holes are also electrically connected to the corresponding electrode transfer holes;

[0012] A first temperature sensor, which is embedded on the supporting platform, and the first temperature sensor is used to detect the shell temperature of the semiconductor device to be tested;

[0013] The substrate is connected to the supporting platform via a movable positioning structure so that the semiconductor device to be tested is in contact with or separated from the first temperature sensor.

[0014] Preferably, a plurality of second temperature sensors are arranged at intervals on the lower surface of the support platform, and the second temperature sensors are used to detect the temperature of the support platform.

[0015] Preferably, the substrate is a PCB board.

[0016] Preferably, the positioning structure includes positioning posts arranged on opposite sides of the support platform and positioning holes arranged on opposite sides of the substrate, the positioning posts can be plugged into the positioning holes, and two groups of positioning holes are arranged on each side of the substrate, so that the substrate is fixed at a first position and a second position on the support platform; in the first position, when the pins of the semiconductor device to be tested are inserted into the plug-in holes in the pin fixing socket, the semiconductor device to be tested abuts against the first temperature sensor; in the second position, when the pins of the semiconductor device to be tested are inserted into the plug-in holes in the pin fixing socket, the semiconductor device to be tested is separated from the first temperature sensor.

[0017] Preferably, a pressing assembly is further provided on the substrate, and the pressing assembly is used to press the semiconductor device to be tested at a corresponding position on the substrate.

[0018] Preferably, the pressing assembly comprises a fixed base, a fixed arm, a telescopic screw and a pressing head;

[0019] The fixing base is arranged on the substrate, the fixing arm includes a first end and a second end, the first end is arranged on the fixing base, the second end is located above the fixing base and extends in the direction of the pin fixing socket, the telescopic screw is arranged on the second end, and the crimping head is arranged at the free end of the telescopic screw, and the crimping head is moved closer to or away from the semiconductor device to be tested by the up and down telescopic movement of the telescopic screw.

[0020] Preferably, two elastic crimping plates are arranged opposite to each other in the plug-in hole of the pin fixing socket, an opening portion and a crimping gap connected to the opening portion are formed between the two crimping plates, the opening portion is used to receive the pins of the semiconductor device to be tested, and when the two crimping plates undergo elastic deformation, the diameter of the crimping gap changes.

[0021] Preferably, two support plates are arranged opposite to each other in the plug-in hole of the pin fixing socket, and the two crimping plates are respectively arranged on the two support plates. A boosting elastic member is also arranged between at least one of the crimping plates and the corresponding support plate, and the boosting elastic member is located at the bending part forming the crimping gap, and the boosting elastic member is used to enhance the elastic crimping force of the crimping plate.

[0022] Preferably, a heat dissipation device is further provided below the temperature control device, and the heat dissipation device is used to dissipate excess heat emitted by the temperature control device so that the temperature of the support platform reaches a dynamic balance.

[0023] Preferably, the substrate is further provided with an escape groove close to the pin fixing socket, and the escape groove is used to accommodate a shell of the semiconductor device to be tested.

[0024] Compared with the prior art, the thermal resistance test fixture for power semiconductor devices provided by the above technical solution of the utility model, firstly, by introducing a substrate with a movable positioning structure, the semiconductor device to be tested can be effectively contacted or separated with the first temperature sensor, so that, in the K coefficient correction of the semiconductor device, the contact between the temperature sensor and the semiconductor device to be tested can be avoided to affect the heat transfer effect between the semiconductor device to be tested and the supporting platform. Therefore, the K coefficient correction of the thermal resistance detection of the semiconductor device and the detection of related parameters of the thermal resistance calculation can be completed by the fixture, that is, it is allowed to directly perform a complete thermal resistance test process on the semiconductor device without changing the test equipment. This not only reduces the amount of hardware required in the test process, reduces the hardware cost, but also improves the test efficiency; secondly, through the design of the pin fixing socket and the electrode transfer hole, the inconvenience of the traditional welding pin connection method and the possible damage to the device pins are avoided, and the accuracy of the test and the integrity of the device are guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the control principle of the test system constructed based on the thermal resistance test tooling in the embodiment of the utility model.

[0026] Figure 2 It is a three-dimensional structural diagram of the thermal resistance testing tooling in the embodiment of the utility model.

[0027] Figure 3 It is a planar structural diagram of a semiconductor device in an embodiment of the utility model.

[0028] Figure 4 for Figure 2 Exploded view of the installation structure of the middle support platform.

[0029] Figure 5 for Figure 2 A three-dimensional structural diagram of the middle fixture assembly.

[0030] Figure 6 for Figure 5 Planar structure diagram of the middle substrate.

[0031] Figure 7 for Figure 6 The connection structure diagram of the semiconductor device under test and the pin fixing socket.

[0032] Figure 8 This is a diagram of the internal structure of the pin fixing socket in the embodiment of the utility model.

[0033] Fig. 9 This is a timing diagram of data collection by the sampling module in an embodiment of the utility model. DETAILED DESCRIPTION

[0034] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation modes and the accompanying drawings.

[0035] The present embodiment discloses a thermal resistance test fixture for a power semiconductor device, which is used to detect the thermal resistance value of a power semiconductor device. The power semiconductor device may be in a TO-247 package and may be applied to discrete power devices such as MOSFET diodes and IGBTs.

[0036] like Figures 1 to 7 The thermal resistance test fixture includes a support platform 1 and a fixture assembly 2. To facilitate the description of the working principle of the test fixture, the structure of the test system constructed based on the test fixture is briefly described in this embodiment, that is, the test system is further configured with a power module, a sampling module 5, a main control module 6 and a data processing module 7 on the basis of the test fixture.

[0037] The fixture assembly 2 is used to fix and transfer the semiconductor device M to be tested and the electronic control device. The fixture assembly 2 is arranged on the upper surface of the supporting platform 1.

[0038] A temperature control device 3 is also provided on the lower surface of the support platform 1. The temperature control device 3 is used to control the temperature of the upper surface of the support platform 1 by heating or cooling, and then control the temperature of the semiconductor device M to be tested by heat transfer between the upper surface of the support platform 1 and the semiconductor device M to be tested. It can be seen that the support platform 1 is made of a heat-conducting material, such as a metal cold plate. The temperature control device 3 in this embodiment is preferably a semiconductor refrigeration plate.

[0039] The fixture assembly 2 in this embodiment includes a substrate 20 and a pin fixing socket 21 and a plurality of electrode transfer holes 22 arranged on the substrate 20. The substrate 20 is preferably a PCB board.

[0040] A plurality of plug holes 210 are provided in the pin fixing socket 21 . The plug holes 210 are used to be electrically connected to the pins of the semiconductor device M to be tested in a plug-in manner. The plug holes 210 are also electrically connected to the corresponding electrode transfer holes 22 .

[0041] A first temperature sensor U1 is also embedded on the support platform 1, and the first temperature sensor U1 is used to detect the shell temperature of the semiconductor device M to be tested. The first temperature sensor U1 in this embodiment is a thermocouple.

[0042] The substrate 20 is connected to the supporting platform 1 via a movable positioning structure, so that the semiconductor device M to be tested is in contact with or separated from the first temperature sensor U1 .

[0043] The sampling module 5 is electrically connected to the first temperature sensor U1 and the electrode adapter hole 22 . The sampling module 5 is used to collect the detection value of the first temperature sensor U1 and the voltage value of the semiconductor device M to be tested.

[0044] The main control module 6 is electrically connected to the sampling module 5 and the temperature control device 3 , and is used to control the working states of the sampling module 5 and the temperature control device 3 .

[0045] The data processing module 7 is electrically connected to the main control module 6 , and is used to calculate the thermal resistance value of the semiconductor device M to be tested based on the parameter value returned by the main control module 6 .

[0046] For the pin fixing socket 21 in this embodiment, each plug hole 210 thereon is connected to two electrode pins at the bottom thereof, and each electrode pin is connected to the electrode transfer hole 22 through a signal wiring on the substrate 20. Figure 6 and Figure 7 , the four plug holes 210 on the pin fixing socket 21 correspond to four groups of eight electrode transfer holes 22, and the four groups of electrode transfer holes 22 are 22A, 22B, 22C, and 22D respectively. Among them, the electrode transfer hole 22B is a Kelvin pin transfer hole, which is opened only when the package of the semiconductor device M to be tested is TO-247-4, and is connected to its Kelvin source pin. Each group of transfer holes can be divided into a force end (power end) and a sense end (measurement end). The force end is connected to the power source, and the sense end is connected to the test source. The power source and the test source are both provided by the power module. In this way, the power input end and the signal test end are separated to form a Kelvin connection to reduce signal interference. The electrode transfer holes 22 corresponding to devices of different types and packages will be different. Please refer to the following Table 1 for details.

[0047]

[0048] Table 1

[0049] Among them, + and - of DIODE represent the anode and cathode of the diode respectively; S, Sk, D, and G of MOSFET represent the source, Kelvin source, drain, and gate respectively; E, Ek, C, and G of IGBT represent the emitter, Kelvin emitter, collector, and gate respectively.

[0050] The thermal resistance test fixture for power semiconductor devices provided by the above technical solution of the utility model, firstly, by introducing a substrate 20 with a movable positioning structure, the semiconductor device M to be tested can be effectively contacted or separated with the first temperature sensor U1, so that, in the K coefficient correction of the semiconductor device, the contact between the temperature sensor and the semiconductor device M to be tested can be avoided to affect the heat transfer effect between the semiconductor device M to be tested and the support platform 1. Therefore, the K coefficient correction of the thermal resistance detection of the semiconductor device and the detection of related parameters of the thermal resistance calculation can be completed by the fixture, that is, it is allowed to directly perform a complete thermal resistance test process on the semiconductor device without changing the test equipment. This not only reduces the amount of hardware required in the test process, reduces the hardware cost, but also improves the test efficiency; secondly, through the design of the pin fixing socket 21 and the electrode transfer hole 22, the inconvenience of the traditional welding pin connection method and the possible damage to the device pins are avoided, and the accuracy of the test and the integrity of the device are guaranteed.

[0051] like Figure 2 and Figure 4 , a plurality of second temperature sensors U2 are arranged at intervals on the lower surface of the support platform 1, and the second temperature sensors U2 are used to detect the temperature of the support platform 1. The main control module 6 is electrically connected to the plurality of second temperature sensors U2, and the main control module 6 controls the state of the temperature control device 3 according to the detection values ​​of the plurality of second temperature sensors U2. In this embodiment, by setting the plurality of second temperature sensors U2, the main control module 6 can accurately control the temperature of the support platform 1 through the temperature control device 3.

[0052] On the other hand, Figure 2 , Figure 4 and Figure 5 The positioning structure includes positioning posts 10 disposed on opposite sides of the support platform 1 and positioning holes 200 disposed on opposite sides of the substrate 20, and the positioning posts 10 can be plugged into the positioning holes 200. Two groups of positioning holes 200 are disposed on each side of the substrate 20, so that the substrate 20 is fixed at a first position and a second position on the support platform 1.

[0053] In the first position, one group of positioning holes 200 ′ is plugged into the positioning posts 10 on the support platform 1 . At this time, when the pins of the semiconductor device M to be tested are inserted into the plugging holes 210 in the pin fixing socket 21 , the semiconductor device M to be tested abuts against the first temperature sensor U1 .

[0054] In the second position, another set of positioning holes 200" is plugged into the positioning posts 10 on the supporting platform 1. At this time, when the pins of the semiconductor device M to be tested are inserted into the plugging holes 210 in the pin fixing socket 21, the semiconductor device M to be tested is separated from the first temperature sensor U1.

[0055] Furthermore, in order to make the semiconductor device M under test closely contact with the supporting platform 1, as Figure 2 and Figure 5 A pressing assembly 4 is also provided on the substrate 20, and the pressing assembly 4 is used to press the semiconductor device M to be tested at a corresponding position of the substrate 20. In this embodiment, the pressing assembly 4 applies a certain pressure to the semiconductor device M to be tested so that it is in close contact with the supporting platform 1, so as to reduce the contact thermal resistance between the two and improve the heat conduction efficiency.

[0056] On the other hand, the pressing assembly 4 includes a fixed base 40 , a fixed arm 41 , a telescopic screw 42 and a pressing head 43 .

[0057] The fixed base 40 is arranged on the substrate 20, and the fixed arm 41 includes a first end 410 and a second end 411. The first end 410 is arranged on the fixed base 40, and the second end 411 is located above the fixed base 40 and extends in the direction of the pin fixing socket 21. The telescopic screw 42 is arranged on the second end 411, and the crimping head 43 is arranged at the free end of the telescopic screw 42. By the up and down telescopic movement of the telescopic screw 42, the crimping head 43 is moved close to or away from the semiconductor device M to be tested.

[0058] When the semiconductor device M to be tested is connected to the pin fixing socket 21, the telescopic screw 42 is rotated so that the crimping head 43 moves downward and abuts against the semiconductor device M to be tested, thereby fixing the semiconductor device M to be tested on the supporting platform 1. After the test is completed, the telescopic screw 42 is rotated in the opposite direction so that the crimping head 43 moves upward and separates from the semiconductor device M to be tested.

[0059] On the other hand, a relief groove 201 is provided on the substrate 20 near the pin fixing socket 21, and the relief groove 201 is used to accommodate the shell of the semiconductor device M to be tested. During the test, the semiconductor device M to be tested is placed in the relief groove 201, so that the pins of the semiconductor device M to be tested are inserted into the plug holes 210 of the pin fixing socket 21, and the shell of the semiconductor device M to be tested abuts against the surface of the support platform 1.

[0060] On the other hand, Figure 8 Two elastic crimping pieces 211 are arranged opposite to each other in the plug hole 210 of the pin fixing socket 21, and an opening 212 and a crimping gap 213 connected to the opening 212 are formed between the two crimping pieces 211. The opening 212 is used to receive the pins of the semiconductor device M to be tested. When the two crimping pieces 211 are elastically deformed, the diameter of the crimping gap 213 changes. In this embodiment, the two elastic crimping pieces 211 are formed by reverse arc bending to form the opening 212 and the crimping gap 213, and the crimping gap 213 is located at the maximum curvature of the two crimping pieces 211.

[0061] When the pin of the semiconductor device M to be tested is inserted into the plug hole 210, the pin first enters the opening 212 of the plug hole 210, and then enters the crimping gap 213 from the opening 212. As the pin is inserted, the crimping gap 213 is pushed open, and the diameter of the crimping gap 213 is expanded, so that the pin enters the crimping gap 213. At this time, based on the elastic restoring force of the crimping piece 211 at the crimping gap 213, the pin is fixed at the crimping gap 213. After the test is completed, the pin can be pulled out from the crimping gap 213 by overcoming the elastic restoring force of the two crimping pieces 211 at the crimping gap 213. The operation is convenient, no welding is required, and the pin is effectively prevented from being damaged.

[0062] Furthermore, two supporting sheets 214 are arranged opposite to each other in the plug hole 210 of the pin fixing socket 21, and two crimping sheets 211 are arranged on the two supporting sheets 214 respectively. A pressurizing elastic member 215 is also arranged between at least one crimping sheet 211 and the corresponding supporting sheet 214. The pressurizing elastic member 215 is located at the bending part where the crimping gap 213 is formed, and the pressurizing elastic member 215 is used to enhance the elastic crimping force of the crimping sheet 211. The pressurizing elastic member 215 in this embodiment is preferably a spring.

[0063] On the other hand, Figure 2 and Figure 4 A heat sink 8 electrically connected to the main control module 6 is provided below the temperature control device 3. The heat sink 8 is used to dissipate the excess heat generated by the temperature control device 3 so that the temperature of the support platform 1 reaches a dynamic balance. For example, when the temperature control device 3 is cooling (keeping the support platform at 25°C), it needs to dissipate heat outward, and the heat sink 8 strengthens the heat dissipation, so that the temperature control device 3 works stably.

[0064] The heat dissipation device 8 in this embodiment includes a heat sink 80 and a heat dissipation fan 81. During the test, the main control module 6 controls the operation state of the heat dissipation fan 81 according to the preset target temperature and the feedback of the second temperature sensor U2, so as to control the temperature of the support platform 1 to achieve dynamic balance.

[0065] The process of performing thermal resistance testing on semiconductor devices by using the testing system constructed by the thermal resistance testing system tooling disclosed in the above embodiment includes a first stage and a second stage.

[0066] The first phase includes the following steps:

[0067] S1: Adjust the position of the substrate 20 on the supporting platform 1, then evenly apply thermal grease on the back of the semiconductor device M to be tested, insert the pins of the semiconductor device M to be tested into the plug holes 210 in the pin fixing socket 21, and fix the semiconductor device M to be tested on the supporting platform 1. At this time, the semiconductor device M to be tested is separated from the first temperature sensor U1, so the semiconductor device M to be tested is in unobstructed contact with the supporting platform 1.

[0068] S2: Connect the sampling module 5 to the corresponding electrode transfer hole 22 according to the type of the semiconductor device M to be tested.

[0069] S3: The main control module 6 controls the temperature control device 3 to work at different powers at different time stages, so that the support platform 1 is stabilized at different temperature points at different time stages.

[0070] At each temperature point, a sensing current is applied to the semiconductor device M to be tested, and the junction voltage value of the semiconductor device M to be tested under current stability is collected by the sampling module 5 to obtain a number of data pairs, each of which includes a junction voltage value and a temperature value.

[0071] Specifically, initially, the temperature control device 3 is controlled to work at the first power, so that the support platform 1 reaches a thermal equilibrium state at the first temperature point T1. That is, the detection values ​​of a plurality of second temperature sensors U2 are monitored in real time. If the fluctuation of each second temperature sensor U2 within a certain time range is less than a preset value, and the temperature difference between the plurality of second temperature sensors U2 is also less than the preset value, it is considered that the support platform 1 and the semiconductor device M to be tested have reached a thermal equilibrium state. At this time, the actual internal temperature (junction temperature) of the semiconductor device M to be tested is equal to the surface temperature of the support platform 1. For example, when the support platform 1 reaches a thermal equilibrium state at the first temperature point T1, the junction temperature of the semiconductor device M to be tested is T1.

[0072] Then, a sensing current I is applied to the semiconductor device M under test. M , and collect the junction voltage value at the current temperature. Then, control the temperature control device 3 to work at the second power (the second power is greater than the first power), so that the support platform 1 reaches a thermal equilibrium state at the second temperature point T2, and collect the junction voltage value at the current temperature. Thus, multiple groups of junction voltage values ​​at different temperature points are collected to obtain several data pairs.

[0073] S4: The data processing module 7 performs fitting processing on the obtained data pairs to obtain the coefficient K of the junction voltage value and the junction temperature of the semiconductor device M to be tested. Since in step S3, the sensing current I M This current will not cause the temperature of the semiconductor device M to be tested to rise. Therefore, the thermal equilibrium temperature of the supporting platform 1 can be equivalent to the junction temperature of the semiconductor device M to be tested.

[0074] The coefficient K in this embodiment is calculated by plotting a number of data pairs in a coordinate diagram of junction voltage and junction temperature, and then obtaining the coefficient K by data fitting. Specifically, the coefficient K can be calculated according to the following calculation formula 1:

[0075]

[0076] Among them, T Hi and T Lo They are the highest junction temperature and the lowest junction temperature in several data pairs, V Hi and V Lo are the highest junction voltage value and the lowest junction voltage value in several data pairs respectively.

[0077] The second phase includes the following steps:

[0078] S5: Adjust the position of the substrate 20 on the supporting platform 1 again, re-apply thermal grease evenly to the back of the semiconductor device M under test, and apply the same torque as in the first stage to the clamping assembly to fix the semiconductor device under test on the supporting platform so that the semiconductor device under test M contacts the first temperature sensor U1.

[0079] S6: The shell temperature fed back by the first temperature sensor U1 and the junction voltage of the semiconductor device M to be tested are collected in real time by the sampling module 5, and the thermal resistance value R of the semiconductor device M to be tested is calculated according to the following formula: th ,

[0080]

[0081] in, T j1 and T c1 are the junction temperature and case temperature of the semiconductor device M under initial load sensing current; V j1 is the junction voltage of the semiconductor device M under initial load sensing current, V j2 is the junction voltage of the semiconductor device M under test when the current changes from power current to sensing current; T c2 I is the shell temperature of the semiconductor device M under test at the moment when the current changes from power current to sensing current; H and V H are the power current and power voltage loaded on the semiconductor device M to be tested respectively.

[0082] Specifically, first, in the initial stage, a sensing current I is applied to the semiconductor device M to be tested. M , through the sampling module 5 to collect the current state (such as Fig. 9 The junction voltage V at time t0 j1 , and record the shell temperature T in the current state c1 .

[0083] Then, close the power source switch to load the power current I to the semiconductor device M under test. H (This power current is much larger than the sensing current, which can cause the semiconductor device M to heat up.) The sampling module 5 collects the power voltage V in the current state. H , then the heating power is P = IH *V H .

[0084] As the temperature of the semiconductor device M under test increases, the heat inside it is dissipated outward through the support platform 1, and the shell temperature of the semiconductor device M under test also increases. At time t1, the semiconductor device M under test reaches a thermally stable state. At time t2, the shell temperature of the semiconductor device M under test is recorded as T c2 , and the power source switch is turned off at the same time, and the current on the semiconductor device M under test changes from the power current I H Rapidly switch to sense current I M , collect the junction voltage V at the switching moment j2 and shell temperature T c2 Finally, the thermal resistance value of the semiconductor device M to be tested is calculated according to the above formula 1. It should be noted that ΔT j It is the junction temperature change during the time period t0-t2, which is calculated by the junction voltage collected at two time points using the K coefficient.

[0085] In summary, the utility model discloses a thermal resistance test fixture for power semiconductor devices, based on which the thermal resistance test of semiconductor devices can be completed on the same system, reducing the test cost and improving the test efficiency. Secondly, a metal crimping device pin fixing method is adopted to reduce the damage to the semiconductor device M to be tested caused by the conventional welding pin method, and also simplifies the corresponding operation process. Furthermore, a semiconductor refrigeration plate is used for constant temperature control, with high control accuracy and compact size, and no need for external liquid cooling constant temperature units and other devices, reducing the overall cost of the system. The test system disclosed by the utility model can adapt to various devices in TO247 series packages, including diodes, MOSFETs and IGBTs, and can also meet the requirements of 2pin and 4pin pins.

[0086] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A thermal resistance test tool for power semiconductor devices, characterized in that: include: A support platform, wherein a fixture assembly is disposed on the upper surface of the support platform, and a temperature control device is disposed on the lower surface of the support platform, wherein the temperature control device is used to control the temperature of the upper surface of the support platform by heating or cooling; The fixture assembly includes a substrate, a pin fixing socket and a plurality of electrode transfer holes arranged on the substrate; The pin fixing socket is provided with a plurality of plug holes, the plug holes are used to be electrically connected to the pins of the semiconductor device to be tested in a plug-in manner, and the plug holes are also electrically connected to the corresponding electrode transfer holes; A first temperature sensor, which is embedded on the supporting platform, and the first temperature sensor is used to detect the shell temperature of the semiconductor device to be tested; The substrate is connected to the supporting platform via a movable positioning structure so that the semiconductor device to be tested is in contact with or separated from the first temperature sensor.

2. The thermal resistance test tool for power semiconductor devices according to claim 1, characterized in that: A plurality of second temperature sensors are arranged at intervals on the lower surface of the support platform, and the second temperature sensors are used to detect the temperature of the support platform.

3. The thermal resistance test tool for power semiconductor devices according to claim 1, characterized in that: The substrate is a PCB board.

4. The thermal resistance test tool for power semiconductor devices according to claim 1, characterized in that: The positioning structure includes positioning posts arranged on opposite sides of the support platform and positioning holes arranged on opposite sides of the substrate, the positioning posts can be plugged into the positioning holes, and two groups of positioning holes are arranged on each side of the substrate, so that the substrate is fixed at a first position and a second position on the support platform; in the first position, when the pins of the semiconductor device to be tested are inserted into the plugging holes in the pin fixing socket, the semiconductor device to be tested abuts against the first temperature sensor; in the second position, when the pins of the semiconductor device to be tested are inserted into the plugging holes in the pin fixing socket, the semiconductor device to be tested is separated from the first temperature sensor.

5. The thermal resistance test tool for power semiconductor devices according to claim 1, characterized in that: A pressing assembly is also provided on the substrate, and the pressing assembly is used to press the semiconductor device to be tested at a corresponding position of the substrate.

6. The thermal resistance test tool for power semiconductor devices according to claim 5, characterized in that: The pressing assembly includes a fixed base, a fixed arm, a telescopic screw and a pressing head; The fixing base is arranged on the substrate, the fixing arm includes a first end and a second end, the first end is arranged on the fixing base, the second end is located above the fixing base and extends in the direction of the pin fixing socket, the telescopic screw is arranged on the second end, and the crimping head is arranged at the free end of the telescopic screw, and the crimping head is moved closer to or away from the semiconductor device to be tested by the up and down telescopic movement of the telescopic screw.

7. The thermal resistance test tool for power semiconductor devices according to claim 1, characterized in that: Two elastic crimping sheets are arranged opposite to each other in the plug-in hole of the pin fixing socket, an opening portion and a crimping gap connected to the opening portion are formed between the two crimping sheets, the opening portion is used to receive the pins of the semiconductor device to be tested, and when the two crimping sheets undergo elastic deformation, the diameter of the crimping gap changes.

8. The thermal resistance test tool for power semiconductor devices according to claim 7, characterized in that: Two support plates are arranged opposite to each other in the plug-in hole of the pin fixing socket, and the two crimping plates are respectively arranged on the two support plates. A boosting elastic member is also arranged between at least one of the crimping plates and the corresponding support plate. The boosting elastic member is located at the bending part forming the crimping gap, and the boosting elastic member is used to enhance the elastic crimping force of the crimping plate.

9. The thermal resistance test tool for power semiconductor devices according to claim 1, characterized in that: A heat dissipation device is also provided below the temperature control device, and the heat dissipation device is used to dissipate the excess heat emitted by the temperature control device so that the temperature of the support platform reaches a dynamic balance.

10. The thermal resistance test tool for power semiconductor devices according to claim 1, characterized in that: The substrate is also provided with an avoidance groove close to the pin fixing socket, and the avoidance groove is used to accommodate the shell of the semiconductor device to be tested.

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