Shift register unit and gate drive circuit

Abstract

The utility model provides a shift register unit and a gate drive circuit. The shift register unit comprises an input circuit, a control circuit, K output circuits, K'isolation circuits and a pull-down circuit. The first end of the kth output circuit is connected to the kth clock signal end, the second end of the kth output circuit is connected to the kth output signal end, K is an integer larger than 1, and k = 1, 2,..., K. The K'isolation circuits are respectively connected between the control ends of K 'output circuits in the K output circuits and the pull-up node, and K' is a positive integer and is smaller than or equal to K. The first end of each isolation circuit is connected to the pull-up node, the second end of each isolation circuit is connected to the control end of the corresponding output circuit, and the control end of each isolation circuit is connected to a control signal end; the isolation circuit is used for connecting or disconnecting the first end and the second end of the isolation circuit under the control of the voltage between the control end of the isolation circuit and the second end of the isolation circuit.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a shift register unit and a gate drive circuit. Background Art

[0002] In display technology, multiple cascaded shift register units are used to generate sequentially shifted output signals to drive pixels for display. This cascade circuit structure is also called a gate on array (GOA) circuit. With the development of technology, the requirements for display effects are getting higher and higher, and the current GOA circuit structure is difficult to meet the increasing display needs. Summary of the invention

[0003] According to one aspect of an embodiment of the present disclosure, there is provided a shift register unit, comprising:

[0004] An input circuit, connected to an input signal terminal and a pull-up node of the shift register, and used for inputting a signal at the input signal terminal to the pull-up node;

[0005] A control circuit connected to the pull-up node and the pull-down node, the power signal terminal and the reference signal terminal of the shift register unit, the control circuit being used to provide a signal of one of the power signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node;

[0006] K output circuits connected to K clock signal terminals, K output signal terminals and a pull-up node of the shift register unit, wherein a first terminal of the kth output circuit is connected to the kth clock signal terminal of the shift register unit, a second terminal of the kth signal output circuit is connected to the kth output signal terminal of the shift register unit, and each output circuit is used to provide a signal at a first terminal of the output circuit to a second terminal of the output circuit under the control of a control terminal of the output circuit, wherein K is an integer greater than 1, k=1, 2, ..., K;

[0007] K' isolation circuits are respectively connected between the control terminals of K' output circuits among the K output circuits and the pull-up node, wherein a first terminal of each isolation circuit is connected to the pull-up node, a second terminal of the isolation circuit is connected to the control terminal of the corresponding output circuit, the control terminal of the isolation circuit is connected to the control signal terminal, and the isolation circuit is used to connect or disconnect the first terminal of the isolation circuit with the second terminal under the control of the voltage between the control terminal of the isolation circuit and the second terminal of the isolation circuit, wherein K' is a positive integer, and K'≤K;

[0008] The pull-down circuit is connected to the pull-down node, the pull-up node, K output signal terminals and the reference signal terminal. The pull-down subcircuit is used to provide the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

[0009] In some embodiments, the K output circuits include a cascade output circuit and K' signal output circuits, the output signal terminal connected to the cascade output circuit is used to connect to other shift register units, and the output signal terminal connected to the signal output circuit is used to provide an output signal;

[0010] The K' isolation circuits are respectively connected between the control terminals and the pull-up nodes of the K' signal output circuits.

[0011] In some embodiments, the K output circuits include a cascade output circuit and K' signal output circuits, one of the K' isolation circuits is connected between the control end of the cascade output circuit and a pull-up node, and the remaining K'-1 isolation circuits are respectively connected between the control end of the K'-1 signal output circuit and the pull-up node.

[0012] In some embodiments, the isolation circuit includes a first transistor, a gate of the first transistor is connected to a control signal terminal, a first electrode of the first transistor serves as a first terminal of the isolation circuit, and a second electrode of the first transistor serves as a second terminal of the isolation circuit.

[0013] In some embodiments, the control signal terminal includes a first control signal terminal and a second control signal terminal, wherein the first control signal terminal is at a first level and the second control signal terminal is at a second level; the isolation circuit also includes a second transistor, wherein the gate of the first transistor is connected to the first control signal terminal, the gate of the second transistor is connected to the second control signal terminal, the first electrode of the first transistor is connected to the first electrode of the second transistor, and the second electrode of the first transistor is connected to the second electrode of the second transistor.

[0014] In some embodiments, K=5, K′=3, 4 or 5.

[0015] In some embodiments, the output circuit includes:

[0016] a third transistor, wherein the gate of the third transistor serves as a control terminal of the output circuit, the first electrode of the third transistor serves as a first terminal of the output circuit, and the second electrode of the third transistor serves as a second terminal of the output circuit;

[0017] A first capacitor, wherein a first electrode of the first capacitor is connected to the gate of the third transistor, and a second electrode of the first capacitor is connected to the second electrode of the third transistor.

[0018] In some embodiments, the input circuit includes a fourth transistor, the fourth transistor, the gate of the fourth transistor is connected to the input signal terminal, the first electrode of the fourth transistor is connected to the power signal terminal, and the second electrode of the fourth transistor is connected to the pull-up node; or

[0019] The input circuit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the input signal terminal, the first electrode of the fourth transistor is connected to the power signal terminal, the second electrode of the fourth transistor is connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the input signal terminal, the first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is connected to the pull-up node.

[0020] In some embodiments, the shift register unit further includes: a reset circuit connected to the reset signal terminal, the pull-up node and the reference signal terminal of the shift register unit, the reset circuit being used to provide the signal of the reference signal terminal to the pull-up node under the control of the reset signal terminal.

[0021] In some embodiments, the reset circuit includes a sixth transistor, a gate of the sixth transistor is connected to the reset signal terminal, a first electrode of the sixth transistor is connected to the reference signal terminal, and a second electrode of the sixth transistor is connected to the pull-up node; or

[0022] The reset circuit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor is connected to the reset signal terminal, the first electrode of the sixth transistor is connected to the reference signal terminal, the second electrode of the sixth transistor is connected to the pull-up node through the seventh transistor, the gate of the seventh transistor is connected to the reset signal terminal, the first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is connected to the pull-up node.

[0023] In some embodiments, the input signal terminal includes a first input signal terminal and a first input signal terminal, the control signal terminal includes a first control signal terminal and a second control signal terminal, and the input circuit includes:

[0024] A first input circuit connected to the first input signal terminal, the pull-up node and the first control signal terminal, the first input circuit being used to provide a signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal;

[0025] A second input circuit connected to the second input signal terminal, the pull-up node and the second control signal terminal, the second input circuit being used to provide a signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal;

[0026] In the forward scanning mode, the first control signal terminal is at the first level and the second control signal terminal is at the second level; in the reverse scanning mode, the first control signal terminal is at the second level and the second control signal terminal is at the first level.

[0027] In some embodiments, the first input circuit comprises:

[0028] A fourth transistor, wherein a gate of the fourth transistor is connected to the first input signal terminal, a first electrode of the fourth transistor is connected to the first control signal terminal, and a second electrode of the fourth transistor is connected to the pull-up node.

[0029] In some embodiments, the first input circuit further comprises:

[0030] A fifth transistor, the second electrode of the fourth transistor is connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the first input signal terminal, the first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is connected to the pull-up node.

[0031] In some embodiments, the second input circuit comprises:

[0032] A sixth transistor, a gate of the sixth transistor is connected to the second input signal terminal, a first electrode of the sixth transistor is connected to the second control signal terminal, and a second electrode of the sixth transistor is connected to the pull-up node.

[0033] In some embodiments, the second input circuit further comprises:

[0034] A seventh transistor, wherein a gate of the seventh transistor is connected to the second control signal terminal, a first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and a second electrode of the seventh transistor is connected to the pull-up node.

[0035] In some embodiments, the first input circuit includes a fourth transistor, the second input circuit includes a sixth transistor, and parameters of the fourth transistor are the same as parameters of the sixth transistor.

[0036] In some embodiments, the first input circuit further includes a fifth transistor, the second input circuit further includes a seventh transistor, and parameters of the fifth transistor are the same as parameters of the seventh transistor.

[0037] In some embodiments, the shift register unit further includes:

[0038] A first voltage stabilizing circuit is connected to the pull-down node, the second input signal terminal and the first control signal terminal, and the first voltage stabilizing circuit is used to provide a signal of the first control signal terminal to the pull-down node under the control of the second input signal terminal;

[0039] The second voltage stabilizing circuit is connected to the pull-down node, the first input signal terminal and the second control signal terminal. The second voltage stabilizing circuit is used for providing the signal of the second control signal terminal to the pull-down node under the control of the first input signal terminal.

[0040] In some embodiments, the first voltage stabilizing circuit includes an eighth transistor, the gate of the eighth transistor is connected to the second input signal terminal, the first electrode of the eighth transistor is connected to the first control signal terminal, and the second electrode of the eighth transistor is connected to the pull-down node; the second voltage stabilizing circuit includes a ninth transistor, the gate of the ninth transistor is connected to the first input signal terminal, the first electrode of the ninth transistor is connected to the second control signal terminal, and the second electrode of the ninth transistor is connected to the pull-down node.

[0041] In some embodiments, parameters of the eighth transistor and the ninth transistor are the same.

[0042] In some embodiments, the shift register unit further includes a first voltage stabilizing circuit, a second voltage stabilizing circuit and an intermediate voltage stabilizing circuit, the first voltage stabilizing circuit, the second voltage stabilizing circuit and the intermediate voltage stabilizing circuit are connected to an intermediate node, wherein:

[0043] The first voltage stabilizing circuit is connected to the intermediate node, the first input signal terminal and the first control signal terminal, and the first voltage stabilizing circuit is used to provide the signal of the first control signal terminal to the intermediate node under the control of the first input signal terminal;

[0044] The second voltage stabilizing circuit is connected to the intermediate node, the second input signal terminal and the second control signal terminal, and the second voltage stabilizing circuit is used to provide the signal of the second control signal terminal to the intermediate node under the control of the second input signal terminal;

[0045] The intermediate voltage stabilizing circuit is connected to the pull-down node, the intermediate node and the reference signal terminal, and is configured to provide the signal of the reference signal terminal to the intermediate node under the control of the pull-down node, and to provide the signal of the reference signal terminal to the pull-down node under the control of the intermediate node.

[0046] In some embodiments, the first voltage stabilization circuit includes an eighth transistor, the second voltage stabilization circuit includes a ninth transistor, and the intermediate voltage stabilization circuit includes a tenth transistor and an eleventh transistor;

[0047] Among them, the gate of the eighth transistor is connected to the first input signal terminal, the first electrode of the eighth transistor is connected to the first control signal terminal, the second electrode of the eighth transistor is connected to the intermediate node, the gate of the ninth transistor is connected to the second input signal terminal, the first electrode of the ninth transistor is connected to the second control signal terminal, the second electrode of the ninth transistor is connected to the intermediate node, the gate of the tenth transistor is connected to the intermediate node, the first electrode of the tenth transistor is connected to the reference signal terminal, the second electrode of the tenth transistor is connected to the pull-down node, the gate of the eleventh transistor is connected to the pull-down node, the first electrode of the eleventh transistor is connected to the reference signal terminal, and the second electrode of the eleventh transistor is connected to the intermediate node.

[0048] In some embodiments, the control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, wherein:

[0049] The gate and the first electrode of the twelfth transistor are connected to the power signal terminal, and the second electrode of the twelfth transistor is connected to the gate of the thirteenth transistor;

[0050] A first electrode of the thirteenth transistor is connected to the power signal terminal, and a second electrode of the thirteenth transistor is connected to the pull-down node;

[0051] The gate of the fourteenth transistor is connected to the pull-up node, the first electrode of the fourteenth transistor is connected to the gate of the thirteenth transistor, and the second electrode of the fourteenth transistor is connected to the reference signal terminal;

[0052] The gate of the fifteenth transistor is connected to the pull-up node, the first electrode of the fifteenth transistor is connected to the pull-down node, and the second electrode of the fifteenth transistor is connected to the reference signal terminal.

[0053] In some embodiments, the control circuit further comprises:

[0054] The sixteenth transistor, the second electrode of the twelfth transistor is connected to the gate of the thirteenth transistor through the sixteenth transistor, wherein the gate of the sixteenth transistor is connected to the power signal terminal, the first electrode of the sixteenth transistor is connected to the second electrode of the twelfth transistor, and the second electrode of the sixteenth transistor is connected to the gate of the thirteenth transistor.

[0055] In some embodiments, the pull-down circuit includes:

[0056] A first pull-down circuit is connected to the pull-down node, the pull-up node and the reference signal terminal, and the first pull-down subcircuit is used to provide the signal of the reference signal terminal to the pull-up node under the control of the pull-down node;

[0057] K second pull-down circuits are respectively connected to K output signal terminals, wherein each second pull-down circuit is connected to a pull-down node, a reference signal terminal and a corresponding output signal terminal, and is configured to provide a signal from the reference signal terminal to the corresponding output signal terminal under the control of the pull-down node.

[0058] In some embodiments, the first pull-down circuit includes a seventeenth transistor, a gate of the seventeenth transistor is connected to the pull-down node, a first electrode of the seventeenth transistor is connected to the reference signal terminal, and a second electrode of the seventeenth transistor is connected to the pull-up node; or

[0059] The first pull-down circuit includes a seventeenth transistor and an eighteenth transistor, the gate of the seventeenth transistor is connected to the pull-down node, the first electrode of the seventeenth transistor is connected to the reference signal terminal through the eighteenth transistor, and the second electrode of the seventeenth transistor is connected to the pull-up node, wherein the gate of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the reference signal terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the seventeenth transistor.

[0060] In some embodiments, the second pull-down circuit includes a nineteenth transistor, a gate of the nineteenth transistor is connected to the pull-down node, a first electrode of the nineteenth transistor is connected to the reference signal terminal, and a second electrode of the nineteenth transistor is connected to the corresponding output signal terminal.

[0061] In some embodiments, the shift register unit further includes:

[0062] The total reset circuit is connected to the total reset signal terminal, the pull-up node and the reference signal terminal of the shift register unit, and is configured to provide the signal of the reference signal terminal to the pull-up node under the control of the total reset signal terminal.

[0063] In some embodiments, the total reset circuit includes a twentieth transistor, the gate of the twentieth transistor is connected to the total reset signal terminal, the first electrode of the twentieth transistor is connected to the reference signal terminal, and the second electrode of the twentieth transistor is connected to the pull-up node; or

[0064] The total reset circuit includes a twentieth transistor and a twenty-first transistor, the gate of the twentieth transistor is connected to the total reset signal terminal, the first electrode of the twentieth transistor is connected to the reference signal terminal through the twenty-first transistor, the second electrode of the twentieth transistor is connected to the pull-up node, the gate of the twenty-first transistor is connected to the total reset signal terminal, the first electrode of the twenty-first transistor is connected to the reference signal terminal, and the second electrode of the twenty-first transistor is connected to the first electrode of the twentieth transistor.

[0065] In some embodiments, the shift register unit also includes: a sensing circuit, connected to a sensing selection signal terminal, a sensing trigger signal terminal, a sensing control node, an input signal terminal and a pull-up node of the shift register unit, the sensing circuit being used to write the signal of the input signal terminal to the sensing control node under the control of the sensing selection signal terminal in the display phase, and to provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal in the blanking phase.

[0066] In some embodiments, the sensing circuit includes:

[0067] A selection subcircuit connected to the sensing selection signal terminal, the sensing control node and the input signal terminal, the selection subcircuit being used to write the signal of the input signal terminal into the sensing control node under the control of the sensing selection signal terminal in the display phase;

[0068] The trigger subcircuit is connected to the sensing trigger signal terminal, the sensing control node and the pull-up node, and is used to provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal in the blanking phase.

[0069] In some embodiments, the selection sub-circuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a second capacitor, wherein:

[0070] The gate of the twenty-second transistor is connected to the sensing selection signal terminal, the first electrode of the twenty-second transistor is connected to the input signal terminal, the second electrode of the twenty-second transistor is connected to the first electrode of the twenty-third transistor, the first electrode of the twenty-third transistor is connected to the sensing selection signal terminal, the second electrode of the twenty-third transistor is connected to the sensing control node, the gate of the twenty-fourth transistor is connected to the sensing control node, the first electrode of the twenty-fourth transistor is connected to the second electrode of the twenty-second transistor, the second electrode of the twenty-fourth transistor is connected to the power supply signal terminal, the first electrode of the second capacitor is connected to the power supply signal terminal, and the second electrode of the second capacitor is connected to the gate of the twenty-fourth transistor.

[0071] In some embodiments, the trigger subcircuit includes a twenty-fifth transistor and a twenty-sixth transistor, the gate of the twenty-fifth transistor is connected to the sensing control node, the first electrode of the twenty-fifth transistor is connected to the power signal terminal, the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor, the gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal, and the second electrode of the twenty-sixth transistor is connected to the pull-up node; or

[0072] The trigger subcircuit includes a twenty-fifth transistor, a twenty-sixth transistor and a twenty-seventh transistor, the gate of the twenty-fifth transistor is connected to the sensing control node, the first electrode of the twenty-fifth transistor is connected to the power signal terminal, the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor, the gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal, the second electrode of the twenty-sixth transistor is connected to the pull-up node through the twenty-seventh transistor, the gate of the twenty-seventh transistor is connected to the sensing trigger signal terminal, the first electrode of the twenty-seventh transistor is connected to the second electrode of the twenty-sixth transistor, and the second electrode of the twenty-seventh transistor is connected to the pull-up node.

[0073] In some embodiments, the sensing circuit further includes: a voltage stabilizing subcircuit connected to a sensing control node, a sensing trigger signal terminal and a reference signal terminal, for providing a signal at the reference signal terminal to a pull-down node under the control of the sensing control node and the sensing trigger signal terminal.

[0074] In some embodiments, the voltage stabilization subcircuit includes a twenty-eighth transistor and a twenty-ninth transistor, the gate of the twenty-eighth transistor is connected to the sensing trigger signal terminal, the first electrode of the twenty-eighth transistor is connected to the pull-up node, the second electrode of the twenty-eighth transistor is connected to the first electrode of the twenty-ninth transistor, the gate of the twenty-ninth transistor is connected to the sensing control node, and the second electrode of the twenty-ninth transistor is connected to the reference signal terminal.

[0075] In some embodiments, the shift register unit further includes: a third voltage stabilizing circuit connected to the voltage stabilizing node, the power signal terminal and the pull-up node of the shift register unit, the third voltage stabilizing circuit being used to provide a signal at the power signal terminal to the voltage stabilizing node under the control of the pull-up node;

[0076] The input circuit of the shift register unit is connected to the voltage stabilization node.

[0077] In some embodiments, the third voltage stabilizing circuit includes a thirtieth transistor and a thirty-first transistor, the gate of the thirtieth transistor is connected to a pull-up node, the first electrode of the thirtieth transistor is connected to a power signal terminal, the second electrode of the thirtieth transistor is connected to the first electrode of a thirty-first transistor, the gate of the thirty-first transistor is connected to the pull-up node, and the second electrode of the thirty-first transistor is connected to the voltage stabilizing node.

[0078] In some embodiments, the input circuit includes a fourth transistor and a fifth transistor and the reset circuit includes a sixth transistor and a seventh transistor, or the input circuit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0079] The second electrode of the fourth transistor, the first electrode of the fifth transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are connected to the voltage stabilization node.

[0080] In some embodiments, the shift register unit further includes at least one of a pull-down circuit, a general reset circuit, and a sensing circuit, and at least one of the pull-down circuit, the general reset circuit, and the sensing circuit is connected to the regulated voltage node.

[0081] In some embodiments, the shift register unit further includes: a fourth voltage stabilizing circuit, the fourth voltage stabilizing circuit connected to the pull-down node, the input signal terminal and the reference signal terminal, for providing the signal of the reference signal terminal to the pull-down node under the control of the input signal terminal.

[0082] In some embodiments, the fourth voltage stabilization circuit includes: a thirty-second transistor, the gate of the thirty-second transistor is connected to the input signal terminal, the first electrode of the thirty-second transistor is connected to the reference signal terminal, and the second electrode of the thirty-second transistor is connected to the pull-down node.

[0083] According to another aspect of the embodiment of the present disclosure, there is further provided a shift register unit, comprising:

[0084] A first input circuit is connected to the first input signal terminal, the pull-up node and the first control signal terminal of the shift register unit, and the first input circuit is used to provide a signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal;

[0085] A second input circuit connected to the second input signal terminal of the shift register unit, the pull-up node and the second control signal terminal, the second input circuit being used to provide a signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal;

[0086] A control circuit connected to the pull-up node and the pull-down node, the power signal terminal and the reference signal terminal of the shift register unit, the control circuit being used to provide a signal of one of the power signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node;

[0087] K output circuits, connected to K clock signal terminals, K output signal terminals and a pull-up node of the shift register unit, wherein a control terminal of the kth output circuit is connected to the pull-up node, a first terminal of the kth output circuit is connected to the kth clock signal terminal of the shift register unit, and a second terminal of the kth output circuit is connected to the kth output signal terminal of the shift register unit, and each output circuit is used to provide a signal at the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit, wherein K is an integer greater than 1, k=1, 2, ..., K;

[0088] A pull-down circuit connected to the pull-down node, the pull-up node, the K output signal terminals and the reference signal terminal, the pull-down circuit being used to provide the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node;

[0089] in,

[0090] In the forward scanning mode, the first control signal terminal is at a first level, and the second control signal terminal is at a second level;

[0091] In the reverse scanning mode, the first control signal terminal is at the second level, and the second control signal terminal is at the first level.

[0092] According to another aspect of an embodiment of the present disclosure, a gate driving circuit is further provided, comprising a plurality of shift register units as described above, wherein the plurality of shift register units are cascade-connected. BRIEF DESCRIPTION OF THE DRAWINGS

[0093] Figure 1A A signal timing diagram of a shift register unit is shown.

[0094] Figure 1B A circuit diagram of a pixel circuit is shown.

[0095] Figure 2 A schematic block diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0096] Figure 3 A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0097] Figure 4A A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0098] Figure 4BA circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0099] Figure 4C A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0100] Figure 4D A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0101] Figure 4E A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0102] Figure 4F A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0103] Figure 5 A signal timing diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0104] Figure 6 FIG. 4 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure.

[0105] Figure 7 A timing diagram of a first control signal and a second control signal according to an embodiment of the present disclosure is shown.

[0106] FIG. 8A to FIG. 8C The figure shows the display effect of the spliced ​​screen.

[0107] Fig. 9 A schematic block diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0108] Fig.10 A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0109] Fig.11A A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0110] Fig. 11B A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0111] Fig.12 A signal timing diagram of a shift register unit in a forward scanning mode according to an embodiment of the present disclosure is shown.

[0112] Fig.13 A signal timing diagram of a shift register unit in a reverse scanning mode according to an embodiment of the present disclosure is shown.

[0113] Fig.14The signal timing diagram of the shift register unit in the display phase and the blanking phase according to the embodiment of the present disclosure is shown.

[0114] Fig.15 A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0115] Fig.16 A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0116] Fig.17 A schematic block diagram of a gate driving circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0117] Although the present disclosure will be fully described with reference to the accompanying drawings containing preferred embodiments of the present disclosure, it should be understood before this description that a person of ordinary skill in the art can modify the disclosure described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the above description is a broad disclosure to a person of ordinary skill in the art, and its content is not intended to limit the exemplary embodiments described in the present disclosure.

[0118] In addition, in the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the disclosed embodiments. However, it is apparent that one or more embodiments may be implemented without these specific details. In other cases, known structures and devices are embodied in a schematic manner to simplify the accompanying drawings.

[0119] In the shift register unit, a plurality of output circuits may share a pull-up node to simplify the circuit structure. However, since the plurality of output circuits share a pull-up node, the potential of the pull-up node will be bootstrapped multiple times in the process of generating multiple outputs of the shift register unit, resulting in different voltages at the control terminals of the output circuits when generating output signals, thereby affecting the display effect.

[0120] Figure 1A A signal timing diagram of a shift register unit is shown. Figure 1B A circuit diagram of a pixel circuit is shown.

[0121] like Figure 1AAs shown, the multiple output circuits of the shift register unit share the pull-up node PU, and each output circuit generates an output signal under the control of the pull-up node PU, so that the shift register unit can generate multiple output signals OUT1, OUT2, OUT3 and OUT4. Since each output circuit shares the pull-up node PU, the multiple output signals OUT1, OUT2, OUT3 and OUT4 will cause the pull-up node PU to be bootstrapped multiple times by the capacitor in the output circuit at different times, resulting in different voltages of the pull-up node when different pulses are output. As shown in Figure 1, the pulse of the output signal OUT1 causes the potential of the pull-up node PU to be raised to VU1, the arrival of the pulse of the output signal OUT2 causes the potential of the pull-up node PU to be further raised from VU1 to VU2, and the arrival of the pulse of the output signal OUT3 causes the potential of the pull-up node to be further raised from VU2 to VU3. Next, each output signal changes from a high level to a low level in turn, so that the voltage of the pull-up node PU falls back in a step-by-step manner, thereby obtaining the PU point signal waveform shown in Figure 1.

[0122] Since the pull-up node PU is directly connected to the gate of the output transistor in each output circuit, the step-by-step change of the voltage of the pull-up node PU causes the output capabilities of the output transistors in different output circuits to be different. Then the rising speed and falling speed of the output signal voltage will be different, that is, the rising delay time and the falling delay time are different, which means that the gate line turn-on waveform for writing grayscale data into the pixel is different.

[0123] As Figure 1B Taking the pixel circuit shown in the figure as an example, Figure 1A The output signal generated by the shift register unit can be used as the gate drive signals Gate1 and Gate2 of the pixel circuit. Figure 1B As shown, the pixel circuit includes transistors T1, T2, T3 and a capacitor Cst. The transistor T3 writes a reference voltage into the source S of the transistor T1 under the control of the gate driving signal Gate2, and the transistor T2 is turned on under the control of the gate driving signal Gate1, thereby writing a data signal into the gate G of the transistor T1. The transistor T1 generates a driving current based on the voltage of the gate G, thereby driving the light emitting element EL to emit light. Figure 1BAlso shown are the parasitic capacitances Cgs_1, Cgs_2, Cgs_3 (hereinafter collectively referred to as Cgs) and Cgd_1, Coled between the nodes. The coupling effects between the capacitances Cgs and Cgs are different, and the voltage loss of grayscale writing is different, which will result in brightness differences between pixel rows, that is, different light and dark horizontal stripes. Taking the gate drive signal Gate1 as an example, due to the influence of the parasitic capacitance Cgs of the transistor T2, in the process of the gate drive signal Gate1 changing from high to low (transistor T2 is turned off), the voltage of the gate G of the transistor T1 will be coupled and pulled down. In other words, the voltage written into the transistor T1 will be reduced by the capacitive coupling effect. The magnitude of the reduction is directly related to the voltage change and change speed of the gate drive signal Gate1. The high and low voltage difference and the falling delay time of the gate drive signal output by the shift register unit are different, and the grayscale loss is different, which will eventually affect the difference in the gate-source voltage Vgs of the transistor T1 in the light-emitting stage and the difference in the driving current generated, resulting in the appearance of horizontal light and dark stripes.

[0124] Therefore, the consistency of the output signals of the shift register unit in aspects such as rise and fall time, high level and low level amplitude etc. becomes increasingly important to minimize the difference of gate drive signals of pixel units in each row, thereby improving display uniformity.

[0125] The embodiment of the present disclosure proposes a shift register unit, which can reduce the differences between output signals caused by multiple self-bootstrapping of the pull-up node by setting an isolation circuit between the output circuit and the pull-up node, thereby facilitating improving display uniformity.

[0126] Figure 2 A schematic block diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0127] like Figure 2 As shown, the shift register unit 100 includes an input circuit 110, a control circuit 120, K output circuits, K' isolation circuits and a pull-down circuit 150. K is an integer greater than 1, k = 1, 2, ..., K. K' is a positive integer, and K' ≤ K. Figure 2 Two output circuits 130_1 and 130_2 and two isolations 140_1 and 140_2 are shown, that is, K=K'=2, however, this is only for example, the embodiments of the present disclosure are not limited thereto, K and K' can be set as needed, as long as K is an integer greater than 1, K' is a positive integer, and K'≤K.

[0128] The input circuit 110 is connected to the input signal terminal IN of the shift register and the pull-up node PU, and is used to input the signal of the input signal terminal IN to the pull-up node PU.

[0129] The control circuit 120 is connected to the pull-up node PU and the pull-down node PD of the shift register unit, the power signal terminal GVDD and the reference signal terminal VGL. The control circuit 120 is used to provide a signal from one of the power signal terminal GVDD and the reference signal terminal VGL to the pull-down node PD under the control of the pull-up node PU.

[0130] K output circuits 130_1 and 130_2 are connected to K clock signal terminals CLK1, CLK2, K output signal terminals OUT1, OUT2 and a pull-up node PU of the shift register unit. The first terminal of the kth output circuit is connected to the kth clock signal terminal of the shift register unit, and the second terminal of the kth signal output circuit is connected to the kth output signal terminal of the shift register unit. For example, Figure 2 As shown, the first end of the output circuit 130_1 (first output circuit) is connected to the clock signal terminal CLK1 (first clock signal terminal), and the second end of the output circuit 130_1 is connected to the output signal terminal OUT1 (first output signal terminal); the first end of the output circuit 130_2 (second output circuit) is connected to the clock signal terminal CLK2 (second clock signal terminal), and the second end of the output circuit 130_2 is connected to the output signal terminal OUT2 (second output signal terminal). The control end of the output circuit 130_1 can be connected to the isolation circuit 140_1 (first isolation circuit), and the control end of the output circuit 130_2 can be connected to the isolation circuit 140_2 (second isolation circuit). Each output circuit can provide the signal of the first end of the output circuit to the second end of the output circuit under the control of the control end of the output circuit.

[0131] K' isolation circuits are respectively connected between the control terminals of K' output circuits among the K output circuits and the pull-up node PU. Figure 2 In the example, K = K', and an isolation circuit is provided between each output circuit and the pull-up node. Figure 2 As shown, the isolation circuit 140_1 is connected between the output circuit 130_1 and the pull-up node PU, and the isolation circuit 140_2 is connected between the output circuit 130_2 and the pull-up node PU. The first end of each isolation circuit is connected to the pull-up node PU, and the second end of the isolation circuit is connected to the control end of the corresponding output circuit. The control end of the isolation circuit 140 is connected to the control signal end. For example, Figure 2As shown, the first ends of the isolation circuits 140_1 and 140_2 are both connected to the pull-up node PU, the second end of the isolation circuit 140_1 is connected to the control end PU1 of the output circuit 130_1, and the second end of the isolation circuit 140_2 is connected to the control end PU2 of the output circuit 130_2. The control ends of the isolation circuits 140_1 and 140_2 are both connected to the control signal end CN. Each isolation circuit can connect or disconnect the first end of the isolation circuit with the second end under the control of the voltage between the control end and the second end of the isolation circuit. Taking the isolation circuit 140_1 as an example, when the voltage between the control end and the second end of the isolation circuit 140_1 (i.e., the voltage between the control signal end CN and the control end PU1 of the output circuit 130_1) is within a preset range, the isolation circuit 140_1 electrically connects the pull-up node PU with the control end PU1 of the output circuit 130_1, and when the voltage exceeds the preset range, the isolation circuit 140_1 disconnects the pull-up node PU from the control end PU1 of the output circuit 130_1.

[0132] The pull-down circuit 150 is connected to the pull-down node PD, the pull-up node PU, K output signal terminals OUT and the reference signal terminal VGL. The pull-down subcircuit is used to provide the signal of the reference signal terminal VGL to the pull-up node PU and the K output signal terminals OUT1 and OUT2 under the control of the pull-down node PD.

[0133] In the embodiment of the present disclosure, an isolation circuit is provided between the output circuit and the pull-up node, and the isolation circuit can control the connection or disconnection between the control end of the output circuit and the pull-up node by the voltage between the control end of the output circuit and the pull-up node. In this way, the voltage bootstrap of one output circuit when outputting a signal will not affect the signal output of other output circuits. For example, when the output signal generated by the output circuit 1301 at the output end OUT1 causes the potential of the control end PU1 to be raised, the raised potential of the control end PU1 can cause the isolation circuit 140_1 to disconnect the output circuit 130_1 from the pull-up node PU, thereby ensuring that the voltage bootstrap of the output circuit 130_1 will not affect the potential of the pull-up node PU, and thus will not affect the subsequent signal output of the output circuit 130_2. In addition, the raised potential of the control end PU1 is also conducive to the stability of the output signal of the output circuit 130_1. In this way, the differences between the output signals caused by the multiple bootstraps of the pull-up node are reduced, which is conducive to improving the display uniformity.

[0134] Figure 3 A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0135] like Figure 3 As shown, the shift register unit 300 includes an input circuit 310, a control circuit 320, K output circuits ( Figure 35 output circuits 330_CR, 330_1, 330_2, 330_3 and 330_4), K' isolation circuits ( Figure 3 5 isolation circuits 340_CR, 340_1, 340_2, 340_3 and 340_4) and a pull-down circuit 150 are shown. The description of the input circuit, the control circuit, the output circuit, the isolation circuit and the pull-down circuit in the above embodiment is also applicable to this embodiment.

[0136] The input circuit 310 may include a fourth transistor M4, a gate of the fourth transistor M1 connected to the input signal terminal IN, a first electrode of the fourth transistor M4 connected to the power signal terminal GVDD1, and a second electrode of the fourth transistor connected to the pull-up node PU. In some embodiments, the gate and the first electrode of the fourth transistor M1 may both be connected to the input signal terminal IN.

[0137] The control circuit includes a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14 and a fifteenth transistor M15. The gate and the first electrode of the twelfth transistor M12 are connected to the power signal terminal, and the second electrode of the twelfth transistor M12 is connected to the gate of the thirteenth transistor M13. The first electrode of the thirteenth transistor M13 is connected to the power signal terminal, and the second electrode of the thirteenth transistor M13 is connected to the pull-down node PD. The gate of the fourteenth transistor M14 is connected to the pull-up node PU, the first electrode of the fourteenth transistor M14 is connected to the gate of the thirteenth transistor M13, and the second electrode of the fourteenth transistor M14 is connected to the reference signal terminal. The gate of the fifteenth transistor M15 is connected to the pull-up node PU, the first electrode of the fifteenth transistor M15 is connected to the pull-down node PD, and the second electrode of the fifteenth transistor M15 is connected to the reference signal terminal VGL2.

[0138] Each output circuit 330_CR, 330_1, 330_2, 330_3, and 330_4 may include a third transistor and a first capacitor. For example, the output circuit 330_CR includes a third transistor M3_CR and a first capacitor C1_CR, the output circuit 330_1 includes a third transistor M3_1 and a first capacitor C1_1, the output circuit 330_2 includes a third transistor M3_2 and a first capacitor C1_2, the output circuit 330_3 includes a third transistor M3_3 and a first capacitor C1_3, and the output circuit 330_4 includes a third transistor M3_4 and a first capacitor C1_4.

[0139] In each output circuit, the gate of the third transistor serves as the control terminal of the output circuit, the first electrode of the third transistor serves as the first terminal of the output circuit, the second electrode of the third transistor serves as the second terminal of the output circuit, the first electrode of the first capacitor is connected to the gate of the third transistor, and the second electrode of the first capacitor is connected to the second electrode of the third transistor. Taking the output circuit 330_1 as an example, the gate of the third transistor M3_1 serves as the control terminal of the third transistor M3_1, the first electrode of the third transistor M3_1 serves as the first terminal of the third transistor M3_1, and the second electrode of the third transistor M3_1 serves as the second terminal of the third transistor M3_1; the first electrode of the first capacitor C1_1 is connected to the gate of the third transistor M3_1, and the second electrode of the first capacitor C1_1 is connected to the second electrode of the third transistor M3_1. The same is true for other output circuits, which will not be repeated here.

[0140] In some embodiments, the K output circuits may include a cascade output circuit and K' signal output circuits. Figure 3 In the embodiment, the output circuit 330_CR may be a cascade output circuit, and the output circuits 330_1, 330_2, 330_3 and 330_4 may be signal output circuits. The output signal terminal CR connected to the cascade output circuit 330CR is used to connect to other shift register units, and the output signal terminals OUT1 to OUT4 connected to the signal output circuits 330_1, 330_2, 330_3 and 330_4 are used to provide output signals.

[0141] The pull-down circuit may include a first pull-down circuit 3501 and K second pull-down circuits, 3502_CR, 3502_1, 3502_2, 3502_3, and 3502_4 (hereinafter collectively referred to as the second pull-down circuit 3502).

[0142] The first pull-down circuit 3501 is connected to the pull-down node PD, the pull-up node PU and the reference signal terminal VGL2, and the first pull-down sub-circuit 3501 is used to provide the signal of the reference signal terminal VGL2 to the pull-up node PU under the control of the pull-down node PD. The first pull-down circuit 3501 may include a seventeenth transistor M17, a gate of the seventeenth transistor M17 is connected to the pull-down node PD, a first electrode of the seventeenth transistor M17 is connected to the reference signal terminal VGL2, and a second electrode of the seventeenth transistor M17 is connected to the pull-up node PU.

[0143] K second pull-down circuits 3502_CR, 3502_1, 3502_2, 3502_3 and 3502_4 are respectively connected to K output signal terminals CR, OUT1, OUT2, OUT3 and OUT4, wherein each second pull-down circuit is connected to a pull-down node PD, a reference signal terminal VGL1 and a corresponding output signal terminal. For example, the second pull-down circuit 3502_CR is connected to the output signal terminal CR, the second pull-down circuit 3502_1 is connected to the output signal terminal OUT1, the second pull-down circuit 3502_2 is connected to the output signal terminal OUT2, and so on. Each second pull-down circuit can provide a signal of the reference signal terminal VGL1 to the corresponding output signal terminal under the control of the pull-down node PD. The second pull-down circuit may include a nineteenth transistor, the gate of the nineteenth transistor is connected to the pull-down node, the first electrode of the nineteenth transistor is connected to the reference signal terminal, and the second electrode of the nineteenth transistor is connected to the corresponding output signal terminal. For example, as Figure 3 As shown, the second pull-down circuit 3502_CR includes a nineteenth transistor M19_CR, the second pull-down circuit 3502_1 includes a nineteenth transistor M19_1, the second pull-down circuit 3502_2 includes a nineteenth transistor M19_2, and so on. In the second pull-down circuit 3502vCR, the gate of the nineteenth transistor M19_CR is connected to the pull-down node PD, the first electrode of the nineteenth transistor M19_CR is connected to the reference signal terminal VGL2, and the second electrode of the nineteenth transistor M19_CR is connected to the output signal terminal CR. In the second pull-down circuit 3502_1, the gate of the nineteenth transistor M19_1 is connected to the pull-down node PD, the first electrode of the nineteenth transistor M19_1 is connected to the reference signal terminal VGL1, and the second end of the nineteenth transistor M19_1 is connected to the output signal terminal OUT2. The nineteenth transistors in the second pull-down circuit 3502_2 to the second pull-down circuit 3502_4 are connected in a similar manner, which will not be repeated here.

[0144] The isolation circuits 340_CR, 340_1, 340_2, 340_3 and 340_4 may each include a first transistor. For example, the isolation circuit 340_CR includes a first transistor M1_CR, the isolation circuit 340_1 includes a first transistor M1_1, the isolation circuit 340_2 includes a first transistor M1_2, the isolation circuit 340_3 includes a first transistor M1_3, and the isolation circuit 340_4 includes a first transistor M1_4. Taking the isolation circuit 340_CR as an example, the gate of the first transistor M1_CR is connected to the control signal terminal CN, the first electrode of the first transistor M1_CR is connected to the pull-up node PU as the first end of the isolation circuit, and the second electrode of the first transistor M1_CR is connected to the control end of the output circuit 330_CR (i.e., the gate of the transistor M3_CR) as the second end of the isolation circuit. Other isolation circuits are connected in a similar manner and will not be repeated here.

[0145] In some embodiments, the shift register unit may further include a reset circuit 360. The reset circuit 360 is connected to the reset signal terminal RST, the pull-up node PU and the reference signal terminal VGL2 of the shift register unit, and the reset circuit 360 is used to provide the signal of the reference signal terminal VGL2 to the pull-up node PU under the control of the reset signal terminal RST. Figure 3 As shown, the reset circuit 360 may include a sixth transistor M6, a gate of the sixth transistor M6 is connected to the reset signal terminal RST, a first electrode of the sixth transistor M6 is connected to the reference signal terminal VGL2, and a second electrode of the sixth transistor M6 is connected to the pull-up node PU.

[0146] In the above embodiment, two groups of power signal terminals and reference signal terminals are shown, namely, power signal terminal GVDD1 and reference signal terminal VGL1 and power signal terminal GVDD2 and reference signal terminal VGL2, wherein the input circuit is connected to GVDD1, the second pull-down circuit is connected to the reference signal terminal VGL1, the first pull-down circuit and the reset circuit are connected to the reference signal terminal VGL2, and the control circuit is connected to the power signal terminal GVDD2 and the reference signal terminal VGL2. In this way, the input and output of the signal use one group of power signal terminals and reference signal terminals, while the voltage control of the pull-down node and the pull-up node uses another group of power signal terminals and reference signal terminals, which is more conducive to the stability of the output signal. However, the embodiments of the present disclosure are not limited to this, and the number of power signal terminals and reference signal terminals can be set as needed, for example, one group of power signal terminals and reference signal terminals is set, or three or more groups of power signal terminals and reference signal terminals are set, and each circuit in the shift register unit can be connected to the corresponding power signal terminal and reference signal terminal as needed.

[0147] During operation, the control signal terminal CN can be a constant high level, so that the transistors M1_CR, M1_1, M1_2, M1_3, and M1_4 of each isolation circuit are all in a conducting state. In the pre-charging stage, the input signal terminal IN is at a high level, and the transistor M4 in the input circuit is turned on, thereby charging the pull-up node PU and the control terminals PUC, PU1, PU2, PU3, and PU4 of each output circuit. At this time, the transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 in the output circuit are all turned on. In the output stage, the high-level pulse signals of the clock signal terminals CLKCR, CLK1, CLK2, CLK3, and CLK4 arrive in sequence, and the turned-on transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 generate high-level output signals at the output signal terminals CR, OUT1, OUT2, OUT3, and OUT4 in turn. In this process, it is assumed that when the high level of the clock signal terminal CLK1 arrives, the potential of the control terminal PU1 is increased due to the bootstrap effect of the capacitor C1_1, which makes the potential of PU1 greater than the potential of the control signal terminal CN, and the difference between the two is greater than the threshold voltage Vth of the transistor M1_1, thereby turning off the transistor M1_1. On the one hand, the turning off of the transistor M1_1 makes the voltage rise of the control terminal PU1 not affect the signal output of other output circuits; on the other hand, the voltage rise of the control terminal PU1 makes the transistor M3_1 work in the linear region, that is, the gate-source voltage of the transistor M3_1 is much greater than the threshold voltage of the transistor M3_1, so as to generate a stable output signal. Due to the existence of the isolation circuit, the voltage bootstrap of the control terminal of each output circuit does not affect each other, and the output capacity of each output circuit is consistent, thereby improving the waveform consistency of the output signal of each output circuit, which is conducive to improving the display uniformity.

[0148] Figure 4A A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown. Figure 4A The shift register unit and Figure 3 Similarly, for ease of explanation, the following will mainly describe the differences in detail.

[0149] like Figure 4AAs shown, the shift register unit includes an input circuit 410, a control circuit 420, an output circuit 430_CR, 430_1, 430_2, 430_3, 430_4 (hereinafter collectively referred to as the output circuit 430), an isolation circuit 440_CR, 440_1, 440_2, 440_3, 440_4 (hereinafter collectively referred to as the isolation circuit 440) and a pull-down circuit (including a first pull-down circuit 4501 and a second pull-down circuit 4502_CR, 4502_1, 4502_2, 4502_3 and 4502_4). The description of the output circuit 430 and the isolation circuit 440 can refer to the output circuit 330 and the isolation circuit 340 of the above embodiment, which will not be repeated here.

[0150] and Figure 3 The difference is that the shift register unit may further include a third voltage stabilizing circuit 490. The third voltage stabilizing circuit 490 is connected to the voltage stabilizing node Q, the power signal terminal GVDD1 and the pull-up node PU of the shift register unit. The third voltage stabilizing circuit 490 may provide the signal of the power signal terminal GVDD1 to the voltage stabilizing node Q under the control of the pull-up node PU. Figure 4A As shown, the third voltage stabilizing circuit includes a thirtieth transistor and a thirty-first transistor, the gate of the thirtieth transistor M30 is connected to the pull-up node PU, the first electrode of the thirtieth transistor M30 is connected to the power signal terminal GVDD1, the second electrode of the thirtieth transistor M30 is connected to the first electrode of the thirty-first transistor M31, the gate of the thirty-first transistor M31 is connected to the pull-up node PU, the first electrode of the thirty-first transistor M31 is connected to the second electrode of the thirtieth transistor M30, and the second electrode of the thirty-first transistor M31 is connected to the voltage stabilizing node.

[0151] In some embodiments, the shift register unit may further include a total reset circuit 470. The total reset circuit 470 is connected to the total reset signal terminal TRST, the pull-up node PU and the reference signal terminal VGL2. The total reset circuit 470 may provide the signal of the reference signal terminal VGL2 to the pull-up node PU under the control of the total reset signal terminal TRST. The total reset circuit 470 may include a twentieth transistor M20, the gate of the twentieth transistor M20 is connected to the total reset signal terminal TRST, the first electrode of the twentieth transistor M20 is connected to the reference signal terminal VGL2, and the second electrode of the twentieth transistor M20 is connected to the pull-up node PU. In some embodiments, the total reset circuit 470 may further include a twenty-first transistor M21, the first electrode of the twentieth transistor M20 is connected to the reference signal terminal VGL2 through the twenty-first transistor M21, wherein the gate of the twenty-first transistor M21 is connected to the total reset signal terminal TRST, the first electrode of the twenty-first transistor M21 is connected to the reference signal terminal VGL2, and the second electrode of the twenty-first transistor M21 is connected to the first electrode of the twentieth transistor M20.

[0152] In some embodiments, the shift register unit may further include a sensing circuit, for example, the sensing circuit may include a selection subcircuit 4801 and a trigger subcircuit 4802. The sensing circuit is connected to the sensing selection signal terminal OE, the sensing trigger signal terminal CLKA, the sensing control node H, the input signal terminal IN and the pull-up node PU of the shift register unit, and the sensing circuit may write the signal of the input signal terminal IN to the sensing control node H under the control of the sensing selection signal terminal OE in the display phase, and provide the signal of the sensing control node H to the pull-up node PU under the control of the sensing trigger signal terminal CLKA in the blanking phase.

[0153] like Figure 4A As shown, the selection sub-circuit 4801 is connected to the sensing selection signal terminal OE, the sensing control node H and the input signal terminal IN. The selection sub-circuit 4801 is used to write the signal of the input signal terminal IN into the sensing control node H under the control of the sensing selection signal terminal OE in the display stage. The selection sub-circuit may include a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24 and a second capacitor C2. The gate of the twenty-second transistor M22 is connected to the sensing selection signal terminal OE, the first electrode of the twenty-second transistor M22 is connected to the input signal terminal IN, the second electrode of the twenty-second transistor M22 is connected to the first electrode of the twenty-third transistor M23, the first electrode of the twenty-third transistor M23 is connected to the sensing selection signal terminal OE, the second electrode of the twenty-third transistor M23 is connected to the sensing control node H, the gate of the twenty-fourth transistor M24 is connected to the sensing control node H, the first electrode of the twenty-fourth transistor M24 is connected to the second electrode of the twenty-second transistor M22, the second electrode of the twenty-fourth transistor M24 is connected to the power signal terminal GVDD1, the first electrode of the second capacitor C2 is connected to the power signal terminal GVDD1, and the second electrode of the second capacitor C2 is connected to the gate of the twenty-fourth transistor M24.

[0154] The trigger subcircuit 4802 is connected to the sensing trigger signal terminal CLKA, the sensing control node H and the pull-up node PU, and the trigger subcircuit is used to provide the signal of the sensing control node H to the pull-up node PU under the control of the sensing trigger signal terminal CLKA in the blanking phase. The trigger subcircuit 4802 may include a twenty-fifth transistor M25 and a twenty-sixth transistor M26, the gate of the twenty-fifth transistor M25 is connected to the sensing control node H, the first electrode of the twenty-fifth transistor M25 is connected to the power signal terminal, the second electrode of the twenty-fifth transistor M25 is connected to the first electrode of the twenty-sixth transistor M26, the gate of the twenty-sixth transistor M26 is connected to the sensing trigger signal terminal CLKA, and the second electrode of the twenty-sixth transistor M26 is connected to the pull-up node PU. In some embodiments, the trigger subcircuit 4802 may also include a twenty-seventh transistor M27, the second electrode of the twenty-sixth transistor M26 is connected to the pull-up node PU through the twenty-seventh transistor M27, the gate of the twenty-seventh transistor M27 is connected to the sensing trigger signal terminal CLKA, the first electrode of the twenty-seventh transistor M27 is connected to the second electrode of the twenty-sixth transistor M26, and the second electrode of the twenty-seventh transistor M27 is connected to the pull-up node PU.

[0155] In some embodiments, the sensing circuit may further include a voltage stabilizing subcircuit 4803. The voltage stabilizing subcircuit 4803 is connected to the sensing control node H, the sensing trigger signal terminal CLKA, and the reference signal terminal VGL2. The voltage stabilizing subcircuit 4803 may provide the signal of the reference signal terminal VGL2 to the pull-down node under the control of the sensing control node H and the sensing trigger signal terminal CLKA. The voltage stabilizing subcircuit 4803 may include a twenty-eighth transistor M28 and a twenty-ninth transistor M29, the gate of the twenty-eighth transistor M28 is connected to the sensing trigger signal terminal CLKA, the first electrode of the twenty-eighth transistor M28 is connected to the pull-up node PU, the second electrode of the twenty-eighth transistor M28 is connected to the first electrode of the twenty-ninth transistor M29, the gate of the twenty-ninth transistor M29 is connected to the sensing control node H, and the second electrode of the twenty-ninth transistor M29 is connected to the reference signal terminal VGL2.

[0156] In some embodiments, at least one of an input circuit, a reset circuit, a pull-down circuit, a master reset circuit, and a sensing circuit may be connected to a regulated voltage node.

[0157] For example, in addition to the fourth transistor M4, the input circuit 410 may further include a fifth transistor M5. The gate of the fourth transistor M4 is connected to the input signal terminal IN, the first electrode of the fourth transistor M4 is connected to the power signal terminal GVDD1, and the second electrode of the fourth transistor M4 is connected to the pull-up node PU through the fifth transistor M5. The gate of the fifth transistor M5 is connected to the input signal terminal IN, the first electrode of the fifth transistor M5 is connected to the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is connected to the pull-up node PU. The second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5 can be connected to the voltage stabilization node Q.

[0158] For example, the reset circuit may include a seventh transistor M7 in addition to the sixth transistor M6. The gate of the sixth transistor M6 is connected to the reset signal terminal RST, the first electrode of the sixth transistor M6 is connected to the reference signal terminal VGL2, the second electrode of the sixth transistor M6 is connected to the pull-up node PU through the seventh transistor M7, the gate of the seventh transistor M7 is connected to the reset signal terminal RST, the first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7 is connected to the pull-up node PU. The first electrode of the sixth transistor M6 and the first electrode of the seventh transistor M7 may be connected to the voltage stabilization node Q.

[0159] For example, the first pull-down circuit 4501 in the pull-down circuit may also include an eighteenth transistor M18 in addition to the seventeenth transistor M17, the first electrode of the seventeenth transistor M17 is connected to the reference signal terminal VGL2 through the eighteenth transistor M18, the gate of the eighteenth transistor M18 is connected to the pull-down node, the first electrode of the eighteenth transistor M18 is connected to the reference signal terminal VGL2, and the second electrode of the eighteenth transistor M18 is connected to the first electrode of the seventeenth transistor M17.

[0160] For example, the total reset circuit may further include a twenty-first transistor M21 in addition to the twentieth transistor M20 , and a first electrode of the twentieth transistor M20 and a second electrode of the twenty-first transistor M21 are connected to the voltage stabilization node Q.

[0161] For example, the trigger sub-circuit 4802 in the sensing circuit may include a 27th transistor M27 in addition to the 25th transistor M25 and the 26th transistor M26. The second electrode of the 26th transistor M26 and the first electrode of the 27th transistor M27 may be connected to the voltage stabilization node Q.

[0162] In some embodiments, Figure 3The difference is that the control circuit 420 may include a sixteenth transistor M16 in addition to the twelfth transistor M12, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15. The second electrode of the twelfth transistor M12 may be connected to the gate of the thirteenth transistor M13 through the sixteenth transistor M16, wherein the gate of the sixteenth transistor M16 is connected to the power signal terminal GVDD2, the first electrode of the sixteenth transistor M16 is connected to the second electrode of the twelfth transistor M12, and the second electrode of the sixteenth transistor M16 is connected to the gate of the thirteenth transistor M13.

[0163] In some embodiments, the shift register unit may further include a fourth voltage stabilizing circuit 491, the fourth voltage stabilizing circuit 491 is connected to the pull-down node PD, the input signal terminal IN and the reference signal terminal VGL2, and is used to provide the signal of the reference signal terminal VGL2 to the pull-down node PD under the control of the input signal terminal IN. The fourth voltage stabilizing circuit 491 may include a thirty-second transistor M32, the gate of the thirty-second transistor M32 is connected to the input signal terminal IN, the first electrode of the thirty-second transistor M32 is connected to the reference signal terminal VGL2, and the second electrode of the thirty-second transistor M32 is connected to the pull-down node PD.

[0164] Figure 4B A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown. Figure 4B The shift register unit and Figure 4A Similar, the difference lies at least in the structure of the isolation circuit. For the convenience of description, the following will mainly describe the difference in detail.

[0165] like Figure 4B As shown, the shift register unit also includes a plurality of isolation circuits 441_CR, 441_1, 441_2, 441_3, 441_4 (hereinafter collectively referred to as isolation circuit 441). Figure 3 The difference is that the isolation circuit includes a second transistor in addition to the first transistor. For example, the isolation circuit 441_CR includes a first transistor M1_CR and a second transistor M2_CR, and the isolation circuit 441_1 includes a first transistor M1_1 and a second transistor M2_1, and so on. Taking the isolation circuit 441_1 as an example, the gate of the first transistor M1_1 is connected to the first control signal terminal CN, and the gate of the second transistor M2_1 is connected to the second control signal terminal CNB. The first electrode of the first transistor M1_1 is connected to the first electrode of the second transistor M2_1, thereby connecting to the pull-up node. The second electrode of the first transistor M1_1 is connected to the second electrode of the second transistor M2_1, thereby connecting to the control terminal PU1 of the corresponding output circuit 430_1. The first transistor and the second transistor in other isolation circuits are connected in a similar manner, which will not be repeated here.

[0166] The first control signal terminal CN and the second control signal terminal CNB can be one at the first level and the other at the second level. For example, in the first period, the first control signal terminal CN is at a high level and the second control signal terminal CNB is at a low level; in the second period, the first control signal terminal CN is at a low level and the second control signal terminal CNB is at a high level. By setting the first transistor and the second transistor in the isolation circuit and setting the levels of the first control signal terminal CN and the second control signal terminal CNB alternately, the first transistor and the second transistor in each isolation circuit can work alternately, thereby alleviating the characteristic deterioration caused by the bias stress of the isolation transistor and extending the service life of the circuit.

[0167] In the above embodiment, K=K' is used as an example for schematic illustration, that is, a corresponding isolation circuit is set in each output circuit and the pull-up node. However, the embodiments of the present disclosure are not limited to this. K' can be smaller than K, that is, the isolation circuit can be omitted for one or more output circuits.

[0168] For example, Figure 4C As shown, Figure 4A Compared with the embodiment of the present invention, the isolation circuit 440_CR of the output circuit 430_CR acting as the cascade output circuit is omitted, and the control terminal PUC of the output circuit 430_CR is connected to the pull-up node PU; corresponding isolation circuits are provided between the output circuits 430_1 to 430_4 acting as signal output circuits and the pull-up nodes. Corresponding isolation circuits are provided between the other output circuits 430_1, 430_2, 430_3 and 430_4 and the pull-up node PU. Since the voltage bootstraps of the control terminals of the output circuits 430_1, 430_2, 430_3 and 430_4 do not affect each other, and do not affect the pull-up node PU, even if the control terminal of the output circuit 430_CR is connected to the pull-up node PU, isolation between all output circuits can be achieved, which is conducive to simplifying the circuit structure.

[0169] For example, Figure 4D As shown, Figure 4AIn comparison, the isolation circuit 440_1 of the output circuit 430_1, which is one of the multiple signal output circuits, is omitted, and the control terminal PU1 of the output circuit 430_1 is connected to the pull-up node PU; corresponding isolation circuits are provided between the other output circuits 430_CR, 430_2, 430_3 and 430_4 and the pull-up node PU. Although the above is illustrated by taking the omission of one isolation circuit as an example, the embodiments of the present disclosure are not limited to this, and two or more isolation circuits may be omitted as needed. For example, the isolation circuits may be omitted for the output circuits 430_1 and 430_4, and corresponding isolation circuits may be provided between the output circuits 430_CR, 430_2, 430_3 and the pull-up node PU. In this way, the number of bootstrap times of the pull-up node PU point can be reduced. For example, in combination with Figure 1A In the timing diagram, when the high level pulse of the output signal terminal OUT1 raises the potential of the pull-up node PU to VU1, the high level pulses of the output signal terminals OUT2 and OUT3 do not affect the potential of the pull-up node PU, and finally when the high level pulse of the output signal terminal OUT4 arrives, the output signal terminal OUT1 has fallen back to a low level, so the pull-up node PU remains at VU1. In this way, the pull-up node PU is only raised once.

[0170] The omission of the isolation circuit also applies to the case of dual isolation transistors. Figure 4B The shift register unit can also omit the isolation circuit 441_CR of the cascade output circuit 430_CR, and obtain the following Figure 4E or omitting the isolation circuit 441_1 of the signal output circuit 430_1, and obtaining Figure 4F The structure shown will not be described in detail here.

[0171] The embodiment of the present disclosure proposes a control method of a shift register unit, which is applicable to the shift register unit of any of the above embodiments. In the input period, the input circuit inputs the signal of the input signal end to the pull-up node, and the control circuit provides the signal of the reference signal end to the pull-down node under the control of the pull-up node. In the output period, each of the K output circuits provides the signal of the first end of the output circuit to the second end of the output circuit under the control of the control end of the output circuit, thereby generating an output signal at the K output signal ends based on the signals of the K clock signal ends. In the reset period, the control circuit provides the signal of the power signal end to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal of the reference signal end to the pull-up node and the K output signal ends under the control of the pull-down node. In the above process, before the output circuit connected to the k'th isolation circuit generates an output signal, the signal of the control signal end connects the first control end and the second control end of the k'th isolation circuit. In response to the output circuit connected to the k'th isolation circuit generating an output signal, the potential of the control end of the k'th isolation circuit disconnects the first end and the second end of the k'th isolation circuit, where k'=1, 2, ..., K'.

[0172] Figure 5 FIG. 1 shows a signal timing diagram of a shift register unit according to an embodiment of the present disclosure. The timing diagram is applicable to the shift register unit of any of the above embodiments. Figure 4A Take the shift register unit as an example. Figure 5 The signal timing is described in the following figure.

[0173] In the input period (corresponding to the period P1 to P3), the input signal terminal IN is at a high level, and the transistors M4 and M5 are turned on, thereby providing the high level of the power signal terminal GVDD1 to the pull-up node PU. The control signal terminal CN is at a constant high level, and the transistors M1_CR, M1_1, M1_2, M1_3 and M1_4 (hereinafter collectively referred to as transistors M1) in each isolation circuit are all turned on, so that the control terminals PUC, PU1, PU2, PU3 and PU4 of each output circuit are all at a high level, and the transistors M3_CR, M3_1, M3_2, M3_3 and M3_4 (hereinafter collectively referred to as transistors M3) in the output circuit are all turned on.

[0174] In the output period (corresponding to period P4 to P16), the high-level pulses of the clock signals of each clock signal terminal CLK1, CLK2, CLK3, CLK4, and CLKCR arrive in sequence, and the turned-on transistor M3 provides the clock signal of the corresponding clock signal terminal to the output signal terminals OUT1, OUT2, OUT3, OUT4, and CR.

[0175] In the reset period (corresponding to the period P17 to P19), the reset signal terminal RST is at a high level, and the transistors M7 and M8 are turned on, thereby providing the low level of the reference signal terminal VGL2 to the pull-up node PU, thereby resetting the pull-up node PU to a low level. The low level of the pull-up node PU also turns off the transistors M14 and M15, so that the transistors M12, M13 and M16 provide the high level of the power signal terminal GVDD2 to the pull-up node PD, and the high level of the pull-up node PD turns on the transistors M19_1, M19_2, M19_3, M19_4, and M19_CR, thereby maintaining the output signal terminals OUT1, OUT2, OUT3, OUT4, and CR at a low level.

[0176] In the above process, the control signal terminal CN is at a constant high level, and the transistors M1 in each isolation circuit are all in the on state before the output signal is generated. When an output signal terminal generates a high-level output signal, for example, in period P5, the output signal terminal OUT1 generates a high-level output signal, and the bootstrap effect of the capacitor C1_1 causes the potential of the gate of the transistor M3_1 (i.e., the control terminal PU1 of the output circuit 430_1) to be further raised from GVDD1 to VPU, as shown in FIG. Figure 4A As shown, this makes the potential of PU1 higher than the potential of the control signal terminal CN and the difference between the two is greater than the threshold voltage of the transistor M1_1, so that the transistor M1_1 is turned off. The turning off of the transistor M1_1 disconnects the control terminal PU1 of the output circuit 430_1 from the pull-up node PU, thereby preventing the potential of the pull-up node PU from being affected by the control terminal PU1. Figure 4AAs shown, the potential of the pull-up node PU remains at GVDD1. Similarly, when the output signal terminal OUT2 generates a high-level output signal in the next period P6, the bootstrap effect of the capacitor C1_2 raises the potential of the control terminal PU2, and the raised potential of the control terminal PU2 turns off the transistor M1_2, so that the potential of the pull-up node PU remains unchanged. By analogy, the presence of the transistor M1 makes the voltage rise of the control terminal of each output circuit 430_2, 430_3, 430_4 and 430_CR independent of each other, ensuring that the gate-source voltage Vgs of the transistor M3 in each output circuit is>>threshold voltage Vth, that is, in the linear region, and the output capacity is consistent, the load is consistent, so that an output signal with a consistent waveform is generated at each output signal terminal. In some embodiments, each signal output circuit can be configured to have exactly the same structure, for example, transistors M3_1, M3_2, M3_3, and M3_4 are of the same size, drive the same load, and capacitors C1_1, C1_2, C1_3, and C1_4 are the same, so that the voltage after bootstrapping is the same as VPU, ensuring that the driving capabilities of each signal output circuit are the same and the driving waveforms are the same (for example, the rising delay time, the negative values ​​of the high and low voltages, and the falling delay time are the same). In some embodiments, the structure of the cascade output circuit can be different from the signal output circuit, for example, the parameters of the transistor M3_CR can be different from the transistors M3_1, M3_2, M3_3, and M3_4 in the signal output circuit, and the capacitor C3_CR can also be different from C3_1, C3_2, C3_3, and C3_4, so the bootstrap voltage VPUC of the control terminal PUC can be different from the bootstrap voltage VPU of the control terminals PU1 to PU4.

[0177] By comparing with the signal timing of FIG. 1 , it can be seen that the embodiment of the present disclosure avoids the step-type voltage conversion caused by multiple self-bootstrapping of the pull-up node PU by setting an isolation circuit, thereby facilitating stable signal output.

[0178] Figure 6 FIG. 1 shows a signal timing diagram of a shift register unit according to another embodiment of the present disclosure. The signal timing diagram can be applied to Figure 4B The shift register unit. Figure 6 The signal timing diagram and Figure 5 Similarly, the difference is that the control signal terminal includes a first control signal terminal CN and a second control terminal CNB. The first control signal terminal CN and the second control terminal CNB can be alternately high level and low level. Figure 7 As shown, in the first time period, the first control terminal CN is at the first level (for example, the high level of the power signal terminal GVDD1), and the second control terminal CNB is at the second level (for example, the low level of the reference signal terminal VGL2); then in the second time period, the first control signal terminal CN is at the second level, and the second control signal terminal CNB is at the first level, and so on.

[0179] When the first control signal terminal CN is at a high level and the second control signal terminal CNB is at a low level, the transistor M1 in each isolation circuit works and the transistor M2 does not work; conversely, when the first control signal terminal CN is at a low level and the second control signal terminal CNB is at a high level, the transistor M2 in each isolation circuit works and the transistor M1 does not work. In this way, the transistor M1 and the transistor M2 in each isolation circuit can work alternately, thereby alleviating the characteristic deterioration caused by the bias stress of the transistor in the isolation circuit and extending the service life of the circuit.

[0180] According to an embodiment of the present disclosure, the high-low level switching frequency or period of the first control signal terminal CN and the second control signal terminal CNB depends on the device characteristics. For example, the switching period can be an integer multiple of the frame time, that is, it alternates once every N*T_frame, where T_frame represents a frame time and N is a positive integer. The high-low level switching of the first control signal terminal CN and the second control signal terminal CNB can be at the beginning of a frame or before the reset signal of the reset signal terminal RST arrives, so as to reduce the noise impact on the pull-up node PU during switching. Switching before the reset signal of the reset signal terminal RST arrives, the noise can be released through the reset process. The reset signal pulse of the reset signal terminal RST will arrive at least once in a frame, that is, a frame is reset at least once, so the time for the first control signal terminal CN and the second control signal terminal CNB to maintain a high level is an integer multiple of a frame time.

[0181] As the application scenarios of display devices become more and more extensive, the application of splicing multiple display panels to achieve larger size display is particularly popular. However, splicing multiple panels may cause the display graphics near the splicing to tear. FIG. 8A to FIG. 8C Let's explain this.

[0182] FIG. 8A to FIG. 8C The figure shows the display effect of the spliced ​​screen.

[0183] The output signals generated by the shift register units in the gate driving circuit are usually used to scan the pixel array on the display panel in a unidirectional scanning manner, that is, scanning from the first row to the last row, or from the last row to the first row.

[0184] A spliced ​​screen is a screen that is made of smaller screens that are spliced ​​side by side to create a larger screen. The splicing of two display panels (also called screens) is done end by end or in by in. Fig. 8AAs shown in the figure, the shift register units in the gate drive circuit (GOA) of screen A and screen B are cascaded in reverse scanning mode, that is, the generated output signals are scanned from the last row to the first row in sequence. The end of screen A (that is, the end where the last stage shift register unit is located) is connected to the end of screen B. In this splicing mode, the graphics near the splicing position are scanned and displayed at the same time, and the picture is synchronized and relatively complete, as shown below Fig. 8A Shown is a smiling face.

[0185] If three screens are spliced ​​vertically, that is, screens A, B and C, the borders of the head end in and the tail end end are different. In order to ensure the same width of the splicing gap, only the head-to-tail (in by end) splicing method can be used, such as Figure 8B and 8C If the GOA scanning direction is consistent, such as Figure 8B As shown in the figure, the smiley face displayed on screen A is delayed compared to the smiley face displayed on screen B. If the smiley face image moves quickly to the right, the display screen will be torn. The joint of screen B and screen C is similar. If the GOA scanning direction of screen B is opposite to the GOA scanning direction of screen A and C, the images at the two joints will be displayed at the same time, and there will be no screen tearing. Figure 8C shown.

[0186] The embodiment of the present disclosure proposes a shift register unit, which can realize positive scanning (forward scanning) and reverse scanning (reverse scanning), so that the signal at the control signal end of the shift register unit can be adjusted to realize forward scanning or reverse scanning. Figures 9 to 14 Let's explain this in detail.

[0187] Fig. 9 A schematic block diagram of a shift register unit according to another embodiment of the present disclosure is shown.

[0188] like Fig. 9 As shown, the shift register unit 500 includes a first input circuit 5101 , a second input circuit 5102 , a control circuit 520 , K output circuits 530_1 , 530_2 , and a pull-down circuit 550 .

[0189] The first input circuit 5101 is connected to the first input signal terminal IN1, the pull-up node PU and the first control signal terminal CN of the shift register unit, and is used to provide the signal of the first control signal terminal CN to the pull-up node PU under the control of the first input signal terminal IN1.

[0190] The second input circuit 5102 is connected to the second input signal terminal IN2 of the shift register unit, the pull-up node PU and the second control signal terminal CNB. The second input circuit 5102 is used to provide the signal of the second control signal terminal CNB to the pull-up node PU under the control of the second input signal terminal IN2.

[0191] The control circuit 520 is connected to the pull-up node PU and the pull-down node PD of the shift register unit, the power signal terminal GVDD and the reference signal terminal VGL. The control circuit 520 is used to provide a signal from one of the power signal terminal GVDD and the reference signal terminal VGL to the pull-down node PD under the control of the pull-up node PU.

[0192] K output circuits 530_1 and 530_2 are connected to K clock signal terminals CLK1 and CLK2, K output signal terminals OUT1 and OUT2 and a pull-up node PU of the shift register unit. The first end of the k-th output circuit is connected to the k-th clock signal terminal of the shift register unit, and the second end of the k-th signal output circuit is connected to the k-th output signal terminal of the shift register unit. For example, the control ends of the output circuits 530_1 and 530_2 are both connected to the pull-up node PU, the first end of the output circuit 530_1 is connected to the clock signal terminal CLK1, and the second end is connected to the output signal terminal OUT1; the first end of the output circuit 530_2 is connected to the clock signal terminal CLK2, and the second end is connected to the output signal terminal OUT2. Each output circuit of the output circuit is used to provide a signal at the first end of the output circuit to the second end of the output circuit under the control of the control end of the output circuit, where K is an integer greater than 1, k=1, 2, ..., K.

[0193] The pull-down circuit 550 is connected to the pull-down node PD, the pull-up node PU, K output signal terminals OUT1, OUT2 and the reference signal terminal VGL. The pull-down sub-circuit 550 is used to provide the signal of the reference signal terminal VGL to the pull-up node PU and the K output signal terminals OUT1, OUT2 under the control of the pull-down node PD.

[0194] In the forward scanning mode, the first control signal terminal CN is at a first level, and the second control signal terminal CNB is at a second level. In this way, when the input signal of the first input signal terminal IN1 arrives, the first input circuit 5101 provides the first level of the first control signal terminal CN to the pull-up node PU under the control of the first input signal terminal IN1, and the signal of the pull-up node PU causes the output circuits 530_1 and 530_2 to generate output signals at the output signal terminals OUT1 and OUT2 at the clock signal terminals CLK1 and CLK2, respectively. When the reset signal of the second input signal terminal IN2 arrives, the second input circuit 5102 provides the second level of the second control signal terminal CNB to the pull-up node PU under the control of the reset signal of the second input signal terminal IN2, thereby resetting the pull-up node PU. That is, in the forward scanning mode, the first input circuit 5101 acts as an input circuit, and the second input circuit 5102 acts as a reset circuit.

[0195] In the reverse scanning mode, the first control signal terminal CN is at the second level, and the second control signal terminal CNB is at the first level. In this way, when the input signal of the second input signal terminal IN2 arrives, the second input circuit 5102 provides the first level of the second control signal terminal CNB to the pull-up node PU under the control of the second input signal terminal IN2, and the signal of the pull-up node PU causes the output circuits 530_1 and 530_2 to generate output signals at the output signal terminals OUT1 and OUT2 at the clock signal terminals CLK1 and CLK2, respectively. When the reset signal of the first input signal terminal IN1 arrives, the first input circuit 5101 provides the second level of the first control signal terminal CN to the pull-up node PU under the control of the reset signal of the first input signal terminal IN1, thereby resetting the pull-up node PU. That is, in the reverse scanning mode, the second input circuit 5102 acts as an input circuit, and the first input circuit 5101 acts as a reset circuit.

[0196] The embodiment of the present disclosure sets a first control signal terminal and a second control signal terminal that are independent of the power signal terminal and the reference signal terminal, and can realize two scanning modes, forward and reverse, by changing the signals of the first control signal terminal and the second control signal terminal, so that the shift register unit can be set to the forward or reverse scanning mode as needed. In this way, the scanning direction of each shift register unit can be designed as needed in screen splicing, thereby avoiding the problem of display screen tearing at the splicing point caused by the shift register unit having only a single scanning direction.

[0197] In some embodiments, the shift register unit may further include a first voltage stabilizing circuit 592 and a second voltage stabilizing circuit 593. The first voltage stabilizing circuit 592 is connected to the pull-down node PD, the second input signal terminal IN2 and the first control signal terminal CN, and the first voltage stabilizing circuit 592 is used to provide the signal of the first control signal terminal CN to the pull-down node PD under the control of the second input signal terminal IN2. The second voltage stabilizing circuit 593 is connected to the pull-down node PD, the first input signal terminal IN1 and the second control signal terminal CNB, and the second voltage stabilizing circuit 593 is used to provide the signal of the second control signal terminal CNB to the pull-down node PD under the control of the first input signal terminal IN1. In the forward scanning mode, the second voltage stabilizing circuit 593 provides the second level of the second control signal terminal CNB to the pull-down node PD under the control of the first input signal terminal IN1; in the reverse scanning mode, the first voltage stabilizing circuit 592 provides the second level of the first control signal terminal CN to the pull-down node PD under the control of the second input signal terminal IN2. By setting the first voltage stabilizing circuit and the second voltage stabilizing circuit, the pull-down node can be stabilized at the second level in the process of generating the output signal, which is conducive to stable signal output.

[0198] Fig.10 A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown. Fig.10 The shift register unit and Figure 3 Similarly, the difference lies at least in the input circuit and the isolation circuit. For the convenience of description, the following will mainly describe the difference in detail.

[0199] like Fig.10 As shown, the shift register unit 600 includes a first input circuit 6101, a second input circuit 6102, a control circuit 620, an output circuit 630_CR, 630_1, 630_2, 630_3, 630_4 and a pull-down circuit, wherein the pull-down circuit may include a first pull-down circuit 6501 and a second pull-down circuit 6502_CR, 6502_1, 6502_2, 6502_3 and 6502_4 (hereinafter collectively referred to as the second pull-down circuit 6502). Figure 3 The description of the control circuit and the pull-down circuit is also applicable to this embodiment and will not be repeated here. Each output circuit 330_CR, 330_1, 330_2, 330_3 and 330_4 may include a third transistor M3_CR, M3_1, M3_2, M3_3, M3_4 (hereinafter collectively referred to as the third transistor M3) and a first capacitor C1_CR, C1_1, C1_2, C1_3C1_4 (hereinafter collectively referred to as the first capacitor C1). Figure 3 The difference is, Fig.10The shift register unit removes the isolation circuit, and the gate of the third transistor M3 of each output circuit is connected to the pull-up node PU. However, the embodiments of the present disclosure are not limited thereto. Fig.10 The shift register unit may also include an isolation circuit, and the isolation circuit structure in any of the above embodiments may be adopted.

[0200] and Figure 3 Differently, the input signal terminal of the shift register unit 600 includes a first input signal terminal IN1 and a first input signal terminal IN2, and the control signal terminal includes a first control signal terminal CN and a second control signal terminal CNB. The shift register unit 600 includes a first input circuit 6101 and a second input circuit 6102.

[0201] The first input circuit 6101 may include a fourth transistor M4 , a gate of the fourth transistor M4 is connected to the first input signal terminal IN1 , a first electrode of the fourth transistor M4 is connected to the first control signal terminal CN, and a second electrode of the fourth transistor M4 is connected to the pull-up node PU.

[0202] The second input circuit 6102 may include a sixth transistor M6 , a gate of the sixth transistor M6 is connected to the second input signal terminal IN2 , a first electrode of the sixth transistor M6 is connected to the second control signal terminal CNB, and a second electrode of the sixth transistor M6 is connected to the pull-up node PU.

[0203] In some embodiments, the parameters of the fourth transistor M4 are the same as the parameters of the sixth transistor M6. This makes the first input circuit and the second input circuit for charging the pull-up node PU have a symmetrical structure, and the shift register unit has the same input capability in the forward scanning mode and the reverse scanning mode, which is beneficial to the stability of the output signal.

[0204] In some embodiments, the shift register unit 600 may further include a first voltage stabilizing circuit 692 and a second voltage stabilizing circuit 693. The first voltage stabilizing circuit 692 may include an eighth transistor M8, a gate of the eighth transistor M8 is connected to the second input signal terminal IN2, a first electrode of the eighth transistor M8 is connected to the first control signal terminal, and a second electrode of the eighth transistor M8 is connected to the pull-down node PD.

[0205] The second voltage stabilizing circuit 693 may include a ninth transistor M9 , a gate of the ninth transistor M9 is connected to the first input signal terminal IN1 , a first electrode of the ninth transistor M9 is connected to the second control signal terminal, and a second electrode of the ninth transistor M9 is connected to the pull-down node PD.

[0206] In some embodiments, the eighth transistor M8 and the ninth transistor M9 have the same parameters, which makes the first voltage stabilizing circuit and the second voltage stabilizing circuit for discharging the pull-down node PD have a symmetrical structure, so that the discharge capacity of the pull-down node in the forward scanning mode and the reverse scanning mode is the same, which is beneficial to the stability of the output signal.

[0207] Fig.11A A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown. Fig.11A The shift register unit and Figure 4A Similarly, the difference lies at least in the input circuit and the isolation circuit. For the convenience of description, the following will mainly describe the difference in detail.

[0208] like Fig.11A As shown, the shift register unit 700 includes a control circuit 720, output circuits 730_CR, 730_1, 730_2, 730_3, 730_4 (hereinafter collectively referred to as output circuit 730), a pull-down circuit (including a first pull-down circuit 7501 and a second pull-down circuit 7502_CR, 7502_1, 7502_2, 7502_3 and 7502_4), a third voltage stabilizing circuit 790, a sensing circuit (including a selection subcircuit 7801, a trigger subcircuit 7802 and a voltage stabilizing subcircuit 7803) and a total reset circuit 770. The above reference Figure 4A The description of the control circuit, the output circuit, the pull-down circuit, the third voltage stabilizing circuit, the sensing circuit and the total reset circuit is also applicable to this embodiment and will not be repeated here.

[0209] and Figure 4A The difference is that the first input circuit 7101 includes a fourth transistor M4 and a fifth transistor M5, the fifth transistor M5, the second electrode of the fourth transistor M4 is connected to the pull-up node PU through the fifth transistor M5, wherein the gate of the fifth transistor M5 is connected to the first input signal terminal IN1, the first electrode of the fifth transistor M5 is connected to the second electrode of the fourth transistor M4, and the second electrode of the fifth transistor M5 is connected to the pull-up node PU. The second input circuit 7102 includes a sixth transistor M6 and a seventh transistor M7, the gate of the sixth transistor M6 is connected to the second input signal terminal IN2, the first electrode of the sixth transistor M6 is connected to the second control signal terminal, the second electrode of the sixth transistor M6 is connected to the pull-up node PU, the gate of the seventh transistor M7 is connected to the second control signal terminal, the first electrode of the seventh transistor M7 is connected to the second electrode of the sixth transistor M6, and the second electrode of the seventh transistor M7 is connected to the pull-up node PU. The second electrode of the fourth transistor M4 and the first electrode of the fifth transistor M5 can be connected to the voltage stabilization node Q. The second electrode of the sixth transistor M6 and the first electrode of the seventh transistor M7 can be connected to the voltage stabilization node Q.

[0210] In some embodiments, the fourth transistor M4 and the sixth transistor M6 may have the same parameters, and the fifth transistor M5 and the seventh transistor M7 may have the same parameters. In other embodiments, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 may have the same parameters. In this way, the first input circuit and the second input circuit for charging the pull-up node PU can form a symmetrical structure, so that the charging capacity of the pull-up node PU in the forward scanning mode and the reverse scanning mode is the same, which is beneficial to the stability of the potential of the pull-up node PU, and thus is beneficial to the stability of the output signal. By setting the first and second input circuits to a dual-transistor structure and connecting them to the voltage stabilization node, the transistors in the input circuit can be prevented from leaking, which is further beneficial to the stability of the potential of the pull-up node PU.

[0211] Fig. 11B A circuit diagram of a shift register unit according to another embodiment of the present disclosure is shown. Fig. 11B The shift register unit and Fig.11A The difference is at least in the structure of the voltage stabilizing circuit. For the convenience of description, the following will mainly describe the difference in detail.

[0212] like Fig. 11B As shown, the shift register unit includes a first voltage stabilizing circuit 792 and a second voltage stabilizing circuit 793 as well as an intermediate voltage stabilizing circuit 794. The first voltage stabilizing circuit 792 and the second voltage stabilizing circuit 793 and the intermediate voltage stabilizing circuit 794 are connected to an intermediate node QQ.

[0213] The first voltage stabilizing circuit 792 is connected to the intermediate node QQ, the first input signal terminal IN1 and the first control signal terminal CN, and the first voltage stabilizing circuit 792 is used to provide the signal of the first control signal terminal CN to the intermediate node QQ under the control of the first input signal terminal IN1. The first voltage stabilizing circuit 792 may include an eighth transistor M8, a gate of the eighth transistor M8 is connected to the first input signal terminal IN1, a first electrode of the eighth transistor M8 is connected to the first control signal terminal CN, and a second electrode of the eighth transistor M8 is connected to the intermediate node QQ.

[0214] The second voltage stabilizing circuit 793 is connected to the middle node QQ, the second input signal terminal IN2 and the second control signal terminal CNB, and the second voltage stabilizing circuit 793 is used to provide the signal of the second control signal terminal CNB to the middle node QQ under the control of the second input signal terminal IN2. The second voltage stabilizing circuit 793 may include a ninth transistor M9, a gate of the ninth transistor M9 is connected to the second input signal terminal IN2, a first electrode of the ninth transistor M9 is connected to the second control signal terminal CNB, and a second electrode of the ninth transistor M9 is connected to the middle node QQ.

[0215] The intermediate voltage stabilizing circuit 794 is connected to the pull-down node PD, the intermediate node QQ and the reference signal terminal VGL2. The intermediate voltage stabilizing circuit 794 can provide the signal of the reference signal terminal VGL2 to the intermediate node QQ under the control of the pull-down node PD, and provide the signal of the reference signal terminal VGL2 to the pull-down node PD under the control of the intermediate node QQ. The intermediate voltage stabilizing circuit 794 may include a tenth transistor M10 and an eleventh transistor M11, the gate of the tenth transistor M10 is connected to the intermediate node QQ, the first electrode of the tenth transistor M10 is connected to the reference signal terminal VGL2, the second electrode of the tenth transistor M10 is connected to the pull-down node PD, the gate of the eleventh transistor M11 is connected to the pull-down node PD, the first electrode of the eleventh transistor M11 is connected to the reference signal terminal VGL2, and the second electrode of the eleventh transistor M11 is connected to the intermediate node QQ.

[0216] In the forward scanning mode, when the high level of the first input signal terminal IN1 arrives, the transistor M8 is turned on, thereby providing the high level of the first control signal terminal CN to the middle node QQ, and the transistor M10 is turned on, thereby providing the low level of the reference signal terminal VGL2 to the pull-down node PD. The low level of the pull-down node PD also keeps the transistor M11 turned off. Then, the high level of the second input signal terminal IN2 arrives, the pull-down node PD is high, the transistor M9 is turned on, thereby providing the low level of the second control signal terminal CNB to the middle node QQ, and the transistor M11 is turned on, thereby keeping the middle node QQ at a low level. The low level of the middle node QQ turns off the transistor M10, thereby preventing the middle node QQ from being mistakenly raised due to noise, thereby misleadingly turning on the tenth transistor M10, causing the power supply signal terminal GVDD2 to be abnormally turned on with the reference signal terminal VGL2 through the transistors M13 and M10.

[0217] In the reverse scanning mode, the high level of the second input signal terminal IN2 arrives, and the transistor M9 is turned on, thereby providing the high level of the second control signal terminal CNB to the middle node QQ, and the transistor M10 is turned on, thereby providing the low level of the reference signal terminal VGL2 to the pull-down node PD. The low level of the pull-down node PD also turns off the transistor M11. Then, the high level of the first input signal terminal IN1 arrives, the pull-down node PD is high, the transistor M8 is turned on, thereby providing the low level of the first control signal terminal CN to the middle node QQ, and the transistor M11 is turned on, thereby keeping the middle node QQ at a low level. The low level of the middle node QQ turns off the transistor M10, thereby preventing the middle node QQ from being mistakenly raised due to noise, thereby misleadingly turning on the tenth transistor M10, causing the power supply signal terminal GVDD2 to be abnormally turned on with the reference signal terminal VGL2 through the transistors M13 and M10.

[0218] The embodiments of the present disclosure enhance the anti-noise capability of the circuit by providing an intermediate voltage stabilization circuit and an intermediate node.

[0219] The embodiments of the present disclosure further provide a control method for a shift register unit, which is applicable to the shift register unit of any of the above embodiments.

[0220] In the forward scanning mode, the first control signal terminal is at a first level, and the second control signal terminal is at a second level, wherein in an input period, the first input circuit provides a signal at the first control signal terminal to a pull-up node under the control of the first input signal terminal; in an output period, each of the K output circuits provides a signal at the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit; in a reset period, the second input circuit provides a signal at the second control signal terminal to the pull-up node under the control of the second input signal terminal, the control circuit provides a signal at the reference signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides a signal at the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

[0221] In the reverse scan mode, the first control signal terminal is at the second level, and the second control signal terminal is at the first level, wherein in the input period, the second input circuit provides the signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal; in the output period, each of the K output circuits provides the signal of the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit; in the reset period, the first input circuit provides the signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal, the control circuit provides the signal of the reference signal terminal to the pull-down node under the control of the pull-up node, and the pull-down circuit provides the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

[0222] Fig.12 A signal timing diagram of a shift register unit in a forward scanning mode according to an embodiment of the present disclosure is shown. Fig.13 A signal timing diagram of a shift register unit in a reverse scanning mode according to an embodiment of the present disclosure is shown. Fig.12 and Fig.13 The signal timing sequence is applicable to the shift register unit with forward and reverse scanning functions in any embodiment. Fig.11A The shift register unit is used to Fig.12 and Fig.13 The signal timing is described in detail.

[0223] like Fig.12As shown, in the forward scanning mode, the first control signal terminal CN is at a high level, and the second control signal terminal CNB is at a low level. In the period P1 to P3, the high level of the first input signal terminal IN1 arrives, the transistors M4 and M5 are turned on, the high level of the first control signal terminal CN is provided to the pull-up node PU, and the transistors M3_CR, M3_1, M3_2, M3_3 and M3_4 are turned on. In the period P5 to P11, the clock signal terminals CLK1, CLK2, CLK3, CLK4 and CLKCR receive the clock signals shifted in sequence, and the turned-on transistors M3_1 to M3_4 respectively provide the clock signals of the clock signal terminals CLK1 to CLK4 to the output signal terminals OUT1 to OUT4, and the turned-on transistor M3_CR provides the clock signal received by the clock signal terminal CLKCR to the output signal terminal CR. Next, in the period P17 to P19, the second input signal terminal IN receives a high-level reset signal, and the transistors M6 and M7 are turned on, thereby resetting the pull-up node PU to the low level of the second control signal terminal CNB. The low level of the pull-up node PU turns off the transistors M14 and M15, so that the pull-down node PD becomes a high level, and the transistors M19_CR, M19_1, M19_2, M19_3 and M19_4 are turned on, so that the output signal terminals OUT1, OUT2, OUT3, OUT4 and CR are all maintained at a low level.

[0224] In the reverse scanning mode, the first control signal terminal CN is at a low level, and the second control signal terminal CNB is at a high level. In the period P1 to P3, the high level of the second input signal terminal IN2 arrives, the transistors M6 and M7 are turned on, the high level of the second control signal terminal CNB is provided to the pull-up node PU, and the transistors M3_CR, M3_1, M3_2, M3_3 and M3_4 are turned on. In the period P5 to P11, the clock signal terminals CLK4, CLK3, CLK2, CLK1, CLKCR receive the clock signals shifted in sequence, and the turned-on transistors M3_1 to M3_4 respectively provide the clock signals of the clock signal terminals CLK1 to CLK4 to the output signal terminals OUT1 to OUT4, and the turned-on transistor M3_CR provides the clock signal received by the clock signal terminal CLKCR to the output signal terminal CR. Next, in the period P17 to P19, the first input signal terminal IN receives a high-level reset signal, and the transistors M4 and M5 are turned on, thereby resetting the pull-up node PU to the low level of the first control signal terminal CN. The low level of the pull-up node PU turns off the transistors M14 and M15, so that the pull-down node PD becomes a high level, and the transistors M19_CR, M19_1, M19_2, M19_3 and M19_4 are turned on, so that the output signal terminals OUT1, OUT2, OUT3, OUT4 and CR are all maintained at a low level.

[0225] In this way, the shift register unit can generate pulses of output signals in the order of OUT1, OUT2, OUT3 and OUT4 in the forward scanning mode, thereby realizing forward scanning; it can also generate pulses of output signals in the order of OUT4, OUT3, OUT2, OUT1 in the reverse scanning mode, thereby realizing reverse scanning.

[0226] Fig.14 The signal timing diagram of the shift register unit in the display phase and the blanking phase according to the embodiment of the present disclosure is shown. The timing diagram is applicable to any embodiment with a sensing circuit in the above embodiments. Fig.11A The shift register unit is used to Fig.14 The signal timing is described in detail. Fig.14 It is assumed that the shift register unit operates in a forward scanning mode, that is, the first input signal terminal IN1 receives an input signal, and the second input signal terminal IN2 receives a reset signal.

[0227] like Fig.14 As shown, a frame may include a display phase and a blanking phase. The shift register unit may generate a display scanning signal for driving the pixel to emit light in the display phase, and may generate a sensing scanning signal for sensing in the blanking phase.

[0228] In the display stage, the shift register unit generates sequentially shifted output signals at the output signal terminals OUT1, OUT2, OUT3, OUT4 and CR respectively in response to the first input signal terminal IN receiving a high-level input signal, based on the clock signals of the clock signal terminals CLK1, CLK2, CLK3, CLK4 and CR. In this process, in the period P1 to P3, the input signal received by the first input signal terminal IN and the selection signal received by the sensing selection signal terminal OE are both high-level, which turns on the transistors M22 and M23, thereby writing the high level of the input signal terminal IN to the sensing control node H, and the high level of the sensing control node H turns on the transistor M25.

[0229] In the blanking phase, when the high level of the sensing trigger signal terminal CLKA arrives, the transistors M26 and M27 are turned on, and the high level of the power signal terminal GVDD1 is provided to the pull-up node PU through the turned-on transistors M25, M26, and M27, thereby charging the PU point, and the transistors M3_CR, M3_1, M3_2, M3_3, and M3_4 are all turned on. Next, the clock signal terminal CLK3 receives a clock signal with a specific waveform, and the turned-on transistor M3_3 provides the clock signal of the clock signal terminal CLK3 to the output signal terminal OUT3, thereby generating a sensing scan signal at the output signal terminal OUT3.

[0230] The gate drive circuit includes a plurality of shift register units connected in cascade, and a certain output signal terminal of a certain shift register unit can be selected by sensing a selection signal, a sensing trigger signal and a clock signal to output a signal in the blanking stage. For example, assuming that the gate drive circuit includes a plurality of shift register units, each shift register unit has four output signal terminals. If a sensing scanning signal for turning on the 7th row of sub-pixels is to be generated in the blanking stage, the third output signal terminal OUT3 of the 2nd shift register unit needs to be controlled. <2> Generate a sensing scan signal. Then, in the display stage, the sensing selection signal terminal of each shift register receives the same sensing selection signal, wherein the sensing selection signal received by the second-stage shift register and the input signal received by its input signal terminal are both high level, so that the sensing control node H of the second-stage shift register is written to a high level, and the sensing control nodes H of other shift register units remain at a low level. In this way, when the high level of the sensing trigger signal terminal CLKA arrives in the blanking stage, only the pull-up node PU of the second-stage shift register unit whose sensing control node H is high level is charged, thereby controlling the third output signal terminal OUT3 of the second-stage shift register unit by applying a preset clock signal to the clock signal terminals of each country (in this embodiment, a high level clock signal is applied to the clock signal terminal CLK3, while other clock signal terminals remain at a low level). <n>Generates a sensing scan signal, such as Fig.14 shown.

[0231] According to the embodiments of the present disclosure, the structure for the forward and reverse scanning functions is also applicable to the shift register unit with the isolation circuit. That is, the shift register unit can include the isolation circuit and have the forward and reverse scanning structure.

[0232] For example, you can Fig. 11B The forward and reverse scanning structure shown is applied to Figure 4B The shift register unit is obtained as Fig.15 The circuit structure of the shift register unit is shown in FIG. Fig.15 As shown, the shift register unit 800 and Figure 4B The shift register unit is similar to Figure 4B The input circuit and reset circuit in the above are replaced by the first input circuit 8101 and the second input circuit 8102, and the shift register unit 800 further includes a first voltage stabilizing circuit 892, a second voltage stabilizing circuit 893 and an intermediate voltage stabilizing circuit 894. Figure 4B Description and reference to the output circuit Fig.11A The description of the first input circuit, the second input circuit, the first voltage stabilizing circuit and the intermediate voltage stabilizing circuit is also applicable to this embodiment and will not be repeated here.

[0233] For example, we can Figure 4A The shift register unit shown is used as Fig.11A The forward and reverse scanning circuit structure shown in the figure can be obtained as follows Fig.16 The shift register unit 900 shown in FIG. Fig.16 As shown, the shift register unit 900 and Figure 4A The shift register unit shown is similar to the one shown in the figure, except that the input circuit and the reset circuit are replaced by the first input circuit 910 and the second input circuit 960, and further includes a first voltage stabilizing circuit 992 and a second voltage stabilizing circuit 993. Fig.11A The description of the first input circuit, the second input circuit, the first voltage stabilizing circuit and the second voltage stabilizing circuit are also applicable to this embodiment and will not be repeated here.

[0234] The above is merely an illustrative description, and the embodiments of the present disclosure are not limited thereto. The forward and reverse scanning structures of any of the above embodiments can be applied to the shift register unit of any embodiment with an isolation circuit. Figures 10 to 11B The forward and reverse scanning circuit structure of any embodiment described is applied to the above reference Figures 3 to 4F A shift register cell with an isolation circuit is described in any of the embodiments.

[0235] In the embodiment of the present disclosure, an isolation circuit is provided in the shift register unit to achieve voltage bootstrapping of the control terminals of the various output circuits without affecting each other, and a forward and reverse scanning circuit structure is provided to provide forward scanning and reverse scanning functions.

[0236] It should be noted that in Figure 5 , Figure 6 as well as Figure 12 to Figure 14 For the sake of convenience, the signal waveform of the clock signal end is shown in the form of a single pulse, but this does not constitute a limitation on the waveform of the clock signal. The clock signal received by the clock signal end of the shift register unit of the embodiment of the present disclosure is a periodic signal, and the period and duty cycle of the clock signal can be set as needed.

[0237] An embodiment of the present disclosure further provides a gate driving circuit, comprising a plurality of shift register units, wherein the plurality of shift register units are cascade-connected, and the plurality of shift register units may be implemented by the shift register units of any of the above embodiments.

[0238] Fig.17 FIG. 1 is a schematic block diagram of a gate drive circuit according to an embodiment of the present disclosure. Fig.17 As shown, the gate driving circuit includes a plurality of shift register units GOA1, GOA2, GOA3, ... Each shift register unit can be implemented by the shift register unit of any of the above embodiments. For the convenience of description, the gate driving circuit includes a plurality of shift register units GOA1, GOA2, GOA3, ... Each shift register unit can be implemented by the shift register unit of any of the above embodiments. Figures 3 to 4F The shift register unit shown is used as an example for explanation. A plurality of shift register units GOA1, GOA2, GOA3, ... in the gate drive circuit are cascaded, wherein the input signal terminal of the nth shift register unit is connected to the cascade output terminal of the nith shift register unit, and the reset signal terminal is connected to the cascade output terminal of the n+jth shift register unit. Here, i and j can be set as needed, for example, i=j=2, in which case, the cascade output terminal CR of the first-stage shift register unit GOA1 is connected to the input signal terminal IN of the third-stage shift register unit GOA3, the cascade output terminal CR of the second-stage shift register unit GOA2 is connected to the input signal terminal of the fourth-stage shift register unit GOA4, and so on; the cascade output terminal of the third-stage shift register unit GOA3 is connected to the reset signal terminal RST of the first-stage shift register unit GOA1, and the cascade output terminal of the fourth-stage shift register unit GOA4 is connected to the reset signal terminal RST of the second-stage shift register unit GOA2, and so on.

[0239] The gate drive circuit can receive multiple clock signals. For example, a shift register unit has four signal output terminals OUT1 to OUT4 and one cascade output terminal CR. The gate drive circuit can receive 12 clock signals Clk1 to Clk12, wherein three shift register units are grouped together to receive the 12 clock signals. Fig.17 As shown, the clock signal terminals CLK1, CLK2, CLK3, CLK4 and CLKCR of the first stage shift register unit GOA1 receive clock signals Clk1 to Clk5 respectively, the clock signal terminals CLK1, CLK2, CLK3, CLK4 and CLKCR of the second stage shift register unit GOA2 receive clock signals Clk5 to Clk9 respectively, and the clock signal terminals CLK1, CLK2, CLK3, CLK4 and CLKCR of the third stage shift register unit GOA3 receive clock signals Clk9 to Clk12 respectively. Referring to the signal timing diagram of the above embodiment, for example Figure 5 , the shift register units GOA1, GOA2, GOA3, ... output sequentially shifted output signals G1, G2, G3, G4, G5, ... .

[0240] In the above embodiment, although Figures 3 to 4F The structure of the gate driving circuit is schematically illustrated by taking the shift register unit with an input signal terminal IN and a reset signal terminal RST as an example, however, the embodiments of the present disclosure are not limited thereto. Figures 10 to 11B The shift register unit having the first input signal terminal IN and the second input signal terminal IN2 described above can be cascade-connected in the cascade manner as described above, with one of the two being used as the input signal terminal IN and the other being used as the reset signal terminal RST.

[0241] In some embodiments, the clock signals Clk1 to Clk12 may be periodic signals with a duty cycle of 1 / 4. The period of the clock signal may be 12H, and the effective level duration may be 3H, where H is the unit scan time, i.e., the time required to scan a row of sub-pixels. Adjacent clock signals may be shifted by H. However, the embodiments of the present disclosure are not limited thereto, and the number, period, and duty cycle of the clock signals may be set as required. For example, the duty cycle of the clock signal may be set to 33% (1 / 3), 50% (1 / 2), 75% (3 / 4), and so on. A corresponding number of output circuits may be provided in the shift register unit and a corresponding cascade connection method may be adopted to generate the desired output signal.

[0242] Those skilled in the art can understand that the embodiments described above are exemplary and can be improved by those skilled in the art. The structures described in various embodiments can be freely combined without causing conflicts in structure or principle.

[0243] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art can clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and the present disclosure is not limited to the implementation methods of the exemplary embodiments listed in the specification.< / n>

Claims

1. A shift register unit, characterized in that: include: An input circuit, connected to an input signal terminal and a pull-up node of the shift register, and used for inputting a signal at the input signal terminal to the pull-up node; a control circuit connected to the pull-up node and the pull-down node, the power signal terminal and the reference signal terminal of the shift register unit, the control circuit being used to provide a signal of one of the power signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node; K output circuits, connected to the K clock signal terminals, K output signal terminals and the pull-up node of the shift register unit, wherein a first terminal of the kth output circuit is connected to the kth clock signal terminal of the shift register unit, a second terminal of the kth signal output circuit is connected to the kth output signal terminal of the shift register unit, and each output circuit is used to provide a signal at the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit, wherein K is an integer greater than 1, k=1, 2, ..., K; K' isolation circuits are respectively connected between the control terminals of K' output circuits among the K output circuits and the pull-up node, wherein a first terminal of each isolation circuit is connected to the pull-up node, a second terminal of the isolation circuit is connected to the control terminal of the corresponding output circuit, the control terminal of the isolation circuit is connected to the control signal terminal, and the isolation circuit is used to connect or disconnect the first terminal of the isolation circuit with the second terminal under the control of the voltage between the control terminal of the isolation circuit and the second terminal of the isolation circuit, wherein K' is a positive integer, and K'≤K; A pull-down circuit is connected to the pull-down node, the pull-up node, the K output signal terminals and the reference signal terminal, and the pull-down circuit is used to provide the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node.

2. The shift register unit according to claim 1, wherein: The K output circuits include a cascade output circuit and K' signal output circuits, the output signal terminals connected to the cascade output circuits are used to connect to other shift register units, and the output signal terminals connected to the signal output circuits are used to provide output signals; The K' isolation circuits are respectively connected between the control terminals of the K' signal output circuits and the pull-up nodes.

3. The shift register unit according to claim 1, wherein: The K output circuits include a cascade output circuit and K' signal output circuits, one of the K' isolation circuits is connected between the control end of the cascade output circuit and the pull-up node, and the remaining K'-1 isolation circuits are respectively connected between the control end of the K'-1 signal output circuit and the pull-up node.

4. The shift register unit according to any one of claims 1 to 3, wherein: The isolation circuit includes a first transistor, a gate of the first transistor is connected to the control signal terminal, a first electrode of the first transistor serves as a first terminal of the isolation circuit, and a second electrode of the first transistor serves as a second terminal of the isolation circuit.

5. The shift register unit according to claim 4, wherein: The control signal terminal includes a first control signal terminal and a second control signal terminal, wherein the first control signal terminal is at a first level and the second control signal terminal is at a second level; The isolation circuit also includes a second transistor, wherein the gate of the first transistor is connected to the first control signal terminal, the gate of the second transistor is connected to the second control signal terminal, the first electrode of the first transistor is connected to the first electrode of the second transistor, and the second electrode of the first transistor is connected to the second electrode of the second transistor.

6. The shift register unit according to claim 1, wherein: K=5, K'=3, 4 or 5.

7. The shift register unit according to claim 1, wherein: The output circuit comprises: a third transistor, wherein the gate of the third transistor serves as the control terminal of the output circuit, the first electrode of the third transistor serves as the first terminal of the output circuit, and the second electrode of the third transistor serves as the second terminal of the output circuit; A first capacitor, wherein a first electrode of the first capacitor is connected to a gate of the third transistor, and a second electrode of the first capacitor is connected to a second electrode of the third transistor.

8. The shift register unit according to claim 1, wherein: The input circuit comprises a fourth transistor, wherein the gate of the fourth transistor is connected to the input signal terminal, the first electrode of the fourth transistor is connected to the power signal terminal, and the second electrode of the fourth transistor is connected to the pull-up node; or The input circuit includes a fourth transistor and a fifth transistor, wherein the gate of the fourth transistor is connected to the input signal terminal, the first electrode of the fourth transistor is connected to the power signal terminal, the second electrode of the fourth transistor is connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the input signal terminal, the first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is connected to the pull-up node.

9. The shift register unit according to claim 1, characterized in that: Also includes: A reset circuit is connected to the reset signal terminal of the shift register unit, the pull-up node and the reference signal terminal, and the reset circuit is used to provide the signal of the reference signal terminal to the pull-up node under the control of the reset signal terminal.

10. The shift register unit according to claim 9, wherein: The reset circuit comprises a sixth transistor, a gate of the sixth transistor is connected to the reset signal terminal, a first electrode of the sixth transistor is connected to the reference signal terminal, and a second electrode of the sixth transistor is connected to the pull-up node; or The reset circuit includes a sixth transistor and a seventh transistor, the gate of the sixth transistor is connected to the reset signal terminal, the first electrode of the sixth transistor is connected to the reference signal terminal, the second electrode of the sixth transistor is connected to the pull-up node through the seventh transistor, the gate of the seventh transistor is connected to the reset signal terminal, the first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and the second electrode of the seventh transistor is connected to the pull-up node.

11. The shift register unit according to claim 1, wherein: The input signal terminal includes a first input signal terminal and a second input signal terminal, the control signal terminal includes a first control signal terminal and a second control signal terminal, and the input circuit includes: A first input circuit, connected to the first input signal terminal, the pull-up node and the first control signal terminal, the first input circuit being used to provide the signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal; a second input circuit connected to the second input signal terminal, the pull-up node and the second control signal terminal, the second input circuit being used to provide a signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal; Among them, in the forward scanning mode, the first control signal end is at the first level, and the second control signal end is at the second level; in the reverse scanning mode, the first control signal end is at the second level, and the second control signal end is at the first level.

12. The shift register unit according to claim 11, wherein: The first input circuit comprises: A fourth transistor, wherein a gate of the fourth transistor is connected to the first input signal terminal, a first electrode of the fourth transistor is connected to the first control signal terminal, and a second electrode of the fourth transistor is connected to the pull-up node.

13. The shift register unit according to claim 12, wherein: The first input circuit further comprises: A fifth transistor, wherein the second electrode of the fourth transistor is connected to the pull-up node through the fifth transistor, wherein the gate of the fifth transistor is connected to the first input signal terminal, the first electrode of the fifth transistor is connected to the second electrode of the fourth transistor, and the second electrode of the fifth transistor is connected to the pull-up node.

14. The shift register unit according to claim 11, wherein: The second input circuit comprises: A sixth transistor, wherein a gate of the sixth transistor is connected to the second input signal terminal, a first electrode of the sixth transistor is connected to the second control signal terminal, and a second electrode of the sixth transistor is connected to the pull-up node.

15. The shift register unit according to claim 14, wherein: The second input circuit further includes: A seventh transistor, wherein a gate of the seventh transistor is connected to the second control signal terminal, a first electrode of the seventh transistor is connected to the second electrode of the sixth transistor, and a second electrode of the seventh transistor is connected to the pull-up node.

16. The shift register unit according to claim 11, wherein: The first input circuit includes a fourth transistor, the second input circuit includes a sixth transistor, and parameters of the fourth transistor are the same as parameters of the sixth transistor.

17. The shift register unit according to claim 16, wherein: The first input circuit further includes a fifth transistor, and the second input circuit further includes a seventh transistor, and parameters of the fifth transistor are the same as parameters of the seventh transistor.

18. The shift register unit according to claim 11, characterized in that: Also includes: a first voltage stabilizing circuit, connected to the pull-down node, the second input signal terminal and the first control signal terminal, the first voltage stabilizing circuit being used for providing a signal of the first control signal terminal to the pull-down node under the control of the second input signal terminal; A second voltage stabilizing circuit is connected to the pull-down node, the first input signal terminal and the second control signal terminal, and the second voltage stabilizing circuit is used to provide the signal of the second control signal terminal to the pull-down node under the control of the first input signal terminal.

19. The shift register unit according to claim 18, wherein: The first voltage stabilizing circuit comprises an eighth transistor, a gate of the eighth transistor is connected to the second input signal terminal, a first electrode of the eighth transistor is connected to the first control signal terminal, and a second electrode of the eighth transistor is connected to the pull-down node; The second voltage stabilizing circuit includes a ninth transistor, a gate of the ninth transistor is connected to the first input signal terminal, a first electrode of the ninth transistor is connected to the second control signal terminal, and a second electrode of the ninth transistor is connected to the pull-down node.

20. The shift register unit according to claim 19, wherein: The eighth transistor and the ninth transistor have the same parameters.

21. The shift register unit according to claim 11, characterized in that: It also includes a first voltage stabilizing circuit, a second voltage stabilizing circuit and an intermediate voltage stabilizing circuit, wherein the first voltage stabilizing circuit, the second voltage stabilizing circuit and the intermediate voltage stabilizing circuit are connected to an intermediate node, wherein: The first voltage stabilizing circuit is connected to the intermediate node, the first input signal terminal and the first control signal terminal, and the first voltage stabilizing circuit is used to provide the signal of the first control signal terminal to the intermediate node under the control of the first input signal terminal; The second voltage stabilizing circuit is connected to the intermediate node, the second input signal terminal and the second control signal terminal, and the second voltage stabilizing circuit is used to provide the signal of the second control signal terminal to the intermediate node under the control of the second input signal terminal; The intermediate voltage stabilization circuit is connected to the pull-down node, the intermediate node and the reference signal terminal, and is configured to provide the signal of the reference signal terminal to the intermediate node under the control of the pull-down node, and to provide the signal of the reference signal terminal to the pull-down node under the control of the intermediate node.

22. The shift register unit according to claim 21, wherein: The first voltage stabilizing circuit includes an eighth transistor, the second voltage stabilizing circuit includes a ninth transistor, and the intermediate voltage stabilizing circuit includes a tenth transistor and an eleventh transistor; Among them, the gate of the eighth transistor is connected to the first input signal terminal, the first electrode of the eighth transistor is connected to the first control signal terminal, the second electrode of the eighth transistor is connected to the intermediate node, the gate of the ninth transistor is connected to the second input signal terminal, the first electrode of the ninth transistor is connected to the second control signal terminal, the second electrode of the ninth transistor is connected to the intermediate node, the gate of the tenth transistor is connected to the intermediate node, the first electrode of the tenth transistor is connected to the reference signal terminal, the second electrode of the tenth transistor is connected to the pull-down node, the gate of the eleventh transistor is connected to the pull-down node, the first electrode of the eleventh transistor is connected to the reference signal terminal, and the second electrode of the eleventh transistor is connected to the intermediate node.

23. The shift register unit according to claim 1, wherein: The control circuit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor and a fifteenth transistor, wherein: The gate and the first electrode of the twelfth transistor are connected to the power signal terminal, and the second electrode of the twelfth transistor is connected to the gate of the thirteenth transistor; A first electrode of the thirteenth transistor is connected to the power signal terminal, and a second electrode of the thirteenth transistor is connected to the pull-down node; The gate of the fourteenth transistor is connected to the pull-up node, the first electrode of the fourteenth transistor is connected to the gate of the thirteenth transistor, and the second electrode of the fourteenth transistor is connected to the reference signal terminal; A gate electrode of the fifteenth transistor is connected to the pull-up node, a first electrode of the fifteenth transistor is connected to the pull-down node, and a second electrode of the fifteenth transistor is connected to the reference signal terminal.

24. The shift register unit according to claim 23, wherein: The control circuit further comprises: A sixteenth transistor, the second electrode of the twelfth transistor is connected to the gate of the thirteenth transistor through the sixteenth transistor, wherein the gate of the sixteenth transistor is connected to the power signal terminal, the first electrode of the sixteenth transistor is connected to the second electrode of the twelfth transistor, and the second electrode of the sixteenth transistor is connected to the gate of the thirteenth transistor.

25. The shift register unit according to claim 1, wherein: The pull-down circuit comprises: a first pull-down circuit connected to the pull-down node, the pull-up node and the reference signal terminal, the first pull-down circuit being used for providing the signal of the reference signal terminal to the pull-up node under the control of the pull-down node; K second pull-down circuits are respectively connected to the K output signal terminals, wherein each second pull-down circuit is connected to the pull-down node, the reference signal terminal and the corresponding output signal terminal, and is configured to provide the signal of the reference signal terminal to the corresponding output signal terminal under the control of the pull-down node.

26. The shift register unit according to claim 25, wherein: The first pull-down circuit comprises a seventeenth transistor, a gate of the seventeenth transistor is connected to the pull-down node, a first electrode of the seventeenth transistor is connected to the reference signal terminal, and a second electrode of the seventeenth transistor is connected to the pull-up node; or The first pull-down circuit includes a seventeenth transistor and an eighteenth transistor, the gate of the seventeenth transistor is connected to the pull-down node, the first electrode of the seventeenth transistor is connected to the reference signal terminal through the eighteenth transistor, the second electrode of the seventeenth transistor is connected to the pull-up node, wherein the gate of the eighteenth transistor is connected to the pull-down node, the first electrode of the eighteenth transistor is connected to the reference signal terminal, and the second electrode of the eighteenth transistor is connected to the first electrode of the seventeenth transistor.

27. The shift register unit according to claim 25, wherein: The second pull-down circuit includes a nineteenth transistor, a gate of the nineteenth transistor is connected to the pull-down node, a first electrode of the nineteenth transistor is connected to the reference signal terminal, and a second electrode of the nineteenth transistor is connected to the corresponding output signal terminal.

28. The shift register unit according to claim 1, characterized in that: Also includes: A total reset circuit is connected to the total reset signal terminal of the shift register unit, the pull-up node and the reference signal terminal, and the total reset circuit is configured to provide the signal of the reference signal terminal to the pull-up node under the control of the total reset signal terminal.

29. The shift register unit according to claim 28, wherein: The total reset circuit comprises a twentieth transistor, the gate of the twentieth transistor is connected to the total reset signal terminal, the first electrode of the twentieth transistor is connected to the reference signal terminal, and the second electrode of the twentieth transistor is connected to the pull-up node; or The total reset circuit includes a twentieth transistor and a twenty-first transistor, the gate of the twentieth transistor is connected to the total reset signal terminal, the first electrode of the twentieth transistor is connected to the reference signal terminal through the twenty-first transistor, the second electrode of the twentieth transistor is connected to the pull-up node, the gate of the twenty-first transistor is connected to the total reset signal terminal, the first electrode of the twenty-first transistor is connected to the reference signal terminal, and the second electrode of the twenty-first transistor is connected to the first electrode of the twentieth transistor.

30. The shift register unit according to claim 1, characterized in that: Also includes: A sensing circuit is connected to the sensing selection signal terminal, the sensing trigger signal terminal, the sensing control node, the input signal terminal and the pull-up node of the shift register unit, and the sensing circuit is used to write the signal of the input signal terminal to the sensing control node under the control of the sensing selection signal terminal in the display phase, and provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal in the blanking phase.

31. The shift register unit according to claim 30, wherein: The sensing circuit comprises: A selection subcircuit connected to the sensing selection signal terminal, the sensing control node and the input signal terminal, the selection subcircuit being used to write the signal of the input signal terminal into the sensing control node under the control of the sensing selection signal terminal in a display phase; A trigger subcircuit is connected to the sensing trigger signal terminal, the sensing control node and the pull-up node, and is used to provide the signal of the sensing control node to the pull-up node under the control of the sensing trigger signal terminal during a blanking phase.

32. The shift register unit according to claim 31, wherein: The selection subcircuit includes a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a second capacitor, wherein: The gate of the twenty-second transistor is connected to the sensing selection signal terminal, the first electrode of the twenty-second transistor is connected to the input signal terminal, the second electrode of the twenty-second transistor is connected to the first electrode of the twenty-third transistor, the first electrode of the twenty-third transistor is connected to the sensing selection signal terminal, the second electrode of the twenty-third transistor is connected to the sensing control node, the gate of the twenty-fourth transistor is connected to the sensing control node, the first electrode of the twenty-fourth transistor is connected to the second electrode of the twenty-second transistor, the second electrode of the twenty-fourth transistor is connected to the power supply signal terminal, the first electrode of the second capacitor is connected to the power supply signal terminal, and the second electrode of the second capacitor is connected to the gate of the twenty-fourth transistor.

33. The shift register unit according to claim 31, wherein: The trigger sub-circuit comprises a twenty-fifth transistor and a twenty-sixth transistor, the gate of the twenty-fifth transistor is connected to the sensing control node, the first electrode of the twenty-fifth transistor is connected to the power signal terminal, the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor, the gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal, and the second electrode of the twenty-sixth transistor is connected to the pull-up node; or The trigger sub-circuit includes a twenty-fifth transistor, a twenty-sixth transistor and a twenty-seventh transistor, the gate of the twenty-fifth transistor is connected to the sensing control node, the first electrode of the twenty-fifth transistor is connected to the power signal terminal, the second electrode of the twenty-fifth transistor is connected to the first electrode of the twenty-sixth transistor, the gate of the twenty-sixth transistor is connected to the sensing trigger signal terminal, the second electrode of the twenty-sixth transistor is connected to the pull-up node through the twenty-seventh transistor, the gate of the twenty-seventh transistor is connected to the sensing trigger signal terminal, the first electrode of the twenty-seventh transistor is connected to the second electrode of the twenty-sixth transistor, and the second electrode of the twenty-seventh transistor is connected to the pull-up node.

34. The shift register unit according to claim 31, wherein: The sensing circuit further includes: a voltage stabilizing subcircuit connected to the sensing control node, the sensing trigger signal terminal and the reference signal terminal, and configured to provide a signal from the reference signal terminal to the pull-down node under the control of the sensing control node and the sensing trigger signal terminal.

35. The shift register unit according to claim 34, wherein: The voltage stabilizing subcircuit includes a twenty-eighth transistor and a twenty-ninth transistor, the gate of the twenty-eighth transistor is connected to the sensing trigger signal terminal, the first electrode of the twenty-eighth transistor is connected to the pull-up node, the second electrode of the twenty-eighth transistor is connected to the first electrode of the twenty-ninth transistor, the gate of the twenty-ninth transistor is connected to the sensing control node, and the second electrode of the twenty-ninth transistor is connected to the reference signal terminal.

36. The shift register unit according to claim 1, characterized in that: Also includes: a third voltage stabilizing circuit, connected to the voltage stabilizing node of the shift register unit, the power signal terminal and the pull-up node, the third voltage stabilizing circuit being used for providing the signal of the power signal terminal to the voltage stabilizing node under the control of the pull-up node; Wherein, the input circuit of the shift register unit is connected to the voltage stabilization node.

37. The shift register unit according to claim 36, wherein: The third voltage stabilizing circuit includes a 30th transistor and a 31st transistor, the gate of the 30th transistor is connected to the pull-up node, the first electrode of the 30th transistor is connected to the power signal terminal, the second electrode of the 30th transistor is connected to the first electrode of the 31st transistor, the gate of the 31st transistor is connected to the pull-up node, and the second electrode of the 31st transistor is connected to the voltage stabilizing node.

38. The shift register unit according to claim 36, wherein: The shift register unit further includes a reset circuit, the input circuit includes a fourth transistor and a fifth transistor and the reset circuit includes a sixth transistor and a seventh transistor; or the input circuit includes a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; The second electrode of the fourth transistor, the first electrode of the fifth transistor, the second electrode of the sixth transistor and the first electrode of the seventh transistor are connected to the voltage stabilization node.

39. The shift register unit according to claim 38, wherein: The shift register unit further includes at least one of a pull-down circuit, a general reset circuit, and a sensing circuit, and at least one of the pull-down circuit, the general reset circuit, and the sensing circuit is connected to the regulated voltage node.

40. The shift register unit according to claim 1, characterized in that: Also includes: A fourth voltage stabilizing circuit is connected to the pull-down node, the input signal terminal and the reference signal terminal, and is used for providing the signal of the reference signal terminal to the pull-down node under the control of the input signal terminal.

41. The shift register unit according to claim 40, wherein: The fourth voltage stabilization circuit includes: a thirty-second transistor, a gate of the thirty-second transistor is connected to the input signal terminal, a first electrode of the thirty-second transistor is connected to the reference signal terminal, and a second electrode of the thirty-second transistor is connected to the pull-down node.

42. A shift register unit, characterized in that: include: A first input circuit, connected to a first input signal terminal, a pull-up node and a first control signal terminal of the shift register unit, wherein the first input circuit is used to provide a signal of the first control signal terminal to the pull-up node under the control of the first input signal terminal; A second input circuit, connected to a second input signal terminal of the shift register unit, the pull-up node and a second control signal terminal, the second input circuit being used to provide a signal of the second control signal terminal to the pull-up node under the control of the second input signal terminal; a control circuit connected to the pull-up node and the pull-down node, the power signal terminal and the reference signal terminal of the shift register unit, the control circuit being used to provide a signal of one of the power signal terminal and the reference signal terminal to the pull-down node under the control of the pull-up node; K output circuits, connected to K clock signal terminals, K output signal terminals and the pull-up node of the shift register unit, wherein the control terminal of the kth output circuit is connected to the pull-up node, the first terminal of the kth output circuit is connected to the kth clock signal terminal of the shift register unit, and the second terminal of the kth output circuit is connected to the kth output signal terminal of the shift register unit, and each output circuit is used to provide a signal at the first terminal of the output circuit to the second terminal of the output circuit under the control of the control terminal of the output circuit, wherein K is an integer greater than 1, k=1, 2, ..., K; a pull-down circuit connected to the pull-down node, the pull-up node, the K output signal terminals and the reference signal terminal, the pull-down circuit being used to provide the signal of the reference signal terminal to the pull-up node and the K output signal terminals under the control of the pull-down node; in, In the forward scanning mode, the first control signal terminal is at a first level, and the second control signal terminal is at a second level; In the reverse scanning mode, the first control signal terminal is at the second level, and the second control signal terminal is at the first level.

43. A gate drive circuit, characterized in that: The method comprises a plurality of shift register units according to any one of claims 1 to 42, wherein the plurality of shift register units are connected in cascade.

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