Isolation SIP chip based on FPGA

Abstract

The utility model provides an isolation SIP (Session Initiation Protocol) chip based on an FPGA (Field Programmable Gate Array), which comprises a microcontroller chip and an FPGA chip which are arranged on a substrate, and the microcontroller chip is connected with the FPGA chip through a parallel interface; signal isolation is carried out among the FPGA chip, the microcontroller chip, the transceiver and the bus control chip through a multi-path digital isolator; signal isolation is carried out between the microcontroller chip and the differential signal transmission control chip through a plurality of pairs of digital isolators. According to the full-isolation SIP chip based on the FPGA, all IO interfaces of the controller on the chip are isolated through the digital isolators, fluctuation of external signals is prevented, the core controller is protected, meanwhile, the multiple multi-channel digital isolators are used for multiplexing, the number of the multi-channel digital isolators can be reduced, and the size of the chip is reduced.

Description

Technical Field

[0001] The utility model belongs to the technical field of system-level packaged chips, and in particular relates to an isolated SIP chip based on FPGA. Background Art

[0002] SIP (System in Package) chip, translated into Chinese as "system-level packaging", is different from traditional single-chip packaging. SIP technology integrates multiple chips or components with different functions in one package. These chips can be digital processors, analog circuits, memories, sensors, etc. In this way, SIP can achieve highly integrated and multifunctional system solutions.

[0003] The FPGA-based fully isolated SIP (System in Package) chip combines the flexibility and high performance of FPGA with the highly integrated and isolated characteristics of SIP. It is suitable for a variety of application scenarios that require high performance, high reliability and electrical isolation. For example, the FPGA chip and the microcontroller chip that controls RISC-V operations can be integrated into a packaged chip, and the RISC-V accelerated operation can be controlled by the FPGA chip, effectively improving the operation speed and efficiency.

[0004] Isolation controllers are widely used in many fields and industries, such as industrial control systems, power systems, communication systems, aerospace, enterprise electronics, automotive electronics, medical equipment, etc. Most of them are based on PCB board-level integrated core controllers, such as MCU, FPGA, ARM, RSIC-V, etc., connecting digital isolators to external general IOs and adding isolated power supplies to the power supply part.

[0005] The basic principle of isolated power supply is to electrically isolate the input power supply from the output power supply through isolation devices such as transformers and optocouplers to prevent current from flowing directly between the input and output. It can provide effective electrical isolation to ensure the safety of personnel and equipment. It can effectively isolate noise, interference and faults on the input side to prevent them from propagating to the output side and protect the back-end load from being affected. It can avoid ground loop problems and reduce potential electrical accidents. It has good stability, and the fluctuation and change of input voltage have little effect on the output voltage, providing a stable output voltage. It has functions such as overvoltage protection, overcurrent protection, and short-circuit protection to improve the reliability and durability of the power supply system and prevent abnormal conditions from damaging the load.

[0006] New requirements have been put forward for microcontrollers such as ARM, MCU, and FPGA, as well as new requirements for the EMC, EMI, and ESD compatibility of electronic components with traditional equipment. However, the traditional discrete device control isolation solution, controller plus isolation chip, occupies a large volume and has a complex external power supply, which is not suitable for small and highly integrated SIP chips. Therefore, it is necessary to design an isolation control solution for SIP chips, which can improve the isolation control capability of the chip without occupying too much volume of the SIP chip. Utility Model Content

[0007] The utility model provides an isolated SIP chip based on FPGA. All IOs on the SIP chip based on FPGA are isolated by a digital isolator, which effectively prevents external signal fluctuations. At the same time, the layout of the digital isolator is designed without occupying too much volume of the chip.

[0008] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one or part or all of the above purposes or other purposes, a technical solution of the utility model provides an isolated SIP chip based on FPGA, including a microcontroller chip and an FPGA chip placed on a substrate, wherein the microcontroller chip and the FPGA chip are connected via a parallel interface;

[0010] A multi-channel digital isolator a, a multi-channel digital isolator b and a multi-channel digital isolator c are arranged between the FPGA chip, the microcontroller chip and the transceiver, and the bus control chip; the two ends of the multi-channel digital isolator a are connected to the FPGA chip and the transceiver; the two ends of the multi-channel digital isolator b are connected to the FPGA chip and the transceiver, and the microcontroller chip and the bus control chip; the two ends of the multi-channel digital isolator c are connected to the transceiver and the FPGA chip, and the microcontroller chip and the bus control chip; the microcontroller chip and the differential signal transmission control chip are isolated by multiple pairs of digital isolators. The fully isolated SIP chip based on FPGA of the utility model uses digital isolators to isolate all IO interfaces of the controller on the chip to prevent fluctuations in external signals and protect the core controller. At the same time, multiple multi-channel digital isolators are used for multiplexing, which can reduce the chip size while ensuring the isolation effect.

[0011] The multi-channel digital isolator a is used for isolating the output signal transmitted from the FPGA chip to the transceiver; the multi-channel digital isolator b is used for isolating the output signal transmitted from the FPGA chip to the transceiver, and for isolating the output signal and data start bit signal transmitted from the microcontroller chip to the bus control chip; the multi-channel digital isolator c is used for isolating the return signal transmitted from the transceiver to the FPGA chip, and for isolating the return signal transmitted from the bus control chip to the microcontroller chip.

[0012] The multi-channel digital isolator b groups the output signals and data start bit signals of the microcontroller chip, each group of signals includes 1 output signal and 1 data start bit signal, and each group of signals is transmitted to a bus control chip.

[0013] The multi-channel digital isolator a, the multi-channel digital isolator b and the multi-channel digital isolator c can isolate the same number of signals.

[0014] The bus control chip is provided with a bus interface, and the bus control chip is fixed on the substrate.

[0015] The FPGA chip is also connected to a multi-channel ADC chip, the multi-channel ADC chip is provided with a plurality of ADC interfaces, and a plurality of the multi-channel ADC chips are fixed on the substrate.

[0016] The differential signal transmission control chips are arranged in plurality on both sides of the microcontroller chip, and the plurality of differential signal transmission control chips are grouped. Each group of the differential signal transmission control chips is connected to a plurality of pairs of digital isolators, and the plurality of pairs of digital isolators are connected to the microcontroller chip through signal lines.

[0017] A pair of signal lines is provided between any of the multiple pairs of digital isolators and the microcontroller chip, and the pair of signal lines is used to transmit the output signal of the microcontroller chip and receive the return signal of the differential signal transmission control chip.

[0018] The differential signal transmission control chip is provided with a plurality of differential signal transmission interfaces, and the differential signal transmission control chip is fixed on the substrate.

[0019] A power chip is arranged on the substrate, and a buck converter chip is integrated in the power chip.

[0020] Compared with the prior art, the beneficial effects of the utility model mainly include:

[0021] 1. Use multiple multi-channel digital isolators for multiplexing. According to the number of signals transmitted between the microcontroller chip and the bus controller chip and between the FPGA chip and the transceiver, reasonably select the number of signals that can be isolated by each multi-channel digital isolator. At the same time, select two multi-channel digital isolators for signal transmission from the microcontroller chip and FPGA chip to the bus controller chip and transceiver, and select one multi-channel digital isolator for signal return. After multiplexing, the number of multi-channel digital isolators can be reduced, and the chip size can be reduced. At the same time, the FPGA, microcontroller chip and digital isolator are integrated in one package, which reduces exposure to the external environment. In one package, the distance and wiring between components can be better controlled to ensure that the isolated SIP chip has a good isolation effect.

[0022] 2. Using the system-in-package (SIP) process to package FPGA, microcontroller chip and digital isolator together can shorten the signal transmission path, reduce signal attenuation and distortion, and improve the stability and reliability of the system.

[0023] In order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, preferred embodiments are given below with reference to the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 This is a chip architecture diagram of the first embodiment of the present invention.

[0026] Figure 2 This is a layout diagram of the internal substrate of the chip of the first embodiment of the present utility model. DETAILED DESCRIPTION

[0027] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0028] Embodiment 1

[0029] Embodiment 1 provides an isolated SIP chip based on FPGA. The isolated SIP chip based on FPGA of the utility model includes an FPGA chip and a microcontroller chip MCU. The microcontroller chip is used for specific control tasks, such as realizing equipment control, data acquisition, communication protocol management, specific operation acceleration and other functions. Specifically, for example: a temperature control processor for realizing temperature control of a device, a mixed signal processor for realizing analog signal and digital signal processing, a processor for realizing operation functions, etc. At the same time, the microcontroller chip communicates with the FPGA chip, which also facilitates the FPGA to control the specific control tasks realized by the microcontroller chip.

[0030] See also Figure 1 The chip architecture diagram, Example 1 takes the RISC-V processor used to implement RISC-V accelerated computing as an example to illustrate the signal isolation solution implemented by the SIP chip of this application. The RISC-V processor and the FPGA chip are connected to a flash memory, and the flash memory stores a startup program and user data. When the RISC-V processor exchanges data with an external device, differential signal transmission technology is used. The RISC-V processor is provided with multiple IO interfaces for exchanging data with external devices. These IO interfaces need to be isolated. In Example 1, four 3-pair digital isolators are used to isolate the IO interfaces set on the RISC-V processor for exchanging data with external devices. In actual use, multiple pairs of digital isolators can be designed as needed. The 3 pairs of digital isolators in Example 1 refer to digital isolators that can isolate and process 3 pairs of differential signals at the same time. Each pair of differential signals includes an output signal and a return signal. Each of the 3 pairs of digital isolators is connected to a group of differential signal transmission control chips. Each group of differential signal transmission control chips is provided with three differential signal transmission control chips, and each differential signal transmission control chip controls the transmission of a group of differential signals. By designing the settings of multiple pairs of digital isolators in this grouping form, the number of digital isolators can be effectively reduced and the integration can be improved.

[0031] Each differential signal transmission control chip is provided with an interface. Taking the first embodiment as an example, the RS422 interface (a serial communication interface standard widely used in applications requiring long-distance, high-speed data transmission. It is a differential signal transmission standard that can provide reliable data transmission over a long distance and has strong anti-interference capabilities) is used. The RS422 interface has low output impedance and can drive multiple loads (receivers), thereby supporting multi-point communication. Each RS422 chip outputs and returns signals to the RISC-V processor, and each of the three pairs of digital isolators can isolate these transmitted signals.

[0032] For interfaces that need to communicate with bus protocols, digital isolators are designed accordingly according to the protocol type of signal transmission and the signal transmission method of the microcontroller. Take the two different bus protocol communications given in Example 1 as an example for explanation. In Example 1, the two methods of communication between the RISC-V processor and the FPGA chip based on the 1553B bus protocol (MIL-STD-1553B) and the external communication are explained.

[0033] The FPGA chip communicates with the outside world based on the 1553B bus protocol (MIL-STD-1553B), and uses a 1553B transceiver to transmit signals to external devices. The FPGA outputs 8 output signals TXD (Transmit Data) to the 1553B transceiver, and 1553B transmits 4 return signals RXD (Receive Data) to the FPGA chip.

[0034] The RISC-V processor outputs 2 output signals TXD and 2 data start bit signals STB (Start Bit, marking the beginning of a data frame, telling the device that a new data frame is about to start) and transmits them to the bus (CAN) control chip, the bus controller chip and the bus interface CAN FD. At the same time, the bus control chip will return two return signals RXD to the RISC-V processor. Among them, for the convenience of operation, the bus (CAN) control chip is set with two, which are used for signal processing respectively. The 2 output signals TXD and 2 data start bit signals STB sent by the RISC-V processor are grouped into two groups of signals. Each group of signals includes 1 output signal TXD and 1 data start bit signal STB to the bus control chip.

[0035] In order to isolate the signals transmitted from the FPGA chip to the transceiver and the signals transmitted from the RISC-V processor to the bus control chip, while not taking up too much chip space, three multi-channel digital isolators are set, namely 6-channel digital isolator a, 6-channel digital isolator b and 6-channel digital isolator c. The 6-channel digital isolator a is used to isolate the 6-channel output signal TXD of the FPGA chip, and the 6-channel digital isolator b can isolate the remaining 2-channel output signal TXD of the FPGA chip, the 2-channel output signal TXD of the RISC-V processor and the 2-channel data start bit signal STB. The 6-channel digital isolator c is used to isolate the 4-channel return signal RXD of the receiver and the 2-channel return signal RXD returned by the bus control chip. Therefore, the multiple 6-channel digital isolators can be multiplexed to complete the isolation of the signals of the FPGA chip and the signals of the RISC-V processor.

[0036] At the same time, the three digital isolators are all set to 6 channels, which can simplify the design, facilitate thermal management design, and make maintenance more convenient.

[0037] Of course, the number of signals that can be isolated by the three digital isolators can be set accordingly according to the requirements for signal transmission in the signal transmission protocol of the FPGA chip and the microcontroller chip. In Example 1, the FPGA chip communicates with the outside based on the 1553B bus protocol (MIL-STD-1553B) (8 output signals TXD, 4 return signals RXD), and the RISC-V processor communicates with the outside based on the CANFD (Controller Area Network Flexible Data-rate) protocol (2 output signals TXD and 2 data start bit signals STB, 2 return signals RXD). There are 12 output signals and 6 return signals between the FPGA, microcontroller, transceiver, and bus control chip above, so setting up three 6-channel digital isolators can reduce the number of multi-channel digital isolators while meeting the same number of isolation signals of the multi-channel digital isolators. In practical applications, the number of isolation signals of the multi-channel digital isolators is selected on the premise that the number of transmission signals and return signals meets the requirements and the number of isolation signals of the multi-channel digital isolators is set to the same.

[0038] The FPGA chip is also provided with an ADC chip at one end away from the 1553B transceiver. The 8-channel ADC chip is provided with 8 ADC interfaces, and the ADC chip is fixed on the substrate.

[0039] In order to facilitate the connection between the FPGA chip and the RISC-V processor, multiple non-isolated IOs can be reserved to facilitate communication with external peripherals (not shown in the figure).

[0040] See also Figure 1 , a bus interface CAN FD is connected to the bus control chip, and the bus interface is set on the bus control chip. See also Figure 2 Layout diagram of the substrate inside the chip. The bus control chip is fixed on the substrate and located above the ADC chip and the FPGA chip.

[0041] Multiple differential signal transmission control chips are arranged on both sides of the microcontroller chip. The multiple differential signal control chips are grouped. Each group of differential signal control chips is connected to a multi-pair digital isolator. The multiple multi-pair digital isolators are connected to the microcontroller chip through signal lines. The signal lines between any multi-pair digital isolators and the microcontroller chip include two signal lines for signal transmission and signal return. Figure 1 Specifically, there are multiple RS422 chips on both sides of the RISC-V processor. The RS422 chips are grouped into three pieces. Three RS422 chips are connected to a three-pair digital isolator. At the same time, four three-pair digital isolators are connected to the RISC-V processor through a pair of signal lines. The pair of signals includes a signal line for transmitting the output signal TXD and a signal line for transmitting the return signal RXD.

[0042] The differential signal transmission control chip is provided with a plurality of differential signal transmission interfaces, and the differential signal transmission control chip is fixed on the substrate. Figure 1 as well as Figure 2 That is, the RS422 chip is fixed on the substrate, and the RS422 chip is provided with an RS422 interface.

[0043] See Figure 2 The FPGA chip and the RISC-V processor are located at the upper and lower ends of the substrate, multiple differential signal transmission control chips with RS442 interfaces are located on both sides of the RISC-V processor, multiple digital isolators are located on both sides of the multiple differential signal transmission control chips, and multiple differential signal transmission control chips, multiple digital isolators and the RISC-V processor are symmetrically arranged along the center line of the substrate.

[0044] See Figure 2 A power chip (packaged using WLSCP packaging technology) is set in the lower right corner of the substrate. The power chip integrates a buck converter chip RK860 (not specifically shown in the figure), which can power the RISC-V processor and FPGA chip.

[0045] The chip package adopts the FGG (Fine-pitch Grid Array) format, with 676 package pins and a pin pitch of 1mm.

[0046] The above is a detailed introduction to an FPGA-based isolated SIP chip provided by the utility model. This article uses specific examples to illustrate the structure and working principle of the utility model. The description of the above embodiments is only used to help understand the method and core idea of ​​the utility model. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the utility model, the utility model can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the utility model.

Claims

1. An FPGA-based isolated SIP chip, characterized in that: It includes a microcontroller chip and an FPGA chip placed on a substrate, wherein the microcontroller chip and the FPGA chip are connected via a parallel interface; A multi-channel digital isolator a, a multi-channel digital isolator b and a multi-channel digital isolator c are arranged between the FPGA chip, the microcontroller chip and the transceiver, and the bus control chip; The two ends of the multi-channel digital isolator a are connected to the FPGA chip and the transceiver; The two ends of the multi-channel digital isolator b are connected to the FPGA chip and the transceiver, and are connected to the microcontroller chip and the bus control chip; Two ends of the multi-channel digital isolator c are connected to the transceiver and the FPGA chip, and to the microcontroller chip and the bus control chip; Signal isolation is performed between the microcontroller chip and the differential signal transmission control chip through multiple pairs of digital isolators.

2. The FPGA-based isolation SIP chip according to claim 1, characterized in that: The multi-channel digital isolator a is used to isolate the output signal transmitted from the FPGA chip to the transceiver; The multi-channel digital isolator b is used for isolating the output signal transmitted from the FPGA chip to the transceiver, and for isolating the output signal and data start bit signal transmitted from the microcontroller chip to the bus control chip; The multi-channel digital isolator c is used to isolate the return signal from the transceiver to the FPGA chip, and to isolate the return signal from the bus control chip to the microcontroller chip.

3. The FPGA-based isolation SIP chip according to claim 2, characterized in that: The multi-channel digital isolator b groups the output signals and data start bit signals of the microcontroller chip, each group of signals includes 1 output signal and 1 data start bit signal, and each group of signals is transmitted to a bus control chip.

4. The FPGA-based isolation SIP chip according to claim 1, characterized in that: The multi-channel digital isolator a, the multi-channel digital isolator b and the multi-channel digital isolator c can isolate the same number of signals.

5. The FPGA-based isolation SIP chip according to claim 1, characterized in that: The bus control chip is provided with a bus interface, and the bus control chip is fixed on the substrate.

6. The FPGA-based isolation SIP chip according to claim 1, characterized in that: The FPGA chip is also connected to a multi-channel ADC chip, the multi-channel ADC chip is provided with a plurality of ADC interfaces, and the multi-channel ADC chip is fixed on the substrate.

7. The FPGA-based isolation SIP chip according to claim 1, characterized in that: The differential signal transmission control chips are arranged in plurality on both sides of the microcontroller chip, and the plurality of differential signal transmission control chips are grouped. Each group of the differential signal transmission control chips is connected to a plurality of pairs of digital isolators, and the plurality of pairs of digital isolators are connected to the microcontroller chip through signal lines.

8. The FPGA-based isolation SIP chip according to claim 7, characterized in that: A pair of signal lines is provided between any of the multiple pairs of digital isolators and the microcontroller chip, and the pair of signal lines is used to transmit the output signal of the microcontroller chip and receive the return signal of the differential signal transmission control chip.

9. The FPGA-based isolation SIP chip according to claim 7, characterized in that: The differential signal transmission control chip is provided with a plurality of differential signal transmission interfaces, and the differential signal transmission control chip is fixed on the substrate.

10. The FPGA-based isolation SIP chip according to claim 1, characterized in that: A power chip is arranged on the substrate, and a buck converter chip is integrated in the power chip.

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