Semiconductor structure

Abstract

The utility model provides a semiconductor structure with a guard ring. In a top view, a semiconductor structure may include an integrated circuit die and an encapsulant surrounding the integrated circuit die. An integrated circuit die may include a substrate having an electrical device, an interconnect structure on the substrate and electrically coupled to the electrical device, a seal ring of the interconnect structure surrounding the electrical device in a top view, and a guard ring at least partially embedded in the substrate. The guard ring may surround the seal ring in a top view and may include a different material than the substrate material.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (transistors, diodes, resistors, capacitors, etc.). In most cases, the integration density increase is due to the iterative reduction of the minimum structure size, which allows more components to be combined into a specific area. As the demand for shrinking electronic devices continues to grow, the need for smaller and more innovative semiconductor die packaging technologies has also emerged. Utility Model Content

[0003] A semiconductor structure includes an integrated circuit die and an encapsulant. The integrated circuit die includes a substrate, an interconnect structure, a sealing ring and a guard ring. The substrate has an electrical device; the interconnect structure is on the substrate, wherein the interconnect structure includes a dielectric layer and a conductive feature, wherein the conductive feature is electrically coupled to the electrical device; the sealing ring is in the dielectric layer of the interconnect structure, wherein the sealing ring surrounds the electrical device in a top view; and at least a portion of the guard ring is embedded in the substrate, wherein the guard ring surrounds the sealing ring in a top view; and the encapsulant surrounds the integrated circuit die in a top view.

[0004] A semiconductor structure includes: a first integrated circuit die, wherein the first integrated circuit die includes: a substrate having a device area; an interconnection structure on the substrate; a sealing ring in the interconnection structure; and a protection feature in the interconnection structure and the substrate, wherein the sealing ring is between the protection feature and the device area.

[0005] A semiconductor structure includes a first integrated circuit die, wherein the first integrated circuit die includes: a substrate having a device area; an interconnect structure on the substrate; a sealing ring in the interconnect structure; and a protection feature in the interconnect structure and the substrate, wherein the sealing ring is between the protection feature and the device area, wherein in a top view, the protection feature is one or more concentric segmented rings surrounding the sealing ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for the purpose of clarity of discussion.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B and Figure 6CDisclosed are various views of intermediate steps in a process of forming an integrated circuit die according to some embodiments;

[0008] Fig. 7A , Figure 7B and Figure 7C Different views of an integrated circuit die are disclosed according to some embodiments;

[0009] Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16A and Fig. 16B Disclosed are various views of intermediate steps in a packaging process for forming an integrated circuit according to some embodiments;

[0010] Fig.17 , Fig.18 , Fig.19A , Fig.19B and Fig.19C Figures disclose different views of different integrated circuit packages according to some embodiments;

[0011] Fig. 20 , Fig.21A , Fig. 21B and Fig. 21C Different views of different integrated circuit dies are disclosed according to some embodiments.

[0012]

Explanation of symbols

[0013] 10: Wafer

[0014] 50: Integrated circuit chips

[0015] 50A: Integrated circuit die

[0016] 51: Grain area

[0017] 52: Substrate

[0018] 54: Fins

[0019] 56: Shallow trench isolation area

[0020] 58: Installation area

[0021] 60: Embedded feature / bottom part

[0022] 60A: Bottom part

[0023] 60B: Bottom part

[0024] 62: Interlayer dielectric

[0025] 64: Conductive characteristics

[0026] 66: Sealing ring segment

[0027] 68: Protection ring segment

[0028] 70: Intermetallic Dielectric

[0029] 72: Conductive characteristics

[0030] 74: Sealing ring segment

[0031] 76: Protection ring segment

[0032] 78: Intermetallic Dielectric

[0033] 80: Conductive characteristics

[0034] 82: Sealing ring segment

[0035] 84: Protection ring segment

[0036] 86: Intermetallic Dielectric

[0037] 88: Conductive characteristics

[0038] 90: Sealing ring segment

[0039] 91: Sealing ring

[0040] 92: Protection ring segment

[0041] 93: Protection Ring

[0042] 93A: Protection ring

[0043] 93B: Guard ring

[0044] 94: Interconnection structure

[0045] 96: Dielectric layer

[0046] 97: Cut Track

[0047] 98: Die Connector

[0048] 99: Central Area

[0049] 100: Integrated circuit chips

[0050] 100A: Integrated circuit die

[0051] 109: Conductive vias

[0052] 118: Dielectric layer

[0053] 120: Die Connector

[0054] 121: Central area

[0055] 122: Bonding layer

[0056] 124: Carrier

[0057] 126: Bonding layer

[0058] 128: Bottom sealant

[0059] 130: Dielectric layer

[0060] 132: Die Connector

[0061] 134: Top sealant

[0062] 136: Bonding layer

[0063] 138: Bonding layer

[0064] 140: Carrier

[0065] 142: Dielectric layer

[0066] 144: Under Bump Metal

[0067] 146: Electrical connector

[0068] 148: Cut Track

[0069] 200: Integrated circuit packaging components

[0070] 202: Package substrate

[0071] 204: Substrate

[0072] 206: Bonding pad

[0073] 208: Bottom filling

[0074] 300: Integrated Circuit Packaging

[0075] A1: Area

[0076] A2: Area

[0077] A3: Area

[0078] A4: Area

[0079] A5: Area

[0080] A6: Area

[0081] A7: Area

[0082] A8: Area

[0083] D1: Distance

[0084] D2: Distance

[0085] D3: Distance

[0086] D4: Distance

[0087] H1: Height

[0088] H2: Height

[0089] H3: Height

[0090] H4: Height

[0091] R1: Ratio

[0092] R2: Ratio

[0093] R3: Ratio

[0094] R4: Ratio

[0095] R5: Ratio

[0096] R6: Ratio

[0097] T1: Thickness

[0098] T2: Thickness

[0099] T3: Thickness

[0100] T4: Thickness

[0101] T5: Thickness

[0102] T6: Thickness

[0103] W1: Width

[0104] W2: Width

[0105] W3: Width

[0106] W4: Width

[0107] A-A': Cross section

[0108] B-B': Cross section DETAILED DESCRIPTION

[0109] The following disclosure provides many different implementations or embodiments to implement the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, the following description may include an embodiment in which the first feature and the second feature are formed in direct contact above or on the second feature, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various examples and / or configurations discussed.

[0110] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted similarly accordingly.

[0111] In some embodiments, an integrated circuit package includes an integrated circuit die having an enlarged size, which may include one or more guard rings disposed, for example, between a seal ring and an edge of the integrated circuit die. The enlarged size of the integrated circuit die may reduce cracks in a sealant around the integrated circuit die, and the one or more guard rings may reduce cracks in the integrated circuit die. Thus, the yield and reliability of the integrated circuit package may be improved. In a top view, the one or more guard rings may be continuous or segmented, and may be disposed in a substrate and / or extend through one or more dielectric layers on the substrate.

[0112] Figures 1 to 6C is a diagram of an intermediate stage in the fabrication of an integrated circuit die 50 according to some embodiments. Figure 6B This is a top view. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A and Figure 6C is Figure 6B The cross-sectional view shown in the top view is shown along the reference section AA'.

[0113] exist Figure 1, a cross-sectional view of a wafer 10 is disclosed. The wafer 10 includes a die region 51, which can be subsequently formed and cut into individual integrated circuit dies. Each die region 51 can include a device region 58. Electrical devices including active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, resistors, etc.) can be subsequently formed in the device region 58. Wafer 10 includes a semiconductor substrate 52, such as doped or undoped silicon (silicon), germanium (germanium), a compound semiconductor (e.g., silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide) or an alloy semiconductor (e.g., containing silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP)). Other substrates, such as multilayer, gradient substrates, semiconductor-on-insulator (SOI) substrates, may also be used. Semiconductor substrate 52 may have an active surface (e.g., a front side) sometimes referred to as a front side. Figure 1 the upward-facing surface), and the inactive surface sometimes called the backside (e.g. Figure 1 The device region 58 may be disposed on the active surface of the semiconductor substrate 52 .

[0114] In some embodiments, a transistor (e.g., a fin field-effect transistor (FinFET), a nanowire field-effect transistor, a complementary field effect transistor (CFET), etc.) is disposed in a device region 58, and a fin 54 and a shallow trench isolation (STI) region 56 are formed in the device region 58. The fin 54 may be a semiconductor strip, which may be formed by forming a patterned mask on a semiconductor substrate 52 and etching a trench in the semiconductor substrate 52 through an opening of the patterned mask. The patterned mask may be deposited and then patterned using one or more suitable optical lithography processes. The etching process may be an acceptable anisotropic etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof.

[0115] The shallow trench isolation region 56 can be formed by depositing an insulating material in the trench and over the semiconductor substrate 52, thinning the insulating material to expose the semiconductor substrate 52, and recessing the insulating material in the trench. The insulating material may include silicon oxide, silicon nitride, etc., or a combination thereof, and may be formed by a suitable deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., or a combination thereof. The thinning process may be chemical mechanical polish (CMP), a grinding process, an etch back process, a combination thereof, etc. The shallow trench isolation region 56 may be recessed using an acceptable etching process, such as a material that is selective to the insulating material over the material of the semiconductor substrate 52.

[0116] Each die region 51 may also include an embedded feature 60 surrounding the device region 58 in a top view. The embedded feature 60 is embedded in the semiconductor substrate 52, wherein the top surface is exposed and the bottom surface and the sidewalls are in contact with the semiconductor substrate 52. The embedded feature 60 may be formed of a material different from the material of the semiconductor substrate 52, such as a conductive material (e.g., copper, aluminum, etc.) or a dielectric material (e.g., silicon oxide, silicon nitride, etc.). The embedded feature 60 may be formed by forming a trench in the semiconductor substrate 52, depositing the material of the embedded feature 60 in the trench and on the semiconductor substrate 52, and thinning the material of the embedded feature 60 to expose the semiconductor substrate 52. The trench in which the embedded feature 60 is formed may be formed by the same or similar method as described above with respect to the shallow trench isolation region 56. The material of the embedded feature 60 may be deposited in the trench by a suitable deposition method, such as CVD, ALD, physical vapor deposition (PVD), electroplating, etc. The thinning process may be the same or similar method as described above with respect to the shallow trench isolation region 56. The embedded feature 60 may have a thickness T1. In some embodiments, the thickness T1 is in a range from about 10 nanometers (nm) to about 100 micrometers (μm).

[0117] In some embodiments, the embedded feature 60 and the shallow trench isolation region 56 are formed simultaneously using the same material and the same process. In such an embodiment, the embedded feature 60 is also recessed, and the top surface of the embedded feature 60 is disposed at a height H1 below the active surface of the semiconductor substrate 52 and is flush with the top surface of the shallow trench isolation region 56. In addition, the bottom surface of the embedded feature 60 is disposed at a height H3 and is flush with the bottom surface of the shallow trench isolation region 56.

[0118] In some embodiments, the embedded features 60 are formed of a different material and / or by a different process than the shallow trench isolation regions 56. In such embodiments, the top surface of the embedded features 60 is substantially coplanar or flush with the active surface of the semiconductor substrate 52. In addition, the bottom surface of the embedded features 60 is disposed at a height H2 (above the bottom surface of the shallow trench isolation regions 56), a height H3 (flush with the bottom surface of the shallow trench isolation regions 56), or a height H4 (below the bottom surface of the shallow trench isolation regions 56). The top surface of the embedded features 60 may be recessed from the shallow trench isolation regions 56 by the same or different amounts.

[0119] exist Figure 2 In the embodiment of the present invention, an interlayer dielectric (ILD) 62 is formed on a semiconductor substrate 52, and a conductive feature 64, a seal ring segment 66, and a guard ring segment 68 are formed in the interlayer dielectric 62. The conductive feature 64, the seal ring segment 66, and the guard ring segment 68 may have a line portion and a via portion, and may extend through the interlayer dielectric 62. For ease of description, the conductive feature 64, the seal ring segment 66, and the guard ring segment 68 are disclosed as a single element. The conductive feature 64 may be electrically coupled to a circuit in the device region 58. The seal ring segment 66 may extend through the interlayer dielectric 62 to reach the semiconductor substrate 52. The guard ring segment 68 may extend through the interlayer dielectric 62 to contact the embedded feature 60. The guard ring segment 68 may include the same material as the embedded feature 60. The interlayer dielectric 62 may be formed of a dielectric material and may be deposited by a suitable deposition method, such as CVD, ALD, etc., or a combination thereof. The dielectric material may include an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), an oxide based on tetraethoxysilane (TEOS), etc.; a nitride, such as silicon nitride, etc.; a combination thereof; or the like.

[0120] The conductive feature 64 and the sealing ring segment 66 can be formed at the same time using the same material and the same process. The material of the conductive feature 64 and the sealing ring segment 66 can be a conductive material, such as copper, silver, gold, tungsten, cobalt, aluminum, nickel, etc. The conductive feature 64 and the sealing ring segment 66 can be formed by a damascene process, including forming an opening in the interlayer dielectric 62 using a suitable optical lithography and etching method, depositing a conductive material in the opening and on the interlayer dielectric 62 using a suitable deposition method (e.g., electroplating, PVD, etc.), and thinning the conductive material to expose the interlayer dielectric 62 using a suitable thinning method (e.g., CMP, grinding, etc.). In some embodiments, the conductive feature 64, the sealing ring segment 66, and the guard ring segment 68 are formed at the same time using the same material and the same process.

[0121] In some embodiments, the guard ring segment 68 is formed of a different material and / or by a different process than the conductive features 64 and the seal ring segment 66. In such embodiments, the guard ring segment 68 may include a dielectric material different from the dielectric material of the interlayer dielectric 62 or a conductive material different from the conductive material of the conductive features 64 and the seal ring segment 66. In such embodiments, the guard ring segment 68 may be formed by forming an opening in the interlayer dielectric 62 using a suitable photolithography and etching method, depositing a dielectric material or a conductive material in the opening and on the interlayer dielectric 62 using a suitable deposition method (e.g., CVD, ALD, PVD, plating, etc.), and thinning the dielectric material or the conductive material to expose the interlayer dielectric 62 using a suitable thinning method (e.g., CMP, grinding, etc.).

[0122] exist Figure 3 8, an inter-metal dielectric (IMD) 70 is formed on an inter-layer dielectric 62, an inter-metal dielectric 78 is formed on the inter-metal dielectric 70, and an inter-metal dielectric 86 is formed on the inter-metal dielectric 78. Conductive feature 72, seal ring segment 74, and guard ring segment 76 are formed in the inter-metal dielectric 70. Conductive feature 80, seal ring segment 82, and guard ring segment 84 are formed in the inter-metal dielectric 78. Conductive feature 88, seal ring segment 90, and guard ring segment 92 are formed in the inter-metal dielectric 86. Conductive features 64, 72, 80, and 88 may be electrically coupled to form various circuits in the device region 58. The inter-metal dielectric 70, the inter-metal dielectric 78, the inter-metal dielectric 86, and the conductive features 72, 80, and 88 may be collectively referred to as an interconnect structure 94. Figure 3 An interconnect structure 94 including three layers is disclosed as an example, and in some implementations, the interconnect structure 94 includes more or less than three layers.

[0123] Seal ring segment 66, seal ring segment 74, seal ring segment 82, and seal ring segment 90 may be connected and form seal ring 91. Embedded feature 60, guard ring segment 68, guard ring segment 76, guard ring segment 84, and guard ring segment 92 may be connected and form guard ring 93. Each seal ring 91 and each guard ring 93 may provide protection for features in a central region of a corresponding die region 51 during a subsequent sawing process, as discussed in more detail below. Each embedded feature 60 may be referred to as a bottom portion 60 of a corresponding guard ring 93. Seal ring 91 and guard ring 93 may be electrically isolated from circuits in device region 58. Figure 3 While the seal ring 91 is disclosed as extending completely through the interconnect structure 94 and the interlayer dielectric 62 as an example, in some embodiments, the seal ring 91 may extend partially through the interconnect structure 94 and / or the interlayer dielectric 62. The guard ring 93 may extend through the interconnect structure 94 and the interlayer dielectric 62 and into the semiconductor substrate 52.

[0124] Intermetal dielectric 70, intermetal dielectric 78, and intermetal dielectric 86 may be formed of the same or similar materials and by the same or similar methods as described above with respect to interlayer dielectric 62. Conductive features 72, conductive features 80, and conductive features 88 may be formed of the same or similar materials and by the same or similar methods as described above with respect to conductive feature 64. Seal ring segment 74, seal ring segment 82, and seal ring segment 90 may be formed of the same or similar materials and by the same or similar methods as described above with respect to seal ring segment 66. Guard ring segment 76, guard ring segment 84, and guard ring segment 92 may be formed of the same or similar materials and by the same or similar methods as described above with respect to guard ring segment 68. The top surfaces of intermetal dielectric 86, conductive features 88, seal ring 91, and guard ring 93 may be substantially coplanar or flush (within process variations).

[0125] exist Figure 4 In the embodiment of the present invention, a dielectric layer 96 is formed on the interconnect structure 94, and a die connector 98 is formed to extend through the dielectric layer 96 to contact the conductive features 88. The dielectric layer 96 may be formed of an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethoxysilane (TEOS)-based oxides, etc.; a nitride, such as silicon nitride, etc.; a combination thereof; or the like. The dielectric layer 96 may be formed by a suitable deposition method, such as CVD, ALD, etc., or a combination thereof. The die connector 98 may be formed to contact the conductive features 88 of the interconnect structure 94. Thus, the die connector 98 may be electrically coupled to the circuit in the device region 58. The die connector 98 may include conductive pillars, pads, etc., which may be used for external connection. The die connector 98 may be formed of a conductive material, such as copper, aluminum, etc., and may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0126] exist Figure 5 In the embodiment, the wafer 10 and the covering structure are cut into discrete integrated circuit dies 50 (eg Fig. 6A and Figure 6B ), where each die region 51 corresponds to an integrated circuit die 50. The dicing process can be completed along the dicing track 97 using a dicing method, such as laser dicing, blade dicing, a combination thereof, etc. Due to the stress caused by the wafer 10 and the covering structure near the dicing track 97 during the dicing process, cracks may appear in the wafer 10 and the covering structure near the dicing track 97. The guard ring 93 can prevent the cracks from propagating to the central region 99 of the die region 51, where the device region 58 and the conductive features in the interlayer dielectric 62 and the interconnect structure 94 forming the circuit of the corresponding integrated circuit die 50 are arranged. Therefore, each guard ring 93 can reduce the risk of cracks in the central region 99 of the corresponding die region 51, and maintain the integrity of the features in the central region 99, such as the semiconductor substrate 52, the device region 58 (including internal active devices and / or passive devices), the interlayer dielectric 62 (including internal conductive features), and the interconnect structure 94 (including internal conductive features). Each seal ring 91 can be disposed on the corresponding central region 99 of the die region 51 in a similar manner to the guard ring 93 for the device region 58 (including internal active devices and / or passive devices), the interlayer dielectric 62 (including internal conductive features), and the interconnect structure 94 (including internal conductive features) to provide additional protection. Therefore, the yield and reliability of the resulting integrated circuit die 50 are improved.

[0127] In FIGS. 6A and 6B, an integrated circuit die 50 is disclosed. Figure 6BThe dielectric layer 96 and the die connector 98 are omitted. The integrated circuit die 50 may be, for example, a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., a wideband analog front end (AFE) die), the like, or a combination thereof.

[0128] The outer edge of the sealing ring 91 can be spaced apart from a first edge of the integrated circuit die 50 by a distance D1, wherein the first edge is the edge of the integrated circuit die 50 that is closest to the outer edge of the sealing ring 91. The second edge of the integrated circuit die 50 can be spaced apart from the first edge of the integrated circuit die 50 by a distance D2, wherein the second edge is on the opposite side of the first edge. The distance D2 can also be referred to as the width of the integrated circuit die 50. When the distance D1 is enlarged relative to the central area 99, the distance D1 can be in a range from about 60 μm to about 120 μm, and the ratio R1 of the distance D1 to the distance D2 can be in a range from about 0.004 to about 0.008. Therefore, the size of the integrated circuit die 50 can be enlarged relative to the size of the central area 99. The enlarged size of the integrated circuit die 50 can reduce the amount of sealant used to encapsulate the integrated circuit die 50 during subsequent manufacturing processes, which can reduce the risk of cracks in the sealant, which will be described in more detail below. The enlarged size of the integrated circuit die 50 can be achieved by separating the dicing tracks 97 (such as Figure 5This may be accomplished by placing the integrated circuit die 50 further away from the seal ring 91 or by narrowing the dicing streets 97 during the sawing process, which may enlarge the size of the integrated circuit die 50 relative to the size of the central region 99 of the integrated circuit die 50.

[0129] Guard ring 93 and seal ring 91 may be rectangular frames, where in a top view, guard ring 93 may surround seal ring 91 and seal ring 91 may surround device region 58. Guard ring 93 may have a width W1. In some embodiments, width W1 is in a range of about 10 nm to about 100 μm. Fig. 6A and Figure 6B The illustrated structure and shape of the guard ring 93 is provided as an example. Other structures and shapes of the guard ring 93 are contemplated, and examples are discussed in more detail below.

[0130] Figure 6C Revealed that Fig. 6A The integrated circuit die 50A is similar in structure to the integrated circuit die 50 shown in FIG. 1 , wherein the same reference numerals represent the same elements, and discloses that the bottom portion 60 of the guard ring 93 and the shallow trench isolation region 56 in the device region 58 are formed simultaneously using the same materials and the same process. Figure 1 In such an embodiment, the bottom portion 60 is recessed, and the top surface of the bottom portion 60 is disposed at a height H1 below the active surface of the semiconductor substrate 52 and is flush with the top surface of the shallow trench isolation region 56 (not shown). In addition, the bottom surface of the bottom portion 60 is disposed at a height H3 and is flush with the bottom surface of the shallow trench isolation region 56. The bottom portion 60 may have a thickness T2, which may be substantially the same as the thickness of the shallow trench isolation region 56. In some embodiments, the thickness T2 is in a range of about 10 nm to about 100 μm. After the bottom portion 60 is recessed, an interlayer dielectric 62 is formed in the recess, and the bottom surface of the interlayer dielectric 62 is disposed below the active surface of the semiconductor substrate 52.

[0131] Fig. 7A and 7B FIG. 1 is a diagram of an integrated circuit die 100 according to some embodiments. Figure 7B is a top view and Fig. 7A 1 is a cross-sectional view along the reference section AA' in the top view. The integrated circuit die 100 may be similar to the integrated circuit die 50 described above, wherein the same symbols represent the same components. For ease of description, Figure 7BSome features are omitted. The integrated circuit die 100 can be, for example, a logic die (e.g., a central processing unit, a graphics processing unit, a system on a chip, an application processor, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory die, a static random access memory die), a power management die (e.g., a power management integrated circuit die), an RF die, a sensor die, a micro-electromechanical system die, a signal processing die (e.g., a digital signal processing die), a front-end die (e.g., a wideband analog front-end die), the like, or a combination thereof. The features of the materials and manufacturing processes in the integrated circuit die 100 can be similarly found with reference to the integrated circuit die 50.

[0132] The integrated circuit die 100 may also include a conductive via 109 in the semiconductor substrate 52. The conductive via 109 may provide backside electrical contact to the circuitry in the device region 58. The conductive via 109 may be formed by forming an opening in the semiconductor substrate 52 using suitable photolithography and etching methods, and depositing a conductive material in the opening before forming active devices and / or passive devices in the device region 58. The semiconductor substrate 52 may be thinned in a subsequent manufacturing process to expose the conductive via 109 at the inactive surface of the semiconductor substrate 52.

[0133] Dielectric layer 118 may be located on interconnect structure 94, and die connector 120 may be embedded in dielectric layer 118 and in contact with conductive features 88 of interconnect structure 94. Thus, die connector 120 may be electrically coupled to circuits in device region 58. Bonding layer 122 may be disposed on dielectric layer 118 to attach a carrier wafer in a subsequent process to thin the semiconductor substrate to expose conductive vias 109. Bonding layer 122 may include a dielectric material, such as silicon dioxide, silicon nitride, etc., and may be formed by a suitable deposition process (e.g., CVD, ALD, etc.).

[0134] The integrated circuit die 100 may also include a seal ring 91 and a guard ring 93. Similar to the top integrated circuit die 50, the integrated circuit die 100 may also be formed as part of a wafer and subsequently cut to form discrete integrated circuit die 100. The cutting process may be the same or similar to the cutting process used to form the integrated circuit die 50. The guard ring 93 and the seal ring 91 may provide the same or similar protection to the features in the central region 121 of the integrated circuit die 100 during the cutting process, as described with respect to the integrated circuit die 50, thereby improving the yield and reliability of the integrated circuit die 100.

[0135] In integrated circuit die 100, bottom portion 60 of guard ring 93 may have a thickness T3. In some embodiments, thickness T3 ranges from about 10 nm to about 100 μm. Guard ring 93 may have a width W2 (see Figure 7B ). In some embodiments, the width W2 is in a range of about 10 nm to about 100 μm. The outer edge of the seal ring 91 can be spaced apart from a first edge of the integrated circuit die 100 by a distance D3, wherein the first edge is the edge of the integrated circuit die 100 closest to the outer edge of the seal ring 91. The second edge of the integrated circuit die 100 can be spaced apart from the first edge of the integrated circuit die 100 by a distance D4, wherein the second edge is on the opposite side of the first edge. The distance D4 can also be referred to as the width of the integrated circuit die 100. When the distance D3 is enlarged relative to the width of the central region 121, the distance D3 can be in a range of about 60 μm to about 120 μm, and the ratio R2 of the distance D3 to the distance D4 can be in a range of about 0.004 to about 0.008. Therefore, the size of the integrated circuit die 100 can be enlarged relative to the size of the central region 121. The enlarged size of the integrated circuit die 100 can reduce the amount of sealant used for the integrated circuit die 100 during subsequent manufacturing processes, which can reduce the risk of cracks in the sealant, as will be described in more detail below. The enlarged size of the integrated circuit die 100 may be achieved during the sawing process by the same or similar methods as described above with respect to the integrated circuit die 50 .

[0136] Figure 7C Revealed the Fig. 7A An embodiment of an integrated circuit die 100A similar in structure to the integrated circuit die 100 shown, wherein the same reference numerals represent the same elements, discloses an embodiment in which the bottom portion 60 of the guard ring 93 and the shallow trench isolation region (not shown) in the device region 58 are formed simultaneously using the same materials and the same processes. In such an embodiment, the bottom portion 60 is recessed, and the top surface of the bottom portion 60 is disposed below the active surface of the semiconductor substrate 52 and is flush with the top surface of the shallow trench isolation region 56. In addition, the bottom surface of the bottom portion 60 is flush with the bottom surface of the shallow trench isolation region 56. The bottom portion 60 can have a thickness T4, which can be substantially the same as the thickness of the shallow trench isolation region 56. In some embodiments, the thickness T4 is in a range of about 10 nm to about 100 μm. After the bottom portion 60 is recessed, an interlayer dielectric 62 is formed in the recess, and the bottom surface of the interlayer dielectric 62 is disposed below the active surface of the semiconductor substrate 52.

[0137] Figures 8 to 16B3 are various views of intermediate stages in the fabrication of an integrated circuit package 300, according to some embodiments. As will be discussed in more detail below, integrated circuit die 100 and integrated circuit die 50 are packaged together to form integrated circuit package 300. Integrated circuit die 100 is located at a bottom layer and is also referred to as bottom integrated circuit die 100. Integrated circuit die 50 is located at a top layer, above bottom integrated circuit die 100, and is also referred to as top integrated circuit die 50. Fig.16A and Fig. 16B 8, 9, 10, 11, 12, 13, 14 and 15 are cross-sectional views along the reference section BB' in the top view. 15, 16A and 16B disclose that the top integrated circuit die 50 and the bottom integrated circuit die 100 are merely exemplary arrangements, and other layouts with more or less top integrated circuit die 50 and various arrangements of the bottom integrated circuit die 100 are contemplated.

[0138] First reference Figure 8 , the bottom integrated circuit die 100 is bonded to a carrier 124. The carrier 124 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 124 may be a wafer. Figure 8 A bottom integrated circuit die 100 bonded to a carrier 124 is disclosed as an example, two or more bottom integrated circuit dies 100 can be bonded to the carrier 124 and processed together during subsequent manufacturing steps until being cut into individual packaged components. One or more bonding layers can be disposed on the carrier 124. In some embodiments, a bonding layer 126 is disposed on the carrier 124. The bonding layer 126 can be composed of a dielectric material, such as silicon dioxide, silicon nitride, etc., and can be formed by a suitable deposition method (e.g., CVD, ALD, etc.).

[0139] The bottom integrated circuit die 100 may be placed on the bonding layer 126 by a pick-and-place process, etc., and then the bottom integrated circuit die 100 may be bonded to the bonding layer 126, and then the bottom integrated circuit die 100 may be bonded to the bonding layer 126. As an embodiment of a bonding process, the bottom integrated circuit die 100 may be bonded to the bonding layer 126 by dielectric-to-dielectric bonding without using an adhesive material (e.g., a die attach film). Bonding may include pre-bonding and annealing. During pre-bonding, a slight pressure is applied to press the bottom integrated circuit die 100 against the bonding layer 126. Pre-bonding is performed at a low temperature, such as room temperature, and after pre-bonding, the bonding layer 122 is bonded to the bonding layer 126. The bonding layer 122 and the bonding layer 126 are then annealed in a subsequent annealing step to improve bonding strength. After annealing, a direct bond, such as a covalent bond, is formed between the bonding layer 122 of the bottom integrated circuit die 100 and the bonding layer 126 of the carrier 124 .

[0140] exist Fig. 9 In the embodiment of the present invention, a bottom encapsulant 128 is formed around the bottom integrated circuit die 100 and between adjacent bottom integrated circuit dies 100 (not shown) above the carrier 124. The bottom encapsulant 128 may have a thermal expansion coefficient (CTE) greater than the thermal expansion coefficient (CTE) of the bottom integrated circuit die 100, which may result in a CTE mismatch between the bottom encapsulant 128 and the bottom integrated circuit die 100. The CTE mismatch may result in cracks in the bottom encapsulant 128 during subsequent manufacturing processes, which may be mitigated by reducing the amount of bottom encapsulant 128 used during the packaging process, as will be discussed in more detail below.

[0141] In some embodiments, the bottom sealant 128 is formed of an organic dielectric material, such as a polymer molding compound (e.g., epoxy resin and resin), etc., which is formed by a suitable deposition process such as compression molding, transfer molding, etc., and then a curing process is performed. In some embodiments, the bottom sealant 128 is formed of an inorganic dielectric material, such as silicon oxide, silicon nitride, etc., which is formed by a suitable deposition process such as CVD, ALD, etc. Initially, the bottom sealant 128 can bury or cover the back side of the semiconductor substrate 52. A thinning process can be performed to remove the bottom sealant 128 from above the bottom integrated circuit die 100 and expose the conductive via 109. The thinning process can be chemical mechanical polishing, a grinding process, an etch-back process, a combination thereof, etc. After the thinning process, the surface of the bottom sealant 128 and the bottom integrated circuit die 100 (including the semiconductor substrate 52 and the conductive via 109) can be substantially coplanar or flush (within process variations).

[0142] exist Fig.10 In the embodiment, a dielectric layer 130 is formed on the bottom sealant 128 and the back side of the semiconductor substrate 52, and a die connector 132 is formed in the dielectric layer 130. The die connector 132 can extend through the dielectric layer 130 and connect to the conductive via 109. The dielectric layer 130 can electrically isolate the die connectors 132 from each other to avoid short circuits, and can also be used in subsequent bonding processes. The dielectric layer 130 can be formed of an oxide such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxide, etc., which can be formed by a suitable deposition process such as CVD, ALD, etc. The die connector 132 can be formed by a damascene process, such as a single damascene process, a dual damascene process, etc. The die connector 132 can be formed of a metal such as copper, aluminum, etc., which can be formed by electroplating, etc. In some embodiments, a planarization process such as CMP, a grinding process, an etch-back process, a combination thereof, etc. is performed on the dielectric layer 130 and the die connector 132. After the planarization process, the surfaces of the dielectric layer 130 and the die connector 132 may be substantially coplanar or flush (within process variations).

[0143] exist Fig.11 1 , the top integrated circuit die 50 is bonded to the dielectric layer 130 and the die connector 132. The die connector 132 electrically couples the top integrated circuit die 50 to the bottom integrated circuit die 100. The top integrated circuit die 50 is placed on the dielectric layer 130 and the die connector 132 by a pick-and-place process, etc., the top integrated circuit die 50 can be bonded to the dielectric layer 130 and the die connector 132, and then the top integrated circuit die 50 is bonded to the dielectric layer 130 and the die connector 132.

[0144] The top integrated circuit die 50 may be bonded to the dielectric layer 130 and the die connector 132 by dielectric-to-dielectric bonding and metal-to-metal bonding. The dielectric layer 96 of the top integrated circuit die 50 may be directly bonded to the dielectric layer 130 by dielectric-to-dielectric bonding without using an adhesive material (e.g., a die attach film). The die connector 98 of the top integrated circuit die 50 may be directly bonded to the corresponding die connector 132 by metal-to-metal bonding without using a eutectic material (e.g., solder). Bonding may include pre-bonding and annealing. During pre-bonding, a slight pressure is applied to press the top integrated circuit die 50 against the dielectric layer 130 and the die connector 132. The pre-bonding is performed at a low temperature, such as room temperature, and after the pre-bonding, the dielectric layer 96 is bonded to the dielectric layer 130. The bonding strength may be increased in a subsequent annealing step. After annealing, a direct bond, such as a covalent bond, is formed between dielectric layer 130 and dielectric layer 96. Die connector 132 is connected to corresponding die connector 98. Die connector 132 and die connector 98 may be in physical contact after pre-bonding, or may expand during annealing to form physical contact. In addition, the materials of die connector 132 and die connector 98 mix during annealing, so that a metal-to-metal bond is formed.

[0145] exist Fig.12 In the embodiment of the present invention, a top encapsulant 134 is formed around the top integrated circuit die 50 and between adjacent top integrated circuit dies 50 above the dielectric layer 130. The top encapsulant 134 may have a coefficient of thermal expansion greater than the coefficient of thermal expansion of the top integrated circuit die 50, which may result in a mismatch in the coefficient of thermal expansion between the top encapsulant 134 and the top integrated circuit die 50. The mismatch in the coefficient of thermal expansion may result in cracks in the top encapsulant 134 during subsequent manufacturing processes, which may be mitigated by reducing the amount of top encapsulant 134 used during the packaging process, as will be discussed in more detail below.

[0146] In some embodiments, the top sealant 134 is formed of an organic dielectric material, such as a polymer molding compound (e.g., epoxy resin and resin), etc., which is formed by a suitable deposition process such as compression molding, transfer molding, etc., and then a curing process is performed. In some embodiments, the top sealant 134 is formed of an inorganic dielectric material, such as silicon oxide, silicon nitride, etc., which is formed by a suitable deposition process, such as CVD, ALD, etc. The top sealant 134 can be formed of the same or similar dielectric material as the bottom sealant 128 and by the same or similar method as the bottom sealant 128. Initially, the top sealant 134 can bury or cover the back side of the top integrated circuit die 50. A thinning process can be performed to remove portions of the semiconductor substrate 52 and the top sealant 134. The thinning process can be chemical mechanical polishing, a grinding process, an etch-back process, a combination thereof, etc. After the thinning process, the top encapsulant 134 , the surface of the top integrated circuit die 50 (including the semiconductor substrate 52 ) may be substantially coplanar or flush (within process variations).

[0147] exist Fig.13 In the embodiment, bonding layer 136 is formed on semiconductor substrate 52 and top sealant 134, and bonding layer 136 is bonded to carrier 140. Then carrier 124, bonding layer 126 and bonding layer 122 (such as Fig.12 As shown). The bonding layer 136 may include a dielectric material, such as silicon dioxide, silicon nitride, etc., and may be formed by a suitable deposition process such as CVD, ALD, etc. The carrier 140 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 140 may be a wafer having the same or similar size as the carrier 124. One or more bonding layers may be disposed on the carrier 140. In some embodiments, a bonding layer 138 is disposed on the carrier 140. The bonding layer 138 may include a dielectric material, such as silicon dioxide, silicon nitride, etc., and may be formed by a suitable deposition method (e.g., CVD, ALD, etc.). The carrier 124, the bonding layer 126, and the bonding layer 122 are then removed by a thinning process. A portion of the bottom sealant 128 may also be removed, and the dielectric layer 118 may be exposed. The thinning process may be a chemical mechanical polishing, a grinding process, an etch-back process, a combination thereof, etc. After the thinning process, the dielectric layer 118 and the bottom sealant 128 may be substantially coplanar or flush (within process variations).

[0148] exist Fig.14In the embodiment, a dielectric layer 142 is formed on the dielectric layer 118 and the bottom sealant 128, an under-bump metallization (UBM) 144 is formed on and through the dielectric layer 142, and an electrical connector 146 is formed on the under-bump metallization 144. Then, a cutting method such as laser cutting, blade cutting, or a combination thereof is used to cut the electrical connector 146 along the dicing track 148. Fig.14 The structure shown is cut so that Fig.14 The structure shown is cut into discrete integrated circuit package components 200. The dielectric layer 142 may include silicon dioxide, silicon nitride, etc., and may be formed by a suitable deposition process such as CVD, ALD, etc. The dielectric layer 142 may be a passivation layer. The under bump metal 144 has a bump portion extending on and along the surface of the dielectric layer 142, and has a through-hole portion extending through the dielectric layer 142 and the dielectric layer 118 to physically couple and electrically couple to the die connector 120. Therefore, the under bump metal 144 is electrically coupled to the bottom integrated circuit die 100. The cutting process may include a sawing process, a laser cutting process, etc. A cleaning process or a rinsing process may be performed after the cutting process.

[0149] As an embodiment of forming an under-bump metallization 144, the dielectric layer 142 and the dielectric layer 118 are patterned to form an opening for the die connector 120 that exposes the bottom layer. The patterning can be accomplished by acceptable optical lithography and etching processes, such as by forming a mask and then performing anisotropic etching. The mask is removed after patterning. A seed layer (not shown) is formed on the dielectric layer 142, in the opening through the dielectric layer 142 and the dielectric layer 118, and on the exposed portion of the die connector 120. A photoresist is then formed on the seed layer, and then the photoresist is patterned. The pattern of the photoresist corresponds to the under-bump metallization 144. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer by plating, such as electroless plating or electroplating. The conductive material may include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof. Then, the photoresist and the portion of the seed layer where the conductive material is not formed are removed, and the remaining portion of the seed layer and the conductive material forms the under bump metallurgy 144 .

[0150] The electrical connector 146 is formed on the under bump metal 144. The electrical connector 146 can be a ball grid array (BGA) connector, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed by electroless nickel electroless palladium immersion gold technique (ENEPIG), etc. The electrical connector 146 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the electrical connector 146 is formed by forming a solder layer by initial evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the electrical connector 146 includes a metal post (e.g., a copper post) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal post can be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal post.

[0151] exist Fig.15, an integrated circuit package component 200 is bonded to a package substrate 202, and an underfill 208 is formed between the integrated circuit package component 200 and the package substrate 202. The resulting structure may be referred to as an integrated circuit package 300. The package substrate 202 includes a substrate 204 and a bonding pad 206 above the substrate 204. In some embodiments, the substrate 204 is formed of a semiconductor material such as silicon, germanium, or a compound material such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like. In some embodiments, the substrate 204 is formed of an insulating material, such as fiberglass reinforced resin, bismaleimide triazine (BT) resin, Ajinomoto build-up film (ABF), and the like.

[0152] Substrate 204 may include active and / or passive devices (not shown), such as transistors, capacitors, resistors, combinations thereof, and the like. Any suitable method may be used to form active and / or passive devices. Substrate 204 may also include metallization layers and through-holes, wherein bonding pads 206 are physically coupled and electrically coupled to the metallization layers and through-holes. The metallization layers may be formed on the active and / or passive devices and are designed to connect various devices to form functional circuits. The metallization layers may be formed by alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with through-holes interconnecting the conductive material layers, and may be formed by any suitable process, such as inlay, dual inlay, and the like.

[0153] During the bonding process, the electrical connector 146 can be reflowed to bond the integrated circuit package component 200 to the bonding pad 206. The electrical connector 146 electrically and physically couples the package substrate 202 to the integrated circuit package component 200. In some embodiments, a solder resist (not shown) is formed on the substrate 204. The electrical connector 146 can be disposed in an opening in the solder resist to electrically and physically couple to the bonding pad 206. The solder resist can be used to protect areas of the substrate 204 from external damage.

[0154] An underfill 208 is formed between the integrated circuit package component 200 and the package substrate 202, surrounding the electrical connector 146. The underfill 208 can reduce stress and protect the joints created by the reflow of the electrical connector 146. The underfill 208 can be formed by a capillary flow process after bonding the integrated circuit package component 200, or can be formed by a suitable deposition method before attaching the integrated circuit package component 200. The underfill 208 can then be cured.

[0155] Fig.16A Revealed Fig.15 A top view of integrated circuit package 300 is shown, with features above top integrated circuit die 50 and top encapsulant 134 omitted for ease of illustration. Fig.16A The arrangement of the top integrated circuit die 50 on the bottom integrated circuit die 100 shown is merely an example, and other arrangements of the top integrated circuit die 50 having more or less various arrangements are contemplated. As described above, there may be a mismatch in the coefficient of thermal expansion between the top integrated circuit die 50 and the top encapsulant 134 surrounding the top integrated circuit die 50, which may lead to cracks in the top encapsulant 134 during subsequent manufacturing processes or use of the integrated circuit package 300. The risk of cracks may be reduced by reducing the amount of top encapsulant 134 used during the encapsulation process, which may be achieved by enlarging the size of the top integrated circuit die 50. Thus, the distance D1 (e.g., the distance between the top integrated circuit die 50 and the top encapsulant 134) may be increased. Fig. 6A and Figure 6B 134) can result in an enlarged size of the top integrated circuit die 50 and can reduce the risk of cracks in the top encapsulant 134, thereby improving the reliability of the integrated circuit package 300. The total area of ​​the top integrated circuit die 50 in the top view is area A1, and the total area of ​​the top encapsulant 134 in the top view is area A2. In some embodiments, a ratio R3 of area A1 to area A2 is in a range of about 2 to about 3.

[0156] Fig. 16B It revealed Fig.15 A top view of the integrated circuit package 300 is shown, wherein features above the bottom integrated circuit die 100 and the bottom encapsulant 128 are omitted for ease of illustration. Fig.16A The arrangement of the bottom integrated circuit die 100 shown is merely an example, and other arrangements of the bottom integrated circuit die 100 with more various arrangements are contemplated. Fig.16A For similar reasons as described above, the distance D3 ( Fig. 7A and Figure 7B128) may result in an enlarged size of the bottom integrated circuit die 100, which may reduce the risk of cracks in the bottom encapsulant 128, thereby improving the reliability of the integrated circuit package 300. The total area of ​​the bottom integrated circuit die 100 in the top view is area A3, and the total area of ​​the bottom encapsulant 128 in the top view is area A4. In some embodiments, a ratio R4 of area A3 to area A4 is in the range of about 2 to about 3.

[0157] Fig.17 Revealed the Fig.15 A cross-sectional view of an integrated circuit package 300 of similar structure is shown, wherein like reference numerals represent like elements, and shows an embodiment in which the guard ring 93 in the top integrated circuit die 50 is formed after the interconnect structure 94 is formed, and an embodiment in which the guard ring 93 in the bottom integrated circuit die 100 is formed after the interconnect structure 94 is formed. The guard ring 93 can be formed by forming an opening through the interconnect structure 94, the interlayer dielectric 62 and into the semiconductor substrate 52 using one or more suitable photolithography and etching methods, depositing a dielectric material or a conductive material in the opening and on the interconnect structure 94 using a suitable deposition method (e.g., CVD, ALD, PVD, plating, etc.), and thinning the dielectric material or the conductive material using a suitable thinning method (e.g., CMP, grinding, etc.) to expose the interconnect structure 94. Thus, the guard ring 93 and the guard ring 93 can have a continuous sidewall extending from the top surface to the bottom surface.

[0158] Fig.18 Revealed the Fig.15 A cross-sectional view of an integrated circuit package 300 of similar structure is shown, wherein like reference numerals represent like elements, and illustrates an embodiment in which the guard ring 93 in the top integrated circuit die 50 is formed only in the semiconductor substrate 52, and the guard ring 93 in the bottom integrated circuit die 100 is formed only in the semiconductor substrate 52. The bottom surface of the guard ring 93 (the surface in contact with the interlayer dielectric 62) and the active surface of the semiconductor substrate 52 can be substantially coplanar or flush (within process variations).

[0159] Fig.19A Revealed the Fig.15 A cross-sectional view of an integrated circuit package 300 of similar structure is shown, wherein like reference numerals represent like elements, and illustrates an embodiment in which a guard ring 93 is not formed in the top integrated circuit die 50 or the bottom integrated circuit die 100 . Fig.19B Revealed Fig.19A The top view of the integrated circuit package 300 is shown, wherein the features above the top integrated circuit die 50 and the top encapsulant 134 are omitted for ease of illustration. Fig.16A and Fig. 16BAs described above, the risk of cracks in the top encapsulant 134 can be reduced by reducing the amount of top encapsulant 134 used during the packaging process, which can be achieved by enlarging the size of the top integrated circuit die 50, and the risk of cracks in the bottom encapsulant 128 can be reduced by reducing the amount of bottom encapsulant 128 used during the encapsulation process, which can be achieved by enlarging the size of the top integrated circuit die 50. The total area of ​​the top integrated circuit die 50 in the top view is area A5, and the total area of ​​the top encapsulant 134 in the top view is area A6. In some embodiments, the ratio R5 of area A5 to area A6 is in the range of about 2 to about 3. Fig.19C Revealed Fig.19A , wherein features above the bottom integrated circuit die 100 and the bottom encapsulant 128 are omitted for ease of illustration. The total area of ​​the bottom integrated circuit die 100 in the top view is area A7, and the total area of ​​the bottom encapsulant 128 in the top view is area A8. In some embodiments, a ratio R6 of area A7 to area A8 is in a range of about 2 to about 3.

[0160] Fig. 20 Revealed the Figure 6B FIG. 5 is a top view of an integrated circuit die 50 having a similar structure as shown in FIG. 5 , wherein like reference numerals represent like elements, and Fig. 20 The top integrated circuit die 50 is shown to have a rectangular shape with chamfered corners (e.g., an octagon). Therefore, the seal ring 91 and the guard ring 93 may be a rectangular frame with chamfered corners (e.g., an octagonal frame). The integrated circuit die 100, and the seal ring 91 and the guard ring 93 in the integrated circuit die 100 may also have the same or similar structure and / or shape.

[0161] Fig.21A and Fig. 21B Respectively revealed the Fig. 6A and Figure 6B , wherein like reference numerals represent like elements, and illustrates an embodiment in which two guard rings 93 (guard ring 93A and guard ring 93B) are disposed in the top integrated circuit die 50 . Fig. 21B It is a top view. Fig.21A It is a cross-sectional view along the reference section AA' in the top view.

[0162] Guard rings 93A and 93B may be concentric segmented rings surrounding seal ring 91. In some embodiments, top integrated circuit die 50 has a rectangular shape, such as Fig. 21BAs shown. Therefore, the sealing ring 91, the guard ring 93A, and the guard ring 93B can be rectangular frames. In some embodiments (not shown), the top integrated circuit die 50 has a rectangular shape with chamfers (e.g., an octagon). Therefore, the sealing ring 91, the guard ring 93A, and the guard ring 93B can be rectangular frames with chamfers (e.g., an octagonal frame). The guard ring 93A may have a width W3 and the guard ring 93B may have a width W4. The width W3 and the width W4 may be the same or different. The bottom portion 60A of the guard ring 93A may have a thickness T5, and the bottom portion 60B of the guard ring 93B may have a thickness T6. The thickness T5 and the thickness T6 may be the same or different. In some embodiments, the width W3 and the width W4 are in the range of about 10nm to about 100μm. In some embodiments, the thickness T5 and the thickness T6 are in the range of about 10nm to about 100μm.

[0163] Fig.21A and Fig. 21B The guard ring 93 in the top integrated circuit die 50 is disclosed as two concentric segmented rings as an example. In some embodiments, the top integrated circuit die 50 has one segmented ring as the guard ring 93. In some embodiments, the top integrated circuit die 50 has more than one guard ring 93, which can be one or more concentric segmented rings, one or more concentric continuous rings, or a combination thereof. In some embodiments, the guard ring 93 in the top integrated circuit die 50 also has a plurality of concentric segmented rings, such as the concentric segmented rings, ... Figure 6C , Fig.17 , Fig.18 and Fig. 20 The structural changes described. Fig. 21C An embodiment is disclosed in which the guard ring 93 in the top integrated circuit die 50 is three concentric segmented rings, and the guard ring 93 is a rectangular frame with chamfered corners (e.g., an octagonal frame). The guard ring 93 in the bottom integrated circuit die 100 may also have the same or similar structure and / or shape as the guard ring 93 in the top integrated circuit die 50.

[0164] Embodiments can achieve advantages. Top integrated circuit die 50 and bottom integrated circuit die 100 can be formed with enlarged sizes without enlarging the sizes of center region 99 and center region 121, which reduces the amount of bottom sealant 128 and top sealant 134 used, respectively. Therefore, the risk of cracks in bottom sealant 128 and top sealant 134 can be reduced. Guard ring 93 and guard ring 93 can be formed in top integrated circuit die 50 and bottom integrated circuit die 100, respectively, which can reduce the risk of cracks in center region 99 and center region 121 during the sawing process, thereby improving the yield and reliability of top integrated circuit die 50 and bottom integrated circuit die 100. Overall, the reliability of integrated circuit package 300 is improved.

[0165] In one embodiment, a semiconductor structure includes an integrated circuit die, the integrated circuit die including a substrate having an electrical device; an interconnect structure on the substrate, wherein the interconnect structure includes a dielectric layer and a conductive feature, wherein the conductive feature is electrically coupled to the electrical device; a seal ring in the dielectric layer of the interconnect structure, wherein the seal ring surrounds the electrical device in a top view; and at least a portion of a guard ring is embedded in the substrate, wherein the guard ring surrounds the seal ring in a top view, and wherein the guard ring includes a material different from the substrate material; and an encapsulant surrounding the integrated circuit die in a top view. In one embodiment, the guard ring is electrically isolated from the electrical device. In one embodiment, the guard ring extends through the dielectric layer of the interconnect structure, and wherein the material of the guard ring is different from the material of the dielectric layer. In one embodiment, the guard ring is completely embedded in the substrate. In one embodiment, the guard ring is located in a top view between an outer edge of the seal ring and a first edge of the integrated circuit die, wherein the first edge of the integrated circuit die is an edge of the integrated circuit die closest to the outer edge of the seal ring, and wherein the first edge of the integrated circuit die includes a chamfer of the integrated circuit die. In one embodiment, the guard ring is located between an outer edge of the seal ring and a first edge of the integrated circuit die in a top view, wherein the first edge of the integrated circuit die is an edge of the integrated circuit die closest to the outer edge of the seal ring, wherein the outer edge of the seal ring is spaced apart from the first edge of the integrated circuit die by a first distance, wherein the integrated circuit die has a first width, and wherein a ratio of the first distance to the first width is in a range of 0.004 to 0.008.

[0166] In one embodiment, a semiconductor structure includes: a first integrated circuit die, wherein the first integrated circuit die includes: a substrate having a device region, wherein the substrate includes a first material; an interconnect structure on the substrate; a seal ring in the interconnect structure; and a protection feature in the interconnect structure and the substrate, wherein the protection feature includes a second material different from the first material, wherein the seal ring is between the protection feature and the device region. In one embodiment, the second material is a dielectric material. In one embodiment, the second material is a conductive material. In one embodiment, a sealant is also included, wherein the sealant includes a polymer. In one embodiment, the first integrated circuit die is one of one or more integrated circuit dies, wherein in a top view, the one or more integrated circuit dies have a first total area, wherein in a top view, the sealant has a second total area, and the ratio of the first total area to the second total area is in a range of 2 to 3. In one embodiment, the protection feature includes a first portion, wherein a surface of the first portion is flush with a surface of the substrate. In one embodiment, in a top view, the protection feature is one or more concentric continuous rings around the seal ring. In one embodiment, in a top view, the protection feature is one or more concentric segmented rings around the seal ring.

[0167] In one embodiment, a semiconductor structure includes a first integrated circuit die, wherein the first integrated circuit die includes: a substrate having a device region; an interconnect structure on the substrate; a seal ring in the interconnect structure; and a protection feature in the interconnect structure and the substrate, wherein the seal ring is between the protection feature and the device region, wherein in a top view, the protection feature is one or more concentric segmented rings surrounding the seal ring.

[0168] In one embodiment, a method of forming a semiconductor structure includes forming a first portion of a protection structure in a semiconductor wafer, wherein the semiconductor wafer includes a first material, wherein the first material of the protection structure includes a second material different from the first material; forming an interconnect structure on the semiconductor wafer, wherein the interconnect structure includes a seal ring in the interconnect structure; and performing a sawing process to separate the semiconductor wafer to form an integrated circuit die, wherein the integrated circuit die includes the protection structure, the seal ring, and the interconnect structure, and wherein in a top view, the protection structure is located between the seal ring and the edge of the integrated circuit die. In one embodiment, it also includes forming a second portion of the protection structure, wherein the second portion of the protection structure extends through the interconnect structure. In one embodiment, the second portion of the protection structure includes a second material, wherein the seal ring includes a third material, and wherein the second material and the third material are the same material. In one embodiment, the protection structure has a frame shape in a top view, wherein the seal ring has a frame shape in a top view, and wherein the protection structure surrounds the seal ring in a top view. In one embodiment, the first portion of the protection structure is disposed below a surface of the semiconductor wafer, and wherein the seal ring contacts the surface of the semiconductor wafer. In one embodiment, the step further includes forming an encapsulant around the integrated circuit die, wherein the encapsulant has a coefficient of thermal expansion greater than a coefficient of thermal expansion of the integrated circuit die.

[0169] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications herein can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, It is characterized in that Include: An integrated circuit die, comprising: A substrate having an electrical device; an interconnect structure on the substrate, wherein the interconnect structure comprises a plurality of dielectric layers and a plurality of conductive features, wherein the plurality of conductive features are electrically coupled to the electrical device; a seal ring in the multi-layer dielectric layer of the interconnect structure, wherein the seal ring surrounds the electrical device in a top view; and At least a portion of a guard ring is embedded in the substrate, wherein the guard ring surrounds the seal ring in a top view; and An encapsulant surrounds the integrated circuit die in a top view.

2. The semiconductor structure according to claim 1, It is characterized in that The protection ring is electrically isolated by the electrical device.

3. The semiconductor structure according to claim 1, It is characterized in that The guard ring is completely embedded in the substrate.

4. The semiconductor structure according to claim 1, It is characterized in that The protection ring is located between an outer edge of the sealing ring and a first edge of the integrated circuit die in the top view, wherein the first edge of the integrated circuit die is an edge of the integrated circuit die closest to the outer edge of the sealing ring, and wherein the first edge of the integrated circuit die includes a chamfer of the integrated circuit die.

5. The semiconductor structure according to claim 1, It is characterized in that The guard ring is located between an outer edge of the seal ring and a first edge of the integrated circuit die in the top view, wherein the first edge of the integrated circuit die is an edge of the integrated circuit die closest to the outer edge of the seal ring, wherein the outer edge of the seal ring is spaced apart from the first edge of the integrated circuit die by a first distance, wherein the integrated circuit die has a first width, and wherein a ratio of the first distance to the first width is in a range of 0.004 to 0.

008.

6. A semiconductor structure, It is characterized in that Include: A first integrated circuit die, wherein the first integrated circuit die comprises: a substrate having a device area; an interconnect structure on the substrate; a sealing ring in the interconnect structure; and A protection feature is formed in the interconnect structure and the substrate, wherein the seal ring is between the protection feature and the device region.

7. The semiconductor structure according to claim 6, It is characterized in that Also included is an encapsulant, wherein the first integrated circuit die is one of one or more integrated circuit die, wherein in a top view, the one or more integrated circuit die have a first total area, wherein in the top view, the encapsulant has a second total area, and a ratio of the first total area to the second total area is within a range of 2 to 3.

8. The semiconductor structure according to claim 6, It is characterized in that The protection feature includes a first portion, wherein a surface of the first portion is flush with a surface of the substrate.

9. The semiconductor structure according to claim 6, It is characterized in that Wherein in a top view, the protection feature is one or more concentric continuous rings surrounding the sealing ring.

10. A semiconductor structure, It is characterized in that Include: A first integrated circuit die, wherein the first integrated circuit die comprises: a substrate having a device area; an interconnect structure on the substrate; a sealing ring in the interconnect structure; and A protection feature is in the interconnect structure and the substrate, wherein the seal ring is between the protection feature and the device region, wherein in a top view, the protection feature is one or more concentric segmented rings surrounding the seal ring.

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